coreboot August 2014

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43 participants
102 discussions

Problems with Coreboot and SeaBIOS on VIA EPIA-M
by xchip＠hush.ai 24 Aug '14

24 Aug '14

Hello, I have been trying to use Coreboot (with SeaBIOS as payload) on a VIA EPIA-M mainboard, but had some problems with it. I have built everything with the toolchain that comes with Coreboot. To make everything (Coreboot + VGA BIOS + SeaBIOS) fit in the 256 KB flash memory, I had to LZMA compress both Coreboot and SeaBIOS. Unfortunately LZMA compression did not work for either Coreboot, nor for the payload. When compressing Coreboot's ramstage with LZMA, on boot it fails with the … [View More]following error message when trying to decompress it: Trying CBFS ramstage loader. CBFS: loading stage fallback/ramstage @ 0x100000 (151600 bytes), entry @ 0x100000 CBFS: tried to decompress 43540 bytes with algorithm #1,but that algorithm id is unsupported. Ramstage was not loaded! The next thing I tried was to omit the VGA BIOS, so I could fit Coreboot and SeaBIOS uncompressed in the flash memory. With that configuration Coreboot was able to finish successfully and then load SeaBIOS. Unfortunately, SeaBIOS did not do much besides printing two lines of text: SeaBIOS (version rel-1.7.5-42-g275672e-20140817_233743-themachine) 0 After that, it would reboot the machine and it would do the same thing over and over again. It made no difference when I increased the debug output level of SeaBIOS. Next I tried to figure out why LZMA compression did not work. LZMA compression is compiled when CBFS_CORE_WITH_LZMA is defined. I figured out that it gets defined at the beginning of src/lib/cbfs.c, depending on a few conditions. Even though I had enabled LZMA compression through the configuration menu, the constant did not get defined, though. So what I then tried was to define it unconditionally in that cbfs.c file. I did not investigate further which condition prevented it from being defined in the first place, but that change allowed me to build a Coreboot ROM where the romstage LZMA decompression worked fine. LZMA decompression of the payload still did not work, though. It failed with an error message: CBFS: located payload @ fffed238, 48776 bytes. Loading segment from rom address 0xfffed238 code (compression=1) New segment dstaddr 0xe9880 memsize 0x16780 srcaddr 0xfffed270 filesize 0xbe50 (cleaned up) New segment addr 0xe9880 size 0x16780 offset 0xfffed270 filesize 0xbe50 Loading segment from rom address 0xfffed254 Entry Point 0x000fd1e9 Bounce Buffer at 0df95000, 303200 bytes Loading Segment: addr: 0x00000000000e9880 memsz: 0x0000000000016780 filesz: 0x000000000000be50 lb: [0x0000000000100000, 0x0000000000125030) Post relocation: addr: 0x00000000000e9880 memsz: 0x0000000000016780 filesz: 0x000000000000be50 using LZMA lzma: Decoding error = 1 Could not load payload Using a compressed Coreboot and uncompressed SeaBIOS did not change SeaBIOS' behavior. It still prints only its version string and a 0 on the next line. I tried both the default configuration of SeaBIOS and with a more stripped down configuration (leaving out unused stuff like XHCI and OHCI, no splash screen etc. to reduce its size). None of the changes I tried made a difference in SeaBIOS' behavior. Any help or hints on what I might be missing are very appreciated. If you need any more information, please let me know. I did not attach any config files/log files yet, because I tried so many different things. Thanks xchip [View Less]

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Re: [coreboot] Problems with Coreboot and SeaBIOS on VIA EPIA-M
by xchip＠hush.ai 24 Aug '14

24 Aug '14

Hi, On 8/24/2014 at 1:48 AM, "ron minnich" <rminnich(a)gmail.com> wrote: > >Hi, > >when I'm having trouble with lzma what I do is not build a payload, >and run the ramstage uncompressed, and at least make sure that >works. I tried that as well and it does work indeed. It does basically the same thing as if I apply that "hack" to define that LZMA constant, as I mentioned before. In both cases the coreboot initializations seems to be fine, as far as I can tell. > &… [View More]

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X60: ethernet LED still on when machine is powered off or suspended
by The Gluglug 22 Aug '14

22 Aug '14

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 A little quirk I noticed. If I put the machine in suspend while an ethernet cable is plugged in to a switch (or if plugging it in after suspending), the green light from the ethernet/eth0 is still active. Any ideas? -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQEcBAEBAgAGBQJT9l/NAAoJEP9Ft0z50c+UaF4H/jqCZlmVadTnM0YZidrhRL2Q … [View More]

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problem with wake from suspend (asus chromebox 2955u)
by a a 19 Aug '14

19 Aug '14

I have a chrombox (asus 2995u) that in setup last weekend using coreboot and seabios fix to install linux (ubuntu 14.04) The system runs fine with one flaw and I can't find the fix; it only wakes from suspend if I hit the power button - usb devices (mouse, keyboard, ...) does not wake the system. Given that I installed it last weekend (~Aug 9) I thought it carried the wake from usb fix that was added in july are there any suggestion for fix or work around ?

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CBFS size
by John Lewis 19 Aug '14

19 Aug '14

Another question - At the moment CBFS size seems to be restricted to a maximum of 4 MB in an 8 MB ROM, and I'm wondering if there is any way to get around the "power of 2" and use a 6 MB CBFS? I've disabled the check, but it results in floppy images which fail to decompress/extract correctly, presumably due to some technical alignment reason. Thanks in advance, John.

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Re: [coreboot] ASUS C200 Chromebook
by John Lewis 19 Aug '14

19 Aug '14

On 19/08/14 16:22, Aaron Durbin wrote: > > How are you extracting it? Does cbfstool list the file? You could add > it as a raw file as a workaround. Alternatively, it's possible to > re-make it into an elf. This is the same problem as any other stage. > Once you add it and pull it out it can't be added back w/ add-stage. > It's not loaded like a stage, and to be honest I can't remember why I > chose to use add-stage to begin with. I have a feeling I didn't want to > … [View More]

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ASUS C200 Chromebook
by John Lewis 19 Aug '14

19 Aug '14

Hi Guys, long time no speak. I'm building a ROM for the subject using ChromiumOS coreboot with the relevant branch, and I'm just wondering if the external reference code binary is needed? It builds okay without it (commenting out ChromeOS specific bits that it complains about), and I can even get it to compile cleanly with the option enabled. However, I can't seem to correctly extract the binary from the shell-ball ROM using cbfstool, because at build time, it complains "E: The stage … [View More]

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Coreboot on an Asus P9X79 LE (2)
by David Melik 19 Aug '14

19 Aug '14

I had missed the part I have to give info on the type of BIOS chip. It looks like a DIP8 and says the below. Winbond 25064FVAIG 1231 --David _____________________________________________________________ Find out what's HIP! Visit Hip Planet for news, shopping, forums, chatrooms, free personal and classified ads and much more! Get FREE E-MAIL! at HipPlanet now! It's all waiting for you, at http://www.hipplanet.com

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Coreboot on an Asus P9X79 LE
by David Melik 19 Aug '14

19 Aug '14

I would like to find out if Coreboot could work for a couple relatively new Asus systemboards--for now a P9X79 LE. I am not sure about all the details about the north & south bridges, but the manual says it has an Intel X79 chipset and does not really show another large chip on the diagram (I also looked and did not see one, but there is a lot of stuff in my case)... let me know how else I would find out anything else necessary. I am attaching text files with the output of the three … [View More]

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Re: [coreboot] Try to get Intel Atom based COMe-cXLi2 Kontron board running
by Manuel Huber 18 Aug '14

18 Aug '14

Thanks for your quick reply :) - EM100 sounds like a good idea; It seems to me as if I should wait for the POST card. By reading the Intel specification of the SCH I got the feeling that issuing a 'beep' would be quite easy (well - it took me a day to just understand what Intel tried to say - but that's probably my fault...) as there is a simple buzzer connected to some transistor on the output pin of the SCH. Just configuring the Timer and enabling the output... (clock source seems to … [View More]

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coreboot August 2014