coreboot August 2014

coreboot@coreboot.org

43 participants
102 discussions

Re: [coreboot] why is firmware 32 bit as opposed to 64 bit
by The Gluglug 11 Aug '14

11 Aug '14

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 What about 32-bit-only machines, or people that want to use a 32-bit OS? On 10/08/14 22:37, ron minnich wrote: > One of the reasons I"m working to implement paging for 32-bit mode > is for our eventual change to 64-bit mode for coreboot. It's gone > on the back burner for a bit as I'm doing a few other coreboot > things first. > > I'd love to have the help, if you have time. > > ron > > On Sun, Aug 10, 2014 at 1:02 PM, Vladimir 'φ-coder/phcoder' > Serbinenko <phcoder(a)gmail.com> wrote: >> On 10.08.2014 21:06, John de la Garza wrote: >>> I understand that the calling functions in 32 bit C uses the >>> stack and this is why coreboot needs to use cache as RAM. >>> Doesn't 64 bit C use registers to pass arguments to functions? >>> If this is the case why not run in 64 bit mode? >>> >>> Also, even if cache as RAM is used and a stack is available, >>> why not just build a 64 bit binary? What are the advantages >>> to using a 32 bit binary? >>> >>> >> long mode (64-bit) needs paging table in RAM. So no 64-bit for >> preram binary. For rest it's theoretically possible but it's too >> much hassle for no benefit. >> >> >> >> >> -- coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot > -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQEcBAEBAgAGBQJT5+iiAAoJEP9Ft0z50c+U2CsH/i5aWRH4VB4Kwa9k9P4Dl1sf NhnHlg+YBmr82oRKpCR2Dtq78J0JQKOZbc5rfy0IaROxdX6Fkr4CcTxmyqWOLEhW 8RFx03NLqjOgfyVZx8JBz21RfFOJt3YVdbGtMfrRlacucUrL09JD680iwB65Zeqy zooNe2RddsXUvTHflR13MJQoxTUCESlL7XSkNAnzjSBNkwcHisgI8oOlZBvxbzD0 WLul+mvCD15IvyeJuBOSIld1UWdRWMGqK0nUqGdaPMKqeRdwvLYPzpmEbd81YXAr 3cUXnC2sWW9h7xGv1N+IKvMjrjXwaD0czPCmZ/7wAvVlhEAzM3rOabmuvukgOuk= =l8NY -----END PGP SIGNATURE-----

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qemu-armv7: code execution out of RAM or ROM using latest QEMU
by Piotr Król 10 Aug '14

10 Aug '14

Hi all, I tried to boot coreboot using latest qemu and figured out that it fails with: qemu: fatal: Trying to execute code outside RAM or ROM at 0x04000000 R00=00000002 R01=00000000 R02=00000000 R03=00000000 R04=00000000 R05=00000000 R06=00000000 R07=00000000 R08=00000000 R09=00000000 R10=00000000 R11=00000000 R12=00000000 R13=0007fed0 R14=6001032f R15=04000000 PSR=600000d3 -ZC- A svc32 (...) I was able to narrow down qemu commit that breaks coreboot booting. Bisection points to 75c9a1a 'target-arm: Implement vCPU reset via KVM_ARM_VCPU_INIT for 32-bit CPUs': http://git.qemu.org/?p=qemu.git;a=commit;h=75c9a1a0473cc5ca9756d11b236c715c… It was changed by someone from Linaro, can we assume that this change is ok and problem is on coreboot side ? If the problem is on coreboot side than have you got any ideas how to fix it (or where to dig) ? Best Regards, Piotr Król

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good news on video init
by ron minnich 09 Aug '14

09 Aug '14

Some of furquan's very fine work from -- yegads! -- a year ago is just now coming upstream. Take a look. ron

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Re: [coreboot] Intel HM76 support
by David Hendricks 09 Aug '14

09 Aug '14

On Thu, Aug 7, 2014 at 10:21 PM, Alex Henrie <alexhenrie24(a)gmail.com> wrote: > Hi, > > What is needed to support the Intel HM76 chipset? It looks like Intel > has provided some example code already: > https://downloadcenter.intel.com/Detail_Desc.aspx?agr=Y&DwnldID=23615 The good news is that HM76 (or at least very similar chipsets) are already supported in coreboot :-) The bad news is that there are many other factors to consider which are specific to the platform you intend to target. Look around the codebase and try to find something that most matches the criteria you are targeting. The Kconfig files under src/mainboard/* list the components of each mainboard pretty well. Porting to a totally new mainboard can take a few days or maybe weeks if you have all the CPU/chipset documentation, mainboard schematics, and requisite vendor-provided binaries (especially for Intel platforms). If you have none of the documentation or binaries then it can take several months assuming you're skilled and knowledgeable of x86 platforms, years if not. Start with the Lenovo x230 (Ivy Bridge) since phcoder (a highly skilled and knowledgeable dude) wrote native RAM init code on his own <http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=7686a56574a6773…>, an impressive feat that probably took him a few months. If you have a business relationship with Intel you can ask them for a binary to do the same thing for whatever northbridge you are targeting. HTH. -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

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Intel HM76 support
by Alex Henrie 08 Aug '14

08 Aug '14

Hi, What is needed to support the Intel HM76 chipset? It looks like Intel has provided some example code already: https://downloadcenter.intel.com/Detail_Desc.aspx?agr=Y&DwnldID=23615 I'm willing to donate hardware if it will help. I'm also not opposed to hunting for documentation or writing some C code. -Alex

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Re: [coreboot] Chromium Upstreaming / Introduction
by Stefan Reinauer 07 Aug '14

07 Aug '14

* Gregg Levine <gregg.drwho8(a)gmail.com> [140805 21:35]: > Hello! > Stefan, by what you posted there, (and correct me if I'm wrong) if I > were to put together a system who would be running ChromeOS and of > course using coreboot to bring it up, the OS would be constructed from > the head of the entire Chromium set? That is correct. We start out with chromium.org's HEAD and then move into a branch once development has stabilized. Stefan

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iy my pc supported for coreboot?
by Simon Andrä 07 Aug '14

07 Aug '14

Hello, i make it short and simple. I want use coreboot but i dont know if my system is supportet: Mainboard infos: I have an Acer Predator G3620 and my mainboard have the same nameand i have I7-3770 More Infos: I have try to get my Super I/O under linux but i get always the outpput "No Super I/O found: Bios device is " Found Winbond flash chip "W25Q64.V" (8192 kB, SPI)." And here is my "lspci" output:http://pastebin.com/CvccKqsH I hope someone can help me

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events from GPIO in ACPI
by Krzysztof Pierwieniecki 06 Aug '14

06 Aug '14

I know why it didn't work. For GPIO8 it should be: 'Method(_L18, 0, NotSerialized)' instead of: 'Method(_L08, 0, NotSerialized)' I don't know why but I heard that gpio in acpi have to be with offset 0x10. Now it works. Chris

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Re: [coreboot] Chromium Upstreaming / Introduction
by Kyösti Mälkki 05 Aug '14

05 Aug '14

On 07/29/2014 09:20 PM, David Hendricks wrote: > On Tue, Jul 29, 2014 at 9:55 AM, Isaac <isaac.christensen(a)se-eng.com> wrote: > >> Hello all, >> >> I am currently working on helping the Chromium team get their coreboot >> patches upstreamed so I thought I should introduce myself to the community. >> My name is Isaac Christensen and I've been working for Sage Electronic >> Engineering since October. These will be my first pushes up to >> coreboot.org >> so if you have any comments on process or workflow feel free to let me know >> as I'm still learning. >> > > Great! We'll look forward to working with you on this. > > It might be beneficial to drop by #coreboot on irc.freenode.net to answer > questions / feedback about patches in real-time. > > > Excellent. A couple questions though: Do you plan to upstream all Chromebook coreboot and libpayload branches from Chromium git, or just the individual patches Sage finds useful and necessary for the boards You currently work on? Do we expect the original authors to review the rebased, possibly modified work, or is the plan these patches just get rubberstamped as +2 by a 3rd party once they build cleanly? I see some of you first patches had a couple commits from Chromium tree squashed into one. Why was the approach changed from how eg. Aaron and Stefan handled the process? This has the unpleasant effect that commit ownership (and eg. git blame) will no longer reflect the actual author of change and also git log --oneline no longer serves as a datapoint in attempt to compare which changes from Chromium branches have been upstreamed or not. Did you develop some nice method to keep track of which branches from Chromium we can consider as completely upstreamed? Do you have the facilities to do regular board-status script runs for recent Chromebooks? Kyösti

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Minimum Steps Neccessary to Boot an Intel Architecture Platform in 2010
by Peter Stuge 04 Aug '14

04 Aug '14

http://www.intel.com/content/www/us/en/intelligent-systems/intel-boot-loade… http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/mi… It does not go into any detail, but it gives a good high-level overview. //Peter

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coreboot August 2014