coreboot November 2014

coreboot@coreboot.org

43 participants
82 discussions

Re: [coreboot] WOL/PCI PME wakeup from S3 Baytrail SoC (Bayleybay CRB)
by Gailu Singh 25 Nov '14

25 Nov '14

Hi Sean, Thanks for your help and showing me the direction. You are right GPIO pins for PMC_WAKE_PCIE were set to GPIO_DEFAULT in src/mainboard/intel/bayleybay_fsp/gpio.c. I have changed that to GPIO_ACPI_WAKE now. This seems to be one step closer to the solution but looks like something still missing as wakeup from PCIE device is still not working with coreboot. Any other thing that I should look at? Best Regards >>Perhaps you do not have all your GPIO pins set properly. On Mon, Nov 24, 2014 at 5:04 PM, Gailu Singh <gailu96(a)gmail.com> wrote: > Hi Experts, > > I have PCIe card that supports wake on lan and it works fine with BIOS. On > sending magic packet System wakes up from S3. > > However If I use same Linux image with coreboot wake from PCI device does > not wake the system. System wakes up from S3 using power button only. > > I suspected the problem with dsdt and took dsdt binary from bios setup, > disassembled it and replaced dsdt.asl in coreboot with the one from bios to > match dsdt configuration. Now my dsdt and linux image are same but still > system does not wake from PCI PME (WOL) in coreboot but works fine with > bios. > > In both cases wakeup is enabled in > /sys/bus/pci/devices/0000\:01\:00.0/power/wakeup > > Can you please advise what else could be the problem? > > PME signal is connected to GPIOS5 on the SoC. > > Best Regards > >

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Re: [coreboot] WOL/PCI PME wakeup from S3 Baytrail SoC (Bayleybay CRB)
by Sean McNeil 25 Nov '14

25 Nov '14

Perhaps you do not have all your GPIO pins set properly. On 11/24/2014 06:34 PM, Gailu Singh wrote: > Hi Experts, > > I have PCIe card that supports wake on lan and it works fine with > BIOS. On sending magic packet System wakes up from S3. > > However If I use same Linux image with coreboot wake from PCI device > does not wake the system. System wakes up from S3 using power button only. > > I suspected the problem with dsdt and took dsdt binary from bios > setup, disassembled it and replaced dsdt.asl in coreboot with the one > from bios to match dsdt configuration. Now my dsdt and linux image are > same but still system does not wake from PCI PME (WOL) in coreboot but > works fine with bios. > > In both cases wakeup is enabled in > /sys/bus/pci/devices/0000\:01\:00.0/power/wakeup > Tracking number: 771932980699 > <https://www.fedex.com/fedextrack/html/index.html?tracknumbers=771932980699> > > Can you please advise what else could be the problem? > > PME signal is connected to GPIOS5 on the SoC. > > Best Regards > > >

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 24 Nov '14

24 Nov '14

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 5 new defect(s) introduced to coreboot found with Coverity Scan. 9 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 5 of 5 defect(s) ** CID 1255946: Out-of-bounds access (ARRAY_VS_SINGLETON) /src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c: 155 in ConfigureDefaultUpdData() ** CID 1255945: Dereference null return value (NULL_RETURNS) /coreboot-builds/amd_olivehillplus/agesa/AGESA.c: 98 in LocateModule() ** CID 1255944: Dereference null return value (NULL_RETURNS) /src/northbridge/amd/pi/00730F01/dimmSpd.c: 37 in AmdMemoryReadSPD() ** CID 1255943: Dereference null return value (NULL_RETURNS) /src/cpu/amd/pi/s3_resume.c: 164 in move_stack_high_mem() ** CID 1255942: Unused value (UNUSED_VALUE) /src/drivers/usb/ehci_debug.c: 573 in usbdebug_init_() ________________________________________________________________________________________________________ *** CID 1255946: Out-of-bounds access (ARRAY_VS_SINGLETON) /src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c: 155 in ConfigureDefaultUpdData() 149 case MIPI_DEV_FUNC: /* Camera / Image Signal Processing */ 150 if (FspInfo->ImageRevision >= FSP_GOLD3_REV_ID) { 151 UpdData->ISPEnable = dev->enabled; 152 } else { 153 /* Gold2 and earlier FSP: ISPEnable is the filed */ 154 /* next to PcdGttSize in UPD_DATA_REGION struct */ >>> CID 1255946: Out-of-bounds access (ARRAY_VS_SINGLETON) >>> Using "&UpdData->PcdGttSize" as an array. This might corrupt or misinterpret adjacent memory locations. 155 *(&(UpdData->PcdGttSize)+sizeof(UINT8)) = dev->enabled; 156 printk (BIOS_DEBUG, 157 "Baytrail Gold2 or earlier FSP, adjust ISPEnable offset.\n"); 158 } 159 printk(BIOS_DEBUG, "MIPI/ISP:\t\t%s\n", 160 UpdData->PcdEnableSdio?"Enabled":"Disabled"); ________________________________________________________________________________________________________ *** CID 1255945: Dereference null return value (NULL_RETURNS) /coreboot-builds/amd_olivehillplus/agesa/AGESA.c: 98 in LocateModule() 92 file = cbfs_get_file(&media, (const char*)CONFIG_CBFS_AGESA_NAME); 93 if (!file) return NULL; 94 agesa = cbfs_get_file_content(&media, (const char*)CONFIG_CBFS_AGESA_NAME, ntohl(file->type), &file_size); 95 if (!agesa) return NULL; 96 97 image = LibAmdLocateImage(agesa, agesa + ntohl(file->len) - 1, 4096, name); >>> CID 1255945: Dereference null return value (NULL_RETURNS) >>> Dereferencing a null pointer "image". 98 module = (AMD_MODULE_HEADER*)image->ModuleInfoOffset; 99 100 return module; 101 } 102 103 /********************************************************************** ________________________________________________________________________________________________________ *** CID 1255944: Dereference null return value (NULL_RETURNS) /src/northbridge/amd/pi/00730F01/dimmSpd.c: 37 in AmdMemoryReadSPD() 31 #define DIMENSION(array)(sizeof (array)/ sizeof (array [0])) 32 33 AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info) 34 { 35 int spdAddress; 36 ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2)); >>> CID 1255944: Dereference null return value (NULL_RETURNS) >>> Dereferencing a null pointer "dev". 37 ROMSTAGE_CONST struct northbridge_amd_pi_00730F01_config *config = dev->chip_info; 38 39 if ((dev == 0) || (config == 0)) 40 return AGESA_ERROR; 41 42 if (info->SocketId >= DIMENSION(config->spdAddrLookup )) ________________________________________________________________________________________________________ *** CID 1255943: Dereference null return value (NULL_RETURNS) /src/cpu/amd/pi/s3_resume.c: 164 in move_stack_high_mem() 158 159 static void move_stack_high_mem(void) 160 { 161 void *high_stack; 162 163 high_stack = cbmem_find(CBMEM_ID_RESUME_SCRATCH); >>> CID 1255943: Dereference null return value (NULL_RETURNS) >>> Dereferencing a pointer that might be null "high_stack" when calling "memcpy". [Note: The source code implementation of the function has been overridden by a builtin model.] 164 memcpy(high_stack, (void *)BSP_STACK_BASE_ADDR, 165 (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE)); 166 167 __asm__ 168 volatile ("add %0, %%esp; add %0, %%ebp; invd"::"g" 169 (high_stack - BSP_STACK_BASE_ADDR) ________________________________________________________________________________________________________ *** CID 1255942: Unused value (UNUSED_VALUE) /src/drivers/usb/ehci_debug.c: 573 in usbdebug_init_() 567 568 dbgp_mdelay(100); 569 570 ret = dbgp_probe_gadget(info->ehci_debug, &info->ep_pipe[0]); 571 if (ret < 0) { 572 dprintk(BIOS_INFO, "Could not probe gadget on debug port.\n"); >>> CID 1255942: Unused value (UNUSED_VALUE) >>> Value "-6" is assigned to "ret" here, but that stored value is not used before it is overwritten. 573 ret = -6; 574 goto err; 575 } 576 577 return 0; 578 err: ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, http://scan.coverity.com/projects/1016?tab=overview To unsubscribe from the email notification for new defects, http://scan5.coverity.com/cgi-bin/unsubscribe.py

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How to get coreboot debug prints during suspend resume
by Gailu Singh 24 Nov '14

24 Nov '14

Hi Experts, Is it possible to get coreboot debug prints during suspend/resume? Best Regards

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WOL/PCI PME wakeup from S3 Baytrail SoC (Bayleybay CRB)
by Gailu Singh 24 Nov '14

24 Nov '14

Hi Experts, I have PCIe card that supports wake on lan and it works fine with BIOS. On sending magic packet System wakes up from S3. However If I use same Linux image with coreboot wake from PCI device does not wake the system. System wakes up from S3 using power button only. I suspected the problem with dsdt and took dsdt binary from bios setup, disassembled it and replaced dsdt.asl in coreboot with the one from bios to match dsdt configuration. Now my dsdt and linux image are same but still system does not wake from PCI PME (WOL) in coreboot but works fine with bios. In both cases wakeup is enabled in /sys/bus/pci/devices/0000\:01\:00.0/power/wakeup Can you please advise what else could be the problem? PME signal is connected to GPIOS5 on the SoC. Best Regards

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Re: [coreboot] coreboot Prague meeting - details
by Werner Zeh 24 Nov '14

24 Nov '14

Hi Rudolf. Do you know from which time the hotel is accessible on Thursday? I just need to know if I can arrive at the hotel directly and leave my car there or if I should go to the university first. Thanks Werner Am 14.10.2014 um 13:31 schrieb Rudolf Marek: > Hi all, > > Sorry for the noise I managed to exchange euros already. I did a > favor to a colleague who needed urgently cash in CZK. If you need to > exchange, > I would try either ATMs or as I have written on wiki page the > exchange8.cz (todays rate is 1 EUR =27.68 CZK) or any other exchange > office > where is acceptable ratio and no fees. > > Thanks > Rudolf >

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Donating hardware
by Vincent Pelletier 23 Nov '14

23 Nov '14

Hi. (please keep me CC'ed, I'm not subscribed) I am getting rid of two old motherboards and would like to donate them to coreboot. Both cards are ASUS: - M2N32-SLI deluxe http://www.asus.com/Motherboards/M2N32SLI_DeluxeWireless_Edition/ - M5A88-V EVO http://www.asus.com/Motherboards/M5A88V_EVO/ Any dev interested ? Questions welcome. Regards, -- Vincent Pelletier

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cbfstool build issue in gcc 4.6.3
by The Gluglug 23 Nov '14

23 Nov '14

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi, cbfs-mkstage.c: In function ‘is_phdr_ignored’: cbfs-mkstage.c:45:84: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast] The fix was made in http://review.coreboot.org/#/c/7545/ but some people were unhappy about the use of extra type casting. One possible solution is to simply upgrade GCC, which I will, but I would also like to get cbfstool to build again for this version of GCC. The patch in the gerrit link works, but is not accepted for upstream. Does anyone know a better way of doing it? Regards, Francis Rowe. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQEcBAEBAgAGBQJUbsexAAoJEP9Ft0z50c+UGU4H/3nXZpc3OlaLNg+Otfv16Xw1 Cu9lj59jqYZ4BKCWIl/ZFeZ2Dgpjgc2hJcYk+V5VcQwAWzAt/UquQJQLFBcR0gMd eZycL6z3iJS9vGh3wqpT0y1xnOXk+CckrU+3wUpGcwYuVRw2PnTllrhBDirTFObJ bOGuns8b8+wdRkuEc9kIyGgOqzSC2pLKNaPI9uYo2bAIz7J2O8IO0T6vLrfnYMqu ytV1fArz/CViF685KDB4IXbqHKlKmnVLwRWZw5mEtic0TGrcKElrHry3KgnK3Z4z eYgQ2SZ6AyA0fs7gjkC3JN9M7peWiKZ+q1DPugBnx8HBoDXIYs65QzDDFOE4yRw= =caB/ -----END PGP SIGNATURE-----

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Re: [coreboot] cbfstool build issue in gcc 4.6.3
by Stefan Reinauer 23 Nov '14

23 Nov '14

On 11/21/14 4:31 AM, Idwer Vollering wrote: > 2014-11-21 6:03 GMT+01:00 The Gluglug <info(a)gluglug.org.uk>: > >> One possible solution is to simply upgrade GCC, which I will, but I >> would also like to get cbfstool to build again for this version of >> GCC. The patch in the gerrit link works, but is not accepted for >> upstream. >> >> Does anyone know a better way of doing it? > Yes, we should use CC_x86_32 and co. from .xcompile instead. Can you > make that work? No, that's the target compiler. It can't be used for host binaries.

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Infrastructure work
by Vladimir 'φ-coder/phcoder' Serbinenko 23 Nov '14

23 Nov '14

Hello, all. I know I've signed up to fix board-status and cmos but I don't want to go through painful reviews, so I'm not going to do this, even though maintaining current CMOS stuff is a pain in itself.

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coreboot November 2014