coreboot November 2014

coreboot@coreboot.org

43 participants
82 discussions

Re: [coreboot] kt266b + vt8233a support
by Gregg Levine 30 Nov '14

30 Nov '14

Hello! And whose are those? You'll need to give us some specifics first. There is a Wiki who lists some boards. And some because of their parts may not be directly supported. To do so would require considerable work. For the KT266B one, please provide the specs also found on the Wiki. And for the VT8233A one, please do the same. ----- Gregg C Levine gregg.drwho8(a)gmail.com "This signature fought the Time Wars, time and again." On Sat, Nov 29, 2014 at 8:30 PM, Rogelio M. Serrano Jr. <rogelios664(a)gmail.com> wrote: > Hi > > Is there any coreboot support for the kt266b and vt8233a motherboards out > there? > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot

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kt266b + vt8233a support
by Rogelio M. Serrano Jr. 30 Nov '14

30 Nov '14

Hi Is there any coreboot support for the kt266b and vt8233a motherboards out there?

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lpgcc including the default gcc library?
by Vadim Bendebury (вб) 29 Nov '14

29 Nov '14

Guys, there is this line in lpgcc (http://review.coreboot.org/gitweb?p=coreboot.git;a=blob_plain;f=payloads/li…): _LIBGCC=`$DEFAULT_CC $_ARCHEXTRA -print-libgcc-file-name` why is this required? Isn't the idea that libpayload provides the entire set of modules required by the user? TIA, --vb

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Re: [coreboot] WOL/PCI PME wakeup from S3 Baytrail SoC (Bayleybay CRB)
by Gailu Singh 28 Nov '14

28 Nov '14

Also there are 0 acpi interrupts in /proc/acpi/interrupts #cat /proc/interrupts | grep -i acpi 9: 0 0 IO-APIC-fasteoi acpi On Fri, Nov 28, 2014 at 11:13 PM, Gailu Singh <gailu96(a)gmail.com> wrote: > When tracing the problem I found that there is no GPE events getting > triggered even though they are enabled. All the gpe interrupt counters are > zero in /sys/firmware/acpi/interrupts. GPE0a_EN register has desired bits > enabled. Any idea what could be the reason for not getting GPE events? > > On Fri, Nov 28, 2014 at 3:52 PM, WANG FEI <wangfei.jimei(a)gmail.com> wrote: > >> Guilu, >> >> About the item 2, please refer to >> https://www.pcisig.com/specifications/conventional/pcipm1.2.pdf, chapter >> 3, my experience is based on this spec. I bet PCIE devices should be >> compatible with this doc. >> >> This doc will focus on PCI/PCIE devices behind PCI/PCIE bridges/root >> ports, it's described how to configure the PCI/PCIE devices to wake >> themselves from PME signals. This job suppose to be done before system >> sleep(S1/S3/S4/S5). >> >> -Fei >> >> On Fri, Nov 28, 2014 at 6:42 AM, Gailu Singh <gailu96(a)gmail.com> wrote: >> >>> Hi Wang Fei, >>> >>> Thank you very much for your help. I checked the things you suggested >>> but still it does not work. Here are some details. >>> >>> >>1) SoC ACPI registers: Enable PCIE PME in PM and GPE registers. >>> You are right PCIE Wake was disabled in smm.c I enabled it >>> - enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS); >>> + enable_pm1(PWRBTN_EN | GBL_EN); >>> I Enabled GPE registers as well >>> + enable_gpe(PCI_EXP_EN | PCIE_WAKE1_EN | PCIE_WAKE2_EN >>> | SUS_GPIO_EN1 | SUS_GPIO_EN2); >>> >>> >>3) Report WOL PME single in ASL _GPE{} with _Lxx method >>> I have _Lxx methods in GPE as below >>> Method(_L11) { >>> Notify(PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ >>> } >>> >>> >> 4) (Option) If WOL PME single connect a GPIO, you have to configure >>> GPIO pin as well. >>> I tried configuring GPIO in gpio.c as GPIO_ACPI_WAKE and >>> GPIO_ACPI_SCI >>> - GPIO_DEFAULT, /* GPIO_S5[01] */ >>> - GPIO_DEFAULT, /* GPIO_S5[02] */ >>> + GPIO_ACPI_WAKE, /* GPIO_S5[01] */ >>> + GPIO_ACPI_WAKE, /* GPIO_S5[02] */ >>> >>> >>2) PCIE Card ACPI register: Yeah, you need set some registers of the >>> PCIE card to allow it waked by packages. >>> I am not clear about this. Can you please elaborate little more >>> on this. Do I need it to wake SoC or is it required for SoC to wake PCIe >>> card after resume? From power button resume card works fine post resume. >>> >>> Am I doing something wrong in the first three things you suggested? >>> >>> Best Regards >>> >>> On Wed, Nov 26, 2014 at 8:33 PM, WANG FEI <wangfei.jimei(a)gmail.com> >>> wrote: >>> >>>> I remember WOL PME wakeup function need configure 3-4 different areas, >>>> >>>> 1) SoC ACPI registers: Enable PCIE PME in PM and GPE registers. >>>> >>>> 2) PCIE Card ACPI register: Yeah, you need set some registers of the >>>> PCIE card to allow it waked by packages. >>>> >>>> 3) Report WOL PME single in ASL _GPE{} with _Lxx method >>>> >>>> 4) (Option) If WOL PME single connect a GPIO, you have to configure >>>> GPIO pin as well. >>>> >>>> Please check your code and see if anything missed. >>>> >>>> On Tue, Nov 25, 2014 at 2:27 PM, Gailu Singh <gailu96(a)gmail.com> wrote: >>>> >>>>> Hi Sean, >>>>> >>>>> Thanks for your help and showing me the direction. You are right GPIO >>>>> pins for PMC_WAKE_PCIE were set to GPIO_DEFAULT in >>>>> src/mainboard/intel/bayleybay_fsp/gpio.c. I have changed that to >>>>> GPIO_ACPI_WAKE now. This seems to be one step closer to the solution but >>>>> looks like something still missing as wakeup from PCIE device is still not >>>>> working with coreboot. Any other thing that I should look at? >>>>> >>>>> Best Regards >>>>> >>>>> >>Perhaps you do not have all your GPIO pins set properly. >>>>> >>>>> On Mon, Nov 24, 2014 at 5:04 PM, Gailu Singh <gailu96(a)gmail.com> >>>>> wrote: >>>>> >>>>>> Hi Experts, >>>>>> >>>>>> I have PCIe card that supports wake on lan and it works fine with >>>>>> BIOS. On sending magic packet System wakes up from S3. >>>>>> >>>>>> However If I use same Linux image with coreboot wake from PCI device >>>>>> does not wake the system. System wakes up from S3 using power button only. >>>>>> >>>>>> I suspected the problem with dsdt and took dsdt binary from bios >>>>>> setup, disassembled it and replaced dsdt.asl in coreboot with the one from >>>>>> bios to match dsdt configuration. Now my dsdt and linux image are same but >>>>>> still system does not wake from PCI PME (WOL) in coreboot but works fine >>>>>> with bios. >>>>>> >>>>>> In both cases wakeup is enabled in >>>>>> /sys/bus/pci/devices/0000\:01\:00.0/power/wakeup >>>>>> >>>>>> Can you please advise what else could be the problem? >>>>>> >>>>>> PME signal is connected to GPIOS5 on the SoC. >>>>>> >>>>>> Best Regards >>>>>> >>>>>> >>>>> >>>>> -- >>>>> coreboot mailing list: coreboot(a)coreboot.org >>>>> http://www.coreboot.org/mailman/listinfo/coreboot >>>>> >>>> >>>> >>> >> >

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Re: [coreboot] WOL/PCI PME wakeup from S3 Baytrail SoC (Bayleybay CRB)
by Gailu Singh 28 Nov '14

28 Nov '14

When tracing the problem I found that there is no GPE events getting triggered even though they are enabled. All the gpe interrupt counters are zero in /sys/firmware/acpi/interrupts. GPE0a_EN register has desired bits enabled. Any idea what could be the reason for not getting GPE events? On Fri, Nov 28, 2014 at 3:52 PM, WANG FEI <wangfei.jimei(a)gmail.com> wrote: > Guilu, > > About the item 2, please refer to > https://www.pcisig.com/specifications/conventional/pcipm1.2.pdf, chapter > 3, my experience is based on this spec. I bet PCIE devices should be > compatible with this doc. > > This doc will focus on PCI/PCIE devices behind PCI/PCIE bridges/root > ports, it's described how to configure the PCI/PCIE devices to wake > themselves from PME signals. This job suppose to be done before system > sleep(S1/S3/S4/S5). > > -Fei > > On Fri, Nov 28, 2014 at 6:42 AM, Gailu Singh <gailu96(a)gmail.com> wrote: > >> Hi Wang Fei, >> >> Thank you very much for your help. I checked the things you suggested but >> still it does not work. Here are some details. >> >> >>1) SoC ACPI registers: Enable PCIE PME in PM and GPE registers. >> You are right PCIE Wake was disabled in smm.c I enabled it >> - enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS); >> + enable_pm1(PWRBTN_EN | GBL_EN); >> I Enabled GPE registers as well >> + enable_gpe(PCI_EXP_EN | PCIE_WAKE1_EN | PCIE_WAKE2_EN | >> SUS_GPIO_EN1 | SUS_GPIO_EN2); >> >> >>3) Report WOL PME single in ASL _GPE{} with _Lxx method >> I have _Lxx methods in GPE as below >> Method(_L11) { >> Notify(PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ >> } >> >> >> 4) (Option) If WOL PME single connect a GPIO, you have to configure >> GPIO pin as well. >> I tried configuring GPIO in gpio.c as GPIO_ACPI_WAKE and >> GPIO_ACPI_SCI >> - GPIO_DEFAULT, /* GPIO_S5[01] */ >> - GPIO_DEFAULT, /* GPIO_S5[02] */ >> + GPIO_ACPI_WAKE, /* GPIO_S5[01] */ >> + GPIO_ACPI_WAKE, /* GPIO_S5[02] */ >> >> >>2) PCIE Card ACPI register: Yeah, you need set some registers of the >> PCIE card to allow it waked by packages. >> I am not clear about this. Can you please elaborate little more >> on this. Do I need it to wake SoC or is it required for SoC to wake PCIe >> card after resume? From power button resume card works fine post resume. >> >> Am I doing something wrong in the first three things you suggested? >> >> Best Regards >> >> On Wed, Nov 26, 2014 at 8:33 PM, WANG FEI <wangfei.jimei(a)gmail.com> >> wrote: >> >>> I remember WOL PME wakeup function need configure 3-4 different areas, >>> >>> 1) SoC ACPI registers: Enable PCIE PME in PM and GPE registers. >>> >>> 2) PCIE Card ACPI register: Yeah, you need set some registers of the >>> PCIE card to allow it waked by packages. >>> >>> 3) Report WOL PME single in ASL _GPE{} with _Lxx method >>> >>> 4) (Option) If WOL PME single connect a GPIO, you have to configure GPIO >>> pin as well. >>> >>> Please check your code and see if anything missed. >>> >>> On Tue, Nov 25, 2014 at 2:27 PM, Gailu Singh <gailu96(a)gmail.com> wrote: >>> >>>> Hi Sean, >>>> >>>> Thanks for your help and showing me the direction. You are right GPIO >>>> pins for PMC_WAKE_PCIE were set to GPIO_DEFAULT in >>>> src/mainboard/intel/bayleybay_fsp/gpio.c. I have changed that to >>>> GPIO_ACPI_WAKE now. This seems to be one step closer to the solution but >>>> looks like something still missing as wakeup from PCIE device is still not >>>> working with coreboot. Any other thing that I should look at? >>>> >>>> Best Regards >>>> >>>> >>Perhaps you do not have all your GPIO pins set properly. >>>> >>>> On Mon, Nov 24, 2014 at 5:04 PM, Gailu Singh <gailu96(a)gmail.com> wrote: >>>> >>>>> Hi Experts, >>>>> >>>>> I have PCIe card that supports wake on lan and it works fine with >>>>> BIOS. On sending magic packet System wakes up from S3. >>>>> >>>>> However If I use same Linux image with coreboot wake from PCI device >>>>> does not wake the system. System wakes up from S3 using power button only. >>>>> >>>>> I suspected the problem with dsdt and took dsdt binary from bios >>>>> setup, disassembled it and replaced dsdt.asl in coreboot with the one from >>>>> bios to match dsdt configuration. Now my dsdt and linux image are same but >>>>> still system does not wake from PCI PME (WOL) in coreboot but works fine >>>>> with bios. >>>>> >>>>> In both cases wakeup is enabled in >>>>> /sys/bus/pci/devices/0000\:01\:00.0/power/wakeup >>>>> >>>>> Can you please advise what else could be the problem? >>>>> >>>>> PME signal is connected to GPIOS5 on the SoC. >>>>> >>>>> Best Regards >>>>> >>>>> >>>> >>>> -- >>>> coreboot mailing list: coreboot(a)coreboot.org >>>> http://www.coreboot.org/mailman/listinfo/coreboot >>>> >>> >>> >> >

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Fwd: coreboot Kconfig missing deps on x201 board
by Andrey Korolyov 28 Nov '14

28 Nov '14

Hi list, unfortunately Vladimir who probably is a right person to talk about this issue did not responded yet, so I am reposting my issue for a wider audience: both master and classic-2014.10 are not able to fulfill config dependencies when this particular board is selected: warning: (CPU_AMD_AGESA && CPU_AMD_PI && CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS && NORTHBRIDGE_SPECIFIC_OPTIONS) selects LAPIC_MONOTONIC_TIMER which has unmet direct dependencies (UDELAY_LAPIC) Should I simply fix the conditions to match timer settings for ones in x220 model, as they are probably the same? Please find sample config attached (default one, just board was selected). Also there is a clear difference b/w x201 and x220 configs for CONFIG_MMX which should be set for x201 board almost for sure. Thanks!

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Re: [coreboot] WOL/PCI PME wakeup from S3 Baytrail SoC (Bayleybay CRB)
by WANG FEI 28 Nov '14

28 Nov '14

Guilu, About the item 2, please refer to https://www.pcisig.com/specifications/conventional/pcipm1.2.pdf, chapter 3, my experience is based on this spec. I bet PCIE devices should be compatible with this doc. This doc will focus on PCI/PCIE devices behind PCI/PCIE bridges/root ports, it's described how to configure the PCI/PCIE devices to wake themselves from PME signals. This job suppose to be done before system sleep(S1/S3/S4/S5). -Fei On Fri, Nov 28, 2014 at 6:42 AM, Gailu Singh <gailu96(a)gmail.com> wrote: > Hi Wang Fei, > > Thank you very much for your help. I checked the things you suggested but > still it does not work. Here are some details. > > >>1) SoC ACPI registers: Enable PCIE PME in PM and GPE registers. > You are right PCIE Wake was disabled in smm.c I enabled it > - enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS); > + enable_pm1(PWRBTN_EN | GBL_EN); > I Enabled GPE registers as well > + enable_gpe(PCI_EXP_EN | PCIE_WAKE1_EN | PCIE_WAKE2_EN | > SUS_GPIO_EN1 | SUS_GPIO_EN2); > > >>3) Report WOL PME single in ASL _GPE{} with _Lxx method > I have _Lxx methods in GPE as below > Method(_L11) { > Notify(PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ > } > > >> 4) (Option) If WOL PME single connect a GPIO, you have to configure > GPIO pin as well. > I tried configuring GPIO in gpio.c as GPIO_ACPI_WAKE and > GPIO_ACPI_SCI > - GPIO_DEFAULT, /* GPIO_S5[01] */ > - GPIO_DEFAULT, /* GPIO_S5[02] */ > + GPIO_ACPI_WAKE, /* GPIO_S5[01] */ > + GPIO_ACPI_WAKE, /* GPIO_S5[02] */ > > >>2) PCIE Card ACPI register: Yeah, you need set some registers of the > PCIE card to allow it waked by packages. > I am not clear about this. Can you please elaborate little more on > this. Do I need it to wake SoC or is it required for SoC to wake PCIe card > after resume? From power button resume card works fine post resume. > > Am I doing something wrong in the first three things you suggested? > > Best Regards > > On Wed, Nov 26, 2014 at 8:33 PM, WANG FEI <wangfei.jimei(a)gmail.com> wrote: > >> I remember WOL PME wakeup function need configure 3-4 different areas, >> >> 1) SoC ACPI registers: Enable PCIE PME in PM and GPE registers. >> >> 2) PCIE Card ACPI register: Yeah, you need set some registers of the PCIE >> card to allow it waked by packages. >> >> 3) Report WOL PME single in ASL _GPE{} with _Lxx method >> >> 4) (Option) If WOL PME single connect a GPIO, you have to configure GPIO >> pin as well. >> >> Please check your code and see if anything missed. >> >> On Tue, Nov 25, 2014 at 2:27 PM, Gailu Singh <gailu96(a)gmail.com> wrote: >> >>> Hi Sean, >>> >>> Thanks for your help and showing me the direction. You are right GPIO >>> pins for PMC_WAKE_PCIE were set to GPIO_DEFAULT in >>> src/mainboard/intel/bayleybay_fsp/gpio.c. I have changed that to >>> GPIO_ACPI_WAKE now. This seems to be one step closer to the solution but >>> looks like something still missing as wakeup from PCIE device is still not >>> working with coreboot. Any other thing that I should look at? >>> >>> Best Regards >>> >>> >>Perhaps you do not have all your GPIO pins set properly. >>> >>> On Mon, Nov 24, 2014 at 5:04 PM, Gailu Singh <gailu96(a)gmail.com> wrote: >>> >>>> Hi Experts, >>>> >>>> I have PCIe card that supports wake on lan and it works fine with BIOS. >>>> On sending magic packet System wakes up from S3. >>>> >>>> However If I use same Linux image with coreboot wake from PCI device >>>> does not wake the system. System wakes up from S3 using power button only. >>>> >>>> I suspected the problem with dsdt and took dsdt binary from bios setup, >>>> disassembled it and replaced dsdt.asl in coreboot with the one from bios to >>>> match dsdt configuration. Now my dsdt and linux image are same but still >>>> system does not wake from PCI PME (WOL) in coreboot but works fine with >>>> bios. >>>> >>>> In both cases wakeup is enabled in >>>> /sys/bus/pci/devices/0000\:01\:00.0/power/wakeup >>>> >>>> Can you please advise what else could be the problem? >>>> >>>> PME signal is connected to GPIOS5 on the SoC. >>>> >>>> Best Regards >>>> >>>> >>> >>> -- >>> coreboot mailing list: coreboot(a)coreboot.org >>> http://www.coreboot.org/mailman/listinfo/coreboot >>> >> >> >

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Re: [coreboot] WOL/PCI PME wakeup from S3 Baytrail SoC (Bayleybay CRB)
by Gailu Singh 28 Nov '14

28 Nov '14

Hi Wang Fei, Thank you very much for your help. I checked the things you suggested but still it does not work. Here are some details. >>1) SoC ACPI registers: Enable PCIE PME in PM and GPE registers. You are right PCIE Wake was disabled in smm.c I enabled it - enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS); + enable_pm1(PWRBTN_EN | GBL_EN); I Enabled GPE registers as well + enable_gpe(PCI_EXP_EN | PCIE_WAKE1_EN | PCIE_WAKE2_EN | SUS_GPIO_EN1 | SUS_GPIO_EN2); >>3) Report WOL PME single in ASL _GPE{} with _Lxx method I have _Lxx methods in GPE as below Method(_L11) { Notify(PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } >> 4) (Option) If WOL PME single connect a GPIO, you have to configure GPIO pin as well. I tried configuring GPIO in gpio.c as GPIO_ACPI_WAKE and GPIO_ACPI_SCI - GPIO_DEFAULT, /* GPIO_S5[01] */ - GPIO_DEFAULT, /* GPIO_S5[02] */ + GPIO_ACPI_WAKE, /* GPIO_S5[01] */ + GPIO_ACPI_WAKE, /* GPIO_S5[02] */ >>2) PCIE Card ACPI register: Yeah, you need set some registers of the PCIE card to allow it waked by packages. I am not clear about this. Can you please elaborate little more on this. Do I need it to wake SoC or is it required for SoC to wake PCIe card after resume? From power button resume card works fine post resume. Am I doing something wrong in the first three things you suggested? Best Regards On Wed, Nov 26, 2014 at 8:33 PM, WANG FEI <wangfei.jimei(a)gmail.com> wrote: > I remember WOL PME wakeup function need configure 3-4 different areas, > > 1) SoC ACPI registers: Enable PCIE PME in PM and GPE registers. > > 2) PCIE Card ACPI register: Yeah, you need set some registers of the PCIE > card to allow it waked by packages. > > 3) Report WOL PME single in ASL _GPE{} with _Lxx method > > 4) (Option) If WOL PME single connect a GPIO, you have to configure GPIO > pin as well. > > Please check your code and see if anything missed. > > On Tue, Nov 25, 2014 at 2:27 PM, Gailu Singh <gailu96(a)gmail.com> wrote: > >> Hi Sean, >> >> Thanks for your help and showing me the direction. You are right GPIO >> pins for PMC_WAKE_PCIE were set to GPIO_DEFAULT in >> src/mainboard/intel/bayleybay_fsp/gpio.c. I have changed that to >> GPIO_ACPI_WAKE now. This seems to be one step closer to the solution but >> looks like something still missing as wakeup from PCIE device is still not >> working with coreboot. Any other thing that I should look at? >> >> Best Regards >> >> >>Perhaps you do not have all your GPIO pins set properly. >> >> On Mon, Nov 24, 2014 at 5:04 PM, Gailu Singh <gailu96(a)gmail.com> wrote: >> >>> Hi Experts, >>> >>> I have PCIe card that supports wake on lan and it works fine with BIOS. >>> On sending magic packet System wakes up from S3. >>> >>> However If I use same Linux image with coreboot wake from PCI device >>> does not wake the system. System wakes up from S3 using power button only. >>> >>> I suspected the problem with dsdt and took dsdt binary from bios setup, >>> disassembled it and replaced dsdt.asl in coreboot with the one from bios to >>> match dsdt configuration. Now my dsdt and linux image are same but still >>> system does not wake from PCI PME (WOL) in coreboot but works fine with >>> bios. >>> >>> In both cases wakeup is enabled in >>> /sys/bus/pci/devices/0000\:01\:00.0/power/wakeup >>> >>> Can you please advise what else could be the problem? >>> >>> PME signal is connected to GPIOS5 on the SoC. >>> >>> Best Regards >>> >>> >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot >> > >

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Re: [coreboot] WOL/PCI PME wakeup from S3 Baytrail SoC (Bayleybay CRB)
by WANG FEI 26 Nov '14

26 Nov '14

I remember WOL PME wakeup function need configure 3-4 different areas, 1) SoC ACPI registers: Enable PCIE PME in PM and GPE registers. 2) PCIE Card ACPI register: Yeah, you need set some registers of the PCIE card to allow it waked by packages. 3) Report WOL PME single in ASL _GPE{} with _Lxx method 4) (Option) If WOL PME single connect a GPIO, you have to configure GPIO pin as well. Please check your code and see if anything missed. On Tue, Nov 25, 2014 at 2:27 PM, Gailu Singh <gailu96(a)gmail.com> wrote: > Hi Sean, > > Thanks for your help and showing me the direction. You are right GPIO pins > for PMC_WAKE_PCIE were set to GPIO_DEFAULT in > src/mainboard/intel/bayleybay_fsp/gpio.c. I have changed that to > GPIO_ACPI_WAKE now. This seems to be one step closer to the solution but > looks like something still missing as wakeup from PCIE device is still not > working with coreboot. Any other thing that I should look at? > > Best Regards > > >>Perhaps you do not have all your GPIO pins set properly. > > On Mon, Nov 24, 2014 at 5:04 PM, Gailu Singh <gailu96(a)gmail.com> wrote: > >> Hi Experts, >> >> I have PCIe card that supports wake on lan and it works fine with BIOS. >> On sending magic packet System wakes up from S3. >> >> However If I use same Linux image with coreboot wake from PCI device does >> not wake the system. System wakes up from S3 using power button only. >> >> I suspected the problem with dsdt and took dsdt binary from bios setup, >> disassembled it and replaced dsdt.asl in coreboot with the one from bios to >> match dsdt configuration. Now my dsdt and linux image are same but still >> system does not wake from PCI PME (WOL) in coreboot but works fine with >> bios. >> >> In both cases wakeup is enabled in >> /sys/bus/pci/devices/0000\:01\:00.0/power/wakeup >> >> Can you please advise what else could be the problem? >> >> PME signal is connected to GPIOS5 on the SoC. >> >> Best Regards >> >> > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >

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Baytrail How to enable PM1_STS_EN.PCIEXP_WAKE_EN register bit
by Gailu Singh 26 Nov '14

26 Nov '14

Hi Experts, I need to enable power management register bit (PM1_STS_EN.PCIEXP_WAKE_EN) of baytrail. I searched for PM1_STS_EN in the source but didn't find anything related to that. Any suggestion how to do it? Best Regards

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coreboot November 2014