coreboot September 2013

coreboot@coreboot.org

33 participants
75 discussions

Re: [coreboot] Tyan s2912-e (fam10h)
by Stojsavljevic, Zoran 09 Sep '13

09 Sep '13

Hello Mark, I am not sure why you are booting from BIOS (and what kind of BIOS you are using?), but I do not see any necessity to boot from BIOS to Coreboot. You should boot from BIOS to GRUB, most probable. It seems that your BIOS is working and booting, but not handing thread of execution to Coreboot. I would suggest to you to very carefully review your Coreboot settings (make menuconfig, what kind of CPU family you use there). You can also post to us attached Coreboot .config for review. And yes, please, which BIOS (make, version)? Zoran _______ Most of The Time you should be "intel inside" to be capable to think "out of the box". From: coreboot-bounces(a)coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Mark Mc Sent: Saturday, September 07, 2013 5:39 PM To: coreboot(a)coreboot.org Subject: [coreboot] Tyan s2912-e (fam10h) Hi, I was hoping someone could help me out or point me in the right direction with a tyan s2912-e board not booting with coreboot, 2x 2419 opterons 16GB ECC DDR2 RAM Onbard SAS LSI 1064e AMD Radeon 7850 2GB the codes on the onboard POST display (from port 80) are changing so fast that I cannot make them out however it is seems by the pattern of codes outputted that it is in a loop, are there any particular settings in the menuconfig that are required? Or have I missed something obvious? The system flashes with flashrom no problem I have tried booting with 1 CPU and just 1 stick of RAM, removed the PCIe GFX card. I have also built coreboot with and without the onboard VGA bios but none of this makes any difference, any help would be greatly appreciated. Intel GmbH Dornacher Strasse 1 85622 Feldkirchen/Muenchen, Deutschland Sitz der Gesellschaft: Feldkirchen bei Muenchen Geschaeftsfuehrer: Christian Lamprechter, Hannes Schwaderer, Douglas Lusk Registergericht: Muenchen HRB 47456 Ust.-IdNr./VAT Registration No.: DE129385895 Citibank Frankfurt a.M. (BLZ 502 109 00) 600119052

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Re: [coreboot] Please advise: (new toolkit) crossgcc fails on ubuntu 32/64 bit fresh installs
by Scott Duplichan 09 Sep '13

09 Sep '13

Mark Mc wrote: ... ] Is there any way to exclude crossgcc for compiling for armv7? ... Try launching buildgcc directly with no arguments. i386-elf is the default target. Lines 5 and 10 of util/crossgcc/Makefile are where the ARM builds are triggered. Thanks, Scott

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Re: [coreboot] Compiling for Pixel
by John Lewis 08 Sep '13

08 Sep '13

Well, you can try using the upstream coreboot git repo for a start - I haven't had much success using ChromiumOS's version. Largely due to the binaries they're using, I think. John. Liwei <xieliwei(a)gmail.com> wrote: >-- >coreboot mailing list: coreboot(a)coreboot.org >http://www.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] Please advise: (new toolkit) crossgcc fails on ubuntu 32/64 bit fresh installs
by Mark Mc 08 Sep '13

08 Sep '13

Unfortunately it wont compile the rom without crossgcc compiling for both platforms, my crossgcc-build.log ends with and appears to have no other failures than: cc1: fatal error: .vis: No such file or directory compilation terminated. make[5]: *** [libunwind.o] Error 1 make[4]: *** [multi-do] Error 1 make[3]: *** [all-multi] Error 2 make[2]: *** [all-target-libgcc] Error 2 /usr/bin/install: cannot stat ‘libgcc.a’: No such file or directory make[3]: *** [install-leaf] Error 1 make[2]: *** [install-target-libgcc] Error 2 Is there any way to exclude crossgcc for compiling for armv7? ---------- Forwarded message ---------- From: Andrew Wu <andrewwu.tw(a)gmail.com> Date: Sun, Sep 8, 2013 at 6:56 AM Subject: Re: [coreboot] Please advise: (new toolkit) crossgcc fails on ubuntu 32/64 bit fresh installs To: Mark Mc <markymcd13(a)gmail.com> Hi, I remember that crossgcc will output error log into file util/crossgcc/build-gcc/crossgcc-build.log , you can check it first. Also it seems crossgcc for i386-elf target is already successfully built, only armv7 is failed. If you don't need to build ARM target, I think you can ignore it. 2013/9/8 Mark Mc <markymcd13(a)gmail.com>: > Hi, just checking if anyone has any experience with this problem, my output > is: > > :~/coreboot$ make crossgcc > Warning: no suitable GCC for armv7. > Welcome to the coreboot cross toolchain builder v1.22 (July 9th, 2013) > > Target arch is now i386-elf > Will skip GDB ... ok > Downloading tar balls ... > * gmp-5.1.2.tar.bz2 (downloading) > * mpfr-3.1.2.tar.bz2 (downloading) > * mpc-1.0.1.tar.gz (downloading) > * libelf-0.8.13.tar.gz (downloading) > * gcc-4.8.1.tar.bz2 (downloading) > * binutils-2.23.2.tar.bz2 (downloading) > * acpica-unix-20130626.tar.gz (downloading) > Downloaded tar balls ... ok > Unpacking and patching ... > * gmp-5.1.2.tar.bz2 > * mpfr-3.1.2.tar.bz2 > * mpc-1.0.1.tar.gz > * libelf-0.8.13.tar.gz > * gcc-4.8.1.tar.bz2 > * binutils-2.23.2.tar.bz2 > o binutils-2.23.2_armv7a.patch > o binutils-2.23.2_no-bfd-doc.patch > * acpica-unix-20130626.tar.gz > Unpacked and patched ... ok > Building GMP 5.1.2 ... ok > Building MPFR 3.1.2 ... ok > Building MPC 1.0.1 ... ok > Building libelf 0.8.13 ... ok > Building binutils 2.23.2 ... ok > Building GCC 4.8.1 ... ok > Skipping Expat (Python scripting not enabled) > Skipping Python (Python scripting not enabled) > Skipping GDB (GDB support not enabled) > Building IASL 20130626 ... ok > Cleaning up... ok > > You can now run your i386-elf cross toolchain from > /home/mark/coreboot/util/crossgcc/xgcc. > Welcome to the coreboot cross toolchain builder v1.22 (July 9th, 2013) > > Target arch is now armv7a-eabi > Will skip GDB ... ok > Downloading tar balls ... > * gmp-5.1.2.tar.bz2 (cached) > * mpfr-3.1.2.tar.bz2 (cached) > * mpc-1.0.1.tar.gz (cached) > * libelf-0.8.13.tar.gz (cached) > * gcc-4.8.1.tar.bz2 (cached) > * binutils-2.23.2.tar.bz2 (cached) > * acpica-unix-20130626.tar.gz (cached) > Downloaded tar balls ... ok > Unpacking and patching ... > * gmp-5.1.2.tar.bz2 > * mpfr-3.1.2.tar.bz2 > * mpc-1.0.1.tar.gz > * libelf-0.8.13.tar.gz > * gcc-4.8.1.tar.bz2 > * binutils-2.23.2.tar.bz2 > o binutils-2.23.2_armv7a.patch > o binutils-2.23.2_no-bfd-doc.patch > * acpica-unix-20130626.tar.gz > Unpacked and patched ... ok > Building GMP 5.1.2 ... ok > Building MPFR 3.1.2 ... ok > Building MPC 1.0.1 ... ok > Building libelf 0.8.13 ... ok > Building binutils 2.23.2 ... ok > Building GCC 4.8.1 ... failed > make[1]: *** [build-without-gdb] Error 1 > make: *** [crossgcc] Error 2 > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] Please advise: (new toolkit) crossgcc fails on ubuntu 32/64 bit fresh installs
by Andrew Wu 08 Sep '13

08 Sep '13

Hi, I remember that crossgcc will output error log into file util/crossgcc/build-gcc/crossgcc-build.log , you can check it first. Also it seems crossgcc for i386-elf target is already successfully built, only armv7 is failed. If you don't need to build ARM target, I think you can ignore it. 2013/9/8 Mark Mc <markymcd13(a)gmail.com>: > Hi, just checking if anyone has any experience with this problem, my output > is: > > :~/coreboot$ make crossgcc > Warning: no suitable GCC for armv7. > Welcome to the coreboot cross toolchain builder v1.22 (July 9th, 2013) > > Target arch is now i386-elf > Will skip GDB ... ok > Downloading tar balls ... > * gmp-5.1.2.tar.bz2 (downloading) > * mpfr-3.1.2.tar.bz2 (downloading) > * mpc-1.0.1.tar.gz (downloading) > * libelf-0.8.13.tar.gz (downloading) > * gcc-4.8.1.tar.bz2 (downloading) > * binutils-2.23.2.tar.bz2 (downloading) > * acpica-unix-20130626.tar.gz (downloading) > Downloaded tar balls ... ok > Unpacking and patching ... > * gmp-5.1.2.tar.bz2 > * mpfr-3.1.2.tar.bz2 > * mpc-1.0.1.tar.gz > * libelf-0.8.13.tar.gz > * gcc-4.8.1.tar.bz2 > * binutils-2.23.2.tar.bz2 > o binutils-2.23.2_armv7a.patch > o binutils-2.23.2_no-bfd-doc.patch > * acpica-unix-20130626.tar.gz > Unpacked and patched ... ok > Building GMP 5.1.2 ... ok > Building MPFR 3.1.2 ... ok > Building MPC 1.0.1 ... ok > Building libelf 0.8.13 ... ok > Building binutils 2.23.2 ... ok > Building GCC 4.8.1 ... ok > Skipping Expat (Python scripting not enabled) > Skipping Python (Python scripting not enabled) > Skipping GDB (GDB support not enabled) > Building IASL 20130626 ... ok > Cleaning up... ok > > You can now run your i386-elf cross toolchain from > /home/mark/coreboot/util/crossgcc/xgcc. > Welcome to the coreboot cross toolchain builder v1.22 (July 9th, 2013) > > Target arch is now armv7a-eabi > Will skip GDB ... ok > Downloading tar balls ... > * gmp-5.1.2.tar.bz2 (cached) > * mpfr-3.1.2.tar.bz2 (cached) > * mpc-1.0.1.tar.gz (cached) > * libelf-0.8.13.tar.gz (cached) > * gcc-4.8.1.tar.bz2 (cached) > * binutils-2.23.2.tar.bz2 (cached) > * acpica-unix-20130626.tar.gz (cached) > Downloaded tar balls ... ok > Unpacking and patching ... > * gmp-5.1.2.tar.bz2 > * mpfr-3.1.2.tar.bz2 > * mpc-1.0.1.tar.gz > * libelf-0.8.13.tar.gz > * gcc-4.8.1.tar.bz2 > * binutils-2.23.2.tar.bz2 > o binutils-2.23.2_armv7a.patch > o binutils-2.23.2_no-bfd-doc.patch > * acpica-unix-20130626.tar.gz > Unpacked and patched ... ok > Building GMP 5.1.2 ... ok > Building MPFR 3.1.2 ... ok > Building MPC 1.0.1 ... ok > Building libelf 0.8.13 ... ok > Building binutils 2.23.2 ... ok > Building GCC 4.8.1 ... failed > make[1]: *** [build-without-gdb] Error 1 > make: *** [crossgcc] Error 2 > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot

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Please advise: (new toolkit) crossgcc fails on ubuntu 32/64 bit fresh installs
by Mark Mc 08 Sep '13

08 Sep '13

Hi, just checking if anyone has any experience with this problem, my output is: :~/coreboot$ make crossgcc Warning: no suitable GCC for armv7. Welcome to the coreboot cross toolchain builder v1.22 (July 9th, 2013) Target arch is now i386-elf Will skip GDB ... ok Downloading tar balls ... * gmp-5.1.2.tar.bz2 (downloading) * mpfr-3.1.2.tar.bz2 (downloading) * mpc-1.0.1.tar.gz (downloading) * libelf-0.8.13.tar.gz (downloading) * gcc-4.8.1.tar.bz2 (downloading) * binutils-2.23.2.tar.bz2 (downloading) * acpica-unix-20130626.tar.gz (downloading) Downloaded tar balls ... ok Unpacking and patching ... * gmp-5.1.2.tar.bz2 * mpfr-3.1.2.tar.bz2 * mpc-1.0.1.tar.gz * libelf-0.8.13.tar.gz * gcc-4.8.1.tar.bz2 * binutils-2.23.2.tar.bz2 o binutils-2.23.2_armv7a.patch o binutils-2.23.2_no-bfd-doc.patch * acpica-unix-20130626.tar.gz Unpacked and patched ... ok Building GMP 5.1.2 ... ok Building MPFR 3.1.2 ... ok Building MPC 1.0.1 ... ok Building libelf 0.8.13 ... ok Building binutils 2.23.2 ... ok Building GCC 4.8.1 ... ok Skipping Expat (Python scripting not enabled) Skipping Python (Python scripting not enabled) Skipping GDB (GDB support not enabled) Building IASL 20130626 ... ok Cleaning up... ok You can now run your i386-elf cross toolchain from /home/mark/coreboot/util/crossgcc/xgcc. Welcome to the coreboot cross toolchain builder v1.22 (July 9th, 2013) Target arch is now armv7a-eabi Will skip GDB ... ok Downloading tar balls ... * gmp-5.1.2.tar.bz2 (cached) * mpfr-3.1.2.tar.bz2 (cached) * mpc-1.0.1.tar.gz (cached) * libelf-0.8.13.tar.gz (cached) * gcc-4.8.1.tar.bz2 (cached) * binutils-2.23.2.tar.bz2 (cached) * acpica-unix-20130626.tar.gz (cached) Downloaded tar balls ... ok Unpacking and patching ... * gmp-5.1.2.tar.bz2 * mpfr-3.1.2.tar.bz2 * mpc-1.0.1.tar.gz * libelf-0.8.13.tar.gz * gcc-4.8.1.tar.bz2 * binutils-2.23.2.tar.bz2 o binutils-2.23.2_armv7a.patch o binutils-2.23.2_no-bfd-doc.patch * acpica-unix-20130626.tar.gz Unpacked and patched ... ok Building GMP 5.1.2 ... ok Building MPFR 3.1.2 ... ok Building MPC 1.0.1 ... ok Building libelf 0.8.13 ... ok Building binutils 2.23.2 ... ok Building GCC 4.8.1 ... failed make[1]: *** [build-without-gdb] Error 1 make: *** [crossgcc] Error 2

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Compiling for Pixel
by Liwei 08 Sep '13

08 Sep '13

Hello list, I've been tinkering around with the Pixel for a while and today decided to compile a copy of Coreboot on my own. As predicted for a first timer, I made a brick. I can pretty much recover from that by reflashing with a bus pirate-like device, but I'm wondering what did I do wrong? The device wakes up when I open the lid or press the power button (keyboard light goes on) but that's it. It still turns off if I hold on to the power button for a while. Attached are my flash layout ( http://paste.ubuntu.com/6075724/ ) and coreboot config ( http://paste.ubuntu.com/6075719/ ). Source is chromeos-2013.04 branch from https://chromium.googlesource.com/chromiumos/third_party/coreboot . The last commit is 747c728538785498b6d1aa7029a7673c91068ece. SeaBIOS, which is my payload, is firmware-link-2695.B branch from https://chromium.googlesource.com/chromiumos/third_party/seabios . The last commit is 93d1fc99763baa363cbe1855b4533dfd4a1a0308. I'd appreciate it very much if someone can give me some pointers on what I must do to get a working image. Thanks! Liwei

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Re: [coreboot] Tyan s2912-e (fam10h)
by David Hubbard 07 Sep '13

07 Sep '13

Hi Mark, On Sat, Sep 7, 2013 at 9:38 AM, Mark Mc <markymcd13(a)gmail.com> wrote: > Hi, I was hoping someone could help me out or point me in the right > direction with a tyan s2912-e board not booting with coreboot, > 2x 2419 opterons > 16GB ECC DDR2 RAM > Onbard SAS LSI 1064e > AMD Radeon 7850 2GB > > the codes on the onboard POST display (from port 80) are changing so fast > that I cannot make them out however it is seems by the pattern of codes > outputted that it is in a loop, are there any particular settings in the > menuconfig that are required? Or have I missed something obvious? > > The system flashes with flashrom no problem > I have tried booting with 1 CPU and just 1 stick of RAM, removed the PCIe > GFX card. I have also built coreboot with and without the onboard VGA bios > but none of this makes any difference, any help would be greatly > appreciated. > > I don't have personal experience with the s2912-e, so these are general debugging approaches. It could help you find a specific area that is failing. Then someone else might spot what's going on. :-) Would it help if you inserted some busy loops at interesting points in the code? I mean something like for (i = 0; i < 1000000; i++) for (j = 0; j < 1000000; j++) for (k = 0; k < 1000000; k++) { volatile int m = 0; m++; /*to keep the compiler from optimizing the loop away*/ } The wiki has information on where the code starts and the overall flow: http://www.coreboot.org/Developer_Manual#coreboot_Overview >From that you could place busy loops at strategic points to slow down the post codes. Can you get a serial console log? Ok, hope that helps. David

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Tyan s2912-e (fam10h)
by Mark Mc 07 Sep '13

07 Sep '13

Hi, I was hoping someone could help me out or point me in the right direction with a tyan s2912-e board not booting with coreboot, 2x 2419 opterons 16GB ECC DDR2 RAM Onbard SAS LSI 1064e AMD Radeon 7850 2GB the codes on the onboard POST display (from port 80) are changing so fast that I cannot make them out however it is seems by the pattern of codes outputted that it is in a loop, are there any particular settings in the menuconfig that are required? Or have I missed something obvious? The system flashes with flashrom no problem I have tried booting with 1 CPU and just 1 stick of RAM, removed the PCIe GFX card. I have also built coreboot with and without the onboard VGA bios but none of this makes any difference, any help would be greatly appreciated.

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Re: [coreboot] Coreboot supports intel baytrail processor?
by ron minnich 04 Sep '13

04 Sep '13

On Wed, Sep 4, 2013 at 12:53 AM, Stojsavljevic, Zoran <zoran.stojsavljevic(a)intel.com> wrote: > Hello Ron, > > Yes, Baytrail FSP Beta release is already for 4 weeks available in EDS (External Design Specifications), but you must be registered with INTEL to get Baytrail FSP and it documents. Also, as I stated before, you need OTM (Coreboot will come later as part of this picture). I'm on the web site and hunting around and it seems, at present, to be incomplete. Also, saying FSP is available in beta as an EDS (a spec) makes no sense to me. Where's the FSP binary itself? For instance, after passing through many links and looking at many docs, I am here: https://www-ssl.intel.com/content/www/us/en/intelligent-systems/intel-firmw… But all I can are documents, nice looking people, and links that have nothing to do with FSP. Where do I go? What are the redistribution rights on FSP? I assume we'll be able to host the binary at coreboot.org as well as intel.com. ron

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coreboot September 2013