coreboot September 2013

coreboot@coreboot.org

33 participants
75 discussions

Info BIOS Acer Aspire 1300
by valentinorossi10＠alice.it 16 Sep '13

16 Sep '13

Dear staff of the promising project "coreboot", my name is Marco and I am writing to ask you for information about the compatibility of your BIOS with my old laptop Acer Aspire 1300 (following characteristics) that, despite his age, still turns out to be an excellent tool for work and entertainment (especially when used with Linux operating systems), but unfortunately lacks some small drawbacks that do not allow to express the full potential: for example, despite updating the BIOS to the latest version (see 3a71 dating back to 2003), it is not possible to use SSE instructions, which would be fully supported by the CPU (Athlon XP-M 2200 +), but are not enabled in the BIOS, which can not be changed manually, if not to set the time or the boot sequence for devices. Therefore, I was wondering if your brilliant product would be able to solve my little / big problem and, anyway, I hope in the future you manage in your intent to create a new revolutionary and out of the ordinary BIOS for all the coputers on the market. Here are the features of my laptop, which I hope will be sufficient to determine the compatibity: Board vendors: AcerBoard name: Aspire 1300 (ET2S)CPU: AMD Athlon XP-M 2200 +Northbridge: VIA KN133Southbridge: VIA VT8231BIOS: Insyde Software (v.3a71), 512KB ROM I hope soon to receive your news. Sincerely, Marco.

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Re: [coreboot] Tyan s2912-E reset loop, Please help
by Marc Jones 15 Sep '13

15 Sep '13

On Tue, Sep 10, 2013 at 9:07 PM, Mark Mc <markymcd13(a)gmail.com> wrote: > Thank you Kyösti, there was no need to change MAX_CPUS as I had selected > S2912 Fam10 (Thunder n3600R) so it is already set to 12 CPUS, I did change > what else you told me to so that I could get more output to the serial > console. I think I am getting closer to identifying the problem which is > that the MCP55 (Southbridge) needs a warm reset to continue after POST: 0x3a > however in this case it cannot I am currently studying the > /src/mainboard/tyan/s2912_fam10/romstage.c to try and identify what is going > wrong any suggestions are appreciated. > > My coreboot log now looks like this: > ----------------------------------------------------------------------------------------------------------------------------------------- > > coreboot-4.0-4671-g25dd247 Mon Sep 9 23:54:49 BST 2013 starting... > BSP Family_Model: 00100f80 > *sysinfo range: [000c4000,000c5fa0] > bsp_apicid = 00 > cpu_init_detectedx = 00000000 > microcode: rev id not found. Skipping microcode patch! > POST: 0x33 > cpuSetAMDMSR done > POST: 0x34 > Enter amd_ht_init() > AMD_CB_ManualBUIDSwapList() > AMD_CB_EventNotify() > event class: 05 > event: 2006 > data: 04 00 02 ff > Exit amd_ht_init() > POST: 0x35 > cpuSetAMDPCI 00 done > Prep FID/VID Node:00 > F3x80: e600e681 > F3x84: 80e641e6 > F3xD4: c3310f27 > F3xD8: 03000215 > F3xDC: 00006428 > POST: 0x36 > core0 started: > start_other_cores() > init node: 00 cores: 05 > Start other core - nodeid: 00 cores: 05 > POST: 0x37 > started ap apicid: * AP 01started > * AP 02started > * AP 03started > * AP 04started > * AP 05started > > POST: 0x38 > > Begin FIDVID MSR 0xc0010071 0x38a400c4 0x38044c40 > POST: 0x39 > FIDVID on BSP, APIC_id: 00 > BSP fid = 0 > Wait for AP stage 1: ap_apicid = 1 > readback = 1000001 > common_fid(packed) = 0 > Wait for AP stage 1: ap_apicid = 2 > readback = 2000001 > common_fid(packed) = 0 > Wait for AP stage 1: ap_apicid = 3 > readback = 3000001 > common_fid(packed) = 0 > Wait for AP stage 1: ap_apicid = 4 > readback = 4000001 > common_fid(packed) = 0 > Wait for AP stage 1: ap_apicid = 5 > readback = 5000001 > common_fid(packed) = 0 > common_fid = 0 > POST: 0x3a > End FIDVIDMSR 0xc0010071 0x38a400c4 0x38044c40 > mcp55_num:01 > POST: 0x30 > > > > INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} --- > > Issuing SOFT_RESET... > --------------------------------------------------------------------------------------------------------------------------------------------- > Cheers > Mark > After the soft reset, it should got through romstage again, but skip the clock init (fid/vid) and then do the memory init. It might have a problem with detecting the warm reset. Marc > > > On Tue, Sep 10, 2013 at 4:54 AM, Kyösti Mälkki <kyosti.malkki(a)gmail.com> > wrote: >> >> On Tue, 2013-09-10 at 02:01 +0100, Mark Mc wrote: >> > Hi, I finally got coreboot compiled correctly and I am getting >> > somewhere as my console output shows: >> > >> > coreboot-4.0-4671-g25dd247 Mon Sep 9 23:54:49 BST 2013 starting... >> > BSP Family_Model: 00100f80 >> > *sysinfo range: [000c4000,000c5fa0] >> > bsp_apicid = 00 >> > cpu_init_detectedx = 00000000 >> > microcode: rev id not found. Skipping microcode patch! >> > POST: 0x33 >> > cpuSetAMDMSR done >> > POST: 0x34 >> > Enter amd_ht_init() >> > AMD_CB_ManualBUIDSwapList() >> > AMD_CB_EventNotify() >> > event class: 05 >> > event: 2006 >> > data: 04 00 02 ff >> > Exit amd_ht_init() >> > POST: 0x35 >> > cpuSetAMDPCI 00 done >> > Prep FID/VID Node:00 >> > F3x80: e600e681 >> > F3x84: 80e641e6 >> > F3xD4: c3310f27 >> > F3xD8: 03000215 >> > F3xDC: 00006428 >> > POST: 0x36 >> > core0 started: >> > start_other_cores() >> > init node: 00 cores: 05 >> > Start other core - nodeid: 00 cores: 05 >> > POST: 0x37 >> > started ap apicid: * AP 01started >> > * AP 02started >> > * AP 03started >> > * AP 04started >> > * AP 05started >> > >> >> > INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} --- >> > Issuing SOFT_RESET... >> > >> > >> > However it just keeps looping like this, any guidance would be really >> > appreciated, so far I have tried booting with just 1 dimm (4GB),1 CPU >> > (opteron 2419) and no PCI-E cards, both stable and master seabios >> > payloads but so far absolutely no difference. >> >> >> First increase MAX_CPUS in src/mainboard/tyan/2912/Kconfig from 4 to 12. >> >> If that alone does not work, try change SERIAL_CPU_INIT=yes in same >> file. Additionally in menuconfig under consoles, try with >> SQUELCH_EARLY_SMP=no. >> >> Last two changes should not be required, just something to try as they >> will slow down the boot sequence and give more output on serial console. >> >> Remember that after modifying any Kconfig file, you need a clean build: >> make clean && make oldconfig && make >> >> >> Regards, >> Kyösti >> > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot -- http://se-eng.com

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Coreboot Haswell Support
by Karl-Heinz Nirschl 11 Sep '13

11 Sep '13

Hi List, There seems to be some support for intel haswell platform in coreboot. But i can not find the neccessary systemagent / mrb.bin binary. Isnt it released yet? Best regards,

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GNU30 Security Hackathon
by hellekin 10 Sep '13

10 Sep '13

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA512 Hello, your project is part of the selection for the GNU30 hackathon listed at http://www.gnu.org/gnu30/celebration In the course of the anniversary, there's a security conference in Buenos Aires, called Ekoparty, and I'm willing to organize a GNU security hackathon there. [0] Here is how it's supposed to work. Security hackers will be invited to do one of the following things: (1) Report zeroday vulnerabilities (2) Fix security or privacy bugs (3) Create, or give away security tools to the GNU project My objective with this email is to gather a list of suggestions as to where to put the effort on your various projects, in order to make it more convenient for them to choose. I'm willing to gather security-related bugs that they can look into and fix over a period of 3 days (obviously not full time), or ideas for useful tools related to privacy or security. Any suggestion welcome! Feel free to share this message in full or in parts with your fellow hackers. The sooner I get answers, and the better the participants can get ready and explore possibilities. Regards, and happy hacking! == hk [0] http://ekoparty.org/ P.S.: it might be interesting as well to gather participants' laptop info for the Coreboot project. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) Comment: Using GnuPG with Icedove - http://www.enigmail.net/ iQIcBAEBCgAGBQJSL9qHAAoJEEgGw2P8GJg99WwP/jYohUj7gJ8S162ImQjSDDyF LM9bZihbiI7i7fdqR9B7+geSfx/C2I3z7pLGKFmhg92Jbh4yXyuEd9cxGOL9S+nr U3TQyCDvkEbmGZRov8OSnKJxPJ2s8tgW00dh4v5syZtyCbBHPcZ3owMU7HHrvu10 MtPzgc8GXBxsFo6WisSunmCzkrrfX12gKSnpyKAxV3XOvNQJENbH8Sb5+8VxaCUl /OTlfrp02wTGZRW6JSJgLhiXcRGFjCIFIynEg0jjKvLVbrmeSZAWii4lkNf2g2w7 q445FbaOCb15hV7AnMQ8V3OY1Akgi9yv9976QVUljKTCihI3UfYttoi0j+i6JI1n YHmDxtX5MubDj5V8I5Mkm6VaFC4L03PJClzDi4wLD8nC6/rGDU4zJelBctJW37bX kFOpP9scmhM1l8nL6ZKxdHgYQYTWxEVa+PbpbcrnfR8bn3iwEBGBqa7xXf/IjFHJ uh3GV6rFHZW12YyQh+i07NdwKxuURdg0THZ/BDoKk9kMV+eOKWP/Uf/+7ZcZI3Z3 AHFEAXcQsePI/ok1JrNvg2RnJhFmbmHGc3Wh00I8W0buEhg3xPtp/jGNWqXDUk+w xmQ+J2WPewe2ABHvyujNI5l75rkjziAaBB0rIkC4sdn9K6KpC+Lx+5gWUhqlopO8 Q2RcI/sE6BBwRKWctiSH =JjH8 -----END PGP SIGNATURE-----

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Re: [coreboot] Tyan s2912-E reset loop, Please help
by Kyösti Mälkki 10 Sep '13

10 Sep '13

On Tue, 2013-09-10 at 02:01 +0100, Mark Mc wrote: > Hi, I finally got coreboot compiled correctly and I am getting > somewhere as my console output shows: > > coreboot-4.0-4671-g25dd247 Mon Sep 9 23:54:49 BST 2013 starting... > BSP Family_Model: 00100f80 > *sysinfo range: [000c4000,000c5fa0] > bsp_apicid = 00 > cpu_init_detectedx = 00000000 > microcode: rev id not found. Skipping microcode patch! > POST: 0x33 > cpuSetAMDMSR done > POST: 0x34 > Enter amd_ht_init() > AMD_CB_ManualBUIDSwapList() > AMD_CB_EventNotify() > event class: 05 > event: 2006 > data: 04 00 02 ff > Exit amd_ht_init() > POST: 0x35 > cpuSetAMDPCI 00 done > Prep FID/VID Node:00 > F3x80: e600e681 > F3x84: 80e641e6 > F3xD4: c3310f27 > F3xD8: 03000215 > F3xDC: 00006428 > POST: 0x36 > core0 started: > start_other_cores() > init node: 00 cores: 05 > Start other core - nodeid: 00 cores: 05 > POST: 0x37 > started ap apicid: * AP 01started > * AP 02started > * AP 03started > * AP 04started > * AP 05started > > INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} --- > Issuing SOFT_RESET... > > > However it just keeps looping like this, any guidance would be really > appreciated, so far I have tried booting with just 1 dimm (4GB),1 CPU > (opteron 2419) and no PCI-E cards, both stable and master seabios > payloads but so far absolutely no difference. First increase MAX_CPUS in src/mainboard/tyan/2912/Kconfig from 4 to 12. If that alone does not work, try change SERIAL_CPU_INIT=yes in same file. Additionally in menuconfig under consoles, try with SQUELCH_EARLY_SMP=no. Last two changes should not be required, just something to try as they will slow down the boot sequence and give more output on serial console. Remember that after modifying any Kconfig file, you need a clean build: make clean && make oldconfig && make Regards, Kyösti

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Re: [coreboot] Please advise: (new toolkit) crossgcc fails on ubuntu 32/64 bit fresh installs
by Peter Stuge 09 Sep '13

09 Sep '13

David Hubbard wrote: > My locally modified util/crossgcc/Makefile does not do armv7, but instead: > > bash ./buildgcc -j $(shell awk '/^processor/{n=n+1}END{print n+1}' /proc/cpuinfo) -p i386-elf This is great on Linux but unfortunately not portable. > Who is the maintainer of the build system? Nobody really. Everybody generally works wherever and complaints are dealt with (or not) lazily rather than proactively. //Peter

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Re: [coreboot] Please advise: (new toolkit) crossgcc fails on ubuntu 32/64 bit fresh installs
by Peter Stuge 09 Sep '13

09 Sep '13

Andrew Wu wrote: > You can see util/crossgcc/Makefile : > > > all: build > > build: > bash ./buildgcc -G -p i386-elf > bash ./buildgcc -G -p armv7a-eabi IMNSHO this is a stupid problem seriously in need of an intelligent solution. I can not understand the rationale for defaulting to what is clearly NOT the common case; i386 *and* armv7a. This is not the first time that the above has caused problems, I can not understand why this was introduced in the first place (it seems pretty obvious that it will cause problems) and I can not understand why it is *still* there even after multiple problem reports. Is every single developer suffering from total tunnel vision? Come on. //Peter

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Tyan s2912-E reset loop, Please help
by Mark Mc 09 Sep '13

09 Sep '13

Hi, I finally got coreboot compiled correctly and I am getting somewhere as my console output shows: coreboot-4.0-4671-g25dd247 Mon Sep 9 23:54:49 BST 2013 starting... BSP Family_Model: 00100f80 *sysinfo range: [000c4000,000c5fa0] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: rev id not found. Skipping microcode patch! POST: 0x33 cpuSetAMDMSR done POST: 0x34 Enter amd_ht_init() AMD_CB_ManualBUIDSwapList() AMD_CB_EventNotify() event class: 05 event: 2006 data: 04 00 02 ff Exit amd_ht_init() POST: 0x35 cpuSetAMDPCI 00 done Prep FID/VID Node:00 F3x80: e600e681 F3x84: 80e641e6 F3xD4: c3310f27 F3xD8: 03000215 F3xDC: 00006428 POST: 0x36 core0 started: start_other_cores() init node: 00 cores: 05 Start other core - nodeid: 00 cores: 05 POST: 0x37 started ap apicid: * AP 01started * AP 02started * AP 03started * AP 04started * AP 05started POST: 0x38 Begin FIDVID MSR 0xc0010071 0x38a400c4 0x38044c40 POST: 0x39 FIDVID on BSP, APIC_id: 00 BSP fid = 0 Wait for AP stage 1: ap_apicid = 1 readback = 1000001 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 2 readback = 2000001 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 3 readback = 3000001 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 4 readback = 4000001 common_fid(packed) = 0 Wait for AP stage 1: ap_apicid = 5 readback = 5000001 common_fid(packed) = 0 common_fid = 0 POST: 0x3a End FIDVIDMSR 0xc0010071 0x38a400c4 0x38044c40 mcp55_num:01 POST: 0x30 INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} --- Issuing SOFT_RESET... However it just keeps looping like this, any guidance would be really appreciated, so far I have tried booting with just 1 dimm (4GB),1 CPU (opteron 2419) and no PCI-E cards, both stable and master seabios payloads but so far absolutely no difference. Cheers Mark

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Re: [coreboot] Please advise: (new toolkit) crossgcc fails on ubuntu 32/64 bit fresh installs
by Mark Mc 09 Sep '13

09 Sep '13

Hi, Removing armv7 target fromthe util/crossgcc/Makefile removed so much output from the crossgcc-build.log that the actual problem became obvious I was missing g++, so now crossgcc compiles, cheers for the help guys

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Re: [coreboot] Please advise: (new toolkit) crossgcc fails on ubuntu 32/64 bit fresh installs
by Andrew Wu 09 Sep '13

09 Sep '13

Hi, You can see util/crossgcc/Makefile : all: build build: bash ./buildgcc -G -p i386-elf bash ./buildgcc -G -p armv7a-eabi .PHONY: build-without-gdb build-without-gdb: bash ./buildgcc -p i386-elf bash ./buildgcc -p armv7a-eabi clean: rm -rf xgcc .PHONY: all build clean So, I think you only need to run "bash ./buildgcc -G -p i386-elf" to build crossgcc for i386 only. 2013/9/8 Mark Mc <markymcd13(a)gmail.com>: > Unfortunately it wont compile the rom without crossgcc compiling for both > platforms, my crossgcc-build.log ends with and appears to have no other > failures than: > > cc1: fatal error: .vis: No such file or directory > compilation terminated. > make[5]: *** [libunwind.o] Error 1 > make[4]: *** [multi-do] Error 1 > make[3]: *** [all-multi] Error 2 > make[2]: *** [all-target-libgcc] Error 2 > /usr/bin/install: cannot stat ‘libgcc.a’: No such file or directory > make[3]: *** [install-leaf] Error 1 > make[2]: *** [install-target-libgcc] Error 2 > > Is there any way to exclude crossgcc for compiling for armv7? > > ---------- Forwarded message ---------- > From: Andrew Wu <andrewwu.tw(a)gmail.com> > Date: Sun, Sep 8, 2013 at 6:56 AM > Subject: Re: [coreboot] Please advise: (new toolkit) crossgcc fails on > ubuntu 32/64 bit fresh installs > To: Mark Mc <markymcd13(a)gmail.com> > > > Hi, > > I remember that crossgcc will output error log into file > util/crossgcc/build-gcc/crossgcc-build.log , you can check it first. > > Also it seems crossgcc for i386-elf target is already successfully > built, only armv7 is failed. If you don't need to build ARM target, I > think you can ignore it. > > 2013/9/8 Mark Mc <markymcd13(a)gmail.com>: >> Hi, just checking if anyone has any experience with this problem, my >> output >> is: >> >> :~/coreboot$ make crossgcc >> Warning: no suitable GCC for armv7. >> Welcome to the coreboot cross toolchain builder v1.22 (July 9th, 2013) >> >> Target arch is now i386-elf >> Will skip GDB ... ok >> Downloading tar balls ... >> * gmp-5.1.2.tar.bz2 (downloading) >> * mpfr-3.1.2.tar.bz2 (downloading) >> * mpc-1.0.1.tar.gz (downloading) >> * libelf-0.8.13.tar.gz (downloading) >> * gcc-4.8.1.tar.bz2 (downloading) >> * binutils-2.23.2.tar.bz2 (downloading) >> * acpica-unix-20130626.tar.gz (downloading) >> Downloaded tar balls ... ok >> Unpacking and patching ... >> * gmp-5.1.2.tar.bz2 >> * mpfr-3.1.2.tar.bz2 >> * mpc-1.0.1.tar.gz >> * libelf-0.8.13.tar.gz >> * gcc-4.8.1.tar.bz2 >> * binutils-2.23.2.tar.bz2 >> o binutils-2.23.2_armv7a.patch >> o binutils-2.23.2_no-bfd-doc.patch >> * acpica-unix-20130626.tar.gz >> Unpacked and patched ... ok >> Building GMP 5.1.2 ... ok >> Building MPFR 3.1.2 ... ok >> Building MPC 1.0.1 ... ok >> Building libelf 0.8.13 ... ok >> Building binutils 2.23.2 ... ok >> Building GCC 4.8.1 ... ok >> Skipping Expat (Python scripting not enabled) >> Skipping Python (Python scripting not enabled) >> Skipping GDB (GDB support not enabled) >> Building IASL 20130626 ... ok >> Cleaning up... ok >> >> You can now run your i386-elf cross toolchain from >> /home/mark/coreboot/util/crossgcc/xgcc. >> Welcome to the coreboot cross toolchain builder v1.22 (July 9th, 2013) >> >> Target arch is now armv7a-eabi >> Will skip GDB ... ok >> Downloading tar balls ... >> * gmp-5.1.2.tar.bz2 (cached) >> * mpfr-3.1.2.tar.bz2 (cached) >> * mpc-1.0.1.tar.gz (cached) >> * libelf-0.8.13.tar.gz (cached) >> * gcc-4.8.1.tar.bz2 (cached) >> * binutils-2.23.2.tar.bz2 (cached) >> * acpica-unix-20130626.tar.gz (cached) >> Downloaded tar balls ... ok >> Unpacking and patching ... >> * gmp-5.1.2.tar.bz2 >> * mpfr-3.1.2.tar.bz2 >> * mpc-1.0.1.tar.gz >> * libelf-0.8.13.tar.gz >> * gcc-4.8.1.tar.bz2 >> * binutils-2.23.2.tar.bz2 >> o binutils-2.23.2_armv7a.patch >> o binutils-2.23.2_no-bfd-doc.patch >> * acpica-unix-20130626.tar.gz >> Unpacked and patched ... ok >> Building GMP 5.1.2 ... ok >> Building MPFR 3.1.2 ... ok >> Building MPC 1.0.1 ... ok >> Building libelf 0.8.13 ... ok >> Building binutils 2.23.2 ... ok >> Building GCC 4.8.1 ... failed >> make[1]: *** [build-without-gdb] Error 1 >> make: *** [crossgcc] Error 2 >> >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot

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coreboot September 2013