coreboot August 2013

coreboot@coreboot.org

29 participants
54 discussions

Re: [coreboot] No VGA output on e350m1 after flashing. what to do?
by Reiner Luett 12 Sep '17

12 Sep '17

Hi! On 30.06.2013 19:28, Christian Weinz wrote: > Maybe I didn't include the VGA option in the make menuconfig process. > How can I solve this problem? You need to add the VGA Option ROM (VGA BIOS -> Add VGA BIOS image). I've extracted it from the UEFI, but you also could use these: http://www.coreboot.org/index.php?title=ASRock_E350M1&oldid=11114 at the end of the page or you also may be able to use the default AMD fam14 (Persimmon) vbios. You will need to agree to the click … [View More]

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#95: Run coreboot in VirtualBox
by coreboot 10 Dec '14

10 Dec '14

#95: Run coreboot in VirtualBox ---------------------------------+------------------------------------------ Reporter: uwe | Owner: somebody Type: defect | Status: new Priority: minor | Milestone: Component: misc | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+---------------… [View More]

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EHCI debug port finder
by Carl-Daniel Hailfinger 30 May '14

30 May '14

I wanted to know which physical port of my multiple USB controllers have the debug capability. There was no way to find that easily, so I created a tool which will do most of the work for the user. Example output: The following PCI devices support a USB debug port (says lspci): 0000:00:1d.7 The following PCI devices support a USB debug port (says the kernel): 0000:00:1d.7 PCI device 0000:00:1d.7, USB bus 3, USB physical port 1 Currently connected high-speed devices: /: Bus 03.Port 1: Dev 1, … [View More]

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Dual SPI Flash adapter attempt 2.0
by Oliver Schinagl 09 Mar '14

09 Mar '14

Hi list(s), Here's my second attempt at routing the previously mailed png of my schema. It was a lot trickier to route then my previous version, but I think it worked out! As mentioned, S1 and S2 need to be shorted if U3 is to be omitted. RN1 should be 10k or ideally 100k, as Peter mentioned earlier. Hopefully there's no obvious mistakes and can start working on alternative layouts (so it is insert-able in different angles). DRC Check fails on S1, S2 and U3. It thinks the distance is to … [View More]

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fixed AMD SPI speed settings (leading to problems on E350M1/USB3)
by Stefan Tauner 02 Feb '14

02 Feb '14

Hi, andor reported a problem where flashrom does reproducibly not work with coreboot but does with the vendor BIOS http://paste.flashrom.org/view.php?id=1614 Apparently it is related to fast reads and/or the frequency. We have forced the fastReadEnable bit in the SPI_Cntrl0 from 1 to 0 and also set NormSpeed in SPI_Cntrl1 to 16.5 Mhz (previously was 0 i.e. 66 MHz) in flashrom and the problem vanished. Coreboot hard codes the fast read setting in src/southbridge/amd/cimx/sb800/bootblock.c: … [View More]

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#186: 3com 3c905tx / gpxe boot problem
by coreboot 11 Jan '14

11 Jan '14

#186: 3com 3c905tx / gpxe boot problem -----------------------------------+---------------------------------- Reporter: jeroenkrabbendam@… | Owner: stepan@… Type: defect | Status: new Priority: minor | Milestone: Component: coreboot | Keywords: gpxe Dependencies: | Patch Status: there is no patch -----------------------------------+---------------------------------- Although (or: … [View More]

1 1

#191: Coreboot:libpayload-size_t conflicting types compiler error
by coreboot 05 Nov '13

05 Nov '13

#191: Coreboot:libpayload-size_t conflicting types compiler error ---------------------------+---------------------------------- Reporter: Pradish | Owner: uwe@… Type: defect | Status: new Priority: blocker | Milestone: Component: libpayload | Keywords: Dependencies: | Patch Status: there is no patch ---------------------------+---------------------------------- Hi I have question related to libpayload, which I am … [View More]

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tyan s8226 status
by Nick Lewycky 03 Sep '13

03 Sep '13

What's the status of the Tyan s8226? There's a src/mainboard/tyan/s8226 directory in git coreboot, but no entry for s8226 under "board status pages". Does this mean that it's unsupported? Or conversely, is it known to work? Nick

1 1

Problem in building coreboot + FILO for ASI_MB-5BLMP
by michele.montani＠libero.it 30 Aug '13

30 Aug '13

Hi, I'm trying to make live again an old thin client based on ASI_MB-5BLMP motherboard. The original BIOS is blocked and I can't use it as is, so I thought to use coreboot and FILO, following the instructions found in "How to build". I retrived an old pc, installed Lubuntu and all packets listed in coreboot instructions: gcc / g++, make, ncurses-dev (when installed, a note from apt-get said that was selected libncurses5-dev), doxygen, iasl, gdb, flex and bison, used git for coreboot and … [View More]

2 1

Change vga bios timing
by Piero 30 Aug '13

30 Aug '13

Hi all, After some search on internet and on the coreboot wiki and forum, I decided to buy the E350m1 Asrock motherboard that seems to be full supported from coreboot community. But I'd like to modify the bios and/or the vgabios to use with an old CGA/EGA monitors that work with an HSYNC at (about) 15kHz despite the VGA at 31kHz. I found some interesting project on internet (1 free and 1 commercial), i.e. : http://tinyurl.com/r6n4l where the author has modified the Award 4.51pg bios to … [View More]

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coreboot August 2013