coreboot May 2013

coreboot@coreboot.org

38 participants
91 discussions

Re: [coreboot] Trying to get coreboot running on VIA EPIA-M (lzma: Decoding error = 1)
by ron minnich 20 May '13

20 May '13

if you ever see an lzma issue turn off payload compression. It's a quick easy test to see if there is something else going on -- like, bad memory configuration, which is always an issue with these boards. ron

1 0

Re: [coreboot] Trying to get coreboot running on VIA EPIA-M (lzma: Decoding error = 1)
by Patrick Georgi 20 May '13

20 May '13

Am 20.05.2013 17:16, schrieb Marius Schäfer: > Can you give me a hint please? > Thank you. That problem looks like the one solved by 33e83caff59f7b6ff2ba62d3b496235ef5c4e543 from 2013-04-08. Since I can't figure out the revision you used for this build, please check that this is in. If that's not the issue (ie. your tree contains this change), please tell us more about your config, in particular the coreboot revision and the payload you used. Regards, Patrick

2 1

Trying to get coreboot running on VIA EPIA-M (lzma: Decoding error = 1)
by Marius Schäfer 20 May '13

20 May '13

Hello, I just want to play around with coreboot on my old VIA EPIA-M, as it should be supportet and a good place to start. I just followed the Build HOWTO. But I always end up with 'lzma: Decoding error = 1'. I clonded coreboot from git, in menuconfig I choose the VIA EPIA-M board and built everything Thats what I get on the serial console when I try to boot it: Enabling mainboard devices Enabling shadow ram vt8623 init starting Detecting Memory Number of Banks 04 Number of Rows 0d Priamry DRAM width08 No Columns 0a MA type e0 Bank 0 (*16 Mb) 10 No Physical Banks 02 Total Memory (*16 Mb) 20 CAS Supported 2 2.5 3 Cycle time at CL X (nS)50 Cycle time at CL X-0.5 (nS)60 Cycle time at CL X-1 (nS)75 Starting at CAS 3 We can do CAS 2.5 We can do CAS 2 tRP 3c tRCD 3c tRAS 28 Low Bond 00 High Bondb7 Setting DQS delay7avt8623 done 00:06 11 23 31 06 00 30 22 00 00 00 06 00 00 00 00 10:08 00 00 d0 00 00 00 00 00 00 00 00 00 00 00 00 20:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30:00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 40:00 18 88 80 82 44 00 00 18 99 88 80 82 44 00 00 50:c8 de cf 88 e0 07 00 00 e0 00 10 20 20 20 00 00 60:02 ff 00 30 52 32 01 38 42 2d 43 58 84 55 00 00 70:82 48 00 01 01 08 50 00 01 00 00 00 00 00 00 02 80:0f 61 00 00 80 00 00 00 02 00 00 00 00 00 00 00 90:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0:02 c0 20 00 07 02 00 1f 04 00 00 00 2f 02 04 00 b0:00 00 00 00 c0 00 00 00 a8 00 00 00 00 00 00 00 c0:01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0:00 dd 00 01 00 00 01 00 40 00 00 00 00 00 00 00 f0:00 00 00 00 00 00 03 13 00 00 00 00 00 00 00 00 AGP coreboot-4.0-4169-g963bed5 Mon May 20 16:36:02 CEST 2013 booting... clocks_per_usec: 601 Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:10.1: enabled 1 PCI: 00:10.2: enabled 1 PCI: 00:10.3: enabled 1 PCI: 00:11.0: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.b: enabled 1 PCI: 00:11.1: enabled 1 PCI: 00:11.5: enabled 1 PCI: 00:11.6: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:0a.0: enabled 1 PCI: 00:0a.1: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:10.1: enabled 1 PCI: 00:10.2: enabled 1 PCI: 00:10.3: enabled 1 PCI: 00:11.0: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.b: enabled 1 PCI: 00:11.1: enabled 1 PCI: 00:11.5: enabled 1 PCI: 00:11.6: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:0a.0: enabled 1 PCI: 00:0a.1: enabled 1 scan_static_bus for Root Device In vt8623 enable_dev for device CPU_CLUSTER: 0. CPU_CLUSTER: 0 enabled In vt8623 enable_dev for device DOMAIN: 0000. DOMAIN: 0000 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 In vt8623 enable_dev for device PCI: 00:00.0. PCI: 00:00.0 [1106/3123] ops PCI: 00:00.0 [1106/3123] enabled In vt8623 enable_dev for device PCI: 00:01.0. PCI: 00:01.0 [1106/b091] bus ops PCI: 00:01.0 [1106/b091] enabled PCI: Static device PCI: 00:0a.0 not found, disabling it. PCI: Static device PCI: 00:0a.1 not found, disabling it. PCI: 00:0d.0 [1106/3044] enabled In vt8235_enable 1106 3038. PCI: 00:10.0 [1106/3038] ops PCI: 00:10.0 [1106/3038] enabled In vt8235_enable 1106 3038. PCI: 00:10.1 [1106/3038] ops PCI: 00:10.1 [1106/3038] enabled In vt8235_enable 1106 3038. PCI: 00:10.2 [1106/3038] ops PCI: 00:10.2 [1106/3038] enabled In vt8235_enable ffff ffff. PCI: Static device PCI: 00:10.3 not found, disabling it. In vt8235_enable 1106 3177. Initialising Devices Keyboard init... Keyboard controller output buffer result timeout PCI: 00:11.0 [1106/3177] bus ops PCI: 00:11.0 [1106/3177] enabled In vt8235_enable 1106 0571. PCI: 00:11.1 [1106/0571] ops PCI: 00:11.1 [1106/0571] enabled In vt8235_enable 1106 3059. PCI: 00:11.5 [1106/3059] enabled In vt8235_enable 1106 3068. PCI: 00:11.6 [1106/3068] disabled In vt8235_enable 1106 3065. PCI: 00:12.0 [1106/3065] ops PCI: 00:12.0 [1106/3065] enabled do_pci_scan_bridge for PCI: 00:01.0 PCI: pci_scan_bus for bus 01 PCI: 01:00.0 [1106/3122] ops PCI: 01:00.0 [1106/3122] enabled PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 scan_static_bus for PCI: 00:11.0 PNP: 002e.0 enabled PNP: 002e.1 enabled PNP: 002e.2 enabled PNP: 002e.3 enabled PNP: 002e.b enabled PNP: 002e.6 enabled PNP: 002e.7 enabled PNP: 002e.8 enabled PNP: 002e.9 enabled PNP: 002e.a enabled PNP: 002e.c enabled PNP: 002e.d enabled scan_static_bus for PCI: 00:11.0 done PCI: pci_scan_bus returning with max=001 scan_static_bus for Root Device done done found VGA at PCI: 01:00.0 Setting up VGA for PCI: 01:00.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources CPU_CLUSTER: 0 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:11.0 read_resources bus 0 link: 0 PCI: 00:11.0 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:01.0 child on link 0 PCI: 01:00.0 PCI: 01:00.0 PCI: 01:00.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 1200 index 10 PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 14 PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI: 00:0a.0 PCI: 00:0a.1 PCI: 00:0d.0 PCI: 00:0d.0 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 10 PCI: 00:0d.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 14 PCI: 00:10.0 PCI: 00:10.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:10.1 PCI: 00:10.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:10.2 PCI: 00:10.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:10.3 PCI: 00:11.0 child on link 0 PNP: 002e.0 PCI: 00:11.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 PCI: 00:11.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.1 PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.1 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.2 PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.b PNP: 002e.b resource base ec00 size 100 align 8 gran 8 limit ffff flags c0000100 index 60 PNP: 002e.b resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.6 PNP: 002e.6 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 60 PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.7 PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 60 PNP: 002e.8 PNP: 002e.8 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 60 PNP: 002e.8 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.9 PNP: 002e.9 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 60 PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.a PNP: 002e.a resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 60 PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.c PNP: 002e.c resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 60 PNP: 002e.c resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.c resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.d PCI: 00:11.1 PCI: 00:11.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:11.5 PCI: 00:11.5 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10 PCI: 00:11.6 PCI: 00:12.0 PCI: 00:12.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10 PCI: 00:12.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 14 DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:11.5 10 * [0x0 - 0xff] io PCI: 00:12.0 10 * [0x400 - 0x4ff] io PCI: 00:0d.0 14 * [0x800 - 0x87f] io PCI: 00:10.0 20 * [0x880 - 0x89f] io PCI: 00:10.1 20 * [0x8a0 - 0x8bf] io PCI: 00:10.2 20 * [0x8c0 - 0x8df] io PCI: 00:11.1 20 * [0x8e0 - 0x8ef] io DOMAIN: 0000 compute_resources_io: base: 8f0 size: 8f0 align: 8 gran: 0 limit: ffff done DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:0d.0 10 * [0x0 - 0x7ff] mem PCI: 00:12.0 14 * [0x800 - 0x8ff] mem DOMAIN: 0000 compute_resources_mem: base: 900 size: 900 align: 11 gran: 0 limit: ffffffff done avoid_fixed_resources: DOMAIN: 0000 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff constrain_resources: DOMAIN: 0000 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:01.0 constrain_resources: PCI: 01:00.0 constrain_resources: PCI: 00:0d.0 constrain_resources: PCI: 00:10.0 constrain_resources: PCI: 00:10.1 constrain_resources: PCI: 00:10.2 constrain_resources: PCI: 00:11.0 constrain_resources: PNP: 002e.0 constrain_resources: PNP: 002e.1 constrain_resources: PNP: 002e.2 constrain_resources: PNP: 002e.3 constrain_resources: PNP: 002e.b constrain_resources: PNP: 002e.6 constrain_resources: PNP: 002e.7 constrain_resources: PNP: 002e.8 constrain_resources: PNP: 002e.9 constrain_resources: PNP: 002e.a constrain_resources: PNP: 002e.c constrain_resources: PNP: 002e.d constrain_resources: PCI: 00:11.1 constrain_resources: PCI: 00:11.5 constrain_resources: PCI: 00:12.0 avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff lim->base 00001000 lim->limit 0000ebff avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff lim->base 00000000 lim->limit febfffff Setting resources... DOMAIN: 0000 allocate_resources_io: base:1000 size:8f0 align:8 gran:0 limit:ebff Assigned: PCI: 00:11.5 10 * [0x1000 - 0x10ff] io Assigned: PCI: 00:12.0 10 * [0x1400 - 0x14ff] io Assigned: PCI: 00:0d.0 14 * [0x1800 - 0x187f] io Assigned: PCI: 00:10.0 20 * [0x1880 - 0x189f] io Assigned: PCI: 00:10.1 20 * [0x18a0 - 0x18bf] io Assigned: PCI: 00:10.2 20 * [0x18c0 - 0x18df] io Assigned: PCI: 00:11.1 20 * [0x18e0 - 0x18ef] io DOMAIN: 0000 allocate_resources_io: next_base: 18f0 size: 8f0 align: 8 gran: 0 done DOMAIN: 0000 allocate_resources_mem: base:febff000 size:900 align:11 gran:0 limit:febfffff Assigned: PCI: 00:0d.0 10 * [0xfebff000 - 0xfebff7ff] mem Assigned: PCI: 00:12.0 14 * [0xfebff800 - 0xfebff8ff] mem DOMAIN: 0000 allocate_resources_mem: next_base: febff900 size: 900 align: 11 gran: 0 done Root Device assign_resources, bus 0 link: 0 Entering vt8623 pci_domain_set_resources. I would set ram size to 0x80000 Kbytes tom: 1e000000, high_tables_base: 1dfe0000, high_tables_size: 20000 DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:0d.0 10 <- [0x00febff000 - 0x00febff7ff] size 0x00000800 gran 0x0b mem PCI: 00:0d.0 14 <- [0x0000001800 - 0x000000187f] size 0x00000080 gran 0x07 io PCI: 00:10.0 20 <- [0x0000001880 - 0x000000189f] size 0x00000020 gran 0x05 io PCI: 00:10.1 20 <- [0x00000018a0 - 0x00000018bf] size 0x00000020 gran 0x05 io PCI: 00:10.2 20 <- [0x00000018c0 - 0x00000018df] size 0x00000020 gran 0x05 io PCI: 00:11.0 assign_resources, bus 0 link: 0 PNP: 002e.0 60 <- [0x00000003f0 - 0x00000003f7] size 0x00000008 gran 0x03 io PNP: 002e.0 70 <- [0x0000000006 - 0x0000000006] size 0x00000001 gran 0x00 irq PNP: 002e.0 74 <- [0x0000000002 - 0x0000000002] size 0x00000001 gran 0x00 drq PNP: 002e.1 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io PNP: 002e.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq PNP: 002e.1 74 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 drq PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq PNP: 002e.b 60 <- [0x000000ec00 - 0x000000ecff] size 0x00000100 gran 0x08 io ERROR: PNP: 002e.b 70 irq size: 0x0000000001 not assigned ERROR: PNP: 002e.6 60 io size: 0x0000000004 not assigned ERROR: PNP: 002e.6 70 irq size: 0x0000000001 not assigned ERROR: PNP: 002e.7 60 io size: 0x0000000008 not assigned ERROR: PNP: 002e.8 60 io size: 0x0000000010 not assigned ERROR: PNP: 002e.8 70 irq size: 0x0000000001 not assigned ERROR: PNP: 002e.9 60 io size: 0x0000000010 not assigned ERROR: PNP: 002e.9 70 irq size: 0x0000000001 not assigned ERROR: PNP: 002e.a 60 io size: 0x0000000010 not assigned ERROR: PNP: 002e.a 70 irq size: 0x0000000001 not assigned ERROR: PNP: 002e.c 60 io size: 0x0000000100 not assigned ERROR: PNP: 002e.c 70 irq size: 0x0000000001 not assigned ERROR: PNP: 002e.c 74 drq size: 0x0000000001 not assigned PCI: 00:11.0 assign_resources, bus 0 link: 0 PCI: 00:11.1 20 <- [0x00000018e0 - 0x00000018ef] size 0x00000010 gran 0x04 io PCI: 00:11.5 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 00:12.0 10 <- [0x0000001400 - 0x00000014ff] size 0x00000100 gran 0x08 io PCI: 00:12.0 14 <- [0x00febff800 - 0x00febff8ff] size 0x00000100 gran 0x08 mem DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 1000 size 8f0 align 8 gran 0 limit ebff flags 40040100 index 10000000 DOMAIN: 0000 resource base febff000 size 900 align 11 gran 0 limit febfffff flags 40040200 index 10000100 DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a DOMAIN: 0000 resource base c0000 size 1df40000 align 0 gran 0 limit 0 flags e0004200 index b PCI: 00:00.0 PCI: 00:01.0 child on link 0 PCI: 01:00.0 PCI: 01:00.0 PCI: 01:00.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 1200 index 10 PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 14 PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI: 00:0a.0 PCI: 00:0a.1 PCI: 00:0d.0 PCI: 00:0d.0 resource base febff000 size 800 align 11 gran 11 limit febfffff flags 60000200 index 10 PCI: 00:0d.0 resource base 1800 size 80 align 7 gran 7 limit ebff flags 60000100 index 14 PCI: 00:10.0 PCI: 00:10.0 resource base 1880 size 20 align 5 gran 5 limit ebff flags 60000100 index 20 PCI: 00:10.1 PCI: 00:10.1 resource base 18a0 size 20 align 5 gran 5 limit ebff flags 60000100 index 20 PCI: 00:10.2 PCI: 00:10.2 resource base 18c0 size 20 align 5 gran 5 limit ebff flags 60000100 index 20 PCI: 00:10.3 PCI: 00:11.0 child on link 0 PNP: 002e.0 PCI: 00:11.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 PCI: 00:11.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags e0000800 index 74 PNP: 002e.1 PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.1 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000800 index 74 PNP: 002e.2 PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.b PNP: 002e.b resource base ec00 size 100 align 8 gran 8 limit ffff flags e0000100 index 60 PNP: 002e.b resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.6 PNP: 002e.6 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 60 PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.7 PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 60 PNP: 002e.8 PNP: 002e.8 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 60 PNP: 002e.8 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.9 PNP: 002e.9 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 60 PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.a PNP: 002e.a resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 60 PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.c PNP: 002e.c resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 60 PNP: 002e.c resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.c resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.d PCI: 00:11.1 PCI: 00:11.1 resource base 18e0 size 10 align 4 gran 4 limit ebff flags 60000100 index 20 PCI: 00:11.5 PCI: 00:11.5 resource base 1000 size 100 align 8 gran 8 limit ebff flags 60000100 index 10 PCI: 00:11.6 PCI: 00:12.0 PCI: 00:12.0 resource base 1400 size 100 align 8 gran 8 limit ebff flags 60000100 index 10 PCI: 00:12.0 resource base febff800 size 100 align 8 gran 8 limit febfffff flags 60000200 index 14 Done allocating resources. Enabling resources... PCI: 00:00.0 cmd <- 06 PCI: 00:01.0 bridge ctrl <- 000f PCI: 00:01.0 cmd <- 07 PCI: 00:0d.0 cmd <- 83 PCI: 00:10.0 cmd <- 01 PCI: 00:10.1 cmd <- 01 PCI: 00:10.2 cmd <- 01 PCI: 00:11.0 cmd <- 07 PCI: 00:11.1 cmd <- 81 PCI: 00:11.5 subsystem <- 0000/0000 PCI: 00:11.5 cmd <- 01 PCI: 00:12.0 cmd <- 83 PCI: 01:00.0 cmd <- 03 PNP: 002e.0 - enabling PNP: 002e.1 - enabling PNP: 002e.2 - enabling PNP: 002e.3 - enabling PNP: 002e.b - enabling PNP: 002e.6 - enabling PNP: 002e.7 - enabling PNP: 002e.8 - enabling PNP: 002e.9 - enabling PNP: 002e.a - enabling PNP: 002e.c - enabling PNP: 002e.d - enabling done. Initializing devices... Root Device init CPU_CLUSTER: 0 init Initializing CPU #0 CPU: vendor Centaur device 673 CPU: family 06, model 07, stepping 03 Using generic cpu ops (good) Enabling cache MTRR: Physical address space: 0x0000000000000000 - 0x0000000004000000 size 0x04000000 type 0 0x0000000004000000 - 0x000000001e000000 size 0x1a000000 type 6 0x000000001e000000 - 0x0000000100000000 size 0xe2000000 type 0 MTRR: Fixed MSR 0x250 0x0000000000000000 MTRR: Fixed MSR 0x258 0x0000000000000000 MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0000000000000000 MTRR: Fixed MSR 0x269 0x0000000000000000 MTRR: Fixed MSR 0x26a 0x0000000000000000 MTRR: Fixed MSR 0x26b 0x0000000000000000 MTRR: Fixed MSR 0x26c 0x0000000000000000 MTRR: Fixed MSR 0x26d 0x0000000000000000 MTRR: Fixed MSR 0x26e 0x0000000000000000 MTRR: Fixed MSR 0x26f 0x0000000000000000 call enable_fixed_mtrr() CPU physical address size: 32 bits MTRR: default type WB/UC MTRR counts: 5/4. MTRR: UC selected as default type. MTRR: 0 base 0x0000000004000000 mask 0x00000000fc000000 type 6 MTRR: 1 base 0x0000000008000000 mask 0x00000000f8000000 type 6 MTRR: 2 base 0x0000000010000000 mask 0x00000000f0000000 type 6 MTRR: 3 base 0x000000001e000000 mask 0x00000000fe000000 type 0 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Disabling local apic...done. CPU #0 initialized PCI: 00:00.0 init VT8623 random fixup ... Frame buffer at d0000000 PCI: 00:01.0 init VT8623 AGP random fixup ... PCI: 00:0d.0 init PCI: 00:10.0 init Configuring VIA USB 1.1 PCI: 00:10.1 init Configuring VIA USB 1.1 PCI: 00:10.2 init Configuring VIA USB 1.1 PCI: 00:11.0 init vt8235 init RTC Init pci_routing_fixup: dev is 0011753c setting firewire Assigning IRQ 9 to 0:d.0 i8259_configure_irq_trigger: current interrupts are 0x0 i8259_configure_irq_trigger: try to set interrupts 0x200 setting usb Assigning IRQ 5 to 0:10.0 i8259_configure_irq_trigger: current interrupts are 0x200 i8259_configure_irq_trigger: try to set interrupts 0x220 Assigning IRQ 9 to 0:10.1 i8259_configure_irq_trigger: current interrupts are 0x220 i8259_configure_irq_trigger: try to set interrupts 0x220 Assigning IRQ 9 to 0:10.2 i8259_configure_irq_trigger: current interrupts are 0x220 i8259_configure_irq_trigger: try to set interrupts 0x220 Assigning IRQ 5 to 0:10.3 i8259_configure_irq_trigger: current interrupts are 0x220 i8259_configure_irq_trigger: try to set interrupts 0x220 setting vt8235 Assigning IRQ 5 to 0:11.1 i8259_configure_irq_trigger: current interrupts are 0x220 i8259_configure_irq_trigger: try to set interrupts 0x220 Assigning IRQ 9 to 0:11.5 i8259_configure_irq_trigger: current interrupts are 0x220 i8259_configure_irq_trigger: try to set interrupts 0x220 Assigning IRQ 9 to 0:11.6 i8259_configure_irq_trigger: current interrupts are 0x220 i8259_configure_irq_trigger: try to set interrupts 0x220 setting ethernet Assigning IRQ 5 to 0:12.0 i8259_configure_irq_trigger: current interrupts are 0x220 i8259_configure_irq_trigger: try to set interrupts 0x220 setting vga Assigning IRQ 5 to 1:0.0 i8259_configure_irq_trigger: current interrupts are 0x220 i8259_configure_irq_trigger: try to set interrupts 0x220 setting pci slot setting cardbus slot setting riser slot pci_routing_fixup: DONE PCI: 00:11.1 init Enabling VIA IDE. ide_init: enabling compatibility IDE addresses enables in reg 0x42 0x9 enables in reg 0x42 read back as 0x9 enables in reg 0x40 0x8 enables in reg 0x40 read back as 0xb enables in reg 0x9 0x8a enables in reg 0x9 read back as 0x8a command in reg 0x4 0x81 command in reg 0x4 reads back as 0x7 PCI: 00:11.5 init PCI: 00:12.0 init Configuring VIA Rhine LAN PCI: 01:00.0 init VGA random fixup ... Initializing VGA... Enable VGA console PNP: 002e.0 init PNP: 002e.1 init PNP: 002e.2 init VT1211: Cannot init unknown device! PNP: 002e.3 init VT1211: Cannot init unknown device! PNP: 002e.b init PNP: 002e.6 init PNP: 002e.7 init PNP: 002e.8 init PNP: 002e.9 init PNP: 002e.a init PNP: 002e.c init PNP: 002e.d init Devices initialized Show all devs...After init. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:10.1: enabled 1 PCI: 00:10.2: enabled 1 PCI: 00:10.3: enabled 0 PCI: 00:11.0: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.b: enabled 1 PCI: 00:11.1: enabled 1 PCI: 00:11.5: enabled 1 PCI: 00:11.6: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:0a.0: enabled 0 PCI: 00:0a.1: enabled 0 PCI: 00:0d.0: enabled 1 PCI: 01:00.0: enabled 1 PNP: 002e.6: enabled 1 PNP: 002e.7: enabled 1 PNP: 002e.8: enabled 1 PNP: 002e.9: enabled 1 PNP: 002e.a: enabled 1 PNP: 002e.c: enabled 1 PNP: 002e.d: enabled 1 CPU: 00: enabled 1 Re-Initializing CBMEM area to 0x1dfe0000 Initializing CBMEM area to 0x1dfe0000 (131072 bytes) Adding CBMEM entry as no. 1 Moving GDT to 1dfe0200...ok High Tables Base is 1dfe0000. Copying Interrupt Routing Table to 0x000f0000... done. Adding CBMEM entry as no. 2 Copying Interrupt Routing Table to 0x1dfe0400... done. PIRQ table: 112 bytes. Adding CBMEM entry as no. 3 ACPI: Writing ACPI tables at 1dfe1400... ACPI: * FACS ACPI: * DSDT @ 1dfe1508 Length 3f0 ACPI: * FADT ACPI: added table 1/32, length now 40 ACPI: done. ACPI tables: 1516 bytes. Adding CBMEM entry as no. 4 smbios_write_tables: 1dfec800 Root Device (VIA EPIA-M) CPU_CLUSTER: 0 (VIA VT8623 Northbridge) APIC: 00 (unknown) DOMAIN: 0000 (VIA VT8623 Northbridge) PCI: 00:00.0 (VIA VT8623 Northbridge) PCI: 00:01.0 (VIA VT8623 Northbridge) PCI: 00:10.0 (VIA VT8235 Southbridge) PCI: 00:10.1 (VIA VT8235 Southbridge) PCI: 00:10.2 (VIA VT8235 Southbridge) PCI: 00:10.3 (VIA VT8235 Southbridge) PCI: 00:11.0 (VIA VT8235 Southbridge) PNP: 002e.0 (VIA VT1211 Super I/O) PNP: 002e.1 (VIA VT1211 Super I/O) PNP: 002e.2 (VIA VT1211 Super I/O) PNP: 002e.3 (VIA VT1211 Super I/O) PNP: 002e.b (VIA VT1211 Super I/O) PCI: 00:11.1 (VIA VT8235 Southbridge) PCI: 00:11.5 (VIA VT8235 Southbridge) PCI: 00:11.6 (VIA VT8235 Southbridge) PCI: 00:12.0 (VIA VT8235 Southbridge) PCI: 00:0a.0 (Ricoh RL5C476 CardBus Controller) PCI: 00:0a.1 (Ricoh RL5C476 CardBus Controller) PCI: 00:0d.0 (unknown) PCI: 01:00.0 (unknown) PNP: 002e.6 (unknown) PNP: 002e.7 (unknown) PNP: 002e.8 (unknown) PNP: 002e.9 (unknown) PNP: 002e.a (unknown) PNP: 002e.c (unknown) PNP: 002e.d (unknown) CPU: 00 (unknown) SMBIOS tables: 262 bytes. Adding CBMEM entry as no. 5 Writing table forward entry at 0x00000500 Wrote coreboot table at: 00000500, 0x10 bytes, checksum 11e0 Table forward entry ends at 0x00000528. ... aligned to 0x00001000 Writing coreboot table at 0x1dfed000 rom_table_end = 0x1dfed000 ... aligned to 0x1dff0000 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-000000001dfdffff: RAM 3. 000000001dfe0000-000000001dffffff: CONFIGURATION TABLES Wrote coreboot table at: 1dfed000, 0x1b0 bytes, checksum a601 coreboot table: 456 bytes. Multiboot Information structure has been written. FREE SPACE 0. 1dff5000 0000b000 GDT 1. 1dfe0200 00000200 IRQ TABLE 2. 1dfe0400 00001000 ACPI 3. 1dfe1400 0000b400 SMBIOS 4. 1dfec800 00000800 COREBOOT 5. 1dfed000 00008000 Loading segment from rom address 0xfffd89b8 code (compression=1) New segment dstaddr 0xe6b30 memsize 0x194d0 srcaddr 0xfffd89f0 filesize 0xcc88 (cleaned up) New segment addr 0xe6b30 size 0x194d0 offset 0xfffd89f0 filesize 0xcc88 Loading segment from rom address 0xfffd89d4 Entry Point 0x000fc7a8 Loading Segment: addr: 0x00000000000e6b30 memsz: 0x00000000000194d0 filesz: 0x000000000000cc88 lb: [0x0000000000100000, 0x0000000000122048) Post relocation: addr: 0x00000000000e6b30 memsz: 0x00000000000194d0 filesz: 0x000000000000cc88 using LZMA lzma: Decoding error = 1 Could not load payload Can you give me a hint please? Thank you. Marius

1 0

Where to put configuration of USB debug port (was: [PATCH] intel/bd82x6x: Add Kconfig options for USB debug port)
by Paul Menzel 15 May '13

15 May '13

Dear coreboot folks, today several devices have more than just one USB debug port, so it makes sense to be able to configure it. Patch »intel/bd82x6x: Add Kconfig options for USB debug port« [1] implements that for Intel BD82x6x. I guess this could be made available to all boards right away. So suggestions where to put these Kconfig variables are very much appreciated. Thanks, Paul [1] http://review.coreboot.org/3240

1 0

Re: [coreboot] [flashrom] About flashing mx25l4005 on Itona TC2331
by Bin X 15 May '13

15 May '13

Thanks for the reply. I will do some homework on the coreboot. However I think my chanllenge here is to find a program (I don't have hardware programmer) to flash the chip. I run flashrom.exe -p internal -c MX25L4005(A/C) -VVV and here is what I gotflashrom v0.9.6.1-r1671 on MS-DOS 7 (i686)flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.5, GCC 4.4.4, little endianCommand line (5 args): c:/bios/flashrom.exe -p internal -c MX25L4005(A/C) -VVVCalibrating delay loop... OS timer resolution is 110000 usecs, 298M loops per second, delay more than 10% too short (got 84% of expected delay), recalculating... 347M loops per second, 10 myus = 0 us, 100 myus = 0 us, 1000 myus = 0 us, 10000 myus = 0 us, 440000 myus = 440000 us, OK.Initializing internal programmerNo coreboot table found.DMI string system-manufacturer: ""DMI string system-product-name: ""DMI string system-version: ""DMI string baseboard-manufacturer: ""DMI string baseboard-product-name: ""DMI string baseboard-version: ""DMI string chassis-type: ""DMI chassis-type is not specific enough.Found ITE Super I/O, ID 0x8712 on port 0x2eBad Command or file nameBad Command or file nameBad Command or file nameBad Command or file nameBad Command or file nameBad Command or file name I am not sure which part is wrong. Is it because I don't have a full dos enviroment? Thanks, > Date: Tue, 14 May 2013 22:05:06 +0200 > From: vidwer(a)gmail.com > To: z2333(a)outlook.com > CC: flashrom(a)flashrom.org; coreboot(a)coreboot.org > Subject: Re: [flashrom] About flashing mx25l4005 on Itona TC2331 > > 2013/5/14 Bin X <z2333(a)outlook.com>: > > I apologize if it does not make sense at all since this is my first attempt > > to flash a bios with unmatched bios ID. > > > > I was trying to flash bios on a Itona TC2331 to get rid of the limitation > > they put on of any IDE HDD and USB HDD can’t be larger than 64mb. > > coreboot can do that, but you have to spend 'some' time on adding > support for your particular mainboard. > > See http://b2b.gigabyte.com/products/product-page.aspx?pid=3215#sp > ("Chipset VIA CN700 chipset with VIA VT8237R Plus") and > http://www.coreboot.org/Supported_Chipsets_and_Devices > > > > > The current bios rom, flash program and documentation can be found here: > > > > ftp://ftpguest:letmein@ftp.vxl.net/../Utilities/BIOS/TC23YY/ > > > > Since I don’t have any working rom so I am hoping to use the file from this > > board > > > > http://b2b.gigabyte.com/products/product-page.aspx?pid=3215#dl > > > > Because they are from the same vendor and used the same chipset. I > > understand it may not work at all but decide to take the risk. > > > > However, I can’t find any program to flash the bios that can ignore the bios > > ID. The vendor provided one can flash the bios but does not have the option > > to ignore the unmatched bios ID. Flashrom failed at probing the chipset. > > > > The building Q-Flash tells that it is MX25L4005 which should be supported by > > Flashrom. I also tried “internal:laptop=this_is_not_a_laptop” and still no > > success. > > It's very good that you found that programmer parameter. However, the > Gigabyte product picture shows that this (non-VXL) board uses LPC > flash instead of SPI. > > What we're interested in is what flashrom's output looks like when > there is - your words - no success. Does its output end with many > times "<hexadecimal value>:S"? > > > > > So I am not sure what else I should try to make Flashrom work. > > > > Any suggestions? > > > > Thanks, > > > > > > _______________________________________________ > > flashrom mailing list > > flashrom(a)flashrom.org > > http://www.flashrom.org/mailman/listinfo/flashrom > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom

1 0

Re: [coreboot] [flashrom] About flashing mx25l4005 on Itona TC2331
by Idwer Vollering 14 May '13

14 May '13

2013/5/14 Bin X <z2333(a)outlook.com>: > I apologize if it does not make sense at all since this is my first attempt > to flash a bios with unmatched bios ID. > > I was trying to flash bios on a Itona TC2331 to get rid of the limitation > they put on of any IDE HDD and USB HDD can’t be larger than 64mb. coreboot can do that, but you have to spend 'some' time on adding support for your particular mainboard. See http://b2b.gigabyte.com/products/product-page.aspx?pid=3215#sp ("Chipset VIA CN700 chipset with VIA VT8237R Plus") and http://www.coreboot.org/Supported_Chipsets_and_Devices > > The current bios rom, flash program and documentation can be found here: > > ftp://ftpguest:letmein@ftp.vxl.net/../Utilities/BIOS/TC23YY/ > > Since I don’t have any working rom so I am hoping to use the file from this > board > > http://b2b.gigabyte.com/products/product-page.aspx?pid=3215#dl > > Because they are from the same vendor and used the same chipset. I > understand it may not work at all but decide to take the risk. > > However, I can’t find any program to flash the bios that can ignore the bios > ID. The vendor provided one can flash the bios but does not have the option > to ignore the unmatched bios ID. Flashrom failed at probing the chipset. > > The building Q-Flash tells that it is MX25L4005 which should be supported by > Flashrom. I also tried “internal:laptop=this_is_not_a_laptop” and still no > success. It's very good that you found that programmer parameter. However, the Gigabyte product picture shows that this (non-VXL) board uses LPC flash instead of SPI. What we're interested in is what flashrom's output looks like when there is - your words - no success. Does its output end with many times "<hexadecimal value>:S"? > > So I am not sure what else I should try to make Flashrom work. > > Any suggestions? > > Thanks, > > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom

1 0

Use the constant TSC for AMD Family 10h–15h processors?
by Paul Menzel 14 May '13

14 May '13

Dear coreboot folks, do you know if the timer mentioned in the BIOS and Kernel Developer’s Guide (BKGD) for the AMD Family 14h processors [1] 2.11.4 BIOS Timer The root complex implements a 32-bit microsecond timer (see D0F0xE4_x0130_80F0 and D0F0xE4_x0130_80F1) that the BIOS can use to accurately time wait operations between initialization steps. To ensure that BIOS waits a minimum number of microseconds between steps BIOS should always wait for one microsecond more than the required minimum wait time. could be used for implementing `tsc_freq_mhz()` as done for Intel Haswell processors? The Wikipedia article for Time Stamp Counter (TSC) claims that since AMD family 10h processors a constant TSC is integrated [2]. Indeed, checking the processor flags under GNU/Linux, the flag `tsc_constant` is present. $ grep -i tsc /proc/cpuinfo flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc nonstop_tsc extd_apicid aperfmperf pni monitor ssse3 cx16 popcnt lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch ibs skinit wdt arat hw_pstate npt lbrv svm_lock nrip_save pausefilter flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc nonstop_tsc extd_apicid aperfmperf pni monitor ssse3 cx16 popcnt lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch ibs skinit wdt arat hw_pstate npt lbrv svm_lock nrip_save pausefilter Suggestions, if this should be shared and how the files should be named are appreciated. Thanks, Paul [1] http://review.coreboot.org/3169 [2] http://www.coreboot.org/Datasheets#AMD_Fam14 [3] http://en.wikipedia.org/wiki/Time_Stamp_Counter#Implementation_in_various_p…

2 4

Re: [coreboot] coreboot on a Toshiba A100-151 laptop?
by Peter Stuge 13 May '13

13 May '13

Hi Daniel, d-fischer(a)gmx-topmail.de wrote: > unsure if coreboot could work on my machine under real conditions > after flashing. Always assume no. With the right background and some months of development the answer can become yes. > avoid making mistakes You don't have much choice; either become a coreboot developer, or hire a coreboot developer to work for you, or give up the idea of using coreboot on your machine. > or to brick my laptop at the end. If you want to become a developer you'll brick your laptop many times during development, so one thing you need to sort out fairly early is how you will unbrick your laptop. You will typically need to do some soldering in the machine, and you'll need a suitable flash programmer. > I hope to meet here some friendly persons who are willing to help. coreboot folks may be friendly, but it's completely infeasible for anyone else to port coreboot to your machine for you. Adding a new system, even when components are supported like in your case, requires time-intensive work and moderately advanced electronics debugging equipment. (A 33MHz-capable programmable logic analyzer, or experience with programmable logic development in order to hack something.) > In view of the fact, that my model hasn't been supported yet by > coreboot I would like to provide all needed information You'll have to provide a patch, not just information. Nobody else can create a port for you. > thank you for your commitment concerning this great open source project You're welcome. > ambition to use open source software. I would appreciate your support > so that coreboot might natively run on my system. I'm afraid that seems unlikely. :\ //Peter

1 0

AMD AGESA: How to access an indexed register?
by Paul Menzel 13 May '13

13 May '13

Dear coreboot folks, to read the value of the BIOS Timer (section 2.11.4 of the BIOS and Kernel Developer’s Guide (BKDG) for the AMD Family 14 processors [1]), I am stuck at how to do that. Below is the register description from the BKDG. D0F0xE4_x0130_80F0 BIOS Timer ----------------------------- Reset: 0000_0000h. ----------------------------- Bits 31:0 Description MicroSeconds. Read-write; updated-by hardware. This field increments once every microsecond when the timer is enabled. The counter rolls over and continues counting when it reaches FFFF_FFFFh. A write to this register causes the counter to reset and begin counting from the value written. I could not find any wrapper(?) function in the non-vendor code for that. In the vendor code directory `src/vendorcode/amd/agesa/f14/`, I found only `PcieRegisterRead`, which looks “hard” to access from outside. $ git grep -i iocf8 $ git grep -i d0f0xe4 src/vendorcode/amd/agesa/f14 Any pointers to code already dealing with such indexed registers or instructions how to do that would help me very much. Thanks, Paul [1] http://www.coreboot.org/Datasheets#AMD_Fam14 BKDG 43170 Rev 3.13 – February 17, 2012

2 1

coreboot on a Toshiba A100-151 laptop?
by d-fischer＠gmx-topmail.de 13 May '13

13 May '13

Dear coreboot folks, I admire the coreboot project because it's a fast and up-to-date open source alternative to the proprietary bios crap provided by many vendors. For this reason I am thinking about using coreboot on my Toshiba A100-151 laptop system since it is not supported anymore by Toshiba and even they discontinued to provide all the old drivers for this model in the support section on their homepage (Thank you, you customer-unfriendly profiteers!). How ridiculous that this company has received the German environmental label "Blue Angel" for some of their products in the past (just a little side note). And even with their locked and constricted Firmware updates I feel somehow as if I should be artificially hindered to use the full potentials of hardware features of my laptop. Just to mention some examples: - I cannot use the AHCI mode of the SATA controller although the mainboard should be able to switch to this mode. There is no option in the bios and it's always locked to IDE mode. Therefore, the performance of my new SSD is artificially limited to a low level. - Even Toshiba showes on their homepage that 4GB RAM memory are supported by the mainboard, I could only use 3GB at maximum, even after installing diverse 64bit OS such as Ubuntu Linux 12.04 and Windows 7. I guess that some of the missing 1GB RAM will be addressed to the OS and to my ATI video graphic card in particular, although it was shipped with 128MB of dedicated RAM. But again there is no option in the bios settings to manage the VGA Shared Memory. - Few time ago, I couldn't enable the Intel VT feature of my CPU. However, I found a workaround by flashing a modded custom bios from another forum which enabled some great features. But unfortunately, there is still no ahci support :-( In short, after reading a lot of tutorials in the internet and trying different solutions in Linux and Windows OS (e.g. using registry modifications, pre-boot parameters in grub2 mainly with the command "setpci" as well as trying a MBR mod at the end), I wasn't successful to enable ahci mode and I recognized in general that the bios restrictions by Toshiba obviously represent the biggest problem. But now to coreboot: So far, I made some first experimental steps by testing coreboot in a qemu environment. At least, in qemu I succeeded! The documentation on the coreboot homepage was of great help. However, I am still unsure if coreboot could work on my machine under real conditions after flashing. And because of my very limmited technical knowledge, I would appreciate some help and advices very much in order to avoid making mistakes or to brick my laptop at the end. Therefore, I hope to meet here some friendly persons who are willing to help. In view of the fact, that my model hasn't been supported yet by coreboot I would like to provide all needed information I could get in the following part (with my personal comments marked by "###“): ------ A very brief description of my system: board vendor: Toshiba board name: Satellite A100-151 ### please, don't get confused because later you will also see the product name "Satellite M110". This is due to the modded bios with advanced features which I have flashed. The right name is "Satellite A100-151". CPU: Intel Core2Duo T7200 ### I have upgraded the CPU. Maybe following output from "dmidecode" could be usefull as well: Handle 0x0004, DMI type 4, 35 bytes Processor Information Socket Designation: U2E1 Type: Central Processor Family: Other Manufacturer: Intel ID: F6 06 00 00 FF FB EB BF Signature: Type 0, Family 6, Model 15, Stepping 6 Flags: FPU (Floating-point unit on-chip) VME (Virtual mode extension) DE (Debugging extension) PSE (Page size extension) TSC (Time stamp counter) MSR (Model specific registers) PAE (Physical address extension) MCE (Machine check exception) CX8 (CMPXCHG8 instruction supported) APIC (On-chip APIC hardware supported) SEP (Fast system call) MTRR (Memory type range registers) PGE (Page global enable) MCA (Machine check architecture) CMOV (Conditional move instruction supported) PAT (Page attribute table) PSE-36 (36-bit page size extension) CLFSH (CLFLUSH instruction supported) DS (Debug store) ACPI (ACPI supported) MMX (MMX technology supported) FXSR (FXSAVE and FXSTOR instructions supported) SSE (Streaming SIMD extensions) SSE2 (Streaming SIMD extensions 2) SS (Self-snoop) HTT (Multi-threading) TM (Thermal monitor supported) PBE (Pending break enabled) Version: Intel(R) Core(TM)2 CPU T7200 Voltage: 3.3 V External Clock: Unknown Max Speed: 2048 MHz Current Speed: 2000 MHz Status: Populated, Enabled Upgrade: ZIF Socket L1 Cache Handle: 0x0005 L2 Cache Handle: 0x0006 L3 Cache Handle: Not Provided Serial Number: Not Specified Asset Tag: Not Specified Part Number: Not Specified northbridge: 8086:27a0 (i945GM) ### Here is some further information extraced by using the program "PC Wizard 2012" in Windows. However, I am not sure if this will be usefull. Furthermore, this application reports "Intel i945PM" as northbridge in contrast to the Linux output. Codename : Calistoga Revision : Stepping : A3 Bus Speed : .24 M FSB Frequenz : MHz (QDR) FSB max. Support : MHz RAM max. Support : DDR2 (667) southbridge: SouthBridge : 8086:27b9 (ICH7-M) ### Here is what the Windows program "PC Wizard 2012" reports: GBM (ICH7-M/U) LPC Interface Controller Revision : ------ output of "lspci -tvnn" -[0000:00]-+-00.0 Intel Corporation Mobile 945GM/PM/GMS, 943/940GML and 945GT Express Memory Controller Hub [8086:27a0] +-01.0-[01]----00.0 Advanced Micro Devices [AMD] nee ATI M56P [Radeon Mobility X1600] [1002:71c5] +-1b.0 Intel Corporation N10/ICH 7 Family High Definition Audio Controller [8086:27d8] +-1c.0-[02]-- +-1c.1-[03-04]-- +-1c.2-[05-06]----00.0 Intel Corporation PRO/Wireless 3945ABG [Golan] Network Connection [8086:4222] +-1d.0 Intel Corporation N10/ICH 7 Family USB UHCI Controller #1 [8086:27c8] +-1d.1 Intel Corporation N10/ICH 7 Family USB UHCI Controller #2 [8086:27c9] +-1d.2 Intel Corporation N10/ICH 7 Family USB UHCI Controller #3 [8086:27ca] +-1d.3 Intel Corporation N10/ICH 7 Family USB UHCI Controller #4 [8086:27cb] +-1d.7 Intel Corporation N10/ICH 7 Family USB2 EHCI Controller [8086:27cc] +-1e.0-[07-0b]--+-06.0 Texas Instruments PCIxx12 Cardbus Controller [104c:8039] | +-06.1 Texas Instruments PCIxx12 OHCI Compliant IEEE 1394 Host Controller [104c:803a] | +-06.2 Texas Instruments 5-in-1 Multimedia Card Reader (SD/MMC/MS/MS PRO/xD) [104c:803b] | +-06.3 Texas Instruments PCIxx12 SDA Standard Compliant SD Host Controller [104c:803c] | \-08.0 Intel Corporation PRO/100 VE Network Connection [8086:1092] +-1f.0 Intel Corporation 82801GBM (ICH7-M) LPC Interface Bridge [8086:27b9] +-1f.2 Intel Corporation 82801GBM/GHM (ICH7-M Family) SATA Controller [IDE mode] [8086:27c4] \-1f.3 Intel Corporation N10/ICH 7 Family SMBus Controller [8086:27da] ------ output of "superiotool -dV" superiotool r6637 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0x3503, rev=0x0 Probing for ITE Super I/O (init=it8502e) at 0x2e... Failed. Returned data: id=0x3503, rev=0x0 Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0x3503, rev=0x0 Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0x3503, rev=0x0 Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0x3503, rev=0x0 Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x164e... Failed. Returned data: port=0xff, port+1=0xff Probing for Nuvoton Super I/O at 0x164e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x164e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for Nuvoton Super I/O at 0x2e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x2e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for Nuvoton Super I/O at 0x4e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x4e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0x35, rev=0x03 Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0x00, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for VIA Super I/O at 0x3f0... PCI device 1106:0686 not found. Probing for Server Engines Super I/O at 0x2e... Failed. Returned data: id=0xffff, rev=0xff No Super I/O found ### The Windows program "HWiNFO64" also showes that the Super-IO/LPC Chip is unknown. ------ output of "ectool" EC RAM: : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 : 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 : 00 00 08 1b 00 00 00 00 00 0a 02 00 23 00 7f 68 a0: 00 00 01 07 00 00 03 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 c0: 00 62 67 2d 41 00 00 00 ff 03 00 41 01 00 00 36 d0: 00 00 00 00 00 00 00 00 01 06 00 00 31 00 00 00 e0: 7e 00 00 00 00 00 1e 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Not dumping EC IDX RAM. ### Concerning the Embedded Controller (EC) I could get some little information by the Windows tool "Rw version 1.6" which might be usefull for an advanced technician. According to the information it's an EC6662. ------ output of "flashrom -V" flashrom v0.9.5.2-r1517 on Linux 3.7.0-7-generic (x86_64), built with libpci 3.1.8, GCC 4.6.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1989M loops per second, 10 myus = 10 us, 100 myus = 101 us, 1000 myus = 998 us, 10000 myus = 10162 us, 4 myus = 6 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "TOSHIBA" DMI string system-product-name: "Satellite M110" DMI string system-version: "PSMB0U-1234567" DMI string baseboard-manufacturer: "Intel Corporation" DMI string baseboard-product-name: "CAPELL VALLEY(NAPA) CRB" DMI string baseboard-version: "Not Applicable" DMI string chassis-type: "Other" DMI chassis-type is not specific enough. ### I add here some part of the output from "dmidecode" as well with extracted information only about relevant bios parameters. By "dmidecode" I could figure out that ROM Size is only 1024 kB: Handle 0x0000, DMI type 0, 24 bytes BIOS Information Vendor: Phoenix Technologies LTD Version: 6.00 Release Date: 07/12/2007 Address: 0xE4480 Runtime Size: 113536 bytes ROM Size: 1024 kB Characteristics: ISA is supported PCI is supported PC Card (PCMCIA) is supported PNP is supported APM is supported BIOS is upgradeable BIOS shadowing is allowed ESCD support is available Boot from CD is supported ACPI is supported USB legacy is supported AGP is supported BIOS boot specification is supported Targeted content distribution is supported ------ URL to the mainboard specifications page: http://www.toshiba.de/discontinued-products/satellite-a100-151/?PRODUCT_ID=… ### Unfortunately, I could only find this German website. But I have access to the manual. However, it does not provide much additional information which would be usefull here. ------ Any other relevant information: As I have mentioned before, I have upgraded my system including a new CPU (Intel Core2Duo T7200), more RAM (2 x 2GB, identical and from the same vendor) and a SSD. Furthermore I have flashed a modded custom bios which has enabled some more features and seems to work perfectly untill now. However, after the bios mod the model name has been changed. To end with, I would like to say thank you for your commitment concerning this great open source projet and especially for reading my long message! As I explained I am still a beginner, comming from a completely different working field, but having some ambition to use open source software. I would appreciate your support so that coreboot might natively run on my system. -- With best regards, Daniel

1 0

← Newer
1
2
3
4
5
6
7
8
9
10
Older →

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot May 2013