if you ever see an lzma issue turn off payload compression. It's a
quick easy test to see if there is something else going on -- like,
bad memory configuration, which is always an issue with these boards.
ron
Am 20.05.2013 17:16, schrieb Marius Schäfer:
> Can you give me a hint please?
> Thank you.
That problem looks like the one solved by
33e83caff59f7b6ff2ba62d3b496235ef5c4e543 from 2013-04-08.
Since I can't figure out the revision you used for this build, please
check that this is in.
If that's not the issue (ie. your tree contains this change), please
tell us more about your config, in particular the coreboot revision and
the payload you used.
Regards,
Patrick
Dear coreboot folks,
today several devices have more than just one USB debug port, so it
makes sense to be able to configure it. Patch »intel/bd82x6x: Add
Kconfig options for USB debug port« [1] implements that for Intel
BD82x6x. I guess this could be made available to all boards right away.
So suggestions where to put these Kconfig variables are very much
appreciated.
Thanks,
Paul
[1] http://review.coreboot.org/3240
Thanks for the reply. I will do some homework on the coreboot.
However I think my chanllenge here is to find a program (I don't have hardware programmer) to flash the chip. I run flashrom.exe -p internal -c MX25L4005(A/C) -VVV
and here is what I gotflashrom v0.9.6.1-r1671 on MS-DOS 7 (i686)flashrom is free software, get the source code at http://www.flashrom.org
flashrom was built with libpci 3.1.5, GCC 4.4.4, little endianCommand line (5 args): c:/bios/flashrom.exe -p internal -c MX25L4005(A/C) -VVVCalibrating delay loop... OS timer resolution is 110000 usecs, 298M loops per second, delay more than 10% too short (got 84% of expected delay), recalculating... 347M loops per second, 10 myus = 0 us, 100 myus = 0 us, 1000 myus = 0 us, 10000 myus = 0 us, 440000 myus = 440000 us, OK.Initializing internal programmerNo coreboot table found.DMI string system-manufacturer: ""DMI string system-product-name: ""DMI string system-version: ""DMI string baseboard-manufacturer: ""DMI string baseboard-product-name: ""DMI string baseboard-version: ""DMI string chassis-type: ""DMI chassis-type is not specific enough.Found ITE Super I/O, ID 0x8712 on port 0x2eBad Command or file nameBad Command or file nameBad Command or file nameBad Command or file nameBad Command or file nameBad Command or file name
I am not sure which part is wrong. Is it because I don't have a full dos enviroment?
Thanks,
> Date: Tue, 14 May 2013 22:05:06 +0200
> From: vidwer(a)gmail.com
> To: z2333(a)outlook.com
> CC: flashrom(a)flashrom.org; coreboot(a)coreboot.org
> Subject: Re: [flashrom] About flashing mx25l4005 on Itona TC2331
>
> 2013/5/14 Bin X <z2333(a)outlook.com>:
> > I apologize if it does not make sense at all since this is my first attempt
> > to flash a bios with unmatched bios ID.
> >
> > I was trying to flash bios on a Itona TC2331 to get rid of the limitation
> > they put on of any IDE HDD and USB HDD can’t be larger than 64mb.
>
> coreboot can do that, but you have to spend 'some' time on adding
> support for your particular mainboard.
>
> See http://b2b.gigabyte.com/products/product-page.aspx?pid=3215#sp
> ("Chipset VIA CN700 chipset with VIA VT8237R Plus") and
> http://www.coreboot.org/Supported_Chipsets_and_Devices
>
> >
> > The current bios rom, flash program and documentation can be found here:
> >
> > ftp://ftpguest:letmein@ftp.vxl.net/../Utilities/BIOS/TC23YY/
> >
> > Since I don’t have any working rom so I am hoping to use the file from this
> > board
> >
> > http://b2b.gigabyte.com/products/product-page.aspx?pid=3215#dl
> >
> > Because they are from the same vendor and used the same chipset. I
> > understand it may not work at all but decide to take the risk.
> >
> > However, I can’t find any program to flash the bios that can ignore the bios
> > ID. The vendor provided one can flash the bios but does not have the option
> > to ignore the unmatched bios ID. Flashrom failed at probing the chipset.
> >
> > The building Q-Flash tells that it is MX25L4005 which should be supported by
> > Flashrom. I also tried “internal:laptop=this_is_not_a_laptop” and still no
> > success.
>
> It's very good that you found that programmer parameter. However, the
> Gigabyte product picture shows that this (non-VXL) board uses LPC
> flash instead of SPI.
>
> What we're interested in is what flashrom's output looks like when
> there is - your words - no success. Does its output end with many
> times "<hexadecimal value>:S"?
>
> >
> > So I am not sure what else I should try to make Flashrom work.
> >
> > Any suggestions?
> >
> > Thanks,
> >
> >
> > _______________________________________________
> > flashrom mailing list
> > flashrom(a)flashrom.org
> > http://www.flashrom.org/mailman/listinfo/flashrom
>
> _______________________________________________
> flashrom mailing list
> flashrom(a)flashrom.org
> http://www.flashrom.org/mailman/listinfo/flashrom
2013/5/14 Bin X <z2333(a)outlook.com>:
> I apologize if it does not make sense at all since this is my first attempt
> to flash a bios with unmatched bios ID.
>
> I was trying to flash bios on a Itona TC2331 to get rid of the limitation
> they put on of any IDE HDD and USB HDD can’t be larger than 64mb.
coreboot can do that, but you have to spend 'some' time on adding
support for your particular mainboard.
See http://b2b.gigabyte.com/products/product-page.aspx?pid=3215#sp
("Chipset VIA CN700 chipset with VIA VT8237R Plus") and
http://www.coreboot.org/Supported_Chipsets_and_Devices
>
> The current bios rom, flash program and documentation can be found here:
>
> ftp://ftpguest:letmein@ftp.vxl.net/../Utilities/BIOS/TC23YY/
>
> Since I don’t have any working rom so I am hoping to use the file from this
> board
>
> http://b2b.gigabyte.com/products/product-page.aspx?pid=3215#dl
>
> Because they are from the same vendor and used the same chipset. I
> understand it may not work at all but decide to take the risk.
>
> However, I can’t find any program to flash the bios that can ignore the bios
> ID. The vendor provided one can flash the bios but does not have the option
> to ignore the unmatched bios ID. Flashrom failed at probing the chipset.
>
> The building Q-Flash tells that it is MX25L4005 which should be supported by
> Flashrom. I also tried “internal:laptop=this_is_not_a_laptop” and still no
> success.
It's very good that you found that programmer parameter. However, the
Gigabyte product picture shows that this (non-VXL) board uses LPC
flash instead of SPI.
What we're interested in is what flashrom's output looks like when
there is - your words - no success. Does its output end with many
times "<hexadecimal value>:S"?
>
> So I am not sure what else I should try to make Flashrom work.
>
> Any suggestions?
>
> Thanks,
>
>
> _______________________________________________
> flashrom mailing list
> flashrom(a)flashrom.org
> http://www.flashrom.org/mailman/listinfo/flashrom
Dear coreboot folks,
do you know if the timer mentioned in the BIOS and Kernel Developer’s
Guide (BKGD) for the AMD Family 14h processors [1]
2.11.4 BIOS Timer
The root complex implements a 32-bit microsecond timer (see
D0F0xE4_x0130_80F0 and D0F0xE4_x0130_80F1) that the BIOS can use
to accurately time wait operations between initialization steps.
To ensure that BIOS waits a minimum number of microseconds
between steps BIOS should always wait for one microsecond more
than the required minimum wait time.
could be used for implementing `tsc_freq_mhz()` as done for Intel
Haswell processors?
The Wikipedia article for Time Stamp Counter (TSC) claims that since AMD
family 10h processors a constant TSC is integrated [2]. Indeed, checking
the processor flags under GNU/Linux, the flag `tsc_constant` is present.
$ grep -i tsc /proc/cpuinfo
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc nonstop_tsc extd_apicid aperfmperf pni monitor ssse3 cx16 popcnt lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch ibs skinit wdt arat hw_pstate npt lbrv svm_lock nrip_save pausefilter
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc nonstop_tsc extd_apicid aperfmperf pni monitor ssse3 cx16 popcnt lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch ibs skinit wdt arat hw_pstate npt lbrv svm_lock nrip_save pausefilter
Suggestions, if this should be shared and how the files should be named
are appreciated.
Thanks,
Paul
[1] http://review.coreboot.org/3169
[2] http://www.coreboot.org/Datasheets#AMD_Fam14
[3] http://en.wikipedia.org/wiki/Time_Stamp_Counter#Implementation_in_various_p…
Hi Daniel,
d-fischer(a)gmx-topmail.de wrote:
> unsure if coreboot could work on my machine under real conditions
> after flashing.
Always assume no. With the right background and some months of
development the answer can become yes.
> avoid making mistakes
You don't have much choice; either become a coreboot developer, or
hire a coreboot developer to work for you, or give up the idea of
using coreboot on your machine.
> or to brick my laptop at the end.
If you want to become a developer you'll brick your laptop many times
during development, so one thing you need to sort out fairly early is
how you will unbrick your laptop. You will typically need to do some
soldering in the machine, and you'll need a suitable flash programmer.
> I hope to meet here some friendly persons who are willing to help.
coreboot folks may be friendly, but it's completely infeasible for
anyone else to port coreboot to your machine for you. Adding a new
system, even when components are supported like in your case,
requires time-intensive work and moderately advanced electronics
debugging equipment. (A 33MHz-capable programmable logic analyzer, or
experience with programmable logic development in order to hack
something.)
> In view of the fact, that my model hasn't been supported yet by
> coreboot I would like to provide all needed information
You'll have to provide a patch, not just information. Nobody else
can create a port for you.
> thank you for your commitment concerning this great open source project
You're welcome.
> ambition to use open source software. I would appreciate your support
> so that coreboot might natively run on my system.
I'm afraid that seems unlikely. :\
//Peter
Dear coreboot folks,
to read the value of the BIOS Timer (section 2.11.4 of the BIOS and
Kernel Developer’s Guide (BKDG) for the AMD Family 14 processors [1]), I
am stuck at how to do that.
Below is the register description from the BKDG.
D0F0xE4_x0130_80F0 BIOS Timer
-----------------------------
Reset: 0000_0000h.
-----------------------------
Bits
31:0
Description
MicroSeconds. Read-write; updated-by hardware. This
field increments once every microsecond when the timer
is enabled. The counter rolls over and continues
counting when it reaches FFFF_FFFFh. A write to this
register causes the counter to reset and begin counting
from the value written.
I could not find any wrapper(?) function in the non-vendor code for
that. In the vendor code directory `src/vendorcode/amd/agesa/f14/`, I
found only `PcieRegisterRead`, which looks “hard” to access from
outside.
$ git grep -i iocf8
$ git grep -i d0f0xe4 src/vendorcode/amd/agesa/f14
Any pointers to code already dealing with such indexed registers or
instructions how to do that would help me very much.
Thanks,
Paul
[1] http://www.coreboot.org/Datasheets#AMD_Fam14
BKDG 43170 Rev 3.13 – February 17, 2012
Dear coreboot folks,
I admire the coreboot project because it's a fast and up-to-date open source alternative to the proprietary bios crap provided by many vendors. For this reason I am thinking about using coreboot on my Toshiba A100-151 laptop system since it is not supported anymore by Toshiba and even they discontinued to provide all the old drivers for this model in the support section on their homepage (Thank you, you customer-unfriendly profiteers!). How ridiculous that this company has received the German environmental label "Blue Angel" for some of their products in the past (just a little side note). And even with their locked and constricted Firmware updates I feel somehow as if I should be artificially hindered to use the full potentials of hardware features of my laptop. Just to mention some examples:
- I cannot use the AHCI mode of the SATA controller although the mainboard should be able to switch to this mode. There is no option in the bios and it's always locked to IDE mode. Therefore, the performance of my new SSD is artificially limited to a low level.
- Even Toshiba showes on their homepage that 4GB RAM memory are supported by the mainboard, I could only use 3GB at maximum, even after installing diverse 64bit OS such as Ubuntu Linux 12.04 and Windows 7. I guess that some of the missing 1GB RAM will be addressed to the OS and to my ATI video graphic card in particular, although it was shipped with 128MB of dedicated RAM. But again there is no option in the bios settings to manage the VGA Shared Memory.
- Few time ago, I couldn't enable the Intel VT feature of my CPU. However, I found a workaround by flashing a modded custom bios from another forum which enabled some great features. But unfortunately, there is still no ahci support :-(
In short, after reading a lot of tutorials in the internet and trying different solutions in Linux and Windows OS (e.g. using registry modifications, pre-boot parameters in grub2 mainly with the command "setpci" as well as trying a MBR mod at the end), I wasn't successful to enable ahci mode and I recognized in general that the bios restrictions by Toshiba obviously represent the biggest problem.
But now to coreboot: So far, I made some first experimental steps by testing coreboot in a qemu environment. At least, in qemu I succeeded! The documentation on the coreboot homepage was of great help.
However, I am still unsure if coreboot could work on my machine under real conditions after flashing. And because of my very limmited technical knowledge, I would appreciate some help and advices very much in order to avoid making mistakes or to brick my laptop at the end. Therefore, I hope to meet here some friendly persons who are willing to help.
In view of the fact, that my model hasn't been supported yet by coreboot I would like to provide all needed information I could get in the following part (with my personal comments marked by "###“):
------ A very brief description of my system:
board vendor: Toshiba
board name: Satellite A100-151
### please, don't get confused because later you will also see the product name "Satellite M110". This is due to the modded bios with advanced features which I have flashed. The right name is "Satellite A100-151".
CPU: Intel Core2Duo T7200
### I have upgraded the CPU. Maybe following output from "dmidecode" could be usefull as well:
Handle 0x0004, DMI type 4, 35 bytes
Processor Information
Socket Designation: U2E1
Type: Central Processor
Family: Other
Manufacturer: Intel
ID: F6 06 00 00 FF FB EB BF
Signature: Type 0, Family 6, Model 15, Stepping 6
Flags:
FPU (Floating-point unit on-chip)
VME (Virtual mode extension)
DE (Debugging extension)
PSE (Page size extension)
TSC (Time stamp counter)
MSR (Model specific registers)
PAE (Physical address extension)
MCE (Machine check exception)
CX8 (CMPXCHG8 instruction supported)
APIC (On-chip APIC hardware supported)
SEP (Fast system call)
MTRR (Memory type range registers)
PGE (Page global enable)
MCA (Machine check architecture)
CMOV (Conditional move instruction supported)
PAT (Page attribute table)
PSE-36 (36-bit page size extension)
CLFSH (CLFLUSH instruction supported)
DS (Debug store)
ACPI (ACPI supported)
MMX (MMX technology supported)
FXSR (FXSAVE and FXSTOR instructions supported)
SSE (Streaming SIMD extensions)
SSE2 (Streaming SIMD extensions 2)
SS (Self-snoop)
HTT (Multi-threading)
TM (Thermal monitor supported)
PBE (Pending break enabled)
Version: Intel(R) Core(TM)2 CPU T7200
Voltage: 3.3 V
External Clock: Unknown
Max Speed: 2048 MHz
Current Speed: 2000 MHz
Status: Populated, Enabled
Upgrade: ZIF Socket
L1 Cache Handle: 0x0005
L2 Cache Handle: 0x0006
L3 Cache Handle: Not Provided
Serial Number: Not Specified
Asset Tag: Not Specified
Part Number: Not Specified
northbridge: 8086:27a0 (i945GM)
### Here is some further information extraced by using the program "PC Wizard 2012" in Windows. However, I am not sure if this will be usefull. Furthermore, this application reports "Intel i945PM" as northbridge in contrast to the Linux output.
Codename : Calistoga Revision : Stepping : A3
Bus Speed : .24 M
FSB Frequenz : MHz (QDR)
FSB max. Support : MHz RAM max. Support : DDR2 (667)
southbridge: SouthBridge : 8086:27b9 (ICH7-M)
### Here is what the Windows program "PC Wizard 2012" reports:
GBM (ICH7-M/U) LPC Interface Controller
Revision :
------ output of "lspci -tvnn"
-[0000:00]-+-00.0 Intel Corporation Mobile 945GM/PM/GMS, 943/940GML and 945GT Express Memory Controller Hub [8086:27a0]
+-01.0-[01]----00.0 Advanced Micro Devices [AMD] nee ATI M56P [Radeon Mobility X1600] [1002:71c5]
+-1b.0 Intel Corporation N10/ICH 7 Family High Definition Audio Controller [8086:27d8]
+-1c.0-[02]--
+-1c.1-[03-04]--
+-1c.2-[05-06]----00.0 Intel Corporation PRO/Wireless 3945ABG [Golan] Network Connection [8086:4222]
+-1d.0 Intel Corporation N10/ICH 7 Family USB UHCI Controller #1 [8086:27c8]
+-1d.1 Intel Corporation N10/ICH 7 Family USB UHCI Controller #2 [8086:27c9]
+-1d.2 Intel Corporation N10/ICH 7 Family USB UHCI Controller #3 [8086:27ca]
+-1d.3 Intel Corporation N10/ICH 7 Family USB UHCI Controller #4 [8086:27cb]
+-1d.7 Intel Corporation N10/ICH 7 Family USB2 EHCI Controller [8086:27cc]
+-1e.0-[07-0b]--+-06.0 Texas Instruments PCIxx12 Cardbus Controller [104c:8039]
| +-06.1 Texas Instruments PCIxx12 OHCI Compliant IEEE 1394 Host Controller [104c:803a]
| +-06.2 Texas Instruments 5-in-1 Multimedia Card Reader (SD/MMC/MS/MS PRO/xD) [104c:803b]
| +-06.3 Texas Instruments PCIxx12 SDA Standard Compliant SD Host Controller [104c:803c]
| \-08.0 Intel Corporation PRO/100 VE Network Connection [8086:1092]
+-1f.0 Intel Corporation 82801GBM (ICH7-M) LPC Interface Bridge [8086:27b9]
+-1f.2 Intel Corporation 82801GBM/GHM (ICH7-M Family) SATA Controller [IDE mode] [8086:27c4]
\-1f.3 Intel Corporation N10/ICH 7 Family SMBus Controller [8086:27da]
------ output of "superiotool -dV"
superiotool r6637
Probing for ALi Super I/O at 0x3f0...
Failed. Returned data: id=0xffff, rev=0xff
Probing for ALi Super I/O at 0x370...
Failed. Returned data: id=0xffff, rev=0xff
Probing for Fintek Super I/O at 0x2e...
Failed. Returned data: vid=0xffff, id=0xffff
Probing for Fintek Super I/O at 0x4e...
Failed. Returned data: vid=0xffff, id=0xffff
Probing for Fintek Super I/O at 0x2e...
Failed. Returned data: vid=0xffff, id=0xffff
Probing for Fintek Super I/O at 0x4e...
Failed. Returned data: vid=0xffff, id=0xffff
Probing for ITE Super I/O (init=standard) at 0x25e...
Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8502e) at 0x25e...
Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8761e) at 0x25e...
Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8228e) at 0x25e...
Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x87) at 0x25e...
Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=standard) at 0x2e...
Failed. Returned data: id=0x3503, rev=0x0
Probing for ITE Super I/O (init=it8502e) at 0x2e...
Failed. Returned data: id=0x3503, rev=0x0
Probing for ITE Super I/O (init=it8761e) at 0x2e...
Failed. Returned data: id=0x3503, rev=0x0
Probing for ITE Super I/O (init=it8228e) at 0x2e...
Failed. Returned data: id=0x3503, rev=0x0
Probing for ITE Super I/O (init=0x87,0x87) at 0x2e...
Failed. Returned data: id=0x3503, rev=0x0
Probing for ITE Super I/O (init=standard) at 0x4e...
Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8502e) at 0x4e...
Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8761e) at 0x4e...
Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8228e) at 0x4e...
Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x87) at 0x4e...
Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=legacy/it8661f) at 0x370...
Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=legacy/it8671f) at 0x370...
Failed. Returned data: id=0xffff, rev=0xf
Probing for NSC Super I/O at 0x2e...
Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x4e...
Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x15c...
Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x164e...
Failed. Returned data: port=0xff, port+1=0xff
Probing for Nuvoton Super I/O at 0x164e...
Failed. Returned data: chip_id=0xffff
Probing for Nuvoton Super I/O (sid=0xfc) at 0x164e...
Failed. Returned data: sid=0xff, id=0xffff, rev=0x00
Probing for Nuvoton Super I/O at 0x2e...
Failed. Returned data: chip_id=0xffff
Probing for Nuvoton Super I/O (sid=0xfc) at 0x2e...
Failed. Returned data: sid=0xff, id=0xffff, rev=0x00
Probing for Nuvoton Super I/O at 0x4e...
Failed. Returned data: chip_id=0xffff
Probing for Nuvoton Super I/O (sid=0xfc) at 0x4e...
Failed. Returned data: sid=0xff, id=0xffff, rev=0x00
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e...
Failed. Returned data: id=0x35, rev=0x03
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e...
Failed. Returned data: id=0x00, rev=0x00
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e...
Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e...
Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e...
Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e...
Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e...
Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e...
Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0...
Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0...
Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370...
Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370...
Failed. Returned data: id=0xff, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x2e...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x2e...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x4e...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x4e...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x3f0...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x3f0...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x370...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x370...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x370...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x370...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x250...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x250...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x250...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x250...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for VIA Super I/O at 0x3f0...
PCI device 1106:0686 not found.
Probing for Server Engines Super I/O at 0x2e...
Failed. Returned data: id=0xffff, rev=0xff
No Super I/O found
### The Windows program "HWiNFO64" also showes that the Super-IO/LPC Chip is unknown.
------ output of "ectool"
EC RAM:
: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
: 00 00 08 1b 00 00 00 00 00 0a 02 00 23 00 7f 68
a0: 00 00 01 07 00 00 03 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00
c0: 00 62 67 2d 41 00 00 00 ff 03 00 41 01 00 00 36
d0: 00 00 00 00 00 00 00 00 01 06 00 00 31 00 00 00
e0: 7e 00 00 00 00 00 1e 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Not dumping EC IDX RAM.
### Concerning the Embedded Controller (EC) I could get some little information by the Windows tool "Rw version 1.6" which might be usefull for an advanced technician. According to the information it's an EC6662.
------ output of "flashrom -V"
flashrom v0.9.5.2-r1517 on Linux 3.7.0-7-generic (x86_64), built with libpci 3.1.8, GCC 4.6.3, little endian
flashrom is free software, get the source code at http://www.flashrom.org
Calibrating delay loop... OS timer resolution is 1 usecs, 1989M loops per second, 10 myus = 10 us, 100 myus = 101 us, 1000 myus = 998 us, 10000 myus = 10162 us, 4 myus = 6 us, OK.
Initializing internal programmer
No coreboot table found.
DMI string system-manufacturer: "TOSHIBA"
DMI string system-product-name: "Satellite M110"
DMI string system-version: "PSMB0U-1234567"
DMI string baseboard-manufacturer: "Intel Corporation"
DMI string baseboard-product-name: "CAPELL VALLEY(NAPA) CRB"
DMI string baseboard-version: "Not Applicable"
DMI string chassis-type: "Other"
DMI chassis-type is not specific enough.
### I add here some part of the output from "dmidecode" as well with extracted information only about relevant bios parameters. By "dmidecode" I could figure out that ROM Size is only 1024 kB:
Handle 0x0000, DMI type 0, 24 bytes
BIOS Information
Vendor: Phoenix Technologies LTD
Version: 6.00
Release Date: 07/12/2007
Address: 0xE4480
Runtime Size: 113536 bytes
ROM Size: 1024 kB
Characteristics:
ISA is supported
PCI is supported
PC Card (PCMCIA) is supported
PNP is supported
APM is supported
BIOS is upgradeable
BIOS shadowing is allowed
ESCD support is available
Boot from CD is supported
ACPI is supported
USB legacy is supported
AGP is supported
BIOS boot specification is supported
Targeted content distribution is supported
------ URL to the mainboard specifications page:
http://www.toshiba.de/discontinued-products/satellite-a100-151/?PRODUCT_ID=…
### Unfortunately, I could only find this German website. But I have access to the manual. However, it does not provide much additional information which would be usefull here.
------ Any other relevant information:
As I have mentioned before, I have upgraded my system including a new CPU (Intel Core2Duo T7200), more RAM (2 x 2GB, identical and from the same vendor) and a SSD. Furthermore I have flashed a modded custom bios which has enabled some more features and seems to work perfectly untill now. However, after the bios mod the model name has been changed.
To end with, I would like to say thank you for your commitment concerning this great open source projet and especially for reading my long message! As I explained I am still a beginner, comming from a completely different working field, but having some ambition to use open source software. I would appreciate your support so that coreboot might natively run on my system.
--
With best regards,
Daniel
