coreboot May 2013

coreboot@coreboot.org

38 participants
91 discussions

Re: [coreboot] Rebasing a 2009 branch on current master (VX900 anyone?)
by Alex G. 30 May '13

30 May '13

On 05/30/2013 01:45 PM, Cristian Măgherușan-Stanciu wrote: > Wow, I can't believe I was so close to the commit before the fork ;-D > > I also think this is a good strategy, please keep us posted on any progress. > Peter and Cristi, thank a bunch for your help. Your suggestions helped me a lot in reaching the following conclusions. I tried a couple of things, as Peter suggested. I managed to build a ROM from their tree. It didn't work since it was written for a different board. I pulled in the romstrap table from my board, and the early serial init. That also didn't work. It could be that their code reconfigures the cpu to nb bus in a way not suited for my board; I haven't dug too deeply into the issue. That configuration is best left in the romstrap. Since the raminit code is fairly isolated, I pulled it into my branch, and spent about half a day getting it to compile. I spent a little time finding out why the meat of raminit code is not called, until I found out it was looking for a SO-DIMM. That's already a red flag. The code from VIA has a ton of tables with delays and driving values for DRAM. The most important parameter, how much to wait before reading each set of DQ pins, is also preset. That preset is different than what I have been using. Needless to say, raminit fails. The presets are board-specific. Other than the presets, I can't see anything fundamentally different from the raminit algorithm that's on gerrit. I don't think the effort of rebasing the VIA code is worth the benefits (not even sure there are any benefits -- the gerrit code does the same thing with 20 times less LOC). I'll have to play around with it some more, see if I can get it working. Right now, it looks like the VIA code serves better as a HOWTO (or HOWNOTTO) guide. Will post updates (either here or on IRC). Alex P.S. Limited time offer: Free tickets to join the fun for anyone with a VX900 board.

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Rebasing a 2009 branch on current master (VX900 anyone?)
by Alex G. 30 May '13

30 May '13

Hi, I am that guy that never seems to get VX900 working properly. I've recently received some code[1] for the VX900 from VIA. It is based on a coreboot fork from about 2009. Rather than try to continue my own VX900 effort, I think it is better to use the code provided by VIA, and clean that one up. I don't have the SVN history for the code, but Cristi was able to trace it back to somewhere around hash a9c5ea08d07d343d32d4c083a232107bd84d8064 VIA has no interest in maintaining or rebasing the code, so we're on our own here. The good news is that using this code will reduce the time needed to complete the VX900 port significantly. I therefore ask the gurus, "What is the best way to go about this?" Let's hope we can get this code working with our current master. If we manage to rebase it, I can clean it up, and optimize it a bit. Alex [1] http://g-tech.no-ip.org/~mrnuke/coreboot_vx900_vt8595a.tgz

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Re: [coreboot] Trying to get coreboot running on VIA EPIA-M (lzma: Decoding error = 1)
by Peter Stuge 30 May '13

30 May '13

Marius Schäfer wrote: > Can you read anything out of these lines and help me? .. > WARNING: BIOS bug: CPU MTRRs don't cover all of memory, losing 63MB of RAM. > ------------[ cut here ]------------ > WARNING: at arch/x86/kernel/cpu/mtrr/cleanup.c:971 > mtrr_trim_uncached_memory+0x411/0x42e() > Pid: 0, comm: swapper Not tainted 3.2.44 #7 > Call Trace: > [<c1017964>] ? warn_slowpath_common+0x63/0x74 > [<c12f98f2>] ? mtrr_trim_uncached_memory+0x411/0x42e > [<c10179f8>] ? warn_slowpath_null+0xd/0x11 > [<c12f98f2>] ? mtrr_trim_uncached_memory+0x411/0x42e > [<c12f5165>] ? setup_arch+0x4eb/0x9dd > [<c12f3421>] ? start_kernel+0x5e/0x275 > ---[ end trace 4eaa2a86a8e2da22 ]--- As Ron says, work on fixing this MTRR problem. > update e820 for mtrr > modified physical RAM map: > modified: 0000000000000000 - 0000000000001000 type 16 > modified: 0000000000001000 - 00000000000a0000 (reserved) > modified: 0000000000100000 - 0000000004000000 (reserved) > modified: 0000000004000000 - 000000001dfe0000 (usable) > modified: 000000001dfe0000 - 000000001e000000 type 16 > last_pfn = 0x1dfe0 max_arch_pfn = 0x100000 > Kernel panic - not syncing: Cannot allocate trampoline > > Pid: 0, comm: swapper Tainted: G W 3.2.44 #7 > Call Trace: > [<c12245eb>] ? panic+0x57/0x12a > [<c12f77e7>] ? setup_trampolines+0x40/0xb1 > [<c12f51df>] ? setup_arch+0x565/0x9dd > [<c12f3421>] ? start_kernel+0x5e/0x275 Check the kernel source to find out what the constraints are for that trampoline allocation. Maybe it must be in some region where there isn't any available RAM, which would be a bug in the memory map for this (and more?) mainboards. Try to find out more details. //Peter

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Adding checks for non-ASCII filenames (was: [Gerrit] gitconfig: Add sample checks shipped by git to pre-commit hook)
by Paul Menzel 30 May '13

30 May '13

Dear coreboot folks, Am Donnerstag, den 30.05.2013, 01:57 +0200 schrieb gerrit code review: From <http://review.coreboot.org/3336>: > Change subject: gitconfig: Add sample checks shipped by git to pre-commit hook > ...................................................................... > > > Patch Set 2: Code-Review-2 > > It does not make sense to have a hook that checks a tree-wide policy > and then allow that policy to be disabled by configuration. Either we > decide on the filename policy or we do not need the hook. as non-ASCII characters are not allowed in our source [1], I assume they are also not allowed in file names. The sample pre-commit hook shipped by git has a check for non-ASCII file names, which can be disabled by a config option. Are there any circumstances where non-ASCII characters might be needed? If not, Peter is right and the option can be removed from the script, which I would do then. Thanks, Paul [1] http://review.coreboot.org/2604

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Re: [coreboot] Lenovo X301 information
by Cristian Măgherușan-Stanciu 30 May '13

30 May '13

Hi George, The chip is there and it was easy to find it, but it's a less common package. It is an 8 pin part but wider and closer to the surface than the SOIC8. I tried the Pomona clip and even if the pins would match after mounting the clip, it makes no electric contact to it due to the smaller leads, so Flashrom couldn't detect it. The next step is to solder some wires and make it writable from outside using my RaspberryPi external flasher. The rest of the hardware is quite well supported by coreboot. It is somehow similar to Roda rk9 (same CPU package, NB and SB) but with the rest of the chips(EC and company) similar to other Thinkpad laptops, so in theory a port should not be so hard. Cristi On Wed, May 29, 2013 at 3:26 AM, George Chriss <gschriss(a)gmail.com> wrote: > On Sun, May 26, 2013 at 6:39 AM, Cristian Măgherușan-Stanciu < > cristi.magherusan(a)gmail.com> wrote: > > > > Hi, > > > > Please see the attached files, gathered while running the proprietary > BIOS. > > > > Cheers, > > Cristi > > Hi, > > Is the W25X64 chip physically accessible with exposed surface-mount pins? > A Bus Pirate may be helpful/necessary to gather additional info and to > reprogram the chip. > > Photos from an X201i + Bus Pirate: > http://gchriss.tumblr.com/post/50463745980/a-closer-look > > Sincerely, > George > > > > > > -- > > coreboot mailing list: coreboot(a)coreboot.org > > http://www.coreboot.org/mailman/listinfo/coreboot > >

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Re: [coreboot] Trying to get coreboot running on VIA EPIA-M (lzma: Decoding error = 1)
by ron minnich 30 May '13

30 May '13

a few things. Don't know why the MTRRs are not supporting all of memory but you ought to fix that. Can you get rid of the vga bios? That will save some time. I forget the last thing :-) oh yeah, when you get it for real, turn down the default console log level to ERR. Printing takes a surprising amount of time. ron

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SeaBIOS v1.7.2.2 stable release
by Kevin O'Connor 30 May '13

30 May '13

A new stable release of SeaBIOS (version 1.7.2.2) has been tagged. This release contains bug fixes. The release is available via git: git clone git://git.seabios.org/seabios -b 1.7.2-stable -Kevin Asias He (2): virtio-scsi: Pack struct virtio_scsi_{req_cmd,resp_cmd} virtio-scsi: Set _DRIVER_OK flag before scsi target scanning Kevin O'Connor (1): Cache boot-fail-wait to avoid romfile access after POST. boot.c | 15 +++++++++------ virtio-scsi.c | 5 +++-- virtio-scsi.h | 4 ++-- 3 files changed, 14 insertions(+), 10 deletions(-)

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Re: [coreboot] Trying to get coreboot running on VIA EPIA-M (lzma: Decoding error = 1)
by Marius Schäfer 29 May '13

29 May '13

Ok, I don't know why, but I now can run compressed and uncompressed filo as payload. I even got vga to init and display the output from filo. If I try to use SeaBios as payload, I still encounter lzma errors. I can't test SeaBios uncompressed as it's too big for my 256kB flash. But I could be quite happy with filo as I just want to boot the Linux kernel very fast (faster than the original Bios and syslinux do). I try to build a headless mpd player with buildroot. With the regular Bios and syslinux it takes about 20 seconds from power up to playing music. I think I could save about 5-10 seconds with coreboot. Can you read anything out of these lines and help me? Thank you, Marius Enabling mainboard devices Enabling shadow ram vt8623 init starting Detecting Memory Number of Banks 04 Number of Rows 0d Priamry DRAM width08 No Columns 0a MA type e0 Bank 0 (*16 Mb) 10 No Physical Banks 02 Total Memory (*16 Mb) 20 CAS Supported 2 2.5 3 Cycle time at CL X (nS)50 Cycle time at CL X-0.5 (nS)60 Cycle time at CL X-1 (nS)75 Starting at CAS 3 We can do CAS 2.5 We can do CAS 2 tRP 3c tRCD 3c tRAS 28 Low Bond 00 High Bondb4 Setting DQS delay78vt8623 done 00:06 11 23 31 06 00 30 22 00 00 00 06 00 00 00 00 10:08 00 00 d0 00 00 00 00 00 00 00 00 00 00 00 00 20:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30:00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 40:00 18 88 80 82 44 00 00 18 99 88 80 82 44 00 00 50:c8 de cf 88 e0 07 00 00 e0 00 10 20 20 20 00 00 60:02 ff 00 30 52 32 01 38 42 2d 43 58 84 55 00 00 70:82 48 00 01 01 08 50 00 01 00 00 00 00 00 00 00 80:0f 61 00 00 80 00 00 00 02 00 00 00 00 00 00 00 90:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0:02 c0 20 00 07 02 00 1f 04 00 00 00 2f 02 04 00 b0:00 00 00 00 c0 00 00 00 88 00 00 00 00 00 00 00 c0:01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0:00 dd 00 01 00 00 01 00 40 00 00 00 00 00 00 00 f0:00 00 00 00 00 00 03 13 00 00 00 00 00 00 00 00 AGP coreboot-4.0 Wed May 29 22:37:27 CEST 2013 booting... clocks_per_usec: 600 Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:10.1: enabled 1 PCI: 00:10.2: enabled 1 PCI: 00:10.3: enabled 1 PCI: 00:11.0: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.b: enabled 1 PCI: 00:11.1: enabled 1 PCI: 00:11.5: enabled 1 PCI: 00:11.6: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:0a.0: enabled 1 PCI: 00:0a.1: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:10.1: enabled 1 PCI: 00:10.2: enabled 1 PCI: 00:10.3: enabled 1 PCI: 00:11.0: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.b: enabled 1 PCI: 00:11.1: enabled 1 PCI: 00:11.5: enabled 1 PCI: 00:11.6: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:0a.0: enabled 1 PCI: 00:0a.1: enabled 1 scan_static_bus for Root Device In vt8623 enable_dev for device CPU_CLUSTER: 0. CPU_CLUSTER: 0 enabled In vt8623 enable_dev for device DOMAIN: 0000. DOMAIN: 0000 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 In vt8623 enable_dev for device PCI: 00:00.0. PCI: 00:00.0 [1106/3123] ops PCI: 00:00.0 [1106/3123] enabled In vt8623 enable_dev for device PCI: 00:01.0. PCI: 00:01.0 [1106/b091] bus ops PCI: 00:01.0 [1106/b091] enabled PCI: Static device PCI: 00:0a.0 not found, disabling it. PCI: Static device PCI: 00:0a.1 not found, disabling it. PCI: 00:0d.0 [1106/3044] enabled In vt8235_enable 1106 3038. PCI: 00:10.0 [1106/3038] ops PCI: 00:10.0 [1106/3038] enabled In vt8235_enable 1106 3038. PCI: 00:10.1 [1106/3038] ops PCI: 00:10.1 [1106/3038] enabled In vt8235_enable 1106 3038. PCI: 00:10.2 [1106/3038] ops PCI: 00:10.2 [1106/3038] enabled In vt8235_enable ffff ffff. PCI: Static device PCI: 00:10.3 not found, disabling it. In vt8235_enable 1106 3177. Initialising Devices PCI: 00:11.0 [1106/3177] bus ops PCI: 00:11.0 [1106/3177] enabled In vt8235_enable 1106 0571. PCI: 00:11.1 [1106/0571] ops PCI: 00:11.1 [1106/0571] enabled In vt8235_enable 1106 3059. PCI: 00:11.5 [1106/3059] enabled In vt8235_enable 1106 3068. PCI: 00:11.6 [1106/3068] disabled In vt8235_enable 1106 3065. PCI: 00:12.0 [1106/3065] ops PCI: 00:12.0 [1106/3065] enabled do_pci_scan_bridge for PCI: 00:01.0 PCI: pci_scan_bus for bus 01 PCI: 01:00.0 [1106/3122] ops PCI: 01:00.0 [1106/3122] enabled PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 scan_static_bus for PCI: 00:11.0 PNP: 002e.0 enabled PNP: 002e.1 enabled PNP: 002e.2 enabled PNP: 002e.3 enabled PNP: 002e.b enabled PNP: 002e.6 enabled PNP: 002e.7 enabled PNP: 002e.8 enabled PNP: 002e.9 enabled PNP: 002e.a enabled PNP: 002e.c enabled PNP: 002e.d enabled scan_static_bus for PCI: 00:11.0 done PCI: pci_scan_bus returning with max=001 scan_static_bus for Root Device done done found VGA at PCI: 01:00.0 Setting up VGA for PCI: 01:00.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources CPU_CLUSTER: 0 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:11.0 read_resources bus 0 link: 0 PCI: 00:11.0 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:01.0 child on link 0 PCI: 01:00.0 PCI: 01:00.0 PCI: 01:00.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 1200 index 10 PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 14 PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI: 00:0a.0 PCI: 00:0a.1 PCI: 00:0d.0 PCI: 00:0d.0 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 10 PCI: 00:0d.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 14 PCI: 00:10.0 PCI: 00:10.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:10.1 PCI: 00:10.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:10.2 PCI: 00:10.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:10.3 PCI: 00:11.0 child on link 0 PNP: 002e.0 PCI: 00:11.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 PCI: 00:11.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.1 PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.1 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.2 PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.b PNP: 002e.b resource base ec00 size 100 align 8 gran 8 limit ffff flags c0000100 index 60 PNP: 002e.b resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.6 PNP: 002e.6 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 60 PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.7 PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 60 PNP: 002e.8 PNP: 002e.8 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 60 PNP: 002e.8 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.9 PNP: 002e.9 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 60 PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.a PNP: 002e.a resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 60 PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.c PNP: 002e.c resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 60 PNP: 002e.c resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.c resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.d PCI: 00:11.1 PCI: 00:11.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:11.5 PCI: 00:11.5 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10 PCI: 00:11.6 PCI: 00:12.0 PCI: 00:12.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10 PCI: 00:12.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 14 DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:11.5 10 * [0x0 - 0xff] io PCI: 00:12.0 10 * [0x400 - 0x4ff] io PCI: 00:0d.0 14 * [0x800 - 0x87f] io PCI: 00:10.0 20 * [0x880 - 0x89f] io PCI: 00:10.1 20 * [0x8a0 - 0x8bf] io PCI: 00:10.2 20 * [0x8c0 - 0x8df] io PCI: 00:11.1 20 * [0x8e0 - 0x8ef] io DOMAIN: 0000 compute_resources_io: base: 8f0 size: 8f0 align: 8 gran: 0 limit: ffff done DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:0d.0 10 * [0x0 - 0x7ff] mem PCI: 00:12.0 14 * [0x800 - 0x8ff] mem DOMAIN: 0000 compute_resources_mem: base: 900 size: 900 align: 11 gran: 0 limit: ffffffff done avoid_fixed_resources: DOMAIN: 0000 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff constrain_resources: DOMAIN: 0000 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:01.0 constrain_resources: PCI: 01:00.0 constrain_resources: PCI: 00:0d.0 constrain_resources: PCI: 00:10.0 constrain_resources: PCI: 00:10.1 constrain_resources: PCI: 00:10.2 constrain_resources: PCI: 00:11.0 constrain_resources: PNP: 002e.0 constrain_resources: PNP: 002e.1 constrain_resources: PNP: 002e.2 constrain_resources: PNP: 002e.3 constrain_resources: PNP: 002e.b constrain_resources: PNP: 002e.6 constrain_resources: PNP: 002e.7 constrain_resources: PNP: 002e.8 constrain_resources: PNP: 002e.9 constrain_resources: PNP: 002e.a constrain_resources: PNP: 002e.c constrain_resources: PNP: 002e.d constrain_resources: PCI: 00:11.1 constrain_resources: PCI: 00:11.5 constrain_resources: PCI: 00:12.0 avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff lim->base 00001000 lim->limit 0000ebff avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff lim->base 00000000 lim->limit febfffff Setting resources... DOMAIN: 0000 allocate_resources_io: base:1000 size:8f0 align:8 gran:0 limit:ebff Assigned: PCI: 00:11.5 10 * [0x1000 - 0x10ff] io Assigned: PCI: 00:12.0 10 * [0x1400 - 0x14ff] io Assigned: PCI: 00:0d.0 14 * [0x1800 - 0x187f] io Assigned: PCI: 00:10.0 20 * [0x1880 - 0x189f] io Assigned: PCI: 00:10.1 20 * [0x18a0 - 0x18bf] io Assigned: PCI: 00:10.2 20 * [0x18c0 - 0x18df] io Assigned: PCI: 00:11.1 20 * [0x18e0 - 0x18ef] io DOMAIN: 0000 allocate_resources_io: next_base: 18f0 size: 8f0 align: 8 gran: 0 done DOMAIN: 0000 allocate_resources_mem: base:febff000 size:900 align:11 gran:0 limit:febfffff Assigned: PCI: 00:0d.0 10 * [0xfebff000 - 0xfebff7ff] mem Assigned: PCI: 00:12.0 14 * [0xfebff800 - 0xfebff8ff] mem DOMAIN: 0000 allocate_resources_mem: next_base: febff900 size: 900 align: 11 gran: 0 done Root Device assign_resources, bus 0 link: 0 Entering vt8623 pci_domain_set_resources. I would set ram size to 0x80000 Kbytes tom: 1e000000, high_tables_base: 1dfe0000, high_tables_size: 20000 DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:0d.0 10 <- [0x00febff000 - 0x00febff7ff] size 0x00000800 gran 0x0b mem PCI: 00:0d.0 14 <- [0x0000001800 - 0x000000187f] size 0x00000080 gran 0x07 io PCI: 00:10.0 20 <- [0x0000001880 - 0x000000189f] size 0x00000020 gran 0x05 io PCI: 00:10.1 20 <- [0x00000018a0 - 0x00000018bf] size 0x00000020 gran 0x05 io PCI: 00:10.2 20 <- [0x00000018c0 - 0x00000018df] size 0x00000020 gran 0x05 io PCI: 00:11.0 assign_resources, bus 0 link: 0 PNP: 002e.0 60 <- [0x00000003f0 - 0x00000003f7] size 0x00000008 gran 0x03 io PNP: 002e.0 70 <- [0x0000000006 - 0x0000000006] size 0x00000001 gran 0x00 irq PNP: 002e.0 74 <- [0x0000000002 - 0x0000000002] size 0x00000001 gran 0x00 drq PNP: 002e.1 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io PNP: 002e.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq PNP: 002e.1 74 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 drq PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq PNP: 002e.b 60 <- [0x000000ec00 - 0x000000ecff] size 0x00000100 gran 0x08 io ERROR: PNP: 002e.b 70 irq size: 0x0000000001 not assigned ERROR: PNP: 002e.6 60 io size: 0x0000000004 not assigned ERROR: PNP: 002e.6 70 irq size: 0x0000000001 not assigned ERROR: PNP: 002e.7 60 io size: 0x0000000008 not assigned ERROR: PNP: 002e.8 60 io size: 0x0000000010 not assigned ERROR: PNP: 002e.8 70 irq size: 0x0000000001 not assigned ERROR: PNP: 002e.9 60 io size: 0x0000000010 not assigned ERROR: PNP: 002e.9 70 irq size: 0x0000000001 not assigned ERROR: PNP: 002e.a 60 io size: 0x0000000010 not assigned ERROR: PNP: 002e.a 70 irq size: 0x0000000001 not assigned ERROR: PNP: 002e.c 60 io size: 0x0000000100 not assigned ERROR: PNP: 002e.c 70 irq size: 0x0000000001 not assigned ERROR: PNP: 002e.c 74 drq size: 0x0000000001 not assigned PCI: 00:11.0 assign_resources, bus 0 link: 0 PCI: 00:11.1 20 <- [0x00000018e0 - 0x00000018ef] size 0x00000010 gran 0x04 io PCI: 00:11.5 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 00:12.0 10 <- [0x0000001400 - 0x00000014ff] size 0x00000100 gran 0x08 io PCI: 00:12.0 14 <- [0x00febff800 - 0x00febff8ff] size 0x00000100 gran 0x08 mem DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 1000 size 8f0 align 8 gran 0 limit ebff flags 40040100 index 10000000 DOMAIN: 0000 resource base febff000 size 900 align 11 gran 0 limit febfffff flags 40040200 index 10000100 DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a DOMAIN: 0000 resource base c0000 size 1df40000 align 0 gran 0 limit 0 flags e0004200 index b PCI: 00:00.0 PCI: 00:01.0 child on link 0 PCI: 01:00.0 PCI: 01:00.0 PCI: 01:00.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 1200 index 10 PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 14 PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI: 00:0a.0 PCI: 00:0a.1 PCI: 00:0d.0 PCI: 00:0d.0 resource base febff000 size 800 align 11 gran 11 limit febfffff flags 60000200 index 10 PCI: 00:0d.0 resource base 1800 size 80 align 7 gran 7 limit ebff flags 60000100 index 14 PCI: 00:10.0 PCI: 00:10.0 resource base 1880 size 20 align 5 gran 5 limit ebff flags 60000100 index 20 PCI: 00:10.1 PCI: 00:10.1 resource base 18a0 size 20 align 5 gran 5 limit ebff flags 60000100 index 20 PCI: 00:10.2 PCI: 00:10.2 resource base 18c0 size 20 align 5 gran 5 limit ebff flags 60000100 index 20 PCI: 00:10.3 PCI: 00:11.0 child on link 0 PNP: 002e.0 PCI: 00:11.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 PCI: 00:11.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags e0000800 index 74 PNP: 002e.1 PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.1 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000800 index 74 PNP: 002e.2 PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.b PNP: 002e.b resource base ec00 size 100 align 8 gran 8 limit ffff flags e0000100 index 60 PNP: 002e.b resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.6 PNP: 002e.6 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 60 PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.7 PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 60 PNP: 002e.8 PNP: 002e.8 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 60 PNP: 002e.8 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.9 PNP: 002e.9 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 60 PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.a PNP: 002e.a resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 60 PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.c PNP: 002e.c resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 60 PNP: 002e.c resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.c resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.d PCI: 00:11.1 PCI: 00:11.1 resource base 18e0 size 10 align 4 gran 4 limit ebff flags 60000100 index 20 PCI: 00:11.5 PCI: 00:11.5 resource base 1000 size 100 align 8 gran 8 limit ebff flags 60000100 index 10 PCI: 00:11.6 PCI: 00:12.0 PCI: 00:12.0 resource base 1400 size 100 align 8 gran 8 limit ebff flags 60000100 index 10 PCI: 00:12.0 resource base febff800 size 100 align 8 gran 8 limit febfffff flags 60000200 index 14 Done allocating resources. Enabling resources... PCI: 00:00.0 cmd <- 06 PCI: 00:01.0 bridge ctrl <- 000f PCI: 00:01.0 cmd <- 07 PCI: 00:0d.0 cmd <- 83 PCI: 00:10.0 cmd <- 01 PCI: 00:10.1 cmd <- 01 PCI: 00:10.2 cmd <- 01 PCI: 00:11.0 cmd <- 07 PCI: 00:11.1 cmd <- 81 PCI: 00:11.5 subsystem <- 0000/0000 PCI: 00:11.5 cmd <- 01 PCI: 00:12.0 cmd <- 83 PCI: 01:00.0 cmd <- 03 PNP: 002e.0 - enabling PNP: 002e.1 - enabling PNP: 002e.2 - enabling PNP: 002e.3 - enabling PNP: 002e.b - enabling PNP: 002e.6 - enabling PNP: 002e.7 - enabling PNP: 002e.8 - enabling PNP: 002e.9 - enabling PNP: 002e.a - enabling PNP: 002e.c - enabling PNP: 002e.d - enabling done. Initializing devices... Root Device init CPU_CLUSTER: 0 init Initializing CPU #0 CPU: vendor Centaur device 673 CPU: family 06, model 07, stepping 03 Using generic cpu ops (good) Enabling cache MTRR: Physical address space: 0x0000000000000000 - 0x0000000004000000 size 0x04000000 type 0 0x0000000004000000 - 0x000000001e000000 size 0x1a000000 type 6 0x000000001e000000 - 0x0000000100000000 size 0xe2000000 type 0 MTRR: Fixed MSR 0x250 0x0000000000000000 MTRR: Fixed MSR 0x258 0x0000000000000000 MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0000000000000000 MTRR: Fixed MSR 0x269 0x0000000000000000 MTRR: Fixed MSR 0x26a 0x0000000000000000 MTRR: Fixed MSR 0x26b 0x0000000000000000 MTRR: Fixed MSR 0x26c 0x0000000000000000 MTRR: Fixed MSR 0x26d 0x0000000000000000 MTRR: Fixed MSR 0x26e 0x0000000000000000 MTRR: Fixed MSR 0x26f 0x0000000000000000 call enable_fixed_mtrr() CPU physical address size: 32 bits MTRR: default type WB/UC MTRR counts: 5/4. MTRR: UC selected as default type. MTRR: 0 base 0x0000000004000000 mask 0x00000000fc000000 type 6 MTRR: 1 base 0x0000000008000000 mask 0x00000000f8000000 type 6 MTRR: 2 base 0x0000000010000000 mask 0x00000000f0000000 type 6 MTRR: 3 base 0x000000001e000000 mask 0x00000000fe000000 type 0 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Disabling local apic...done. CPU #0 initialized PCI: 00:00.0 init VT8623 random fixup ... Frame buffer at d0000000 PCI: 00:01.0 init VT8623 AGP random fixup ... PCI: 00:0d.0 init PCI: 00:10.0 init Configuring VIA USB 1.1 PCI: 00:10.1 init Configuring VIA USB 1.1 PCI: 00:10.2 init Configuring VIA USB 1.1 PCI: 00:11.0 init vt8235 init RTC Init pci_routing_fixup: dev is 00114ddc setting firewire Assigning IRQ 9 to 0:d.0 i8259_configure_irq_trigger: current interrupts are 0x0 i8259_configure_irq_trigger: try to set interrupts 0x200 setting usb Assigning IRQ 5 to 0:10.0 i8259_configure_irq_trigger: current interrupts are 0x200 i8259_configure_irq_trigger: try to set interrupts 0x220 Assigning IRQ 9 to 0:10.1 i8259_configure_irq_trigger: current interrupts are 0x220 i8259_configure_irq_trigger: try to set interrupts 0x220 Assigning IRQ 9 to 0:10.2 i8259_configure_irq_trigger: current interrupts are 0x220 i8259_configure_irq_trigger: try to set interrupts 0x220 Assigning IRQ 5 to 0:10.3 i8259_configure_irq_trigger: current interrupts are 0x220 i8259_configure_irq_trigger: try to set interrupts 0x220 setting vt8235 Assigning IRQ 5 to 0:11.1 i8259_configure_irq_trigger: current interrupts are 0x220 i8259_configure_irq_trigger: try to set interrupts 0x220 Assigning IRQ 9 to 0:11.5 i8259_configure_irq_trigger: current interrupts are 0x220 i8259_configure_irq_trigger: try to set interrupts 0x220 Assigning IRQ 9 to 0:11.6 i8259_configure_irq_trigger: current interrupts are 0x220 i8259_configure_irq_trigger: try to set interrupts 0x220 setting ethernet Assigning IRQ 5 to 0:12.0 i8259_configure_irq_trigger: current interrupts are 0x220 i8259_configure_irq_trigger: try to set interrupts 0x220 setting vga Assigning IRQ 5 to 1:0.0 i8259_configure_irq_trigger: current interrupts are 0x220 i8259_configure_irq_trigger: try to set interrupts 0x220 setting pci slot setting cardbus slot setting riser slot pci_routing_fixup: DONE PCI: 00:11.1 init Enabling VIA IDE. ide_init: enabling compatibility IDE addresses enables in reg 0x42 0x9 enables in reg 0x42 read back as 0x9 enables in reg 0x40 0x8 enables in reg 0x40 read back as 0xb enables in reg 0x9 0x8a enables in reg 0x9 read back as 0x8a command in reg 0x4 0x81 command in reg 0x4 reads back as 0x7 PCI: 00:11.5 init PCI: 00:12.0 init Configuring VIA Rhine LAN PCI: 01:00.0 init VGA random fixup ... Initializing VGA... In CBFS, ROM address for PCI: 01:00.0 = fffc04f8 PCI expansion ROM, signature 0xaa55, INIT size 0xec00, data ptr 0x0044 PCI ROM image, vendor ID 1106, device ID 3122, PCI ROM image, Class Code 030000, Code Type 00 Copying VGA ROM Image from fffc04f8 to 0xc0000, 0xec00 bytes Real mode stub @00000600: 867 bytes Calling Option ROM... via_vt8623_int15_handler int15 call returned error. via_vt8623_int15_handler via_vt8623_int15_handler via_vt8623_int15_handler via_vt8623_int15_handler via_vt8623_int15_handler via_vt8623_int15_handler int15 call returned error. via_vt8623_int15_handler via_vt8623_int15_handler ... Option ROM returned. VBE: Getting information about VESA mode 4117 VBE: resolution: 1024x768@16 VBE: framebuffer: d8000000 VBE: Setting VESA mode 4117 via_vt8623_int15_handler Unknown INT15 function 5f03! int15 call returned error. via_vt8623_int15_handler Unknown INT15 function 5f04! int15 call returned error. Enable VGA console via_vt8623_int15_handler Unknown INT15 function 5f06! int15 call returned error. via_vt8623_int15_handler Unknown INT15 function 5f08! int15 call returned error. PNP: 002e.0 init PNP: 002e.1 init PNP: 002e.2 init VT1211: Cannot init unknown device! PNP: 002e.3 init VT1211: Cannot init unknown device! PNP: 002e.b init PNP: 002e.6 init PNP: 002e.7 init PNP: 002e.8 init PNP: 002e.9 init PNP: 002e.a init PNP: 002e.c init PNP: 002e.d init Devices initialized Show all devs...After init. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:10.1: enabled 1 PCI: 00:10.2: enabled 1 PCI: 00:10.3: enabled 0 PCI: 00:11.0: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.b: enabled 1 PCI: 00:11.1: enabled 1 PCI: 00:11.5: enabled 1 PCI: 00:11.6: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:0a.0: enabled 0 PCI: 00:0a.1: enabled 0 PCI: 00:0d.0: enabled 1 PCI: 01:00.0: enabled 1 PNP: 002e.6: enabled 1 PNP: 002e.7: enabled 1 PNP: 002e.8: enabled 1 PNP: 002e.9: enabled 1 PNP: 002e.a: enabled 1 PNP: 002e.c: enabled 1 PNP: 002e.d: enabled 1 CPU: 00: enabled 1 Re-Initializing CBMEM area to 0x1dfe0000 Initializing CBMEM area to 0x1dfe0000 (131072 bytes) Adding CBMEM entry as no. 1 Moving GDT to 1dfe0200...ok High Tables Base is 1dfe0000. Adding CBMEM entry as no. 2 Writing table forward entry at 0x00000500 Wrote coreboot table at: 00000500, 0x10 bytes, checksum dde0 Table forward entry ends at 0x00000528. ... aligned to 0x00001000 Writing coreboot table at 0x1dfe0400 rom_table_end = 0x1dfe0400 ... aligned to 0x1dff0000 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-000000001dfdffff: RAM 3. 000000001dfe0000-000000001dffffff: CONFIGURATION TABLES Wrote coreboot table at: 1dfe0400, 0x1a0 bytes, checksum de7e coreboot table: 440 bytes. FREE SPACE 0. 1dfe8400 00017c00 GDT 1. 1dfe0200 00000200 COREBOOT 2. 1dfe0400 00008000 Loading segment from rom address 0xfffe7b38 parameter section (skipped) Loading segment from rom address 0xfffe7b54 code (compression=1) New segment dstaddr 0x100000 memsize 0x131060 srcaddr 0xfffe7bd8 filesize 0x7696 (cleaned up) New segment addr 0x100000 size 0x131060 offset 0xfffe7bd8 filesize 0x7696 Loading segment from rom address 0xfffe7b70 data (compression=1) New segment dstaddr 0x231060 memsize 0x48 srcaddr 0xfffef26e filesize 0x2e (cleaned up) New segment addr 0x231060 size 0x48 offset 0xfffef26e filesize 0x2e Loading segment from rom address 0xfffe7b8c Entry Point 0x00100000 Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000131060 filesz: 0x0000000000007696 lb: [0x0000000000100000, 0x0000000000120010) segment: [0x0000000000100000, 0x0000000000107696, 0x0000000000231060) bounce: [0x000000001de8ef90, 0x000000001de96626, 0x000000001dfbfff0) Post relocation: addr: 0x000000001de8ef90 memsz: 0x0000000000131060 filesz: 0x0000000000007696 using LZMA [ 0x1de8ef90, 1de9e070, 0x1dfbfff0) <- fffe7bd8 Clearing Segment: addr: 0x000000001de9e070 memsz: 0x0000000000121f80 dest 1de8ef90, end 1dfbfff0, bouncebuffer 1de8ef90 move suffix around: from 1deaefa0, to 120010, amount: 111050 Loading Segment: addr: 0x0000000000231060 memsz: 0x0000000000000048 filesz: 0x000000000000002e lb: [0x0000000000100000, 0x0000000000120010) Post relocation: addr: 0x0000000000231060 memsz: 0x0000000000000048 filesz: 0x000000000000002e using LZMA [ 0x00231060, 002310a8, 0x002310a8) <- fffef26e dest 00231060, end 002310a8, bouncebuffer 1de8ef90 Loaded segments Jumping to boot code at 00100000 CPU0: stack: 0011b000 - 0011c000, lowest used address 0011ba9c, stack used: 1380 bytes entry = 0x00100000 lb_start = 0x00100000 lb_size = 0x00020010 adjust = 0x1debfff0 buffer = 0x1de8ef90 elf_boot_notes = 0x00115db8 adjusted_boot_notes = 0x1dfd5da8 coreboot: 4.0 FILO version 0.6.0 (root@coreboot) Wed May 22 17:36:37 CEST 2013 Press <Enter> for default boot, or <Esc> for boot prompt... 2 1 timed out boot: hda1:/bzimage console=ttyS0,115200n8 earlyprintk=ttyS0,115200 hda: LBA 523MB: M-Systems iDOC V1.03 040128 Found Linux version 3.2.44 (root@mpd) #7 PREEMPT Thu May 16 19:15:44 CEST 2013 bzImage. Loading kernel... ok Jumping to entry point... Linux version 3.2.44 (root@mpd) (gcc version 4.7.2 (Buildroot 2013.02) ) #7 PREEMPT Thu May 16 19:15:44 CEST 2013 BIOS-provided physical RAM map: BIOS-e820: 0000000000000000 - 0000000000001000 type 16 BIOS-e820: 0000000000001000 - 00000000000a0000 (usable) BIOS-e820: 00000000000c0000 - 000000001dfe0000 (usable) BIOS-e820: 000000001dfe0000 - 000000001e000000 type 16 bootconsole [earlyser0] enabled Notice: NX (Execute Disable) protection missing in CPU! DMI not present or invalid. last_pfn = 0x1dfe0 max_arch_pfn = 0x100000 PAT not supported by CPU. WARNING: BIOS bug: CPU MTRRs don't cover all of memory, losing 63MB of RAM. ------------[ cut here ]------------ WARNING: at arch/x86/kernel/cpu/mtrr/cleanup.c:971 mtrr_trim_uncached_memory+0x411/0x42e() Pid: 0, comm: swapper Not tainted 3.2.44 #7 Call Trace: [<c1017964>] ? warn_slowpath_common+0x63/0x74 [<c12f98f2>] ? mtrr_trim_uncached_memory+0x411/0x42e [<c10179f8>] ? warn_slowpath_null+0xd/0x11 [<c12f98f2>] ? mtrr_trim_uncached_memory+0x411/0x42e [<c12f5165>] ? setup_arch+0x4eb/0x9dd [<c12f3421>] ? start_kernel+0x5e/0x275 ---[ end trace 4eaa2a86a8e2da22 ]--- update e820 for mtrr modified physical RAM map: modified: 0000000000000000 - 0000000000001000 type 16 modified: 0000000000001000 - 00000000000a0000 (reserved) modified: 0000000000100000 - 0000000004000000 (reserved) modified: 0000000004000000 - 000000001dfe0000 (usable) modified: 000000001dfe0000 - 000000001e000000 type 16 last_pfn = 0x1dfe0 max_arch_pfn = 0x100000 Kernel panic - not syncing: Cannot allocate trampoline Pid: 0, comm: swapper Tainted: G W 3.2.44 #7 Call Trace: [<c12245eb>] ? panic+0x57/0x12a [<c12f77e7>] ? setup_trampolines+0x40/0xb1 [<c12f51df>] ? setup_arch+0x565/0x9dd [<c12f3421>] ? start_kernel+0x5e/0x275

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Re: [coreboot] Native init for AMD cards
by Deucher, Alexander 29 May '13

29 May '13

> -----Original Message----- > From: ron minnich [mailto:rminnich@gmail.com] > Sent: Wednesday, May 29, 2013 12:17 PM > To: Deucher, Alexander > Cc: Rudolf Marek; David Hubbard; Coreboot > Subject: Re: [coreboot] Native init for AMD cards > > well, we're lighting up 4 laptop panels from source today. So it's doable. Right. My point is just that there's not some special atom function you can call to do all of that. You have to walk the topology and light up the displays. Alex

1 0

Re: [coreboot] Native init for AMD cards
by Rudolf Marek 29 May '13

29 May '13

Hi David, > I read the kernel sources today, looking for a way of doing native init for AMD boards like the F2A85-M. > Comments welcome on the insanity of this proposal :) In fact I did the same some time ago, but there is a problem with the AtomBIOS and the graphical data paths. > 2. Do coreboot developers have contact with the radeon driver developers? A > little nudge from time to time could keep a project like this on track. I was speaking with Alex (I put him on CC) My Q was: > My plan (which may sound bit naiive), is/was to Initialize the GPU with > AsicInit (so simple run of AtomBIOS interpreter) and then switch it to legacy VGA > mode and handle this with SeaBIOS VGA BIOS. Maybe there is a gap between - > setting up a legacy VGA and AsicInit, I don't know, possibly I need to detect what kind of output is used, but all I need is simple text mode > > Please can you throw some light on this topic? Alex told me: The AsicInit table just performs low level setup on the asic, it doesn't mess with the displays at all. The radeon vbios has real mode x86 code that gets executed at post or via vbe calls to read in the information in the atombios tables, figure out the display topology and detect and light up whatever displays are attached. You would need to implement that functionality in your vbios replacement. If you want a bios console, you'll have to use the open source radeon driver as a guide to how to write a vbios replacement that enumerates and lights up the displays. END Also it turned out that the bytecode is there for the OEM so the changed topology does not need the new VBIOS assembly but just the AtomBIOS bytecode. Which is quite bad, because the VBIOS is depending on how it is routed and may only work with similar boards even when chipset is same. We would have to find out a way how to include the AtomBIOS in some form in the coreboot or re-write it somehow, because the bytecode is not even "property" of AMD but OEM and radeon driver needs that to be present in a rom. Maybe it would be possible to write some commmon init and handle just small changes in the bytecode. For now, I would say kind of "reply" init might work, it depends if your goals are similar like we have with intel, so just graphic framebuffer for grub2 or something like I had in my mind. Thanks Rudolf

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coreboot May 2013