coreboot March 2013

coreboot@coreboot.org

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782 discussions

Re: [coreboot] Could some one please give me parameters for QEMU for running Coreboot with Linux payload
by Pankaj Chhabra 11 Mar '13

11 Mar '13

Hello, Please note that I have tried with foo directory with coreboot.rom copied as bios.bin also. qemu-system-i386w.exe -L foo -serial stdio Thanks, Pankaj On Mon, Mar 11, 2013 at 11:02 PM, Pankaj Chhabra <chhabra.pankaj(a)gmail.com>wrote: > Hello Ron, > > I would like to get involved in the project. > > I am running into the issue that Qemu is not loading with the Coreboot > with Linux payload. On the same setup Qemu with Seabios payload works fine. > > I am running Qemu with the attached batch file after replacing the > bios.bin with generated coreboot.rom > > *COREBOOT WITH LINUX PAYLOAD:* > * > * > For now I have built with ROM size of 4MB > > Built the core boot on Linux Ubuntu 12.04 > his is what has been built > GEN generated/crt0.romstage.S > CC generated/crt0.s > CC generated/crt0.romstage.o > CC console/console.romstage.o > CC generated/bootblock.s > CC generated/bootblock.o > LINK cbfs/fallback/bootblock.debug > OBJCOPY cbfs/fallback/bootblock.elf > OBJCOPY cbfs/fallback/bootblock.bin > Created CBFS image (capacity = 4193360 bytes) > LINK cbfs/fallback/romstage_null.debug > OBJCOPY cbfs/fallback/romstage_null.elf > OBJCOPY cbfs/fallback/romstage_null.bin > GEN generated/romstage_xip.ld > LINK cbfs/fallback/romstage_xip.debug > OBJCOPY cbfs/fallback/romstage_xip.elf > CBFS coreboot.pre > CC lib/version.ramstage.o > CC drivers/pc80/mc146818rtc.ramstage.o > CC console/console.ramstage.o > CC arch/x86/boot/smbios.ramstage.o > CC generated/coreboot_ram.o > CC cbfs/fallback/coreboot_ram.debug > OBJCOPY cbfs/fallback/coreboot_ram.elf > CBFS coreboot.rom > PAYLOAD payload.elf (compression: LZMA) > CONFIG .config > CBFSPRINT coreboot.rom > > coreboot.rom: 4096 kB, bootblocksize 848, romsize 4194304, offset 0x0 > alignment: 64 bytes > > Name Offset Type Size > cmos_layout.bin 0x0 cmos_layout 1160 > fallback/romstage 0x4c0 stage 19197 > fallback/coreboot_ram 0x5000 stage 42894 > fallback/payload 0xf800 payload 2513834 > config 0x275400 raw 2873 > (empty) 0x275f80 null 1613016 > > *RUN* > I am running this on Windows Qemo and ran with the following options, I > have modified the batch file which comes with the Linux. Please find > attached the batch file and ROM image that was built. > > > When I try to run int, I am struck the point below. Please let me know how > to fix this. > > > [image: Inline image 1] > > > > > Thanks, > Pankaj > > > On Mon, Mar 11, 2013 at 10:05 PM, ron minnich <rminnich(a)gmail.com> wrote: > >> first question, to start, are you at the point that you can boot >> coreboot at all? That's a first step. >> >> I would *love* to see you get this going, and then we can put it on >> the wiki. Don't hesitate to ask for help. >> >> I'm not on IRC, much, my connectivity is too weird, so email is still >> best for me. >> >> ron >> > >

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New patch to review for coreboot: 9689bab watchdog.h: Fix compile time error on disabling watchdog handling
by Patrick Georgi 11 Mar '13

11 Mar '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2627 -gerrit commit 9689bab5f4381087bc82fa658df325edea1ae03f Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Mar 11 18:32:50 2013 +0100 watchdog.h: Fix compile time error on disabling watchdog handling There's a compile time error that we didn't catch since it's board defaults as used by the build bot won't expose it. Just make watchdog_off() a no-op statement so there aren't any stray semicolons in the preprocessor output. Change-Id: Ib5595e7e8aa91ca54bc8ca30a39b72875c961464 Reported-by: 'lautriv' on irc.freenode.net/#coreboot Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/include/watchdog.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/include/watchdog.h b/src/include/watchdog.h index d626737..b94cd4d 100644 --- a/src/include/watchdog.h +++ b/src/include/watchdog.h @@ -4,7 +4,7 @@ #if CONFIG_USE_WATCHDOG_ON_BOOT void watchdog_off(void); #else -#define watchdog_off() +#define watchdog_off() while(0) {} #endif #endif /* WATCHDOG_H */

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Re: [coreboot] Could some one please give me parameters for QEMU for running Coreboot with Linux payload
by Pankaj Chhabra 11 Mar '13

11 Mar '13

Hello Ron, I would like to get involved in the project. I am running into the issue that Qemu is not loading with the Coreboot with Linux payload. On the same setup Qemu with Seabios payload works fine. I am running Qemu with the attached batch file after replacing the bios.bin with generated coreboot.rom *COREBOOT WITH LINUX PAYLOAD:* * * For now I have built with ROM size of 4MB Built the core boot on Linux Ubuntu 12.04 his is what has been built GEN generated/crt0.romstage.S CC generated/crt0.s CC generated/crt0.romstage.o CC console/console.romstage.o CC generated/bootblock.s CC generated/bootblock.o LINK cbfs/fallback/bootblock.debug OBJCOPY cbfs/fallback/bootblock.elf OBJCOPY cbfs/fallback/bootblock.bin Created CBFS image (capacity = 4193360 bytes) LINK cbfs/fallback/romstage_null.debug OBJCOPY cbfs/fallback/romstage_null.elf OBJCOPY cbfs/fallback/romstage_null.bin GEN generated/romstage_xip.ld LINK cbfs/fallback/romstage_xip.debug OBJCOPY cbfs/fallback/romstage_xip.elf CBFS coreboot.pre CC lib/version.ramstage.o CC drivers/pc80/mc146818rtc.ramstage.o CC console/console.ramstage.o CC arch/x86/boot/smbios.ramstage.o CC generated/coreboot_ram.o CC cbfs/fallback/coreboot_ram.debug OBJCOPY cbfs/fallback/coreboot_ram.elf CBFS coreboot.rom PAYLOAD payload.elf (compression: LZMA) CONFIG .config CBFSPRINT coreboot.rom coreboot.rom: 4096 kB, bootblocksize 848, romsize 4194304, offset 0x0 alignment: 64 bytes Name Offset Type Size cmos_layout.bin 0x0 cmos_layout 1160 fallback/romstage 0x4c0 stage 19197 fallback/coreboot_ram 0x5000 stage 42894 fallback/payload 0xf800 payload 2513834 config 0x275400 raw 2873 (empty) 0x275f80 null 1613016 *RUN* I am running this on Windows Qemo and ran with the following options, I have modified the batch file which comes with the Linux. Please find attached the batch file and ROM image that was built. When I try to run int, I am struck the point below. Please let me know how to fix this. [image: Inline image 1] Thanks, Pankaj On Mon, Mar 11, 2013 at 10:05 PM, ron minnich <rminnich(a)gmail.com> wrote: > first question, to start, are you at the point that you can boot > coreboot at all? That's a first step. > > I would *love* to see you get this going, and then we can put it on > the wiki. Don't hesitate to ask for help. > > I'm not on IRC, much, my connectivity is too weird, so email is still > best for me. > > ron >

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Re: [coreboot] Could some one please give me parameters for QEMU for running Coreboot with Linux payload
by ron minnich 11 Mar '13

11 Mar '13

first question, to start, are you at the point that you can boot coreboot at all? That's a first step. I would *love* to see you get this going, and then we can put it on the wiki. Don't hesitate to ask for help. I'm not on IRC, much, my connectivity is too weird, so email is still best for me. ron

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New patch to review for coreboot: 70ec76c Super i/o W83627DHG UARTB could not function properly.
by Wolfgang Kamp 11 Mar '13

11 Mar '13

Wolfgang Kamp (wmkamp(a)datakamp.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2626 -gerrit commit 70ec76c9f9d7d323cb12ed47726548a240bd9dab Author: Wolfgang Kamp <wmkamp(a)datakamp.de> Date: Mon Mar 11 16:35:42 2013 +0100 Super i/o W83627DHG UARTB could not function properly. Pins 78-85 are set to GPIO after power on or reset. Pins must be redirected to UARTB if enabled. Change-Id: I12b094a60d9c5cb2447a553be4679a4605e19845 Signed-off-by: Wolfgang Kamp <wmkamp(a)datakamp.de> --- src/superio/winbond/w83627dhg/superio.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/src/superio/winbond/w83627dhg/superio.c b/src/superio/winbond/w83627dhg/superio.c index 26f2921..04e9e18 100644 --- a/src/superio/winbond/w83627dhg/superio.c +++ b/src/superio/winbond/w83627dhg/superio.c @@ -14,7 +14,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <arch/io.h> @@ -37,6 +37,16 @@ void pnp_exit_ext_func_mode(device_t dev) outb(0xaa, dev->path.pnp.port); } + static void w83627dhg_enable_UR2(device_t dev) { + u8 reg8; + + pnp_enter_ext_func_mode(dev); + reg8 = pnp_read_config(dev, 0x2c); + reg8 |= (0x3); + pnp_write_config(dev, 0x2c, reg8); // Set pins 78-85-> UART B + pnp_exit_ext_func_mode(dev); +} + static void w83627dhg_init(device_t dev) { struct superio_winbond_w83627dhg_config *conf = dev->chip_info; @@ -45,6 +55,9 @@ static void w83627dhg_init(device_t dev) return; switch(dev->path.pnp.device) { + case W83627DHG_SP2: + w83627dhg_enable_UR2(dev); + break; case W83627DHG_KBC: pc_keyboard_init(&conf->keyboard); break;

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Trac reminder: list of new ticket(s)
by coreboot tracker 11 Mar '13

11 Mar '13

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Patch merged into coreboot/master: 68daf3a pci.h: Drop unused `mainboard_pci_subsystem*` prototypes
by gerrit＠coreboot.org 11 Mar '13

11 Mar '13

the following patch was just integrated into master: commit 68daf3a8757cabb4154c8e2e9712059bab603c3f Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Mar 9 13:24:43 2013 +0100 pci.h: Drop unused `mainboard_pci_subsystem*` prototypes We used to allow mainboards to override subsystems using mainboard_pci_subsystem_vendor_id and mainboard_pci_subsystem_device_id. Mechanisms have changed and the only occurrence of these names is in the header. Change-Id: Ic2ab13201a2740c98868fdf580140b7758b62263 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/2625 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) See http://review.coreboot.org/2625 for details. -gerrit

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Re: [coreboot] AGESA: RunLateApTaskOnAllAPs(..) function and ProbeFilter
by Bao, Zheng 11 Mar '13

11 Mar '13

Yes, it requires IBV to provide a framework to set up the stack and heap to run a task on AP. It seems unreasonable. Zheng > -----Original Message----- > From: Marc Jones [mailto:marcj303@gmail.com] > Sent: Saturday, March 09, 2013 4:38 AM > To: Аладышев Константин; bruce.griffith(a)se-eng.com; Martin Roth; Bao, > Zheng > Cc: coreboot(a)coreboot.org > Subject: Re: [coreboot] AGESA: RunLateApTaskOnAllAPs(..) function and > ProbeFilter > > On Thu, Mar 7, 2013 at 9:53 AM, §Ў§Э§С§Х§н§к§Ц§У §¬§а§Я§г§д§С§Я§д§Ъ§Я > <kostr22(a)rambler.ru> wrote: > > > > AGESA code have two mechanisms to run tasks on AP cores. The first > one is > > used before "Relinquish control of APs", and the second one is used > after > > it. > > > > I doubt in the second one, cause it is used only in probe filter > > initialization (and now OS can't boot with this feature) > > > > I walked "RunLateApTaskOnAllAPs(..)" function [the second mechanism] > step by > > step and didn't find of how system transmits task poinetrs to APs. It > seems > > like code executes on BSC (boot strap core) as many times as APs > present in > > system. > > > > AGESA code is very complicated, we traveles a lot to final function, > that is > > located in the same file. If someone look at code, I drew little > scheme of > > this travel. Here it is: http://tinypic.com/r/25sx7p3/6 Maybe i'am > missing > > something, but I can't see the point, where agesa transmits pointers > to APs. > > > > Also i put LibAmdMsrRead function in DisableAllCaches function and > read MSRs > > containing NodeId and BSC bits. And for all cases of its execution > > DisableAllCaches prints that NodeId=0 and BSC=1. If i didn't mess up, > it > > proves my theory above. > > > > So... How does "RunLateApTaskOnAllAPs(..)" work? > > > > ______________ > > Aladyshev Konstantin > > -- > > coreboot mailing list: coreboot(a)coreboot.org > > http://www.coreboot.org/mailman/listinfo/coreboot > > > I traced the calls and I agree with you. There is a bug here. AGESA > handles the early AP init, but the later init (post memory setup) uses > the callout BiosRunFuncOnAp and it is only running on the BSC, not > being directed to the APs. The re-entry point in AGESA is > AmdLateRunApTaskWrapper. That function clearly states: > > ; Purpose: > ; This entry point is tightly connected with the "AgesaRunFcnOnAp" > ; call out. The AGESA software will call the call-out > "AgesaRunFcnOnAp"; > ; the host environment will then call this entry point to have the > AP > ; execute the requested function. This is needed late in the Post > and > ; Resume branches for running an AP task since the AGESA software > has > ; relinquished control of the APs to the host environment. > ; > ; Dependencies: > ; The host environment must implement the"AgesaRunFcnOnAp" call-out > ; and route execution to the target AP. > > > The coreboot wrapper BiosRunFuncOnAp isn't doing the AP setup and > execution. This needs to be addressed. > > Note, this problem doesn't manifest on APU systems, just multi-node > systems like fam15. > > Marc > > -- > http://se-eng.com

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Could some one please give me parameters for QEMU for running Coreboot with Linux payload
by Pankaj Chhabra 11 Mar '13

11 Mar '13

Hello, Could some one please give me parameters for QEMU for running Coreboot with Linux payload? Thanks, Pankaj

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Patch merged into coreboot/master: ce8410e ASUS M5A88-V: Kconfig: Fix mainboard model name
by gerrit＠coreboot.org 11 Mar '13

11 Mar '13

the following patch was just integrated into master: commit ce8410e1d3c6565d288c4cfd6c315db0e65b968e Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Mar 8 12:10:16 2013 +0100 ASUS M5A88-V: Kconfig: Fix mainboard model name Despite everywhere the model name M5A88-V is used, in Kconfig the string M5A88PM-V is used. Searching for that model string on the WWW does not return anything which is unrelated to coreboot, so change that string to M5A88-V. Change-Id: I25cf9d4a5fc3f9b9356e8616452066ebf873f44c Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2613 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-by: QingPei Wang <wangqingpei(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Mar 8 12:27:54 2013, giving +1 Reviewed-By: QingPei Wang <wangqingpei(a)gmail.com> at Mon Mar 11 07:29:53 2013, giving +2 See http://review.coreboot.org/2613 for details. -gerrit

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coreboot March 2013