coreboot March 2013

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New patch to review for coreboot: 78593b6 lynxpoint: Update device IDs and clock gating setup
by Stefan Reinauer 12 Mar '13

12 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2649 -gerrit commit 78593b6aeecc571f608612be2bc5a46d060a5a3f Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Dec 17 11:31:40 2012 -0800 lynxpoint: Update device IDs and clock gating setup - Add device IDs for lynxpoint mobile and LP variants. - Update the clock gating setup based on BWG - Update the SATA programming based on BWG - Add a DEVSLP0 mux config register Change-Id: Icf4d7bab7f3df7adef5eb7c5e310a6995227a0e5 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/lynxpoint/azalia.c | 2 +- src/southbridge/intel/lynxpoint/chip.h | 5 ++ src/southbridge/intel/lynxpoint/lpc.c | 75 ++++++++++++++++++++--------- src/southbridge/intel/lynxpoint/pcie.c | 12 +++-- src/southbridge/intel/lynxpoint/sata.c | 81 +++++++++++++++++++++----------- 5 files changed, 120 insertions(+), 55 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c index 7b51671..ac2b79d 100644 --- a/src/southbridge/intel/lynxpoint/azalia.c +++ b/src/southbridge/intel/lynxpoint/azalia.c @@ -282,7 +282,7 @@ static void azalia_init(struct device *dev) pci_write_config32(dev, 0xc4, reg32); reg8 = pci_read_config8(dev, 0x43); - reg8 |= (1 << 6); + reg8 |= (1 << 5) | (1 << 6) | (1 << 2) | (1 << 1) | (1 << 0); pci_write_config8(dev, 0x43, reg8); /* Additional programming steps */ diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h index 1e6195b..ffeb977 100644 --- a/src/southbridge/intel/lynxpoint/chip.h +++ b/src/southbridge/intel/lynxpoint/chip.h @@ -69,6 +69,11 @@ struct southbridge_intel_lynxpoint_config { uint8_t sata_port_map; uint32_t sata_port0_gen3_tx; uint32_t sata_port1_gen3_tx; + /* SATA DEVSLP Mux + * 0 = port 0 DEVSLP on DEVSLP0/GPIO33 + * 1 = port 3 DEVSLP on DEVSLP0/GPIO33 + */ + uint8_t sata_devslp_mux; uint32_t gen1_dec; uint32_t gen2_dec; diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 378d624..a44d80f 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -365,38 +365,67 @@ static void enable_hpet(void) static void enable_clock_gating(device_t dev) { +#if CONFIG_INTEL_LYNXPOINT_LP + /* LynxPoint LP */ u32 reg32; u16 reg16; + /* DMI */ RCBA32_AND_OR(0x2234, ~0UL, 0xf); - reg16 = pci_read_config16(dev, GEN_PMCON_1); - reg16 |= (1 << 2) | (1 << 11); + reg16 &= ~((1 << 11) | (1 << 14)); + reg16 |= (1 << 5) | (1 << 6) | (1 << 7) | (1 << 12) | (1 << 13); + reg16 |= (1 << 2); // PCI CLKRUN# Enable pci_write_config16(dev, GEN_PMCON_1, reg16); - pch_iobp_update(0xEB007F07, ~0UL, (1 << 31)); - pch_iobp_update(0xEB004000, ~0UL, (1 << 7)); - pch_iobp_update(0xEC007F07, ~0UL, (1 << 31)); - pch_iobp_update(0xEC004000, ~0UL, (1 << 7)); + reg32 = pci_read_config32(dev, 0x64); + reg32 |= (1 << 6); + pci_write_config32(dev, 0x64, reg32); + + RCBA32_AND_OR(0x2614, 0x8fffffff, 0x0f006500); + RCBA32_OR(0x900, 0x0000031f); reg32 = RCBA32(CG); - reg32 |= (1 << 31); - reg32 |= (1 << 29) | (1 << 28); - reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24); - reg32 |= (1 << 16); - reg32 |= (1 << 17); - reg32 |= (1 << 18); - reg32 |= (1 << 22); - reg32 |= (1 << 23); - reg32 &= ~(1 << 20); - reg32 |= (1 << 19); - reg32 |= (1 << 0); - reg32 |= (0xf << 1); + reg32 |= (1 << 31); // LPC Dynamic + reg32 |= (1 << 30); // LP LPC + reg32 |= (1 << 28); // GPIO Dynamic + reg32 |= (1 << 27); // HPET Dynamic + reg32 |= (1 << 26); // LP LPC + reg32 |= (1 << 22); // HDA Dynamic + reg32 |= (1 << 16); // PCIe Dynamic RCBA32(CG) = reg32; - RCBA32_OR(0x38c0, 0x7); - RCBA32_OR(0x36d4, 0x6680c004); - RCBA32_OR(0x3564, 0x3); + RCBA32_OR(0x3434, 0x7); // LP LPC + + RCBA32_AND_OR(0x333c, 0xff0fffff, 0x00800000); // SATA + + RCBA32_OR(0x38c0, 0x3c07); // SPI Dynamic + + pch_iobp_update(0xCF000000, ~0UL, 0x00007001); + pch_iobp_update(0xCE00C000, ~0UL, 0x00000001); +#else + /* LynxPoint Mobile */ + u32 reg32; + u16 reg16; + + /* DMI */ + RCBA32_AND_OR(0x2234, ~0UL, 0xf); + reg16 = pci_read_config16(dev, GEN_PMCON_1); + reg16 |= (1 << 11) | (1 << 12) | (1 << 14); + reg16 |= (1 << 2); // PCI CLKRUN# Enable + pci_write_config16(dev, GEN_PMCON_1, reg16); + RCBA32_OR(0x900, (1 << 14)); + + reg32 = RCBA32(CG); + reg32 |= (1 << 22); // HDA Dynamic + reg32 |= (1 << 31); // LPC Dynamic + reg32 |= (1 << 16); // PCIe Dynamic + reg32 |= (1 << 27); // HPET Dynamic + reg32 |= (1 << 28); // GPIO Dynamic + RCBA32(CG) = reg32; + + RCBA32_OR(0x38c0, 0x7); // SPI Dynamic +#endif } #if CONFIG_HAVE_SMI_HANDLER @@ -666,6 +695,10 @@ static const unsigned short pci_device_ids[] = { 0x8c4c, /* Q85 SKU */ 0x8c4e, /* Q87 SKU */ 0x8c4f, /* QM87 SKU */ + 0x9c41, /* LP Full Featured Engineering Sample */ + 0x9c43, /* LP Premium SKU */ + 0x9c45, /* LP Mainstream SKU */ + 0x9c47, /* LP Value SKU */ 0 }; static const struct pci_driver pch_lpc __pci_driver = { diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 80cd355..9463d0c 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -260,11 +260,13 @@ static struct device_operations device_ops = { .ops_pci = &pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x1c10, 0x1c12, 0x1c14, 0x1c16, - 0x1c18, 0x1c1a, 0x1c1c, 0x1c1e, - 0x1e10, 0x1e12, 0x1e14, 0x1e16, - 0x1e18, 0x1e1a, 0x1e1c, 0x1e1e, - 0 }; +static const unsigned short pci_device_ids[] = { + /* Lynxpoint Mobile */ + 0x8c10, 0x8c12, 0x8c14, 0x8c16, 0x8c18, 0x8c1a, 0x8c1c, 0x8c1e, + /* Lynxpoint Low Power */ + 0x9c10, 0x9c12, 0x9c14, 0x9c16, 0x9c18, 0x9c1a, + 0 +}; static const struct pci_driver pch_pcie __pci_driver = { .ops = &device_ops, diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 0761323..81d4a1d 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -120,13 +120,37 @@ static void sata_init(struct device *dev) /* for AHCI, Port Enable is managed in memory mapped space */ reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0x3f; /* 6 ports SKU + ORM */ + reg16 &= ~0x3f; reg16 |= 0x8000 | config->sata_port_map; pci_write_config16(dev, 0x92, reg16); + /* Setup register 98h */ + reg32 = pci_read_config16(dev, 0x98); + reg32 |= 1 << 19; /* BWG step 6 */ + reg32 |= 1 << 22; /* BWG step 5 */ + reg32 &= ~(0x3f << 7); + reg32 |= 0x04 << 7; /* BWG step 7 */ + reg32 |= 1 << 20; /* BWG step 8 */ + reg32 &= ~(0x03 << 5); + reg32 |= 1 << 5; /* BWG step 9 */ + reg32 |= 1 << 18; /* BWG step 10 */ + reg32 |= 1 << 29; /* BWG step 11 */ +#if CONFIG_INTEL_LYNXPOINT_LP + reg32 &= ~((1 << 31) | (1 << 30)); + reg32 |= 1 << 23; +#endif + pci_write_config32(dev, 0x98, reg32); + + /* Setup register 9Ch */ + reg16 = 0; /* Disable alternate ID */ + reg16 = 1 << 5; /* BWG step 12 */ + pci_write_config16(dev, 0x9c, reg16); + /* SATA Initialization register */ - pci_write_config32(dev, 0x94, - ((config->sata_port_map ^ 0x3f) << 24) | 0x183); + reg32 = 0x183; + reg32 |= (config->sata_port_map ^ 0x3f) << 24; + reg32 |= (config->sata_devslp_mux & 1) << 15; + pci_write_config32(dev, 0x94, reg32); /* Initialize AHCI memory-mapped space */ abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); @@ -205,31 +229,29 @@ static void sata_init(struct device *dev) config->sata_port1_gen3_tx); /* Additional Programming Requirements */ - sir_write(dev, 0x04, 0x00001600); - sir_write(dev, 0x28, 0xa0000033); - reg32 = sir_read(dev, 0x54); - reg32 &= 0xff000000; - reg32 |= 0x5555aa; - sir_write(dev, 0x54, reg32); - sir_write(dev, 0x64, 0xcccc8484); + /* Power Optimizer */ + sir_write(dev, 0x64, 0x883c9001); + reg32 = sir_read(dev, 0x68); reg32 &= 0xffff0000; - reg32 |= 0xcccc; + reg32 |= 0x880a; sir_write(dev, 0x68, reg32); - reg32 = sir_read(dev, 0x78); - reg32 &= 0x0000ffff; - reg32 |= 0x88880000; - sir_write(dev, 0x78, reg32); - sir_write(dev, 0x84, 0x001c7000); - sir_write(dev, 0x88, 0x88338822); - sir_write(dev, 0xa0, 0x001c7000); - // a4 - sir_write(dev, 0xc4, 0x0c0c0c0c); - sir_write(dev, 0xc8, 0x0c0c0c0c); - sir_write(dev, 0xd4, 0x10000000); - - pch_iobp_update(0xea004001, 0x3fffffff, 0xc0000000); - pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100); + + reg32 = sir_read(dev, 0x60); + reg32 |= (1 << 0) | (1 << 1) | (1 << 3); + sir_write(dev, 0x60, reg32); + + /* Clock Gating */ + sir_write(dev, 0x70, 0x3f00bf1f); +#if CONFIG_INTEL_LYNXPOINT_LP + sir_write(dev, 0x54, 0xcf000f0f); + sir_write(dev, 0x58, 0x00190000); +#endif + + reg32 = pci_read_config32(dev, 0x300); + reg32 |= (1 << 17) | (1 << 16); + reg32 |= (1 << 31) | (1 << 30) | (1 << 29); + pci_write_config32(dev, 0x300, reg32); } static void sata_enable(device_t dev) @@ -278,9 +300,12 @@ static struct device_operations sata_ops = { .ops_pci = &sata_pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x1c00, 0x1c01, 0x1c02, 0x1c03, - 0x1e00, 0x1e01, 0x1e02, 0x1e03, - 0 }; +static const unsigned short pci_device_ids[] = { + 0x8c00, 0x8c02, 0x8c04, 0x8c06, 0x8c08, 0x8c0e, /* Desktop */ + 0x8c01, 0x8c03, 0x8c05, 0x8c07, 0x8c09, 0x8c0f, /* Mobile */ + 0x9c03, 0x9c05, 0x9c07, 0x9c0f, /* Low Power */ + 0 +}; static const struct pci_driver pch_sata __pci_driver = { .ops = &sata_ops,

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New patch to review for coreboot: 961ded0 lynxpoint: Add new GPIO interface for Lynxpoint-LP
by Stefan Reinauer 12 Mar '13

12 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2648 -gerrit commit 961ded07ce0c984b5a5a28253d0c1b9889a3132e Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Dec 17 11:29:10 2012 -0800 lynxpoint: Add new GPIO interface for Lynxpoint-LP The low power variant of the chipset introduces a completely new interface to the GPIOs. This is a 1KB region and so needs to be moved as well so it does not conflict with other IO regions. Also expose the gpio_get functions to ramstage and move the prototypes to pch.h so they can be used for both GPIO interfaces. Change-Id: I20bc18669525af16de8cdf99f0ccfa9612be63ad Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/lynxpoint/Makefile.inc | 10 ++- src/southbridge/intel/lynxpoint/acpi/lpc.asl | 17 +++- src/southbridge/intel/lynxpoint/gpio.c | 20 ++++- src/southbridge/intel/lynxpoint/gpio.h | 24 ++++-- src/southbridge/intel/lynxpoint/lp_gpio.c | 113 +++++++++++++++++++++++++++ src/southbridge/intel/lynxpoint/lp_gpio.h | 110 ++++++++++++++++++++++++++ src/southbridge/intel/lynxpoint/lpc.c | 9 ++- src/southbridge/intel/lynxpoint/pch.h | 35 ++++----- 8 files changed, 307 insertions(+), 31 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index d4522c3..c14a538 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -45,10 +45,18 @@ smm-$(CONFIG_SPI_FLASH_SMM) += spi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c finalize.c -romstage-y += early_usb.c early_smbus.c early_me.c me_status.c gpio.c +romstage-y += early_usb.c early_smbus.c early_me.c me_status.c romstage-$(CONFIG_USBDEBUG) += usb_debug.c romstage-y += reset.c early_spi.c +ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) +romstage-y += lp_gpio.c +ramstage-y += lp_gpio.c +else +romstage-y += gpio.c +ramstage-y += gpio.c +endif + lynxpoint_add_me: $(obj)/coreboot.pre $(IFDTOOL) printf " DD Adding Intel Firmware Descriptor\n" dd if=3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin \ diff --git a/src/southbridge/intel/lynxpoint/acpi/lpc.asl b/src/southbridge/intel/lynxpoint/acpi/lpc.asl index cc59850..03d61eb 100644 --- a/src/southbridge/intel/lynxpoint/acpi/lpc.asl +++ b/src/southbridge/intel/lynxpoint/acpi/lpc.asl @@ -194,7 +194,22 @@ Device (LPCB) IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI //IO (Decode16, 0x800, 0x800, 0x1, 0x10) // ACPI I/O trap IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, 0x1, 0x80) // ICH7-M ACPI - IO (Decode16, DEFAULT_GPIOBASE, DEFAULT_GPIOBASE, 0x1, 0x40) // ICH7-M GPIO + +#if CONFIG_INTEL_LYNXPOINT_LP + // LynxPoint LP GPIO is 1KB + IO (Decode16, DEFAULT_GPIOBASE, + DEFAULT_GPIOBASE, 0x1, 0xff) + IO (Decode16, Add(DEFAULT_GPIOBASE, 0x100), + Add(DEFAULT_GPIOBASE, 0x100), 0x1, 0xff) + IO (Decode16, Add(DEFAULT_GPIOBASE, 0x200), + Add(DEFAULT_GPIOBASE, 0x200), 0x1, 0xff) + IO (Decode16, Add(DEFAULT_GPIOBASE, 0x300), + Add(DEFAULT_GPIOBASE, 0x300), 0x1, 0xff) +#else + // LynxPoint GPIO is 128 bytes + IO (Decode16, DEFAULT_GPIOBASE, + DEFAULT_GPIOBASE, 0x1, DEFAULT_GPIOSIZE) +#endif }) } diff --git a/src/southbridge/intel/lynxpoint/gpio.c b/src/southbridge/intel/lynxpoint/gpio.c index 25eda9a..9d36887 100644 --- a/src/southbridge/intel/lynxpoint/gpio.c +++ b/src/southbridge/intel/lynxpoint/gpio.c @@ -20,16 +20,32 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> + +#ifdef __PRE_RAM__ #include <arch/romcc_io.h> +#else +#include <device/device.h> +#include <device/pci.h> +#endif #include "pch.h" #include "gpio.h" #define MAX_GPIO_NUMBER 75 /* zero based */ +static u16 get_gpio_base(void) +{ +#ifdef __PRE_RAM__ + return pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; +#else + return pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), + GPIO_BASE) & 0xfffc; +#endif +} + void setup_pch_gpios(const struct pch_gpio_map *gpio) { - u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; + u16 gpiobase = get_gpio_base(); /* GPIO Set 1 */ if (gpio->set1.level) @@ -69,7 +85,7 @@ void setup_pch_gpios(const struct pch_gpio_map *gpio) int get_gpio(int gpio_num) { static const int gpio_reg_offsets[] = {0xc, 0x38, 0x48}; - u16 gpio_base = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; + u16 gpio_base = get_gpio_base(); int index, bit; if (gpio_num > MAX_GPIO_NUMBER) diff --git a/src/southbridge/intel/lynxpoint/gpio.h b/src/southbridge/intel/lynxpoint/gpio.h index a6f99f6..20e2eea 100644 --- a/src/southbridge/intel/lynxpoint/gpio.h +++ b/src/southbridge/intel/lynxpoint/gpio.h @@ -20,6 +20,22 @@ #ifndef INTEL_LYNXPOINT_GPIO_H #define INTEL_LYNXPOINT_GPIO_H +/* ICH7 GPIOBASE */ +#define GPIO_USE_SEL 0x00 +#define GP_IO_SEL 0x04 +#define GP_LVL 0x0c +#define GPO_BLINK 0x18 +#define GPI_INV 0x2c +#define GPIO_USE_SEL2 0x30 +#define GP_IO_SEL2 0x34 +#define GP_LVL2 0x38 +#define GPIO_USE_SEL3 0x40 +#define GP_IO_SEL3 0x44 +#define GP_LVL3 0x48 +#define GP_RST_SEL1 0x60 +#define GP_RST_SEL2 0x64 +#define GP_RST_SEL3 0x68 + #define GPIO_MODE_NATIVE 0 #define GPIO_MODE_GPIO 1 #define GPIO_MODE_NONE 1 @@ -150,12 +166,4 @@ struct pch_gpio_map { /* Configure GPIOs with mainboard provided settings */ void setup_pch_gpios(const struct pch_gpio_map *gpio); -/* get GPIO pin value */ -int get_gpio(int gpio_num); -/* - * get a number comprised of multiple GPIO values. gpio_num_array points to - * the array of gpio pin numbers to scan, terminated by -1. - */ -unsigned get_gpios(const int *gpio_num_array); - #endif diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c new file mode 100644 index 0000000..2d2e057 --- /dev/null +++ b/src/southbridge/intel/lynxpoint/lp_gpio.c @@ -0,0 +1,113 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <arch/io.h> +#ifdef __PRE_RAM__ +#include <arch/romcc_io.h> +#else +#include <device/device.h> +#include <device/pci.h> +#endif + +#include "pch.h" +#include "lp_gpio.h" + +static u16 get_gpio_base(void) +{ +#ifdef __PRE_RAM__ + return pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; +#else + return pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), + GPIO_BASE) & 0xfffc; +#endif +} + +void setup_pch_lp_gpios(const struct pch_lp_gpio_map map[]) +{ + u16 gpio_base = get_gpio_base(); + const struct pch_lp_gpio_map *config; + u32 owner[3] = {0}; + u32 route[3] = {0}; + u32 irqen[3] = {0}; + u32 reset[3] = {0}; + u32 blink = 0; + int set, bit; + + for (config = map; config->gpio != GPIO_LIST_END; config++) { + if (config->gpio > MAX_GPIO_NUMBER) + continue; + + /* Setup Configuration registers 1 and 2 */ + outl(config->conf0, gpio_base + GPIO_CONFIG0(config->gpio)); + outl(config->conf1, gpio_base + GPIO_CONFIG1(config->gpio)); + + /* Determine set and bit based on GPIO number */ + set = config->gpio >> 5; + bit = config->gpio % 32; + + /* Apply settings to set specific bits */ + owner[set] |= config->owner << bit; + route[set] |= config->route << bit; + irqen[set] |= config->irqen << bit; + reset[set] |= config->reset << bit; + + if (set == 0) + blink |= config->blink << bit; + } + + for (set = 0; set <= 2; set++) { + outl(owner[set], gpio_base + GPIO_OWNER(set)); + outl(route[set], gpio_base + GPIO_ROUTE(set)); + outl(irqen[set], gpio_base + GPIO_IRQ_IE(set)); + outl(reset[set], gpio_base + GPIO_RESET(set)); + } + + outl(blink, gpio_base + GPIO_BLINK); +} + +int get_gpio(int gpio_num) +{ + u16 gpio_base = get_gpio_base(); + + if (gpio_num < MAX_GPIO_NUMBER) + return 0; + + return !!(inl(gpio_base + GPIO_CONFIG0(gpio_num)) & GPI_LEVEL); +} + +/* + * get a number comprised of multiple GPIO values. gpio_num_array points to + * the array of gpio pin numbers to scan, terminated by -1. + */ +unsigned get_gpios(const int *gpio_num_array) +{ + int gpio; + unsigned bitmask = 1; + unsigned vector = 0; + + while (bitmask && + ((gpio = *gpio_num_array++) != -1)) { + if (get_gpio(gpio)) + vector |= bitmask; + bitmask <<= 1; + } + return vector; +} diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.h b/src/southbridge/intel/lynxpoint/lp_gpio.h new file mode 100644 index 0000000..067b6e2 --- /dev/null +++ b/src/southbridge/intel/lynxpoint/lp_gpio.h @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef INTEL_LYNXPOINT_LP_GPIO_H +#define INTEL_LYNXPOINT_LP_GPIO_H + +/* LynxPoint LP GPIOBASE Registers */ +#define GPIO_OWNER(set) (0x00 + ((set) * 4)) +#define GPIO_PIRQ_APIC_EN 0x10 +#define GPIO_BLINK 0x18 +#define GPIO_SER_BLINK 0x1c +#define GPIO_SER_BLINK_CS 0x20 +#define GPIO_SER_BLINK_DATA 0x24 +#define GPIO_ROUTE(set) (0x30 + ((set) * 4)) +#define GPIO_ALT_GPI_SMI_STS 0x50 +#define GPIO_ALT_GPI_SMI_EN 0x54 +#define GPIO_RESET(set) (0x60 + ((set) * 4)) +#define GPIO_GLOBAL_CONFIG 0x7c +#define GPIO_IRQ_IS(set) (0x80 + ((set) * 4)) +#define GPIO_IRQ_IE(set) (0x90 + ((set) * 4)) +#define GPIO_CONFIG0(gpio) (0x100 + ((gpio) * 8)) +#define GPIO_CONFIG1(gpio) (0x104 + ((gpio) * 8)) + +#define MAX_GPIO_NUMBER 94 /* zero based */ +#define GPIO_LIST_END 0xff + +/* conf0 */ + +#define GPIO_MODE_NATIVE (0 << 0) +#define GPIO_MODE_GPIO (1 << 0) + +#define GPIO_DIR_OUTPUT (0 << 2) +#define GPIO_DIR_INPUT (1 << 2) + +#define GPIO_NO_INVERT (0 << 3) +#define GPIO_INVERT (1 << 3) + +#define GPIO_IRQ_EDGE (0 << 4) +#define GPIO_IRQ_LEVEL (1 << 4) + +#define GPI_LEVEL (1 << 30) + +#define GPO_LEVEL_LOW (0 << 31) +#define GPO_LEVEL_HIGH (1 << 31) + +/* conf1 */ + +#define GPIO_PULL_NONE (0 << 0) +#define GPIO_PULL_DOWN (1 << 0) +#define GPIO_PULL_UP (2 << 0) + +#define GPIO_SENSE_ENABLE (0 << 2) +#define GPIO_SENSE_DISABLE (1 << 2) + +/* owner */ + +#define GPIO_OWNER_ACPI 0 +#define GPIO_OWNER_GPIO 1 + +/* route */ + +#define GPIO_ROUTE_SCI 0 +#define GPIO_ROUTE_SMI 1 + +/* irqen */ + +#define GPIO_IRQ_DISABLE 0 +#define GPIO_IRQ_ENABLE 1 + +/* blink */ + +#define GPO_NO_BLINK 0 +#define GPO_BLINK 1 + +/* reset */ + +#define GPIO_RESET_PWROK 0 +#define GPIO_RESET_RSMRST 1 + +struct pch_lp_gpio_map { + u8 gpio; + u32 conf0; + u32 conf1; + u8 owner; + u8 route; + u8 irqen; + u8 reset; + u8 blink; +} __attribute__ ((packed)); + +/* Configure GPIOs with mainboard provided settings */ +void setup_pch_lp_gpios(const struct pch_lp_gpio_map map[]); + +#endif diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index a121e49..378d624 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -561,13 +561,20 @@ static void pch_lpc_read_resources(device_t dev) res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + /* GPIOBASE */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); + res->base = DEFAULT_GPIOBASE; + res->size = DEFAULT_GPIOSIZE; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); res->base = 0xff800000; res->size = 0x00800000; /* 8 MB for flash */ res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - res = new_resource(dev, 3); /* IOAPIC */ + res = new_resource(dev, io_index++); /* IOAPIC */ res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 81e0131..fa8d75f 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -63,10 +63,16 @@ */ #define SMBUS_IO_BASE 0x0400 #define SMBUS_SLAVE_ADDR 0x24 -/* TODO Make sure these don't get changed by stage2 */ -#define DEFAULT_GPIOBASE 0x0480 #define DEFAULT_PMBASE 0x0500 +#if CONFIG_INTEL_LYNXPOINT_LP +#define DEFAULT_GPIOBASE 0x1000 +#define DEFAULT_GPIOSIZE 0x400 +#else +#define DEFAULT_GPIOBASE 0x480 +#define DEFAULT_GPIOSIZE 0x80 +#endif + #define HPET_ADDR 0xfed00000 #define DEFAULT_RCBA 0xfed1c000 @@ -97,6 +103,15 @@ void enable_usb_bar(void); int smbus_read_byte(unsigned device, unsigned address); int early_spi_read(u32 offset, u32 size, u8 *buffer); #endif +/* + * get GPIO pin value + */ +int get_gpio(int gpio_num); +/* + * get a number comprised of multiple GPIO values. gpio_num_array points to + * the array of gpio pin numbers to scan, terminated by -1. + */ +unsigned get_gpios(const int *gpio_num_array); #endif #define MAINBOARD_POWER_OFF 0 @@ -434,22 +449,6 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define PCH_DISABLE_MEI1 (1 << 1) #define PCH_ENABLE_DBDF (1 << 0) -/* ICH7 GPIOBASE */ -#define GPIO_USE_SEL 0x00 -#define GP_IO_SEL 0x04 -#define GP_LVL 0x0c -#define GPO_BLINK 0x18 -#define GPI_INV 0x2c -#define GPIO_USE_SEL2 0x30 -#define GP_IO_SEL2 0x34 -#define GP_LVL2 0x38 -#define GPIO_USE_SEL3 0x40 -#define GP_IO_SEL3 0x44 -#define GP_LVL3 0x48 -#define GP_RST_SEL1 0x60 -#define GP_RST_SEL2 0x64 -#define GP_RST_SEL3 0x68 - /* ICH7 PMBASE */ #define PM1_STS 0x00 #define WAK_STS (1 << 15)

1 0

New patch to review for coreboot: 7dff566 haswell: Add ULT CPUID and updated microcode
by Stefan Reinauer 12 Mar '13

12 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2647 -gerrit commit 7dff566d0dda1aa999570527db69be8ef13ad750 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Dec 17 11:24:45 2012 -0800 haswell: Add ULT CPUID and updated microcode This adds microcode ffff000a and the CPUIDs for ULT. Change-Id: I341c1148a355d8373b31032b9f209232bd03230a Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/cpu/intel/haswell/haswell_init.c | 3 +- .../intel/haswell/microcode-M7240650_ffff000a.h | 1409 ++++++++++++++++++++ src/cpu/intel/haswell/microcode_blob.h | 2 +- 3 files changed, 1412 insertions(+), 2 deletions(-) diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 9984c55..762b7e8 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -566,7 +566,8 @@ static struct device_operations cpu_dev_ops = { static struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, 0x306c1 }, /* Intel Haswell 4+2 A0 */ { X86_VENDOR_INTEL, 0x306c2 }, /* Intel Haswell 4+2 B0 */ - { X86_VENDOR_INTEL, 0x40660 }, /* Intel Haswell 4+3 B0 */ + { X86_VENDOR_INTEL, 0x40650 }, /* Intel Haswell ULT B0 */ + { X86_VENDOR_INTEL, 0x40651 }, /* Intel Haswell ULT B1 */ { 0, 0 }, }; diff --git a/src/cpu/intel/haswell/microcode-M7240650_ffff000a.h b/src/cpu/intel/haswell/microcode-M7240650_ffff000a.h new file mode 100644 index 0000000..00be3bf --- /dev/null +++ b/src/cpu/intel/haswell/microcode-M7240650_ffff000a.h @@ -0,0 +1,1409 @@ +/* 0x40650 built on 11092012 */ +0x00000001, 0xffff000a, 0x11092012, 0x00040650, +0x52f85222, 0x00000001, 0x00000072, 0x000057d0, +0x00005800, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x000000a1, 0x00020001, 0xffff000a, +0x00000000, 0x00001521, 0x20121109, 0x00001521, +0x00000001, 0x00040650, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x73116830, 0x4311ec75, 0x6c65c019, 0xd560f905, +0xadd9aaae, 0x0bd5e6d2, 0x08d55aa7, 0x7238df8f, +0xa19308a3, 0x5b19c4b7, 0x4a1b425b, 0x7d6a74f6, +0x81624193, 0x3a559605, 0x5475280b, 0xe7319d58, +0x48624ca7, 0x507af030, 0x3b32d96a, 0x30164068, +0x5284d2f5, 0x725b2915, 0xf63c9280, 0x44b7c142, +0xe67ca7b3, 0xd6f163e7, 0xcdf51f3c, 0x41d180a1, +0xcc3931b1, 0xf7a544a9, 0x7f6bf77d, 0xfc45a45f, +0xf0985836, 0x652d7e2e, 0x0324b1f3, 0x24b9548c, +0x7bcae7a5, 0xdcdebf79, 0x27015922, 0x0c83c606, +0x3d2ceeb7, 0x61c5eec8, 0x6b6899c6, 0x3e500531, +0xf08bfa44, 0xb304a8f4, 0xcee8f713, 0x2912c786, +0xfae6c34c, 0xa5292960, 0x7d63e389, 0xaa257a01, +0x1fb25054, 0x963fc676, 0x5bcb9fd3, 0x58f369a4, +0xf6e3beb2, 0xa58b5eb0, 0x33c7eba4, 0x37fe8b66, +0x00714403, 0xf0fd0c4e, 0xaa122996, 0x9a55b184, +0x00201507, 0xc9fb6e3a, 0x11ab60c8, 0x80ff6e84, +0xc37aabdd, 0x0fc23175, 0xb0b18c34, 0xf1ec806c, +0x00000011, 0x4d007130, 0xe18a8db9, 0x00e12a21, +0x9ac2f6fc, 0x2c2928e7, 0x12f59031, 0xa8537092, +0x5199676d, 0xb2799a43, 0xdfd64883, 0xf5422f7a, +0x1b47a43e, 0xff56c423, 0xff88e92c, 0x148259c9, +0x21c3b30e, 0xdd8810f4, 0x57c65f77, 0x056c9bda, +0x590ffd61, 0x6ac6e03c, 0x8e0c89b0, 0xfe64455c, +0x10954822, 0x13834f62, 0x5dc13089, 0x07932b6a, +0xe378fbf1, 0xd86733da, 0x98af05e2, 0x0f1ee23e, +0x8a5ae531, 0xb72b23a8, 0x0600db49, 0x4fd50898, +0xabf583a3, 0x0b65d6b6, 0x40d1ecd4, 0x421698a2, +0x7fa073c7, 0xd1e77761, 0x08089e2e, 0xf846ba4f, +0x70e59471, 0x18135eef, 0x29dcef3e, 0xc8394e33, +0xb7bd3ba1, 0x763bb851, 0x0fa91439, 0xeac0e740, +0xcd1c13a6, 0x06dcd26a, 0x516f3855, 0x23d4c206, +0xe42e29c5, 0x59241b8f, 0x59a2977a, 0x748af9e2, +0xf69cc824, 0xa77c9e70, 0x9f8bd61b, 0xd0af7d25, +0x78111584, 0x49f7ec19, 0xd880d42a, 0xa7416dec, +0xd35f18e1, 0x21580808, 0x44003344, 0x8205ed2b, +0x85ad44ff, 0xe08a8031, 0x43c266c5, 0xbf351b00, +0xf63509fc, 0x112ce9dd, 0x417376eb, 0x93ea223e, +0xbb69570d, 0xfc58b2c4, 0xab61b02c, 0xf3b0398f, +0xd2204713, 0xa1049704, 0x008b46c4, 0xb1343e02, +0xa1ac159e, 0xe569c1e0, 0x5e17fe48, 0x8b145280, +0xbe443260, 0x65cf024c, 0xfdf9cb96, 0x8f22694c, +0xa64b6dd2, 0x6a5ca7d7, 0x148cc1b9, 0x6974394d, +0x1c433133, 0x23cb2a59, 0x8f63f3d2, 0xe1823fb5, +0x6c262522, 0xae9248cf, 0xc9ecd2a3, 0xdbdd038e, +0x8c36bf3c, 0x804d4195, 0xd774b24d, 0x63307563, +0xa662245a, 0x7cb4cdb3, 0x0853e543, 0x022b31ed, +0x37064a88, 0x09275104, 0xcd0ecf65, 0xc944da4b, +0xf11df7cd, 0xecb93fea, 0xe231b5ce, 0x251c4513, +0x7eb69bd1, 0x9a5dd26a, 0x54d42b69, 0x9ee18e95, +0x5a0d5f74, 0x07023736, 0x10abd716, 0x3b21394f, +0x593a8083, 0x209e0caa, 0xec2a572a, 0x19fb4c0f, +0x00d71557, 0x68b3aa4f, 0x3e605451, 0x65419880, +0xd4d393ad, 0xfcdf34e6, 0xd095f9e7, 0x1133979d, +0x26013c2a, 0xab90d805, 0xa382ef4e, 0xa90a80d8, +0x34f2977d, 0x2031a7b1, 0xc258d21d, 0x40a09b5d, +0x0288e52f, 0xf6e27a20, 0xbf3398e9, 0x2a050f1c, +0x8fbb1c47, 0x669763c5, 0xc6f9f40e, 0xd4381505, +0xd6103bb1, 0x4afff3ca, 0xaa4d7dfd, 0xe72f7085, +0x40c5608d, 0x9f8ce280, 0x64284ffd, 0xbecb67cd, +0x031e7e32, 0x54ccaf3e, 0x1e1b2142, 0x98909d7c, +0xa4407a72, 0xa3afb65d, 0xb7412270, 0x4a059fd8, +0x7394dd13, 0x0c1109f2, 0x1ee74959, 0x7128dace, +0x3f8ce909, 0x7757586a, 0x89b9e481, 0x5fda8cc7, +0x958d9112, 0x50470139, 0xb7758ff5, 0x7df7dc2d, +0xe59a55a0, 0xed94f597, 0x1d2f23c7, 0x0d55c46c, +0xd27f78fe, 0x7dce61aa, 0xbbdda622, 0x787571e3, +0xa0563d9e, 0xb5021423, 0x395b60dd, 0x4aed19f7, +0x66e37c24, 0x96d13578, 0xcc04aef0, 0xcfd367a1, +0xaf456650, 0x6df3ad17, 0xa6461772, 0x947c6657, +0xe4089031, 0xf123f547, 0xe60725b4, 0x62f46d65, +0xdef77f65, 0xdf1faf10, 0x5040451c, 0x2fd3a0dd, +0x8b93f3dc, 0xd8176f3d, 0x8012c4cb, 0x896c10e2, +0x4d397593, 0x54930ba7, 0x656dde1a, 0xc4d3b350, +0xfa62bc04, 0xbd04ede8, 0x3e8742c7, 0xf6c17a0f, +0x1fd3c352, 0x0f27ff8a, 0x82fb150e, 0x6b702ed2, +0x8eca76b9, 0xf6111c70, 0xb358490d, 0x2e5410e1, +0xa5ba3227, 0x5502b30e, 0x7a2d4da8, 0xc44b0c7e, +0x6d7c1b98, 0x19dbe903, 0x53008a32, 0x214db13c, +0x2e519b45, 0x915bb046, 0x3829a2e6, 0x3c5fffaf, +0x9fd7169d, 0x7259df0f, 0x36157dd0, 0x173437dd, +0xc494e1ce, 0x14046445, 0x9c89e9e4, 0x4aaa8c5b, +0xa7fb9495, 0xbf12ea08, 0x06aef6d4, 0xbab24dca, +0x6b90d8c2, 0x531505cd, 0xcaff9d80, 0xadeba126, +0xb99230e9, 0x4502ddb6, 0xbb9cc5f2, 0x65ee6697, +0xb3e24ec0, 0x6bbe85be, 0xf032a3a3, 0x43006dbb, +0xf0c0156a, 0x3ccf4ff3, 0xb0fba95f, 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0x4e83b288, 0x88a6bc9b, 0x3d55567b, +0x6fe2cda8, 0x6aa879a5, 0xa48cc2c7, 0x0405b8d2, +0x8ad77a54, 0xe4d9d605, 0xb464bd05, 0xe3f4d3ab, +0x1faac0b5, 0xb4dfed33, 0xc3aaa6bd, 0x9bcdbedb, +0xaf64be94, 0x95ca5d5f, 0xa7e18ff0, 0x26ad1d61, +0x0ce618e9, 0x23405771, 0x517e4b8d, 0xda23cd2d, +0x6b702f50, 0xa7b9c929, 0x7299baae, 0x43cc91b8, +0x7f49c2b7, 0xc0cbee2f, 0xa96df198, 0xff64b8c5, +0x68c76448, 0x7b0d4438, 0x187ed6ed, 0x983ba398, +0xa48bf706, 0x90444918, 0xdd7c6871, 0xdaf99db2, +0xb931c8d5, 0x7fb41420, 0xfde1ea95, 0x106d3d8c, +0xc22326e4, 0x96afc231, 0x90ddf4a6, 0x5cf50bdb, +0x4db37973, 0x047b6850, 0x95560180, 0x996e6e3e, +0xdfe7ccf4, 0x8220448a, 0x32156b28, 0xfbaeda54, +0x6eac9114, 0xebce3179, 0x154c7dbc, 0xcdf426a3, +0x57404025, 0x66ddf4c7, 0x481d9c7e, 0x45de66cd, +0xa02393ea, 0x5491dd71, 0x11df49ff, 0x44c320f0, +0xd5d1e6d3, 0x5f2b4aaa, 0x762642a9, 0x6c8bd246, +0x740a6315, 0x640420a6, 0x6fe3bf2f, 0x7d5fa94b, +0x9890ab42, 0xda96e4a6, 0x4b1f62a1, 0x61c81409, +0xaf6fba36, 0x9dc73610, 0x661c4e1e, 0xa81c414d, +0xe459d28a, 0xa9df9e70, 0x31e7527e, 0x694dfbe6, +0x67a777e7, 0x76e93ea3, 0x81aa3e5a, 0xc67b5739, +0x00f296da, 0x1478b395, 0x1737d544, 0x37dc7cb5, +0xfc703215, 0x110ea94a, 0xe2af1330, 0xe0dc8a07, +0x3b7c262b, 0x8492f71b, 0x9a3afd4b, 0xfe81d817, +0x13f8d741, 0x4aa7cc66, 0x262367c7, 0x4e833321, +0xb565e649, 0x96bf691a, 0xdce2c657, 0xfe9e8480, +0xfdef5da1, 0x914319cf, 0xb1df5367, 0x4cfa2ef6, +0x04c41f50, 0x9a2fb365, 0x48ed984a, 0x83d7e688, +0x2275c128, 0x22f19657, 0x57dca6e2, 0x63b81d43, +0xeb2d6d83, 0xce77562e, 0xde962383, 0x60c53674, +0x620ed171, 0xabb17dd7, 0x85a3941b, 0x5127922a, +0xa7f99b84, 0xebf38db4, 0xe20c47d4, 0x4b852b11, +0x8b83908e, 0x6c033cba, 0x74f890bc, 0x7dfaf103, +0xaafec5fd, 0xc3ba39f0, 0xfc87f72e, 0xb71842c8, +0x4cb323ba, 0x55832812, 0x12ad8506, 0x33dbe9fb, +0xacc4e99f, 0x0425514a, 0x262544dd, 0x069ac3fe, +0x436096f3, 0xca9a9d29, 0x90b897cc, 0x1464d373, +0x71253c8d, 0x6eeaa753, 0xed70127c, 0x3747cdb2, +0x12edf472, 0xee45719d, 0xd871288b, 0x8d78581e, +0xb963f429, 0x0dcf107b, 0xf1970b79, 0x5e5c1163, +0xa40c710b, 0xb0eddcff, 0x5209c8af, 0x47e532ed, +0x2ab55848, 0x32ea2bd6, 0xa463e051, 0x97c40f38, +0xf366ae71, 0x075744f2, 0xb63344f4, 0xcd61f1b6, +0x2e4844c0, 0x517b5bdc, 0xa8d7f25e, 0x429fed6e, +0x1432545c, 0xf8a794d1, 0xdf060fee, 0xe2d9f7a1, +0x0faf7a68, 0xfc58b731, 0x638de155, 0xa89c4405, +0x4bc58195, 0x706f09d9, 0xcd0d9eb7, 0x54133862, +0xdecc6074, 0x96ebfa73, 0x91beab64, 0x6d2375b9, +0x6b12d5e3, 0x01e39cd9, 0x558c88bd, 0x2da66527, +0xda2b1730, 0x85c7c409, 0xfc0550f3, 0x61566f37, +0xcb1e15e1, 0x090d725d, 0x2efc7bb7, 0xa2428457, +0x66d2fd2e, 0xebd2a2f1, 0x99d12d0a, 0x99e8e59c, +0x916da9b2, 0xd725fa6c, 0x50bb54bd, 0x18522d11, +0xda8407c9, 0x40fbc1a1, 0xba91735c, 0xe3c66d34, +0x215a77a1, 0xd6f6a8bb, 0xdae9ef86, 0x1cefdf6b, diff --git a/src/cpu/intel/haswell/microcode_blob.h b/src/cpu/intel/haswell/microcode_blob.h index 1752e73..b37ff21 100644 --- a/src/cpu/intel/haswell/microcode_blob.h +++ b/src/cpu/intel/haswell/microcode_blob.h @@ -20,7 +20,7 @@ #include "microcode-M32306c1_ffff000d.h" #include "microcode-M32306c2_ffff0003.h" #include "microcode-M3240660_ffff000b.h" -#include "microcode-M7240650_ffff0007.h" +#include "microcode-M7240650_ffff000a.h" /* Dummy terminator */ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,

1 0

New patch to review for coreboot: 40da02d haswell: Add ULT device IDs
by Stefan Reinauer 12 Mar '13

12 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2646 -gerrit commit 40da02d497ab66a1ee52e7f6cb61106ca4b87378 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Dec 17 11:22:57 2012 -0800 haswell: Add ULT device IDs Device IDs for northbridge and GPU. Also mask off the lock bit in the memory map registers. Change-Id: I9a4955d4541b938285712e82dd0b1696fa272b63 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/northbridge/intel/haswell/gma.c | 18 +++++++++++++++--- src/northbridge/intel/haswell/northbridge.c | 12 +++++++++--- 2 files changed, 24 insertions(+), 6 deletions(-) diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 08c13df..03a8e79 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -659,9 +659,21 @@ static struct device_operations gma_func0_ops = { .ops_pci = &gma_pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x0102, 0x0106, 0x010a, 0x0112, - 0x0116, 0x0122, 0x0126, 0x0166, - 0 }; +static const unsigned short pci_device_ids[] = { + 0x0402, /* Desktop GT1 */ + 0x0412, /* Desktop GT2 */ + 0x0422, /* Desktop GT3 */ + 0x0406, /* Mobile GT1 */ + 0x0416, /* Mobile GT2 */ + 0x0426, /* Mobile GT3 */ + 0x0d16, /* Mobile 4+3 GT1 */ + 0x0d26, /* Mobile 4+3 GT2 */ + 0x0d36, /* Mobile 4+3 GT3 */ + 0x0a06, /* ULT GT1 */ + 0x0a16, /* ULT GT2 */ + 0x0a26, /* ULT GT3 */ + 0, +}; static const struct pci_driver pch_lpc __pci_driver = { .ops = &gma_func0_ops, diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 52b24ba..5731077 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -175,15 +175,15 @@ static void pci_domain_set_resources(device_t dev) /* Top of Upper Usable DRAM, including remap */ touud = pci_read_config32(dev, TOUUD+4); touud <<= 32; - touud |= pci_read_config32(dev, TOUUD); + touud |= pci_read_config32(dev, TOUUD) & ~1; /* Top of Lower Usable DRAM */ - tolud = pci_read_config32(dev, TOLUD); + tolud = pci_read_config32(dev, TOLUD) & ~1; /* Top of Memory - does not account for any UMA */ tom = pci_read_config32(dev, 0xa4); tom <<= 32; - tom |= pci_read_config32(dev, 0xa0); + tom |= pci_read_config32(dev, 0xa0) & ~1; printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", touud, tolud, tom); @@ -467,6 +467,12 @@ static const struct pci_driver mc_driver_hsw_mobile __pci_driver = { .device = 0x0c04, /* Mobile Haswell */ }; +static const struct pci_driver mc_driver_hsw_ult __pci_driver = { + .ops = &mc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x0a04, /* ULT Haswell */ +}; + static void cpu_bus_init(device_t dev) { initialize_cpus(dev->link_list);

1 0

New patch to review for coreboot: db83cd5 lynxpoint: Add Kconfig entry for Low Power chipset
by Stefan Reinauer 12 Mar '13

12 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2645 -gerrit commit db83cd507a0a21ed7d142b0a05234d1c2b981a85 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Dec 17 11:11:26 2012 -0800 lynxpoint: Add Kconfig entry for Low Power chipset There are enough subtle differences that it is useful to have a Kconfig entry to differentiate the ULT/LP chipet from the desktop/mobile versions. Change-Id: I04ca1bc6f90bcf9e6994ea7125c98347e8def898 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/lynxpoint/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index e1d0e35..6f5bfe2 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -32,6 +32,12 @@ config SOUTH_BRIDGE_OPTIONS # dummy select PCIEXP_COMMON_CLOCK select SPI_FLASH +config INTEL_LYNXPOINT_LP + bool + default n + help + Set this option to y for Lynxpont LP (Haswell ULT). + config EHCI_BAR hex default 0xfef00000

1 0

New patch to review for coreboot: a3b0a71 intel: update fit table defaults to be valid
by Stefan Reinauer 12 Mar '13

12 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2644 -gerrit commit a3b0a71fd817fdcc3a1a44cc3d4e10576c3f3126 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Dec 14 16:49:22 2012 -0600 intel: update fit table defaults to be valid There were 2 things wrong with the existing fit table: 1. The version number was incorrect. 2. The checksum wasn't correct when calculating over the table. Change-Id: Idaf942e5d93887e86b36abe817c76f8aa1cdc1ff Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/fit/fit.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cpu/intel/fit/fit.inc b/src/cpu/intel/fit/fit.inc index 57a2665..e4595c0 100644 --- a/src/cpu/intel/fit/fit.inc +++ b/src/cpu/intel/fit/fit.inc @@ -20,11 +20,11 @@ fit_table: */ .long 0x00000001 /* Version */ -.word 0x1000 +.word 0x0100 /* Type 0 with checksum valid. */ .byte 0x80 /* Checksum byte - must add to zero. */ -.byte 0x6e +.byte 0x7d .fill CONFIG_CPU_INTEL_NUM_FIT_ENTRIES*16 fit_table_end: .previous

1 0

New patch to review for coreboot: c8071f3 haswell: remove GPIO60 memory reset gate on S3 transition
by Stefan Reinauer 12 Mar '13

12 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2643 -gerrit commit c8071f38775c4f5241f744b752b6dfc7be81f306 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Dec 12 09:22:34 2012 -0800 haswell: remove GPIO60 memory reset gate on S3 transition This is no longer tied to a GPIO but has a proper chipset pin. Change-Id: Iba70338e8c67e3c3c1cb32e69bfea1282fda8cb5 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/lynxpoint/smihandler.c | 38 ---------------------------- 1 file changed, 38 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index d31e350..7c982d1 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -290,41 +290,6 @@ static void busmaster_disable_on_bus(int bus) } } -/* - * Drive GPIO 60 low to gate memory reset in S3. - * - * Intel reference designs all use GPIO 60 but it is - * not a requirement and boards could use a different pin. - */ -static void southbridge_gate_memory_reset(void) -{ - u32 reg32; - u16 gpiobase; - - gpiobase = pci_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc; - if (!gpiobase) - return; - - /* Make sure it is set as GPIO */ - reg32 = inl(gpiobase + GPIO_USE_SEL2); - if (!(reg32 & (1 << 28))) { - reg32 |= (1 << 28); - outl(reg32, gpiobase + GPIO_USE_SEL2); - } - - /* Make sure it is set as output */ - reg32 = inl(gpiobase + GP_IO_SEL2); - if (reg32 & (1 << 28)) { - reg32 &= ~(1 << 28); - outl(reg32, gpiobase + GP_IO_SEL2); - } - - /* Drive the output low */ - reg32 = inl(gpiobase + GP_LVL2); - reg32 &= ~(1 << 28); - outl(reg32, gpiobase + GP_LVL2); -} - static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save) { u8 reg8; @@ -372,9 +337,6 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat case 5: printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); - /* Gate memory reset */ - southbridge_gate_memory_reset(); - /* Invalidate the cache before going to S3 */ wbinvd(); break;

1 0

New patch to review for coreboot: be78dea x86 intel: Add Firmware Interface Table support
by Stefan Reinauer 12 Mar '13

12 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2642 -gerrit commit be78dea4076ab383b19b017415b10ce217cf94ec Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Dec 3 16:17:40 2012 -0600 x86 intel: Add Firmware Interface Table support Haswell CPUs require a FIT table in the firmware. This commit adds rudimentary support for a FIT table. The number of entries in the table is based on a configuration option. The code only generates a type 0 entry. A follow-on tool will need to be developed to populate the FIT entries as well as checksumming the table. Verified image has a FIT pointer and table when option is selected. Change-Id: I3a314016a09a1cc26bf1fb5d17aa50853d2ef4f8 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/Makefile.inc | 6 ++++++ src/cpu/intel/Kconfig | 2 ++ src/cpu/intel/fit/Kconfig | 12 ++++++++++++ src/cpu/intel/fit/fit.inc | 30 ++++++++++++++++++++++++++++++ src/cpu/intel/fit/fit.lds | 6 ++++++ src/cpu/intel/haswell/Kconfig | 1 + 6 files changed, 57 insertions(+) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 0892efd..cc7bfc2 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -299,12 +299,18 @@ bootblock_lds += $(src)/cpu/x86/16bit/entry16.lds bootblock_lds += $(src)/cpu/x86/16bit/reset16.lds bootblock_lds += $(src)/arch/x86/lib/id.lds bootblock_lds += $(chipset_bootblock_lds) +ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) +bootblock_lds += $(src)/cpu/intel/fit/fit.lds +endif bootblock_inc = $(src)/arch/x86/init/prologue.inc bootblock_inc += $(src)/cpu/x86/16bit/entry16.inc bootblock_inc += $(src)/cpu/x86/16bit/reset16.inc bootblock_inc += $(src)/cpu/x86/32bit/entry32.inc bootblock_inc += $(src)/arch/x86/lib/id.inc +ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) +bootblock_inc += $(src)/cpu/intel/fit/fit.inc +endif bootblock_inc += $(chipset_bootblock_inc) ifeq ($(CONFIG_SSE),y) diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index 45071d0..106ce1d 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -33,3 +33,5 @@ source src/cpu/intel/socket_441/Kconfig source src/cpu/intel/socket_LGA771/Kconfig source src/cpu/intel/socket_LGA775/Kconfig source src/cpu/intel/socket_rPGA989/Kconfig +# Architecture specific features +source src/cpu/intel/fit/Kconfig diff --git a/src/cpu/intel/fit/Kconfig b/src/cpu/intel/fit/Kconfig new file mode 100644 index 0000000..e619b31 --- /dev/null +++ b/src/cpu/intel/fit/Kconfig @@ -0,0 +1,12 @@ +config CPU_INTEL_FIRMWARE_INTERFACE_TABLE + def_bool n + help + This option selects building a Firmware Interface Table + +config CPU_INTEL_NUM_FIT_ENTRIES + int + default 4 + depends on CPU_INTEL_FIRMWARE_INTERFACE_TABLE + help + This option selects the number of empty FIT entries in the FIT table. + diff --git a/src/cpu/intel/fit/fit.inc b/src/cpu/intel/fit/fit.inc new file mode 100644 index 0000000..57a2665 --- /dev/null +++ b/src/cpu/intel/fit/fit.inc @@ -0,0 +1,30 @@ +.section ".fit_pointer", "a", @progbits + .code32 +.global fit_pointer +fit_pointer: +.long fit_table +.long 0 +.previous + +.section ".rom.data", "a", @progbits +.align 16 +.global fit_table +.global fit_table_end +fit_table: +/* Address for type 0 is '_FIT_ ' */ +.long 0x5449465f +.long 0x2020205f +/* + * There is 1 entry in the table. Other tools will have to update the size + * and checksum when adding entries. + */ +.long 0x00000001 +/* Version */ +.word 0x1000 +/* Type 0 with checksum valid. */ +.byte 0x80 +/* Checksum byte - must add to zero. */ +.byte 0x6e +.fill CONFIG_CPU_INTEL_NUM_FIT_ENTRIES*16 +fit_table_end: +.previous diff --git a/src/cpu/intel/fit/fit.lds b/src/cpu/intel/fit/fit.lds new file mode 100644 index 0000000..9ccfe82 --- /dev/null +++ b/src/cpu/intel/fit/fit.lds @@ -0,0 +1,6 @@ +SECTIONS { + . = 0xffffffc0; + .fit_pointer (.): { + *(.fit_pointer) + } +} diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 5b24a8b..460b497 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -13,6 +13,7 @@ config CPU_SPECIFIC_OPTIONS select CPU_MICROCODE_IN_CBFS #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE + select CPU_INTEL_FIRMWARE_INTERFACE_TABLE config BOOTBLOCK_CPU_INIT string

1 0

New patch to review for coreboot: 451087b lynxpoint: ME to BIOS Payload Updates
by Stefan Reinauer 12 Mar '13

12 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2641 -gerrit commit 451087b71ea2e5676e0e4b264b868181abc7587a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Dec 12 12:40:33 2012 -0600 lynxpoint: ME to BIOS Payload Updates This commit contains a bevy of updates: - PCI device id is updated to match Lynx Point EDS in the ME driver. - Allocate the memory to store the consumption of the MBP. - me_bios_payload structure is now a structure of pointers that point into the allocated memory. - The ICC profile structure was updated to correctly reflect the documentation. Verfied that output of MBP reading can handle unknown items. Change-Id: I43cc45e6b797444c105e7c842eb5684e9c104687 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/intel/lynxpoint/me.h | 35 ++++---- src/southbridge/intel/lynxpoint/me_9.x.c | 149 +++++++++++++++---------------- 2 files changed, 89 insertions(+), 95 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/me.h b/src/southbridge/intel/lynxpoint/me.h index a57f779..ecd12e4 100644 --- a/src/southbridge/intel/lynxpoint/me.h +++ b/src/southbridge/intel/lynxpoint/me.h @@ -394,12 +394,7 @@ typedef struct { u32 reserved_4 : 1; u32 wlan : 1; u32 reserved_5 : 8; -} __attribute__ ((packed)) mefwcaps_sku; - -typedef struct { - mefwcaps_sku fw_capabilities; - u8 available; -} mbp_fw_caps; +} __attribute__ ((packed)) mbp_mefwcaps; typedef struct { u16 device_id; @@ -431,11 +426,17 @@ typedef struct { } mbp_plat_type; typedef struct { + u16 icc_start_address; + u16 mask; +} __attribute__ ((packed)) icc_address_mask; + +typedef struct { u8 num_icc_profiles; u8 icc_profile_soft_strap; u8 icc_profile_index; u8 reserved; - u32 register_lock_mask[3]; + u32 icc_reg_bundles; + icc_address_mask icc_address_mask[0]; } __attribute__ ((packed)) mbp_icc_profile; typedef struct { @@ -451,23 +452,23 @@ typedef struct { u8 state; u8 last_theft_trigger; tdt_state_flag flags; -} __attribute__ ((packed)) tdt_state_info; +} __attribute__ ((packed)) mbp_at_state; typedef struct { - mbp_fw_version_name fw_version_name; - mbp_fw_caps fw_caps_sku; - mbp_rom_bist_data rom_bist_data; - mbp_platform_key platform_key; - mbp_plat_type fw_plat_type; - mbp_icc_profile icc_profile; - tdt_state_info at_state; - u32 mfsintegrity; + mbp_fw_version_name *fw_version_name; + mbp_mefwcaps *fw_capabilities; + mbp_rom_bist_data *rom_bist_data; + mbp_platform_key *platform_key; + mbp_plat_type *fw_plat_type; + mbp_icc_profile *icc_profile; + mbp_at_state *at_state; + u32 *mfsintegrity; } me_bios_payload; struct me_fwcaps { u32 id; u8 length; - mefwcaps_sku caps_sku; + mbp_mefwcaps caps_sku; u8 reserved[3]; } __attribute__ ((packed)); diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 12f7ab7..f2e928a 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -365,7 +365,7 @@ static inline void print_cap(const char *name, int state) static void me_print_fw_version(mbp_fw_version_name *vers_name) { - if (!vers_name->major_version) { + if (!vers_name) { printk(BIOS_ERR, "ME: mbp missing version report\n"); return; } @@ -376,7 +376,7 @@ static void me_print_fw_version(mbp_fw_version_name *vers_name) } /* Get ME Firmware Capabilities */ -static int mkhi_get_fwcaps(mefwcaps_sku *cap) +static int mkhi_get_fwcaps(mbp_mefwcaps *cap) { u32 rule_id = 0; struct me_fwcaps cap_msg; @@ -402,10 +402,11 @@ static int mkhi_get_fwcaps(mefwcaps_sku *cap) } /* Get ME Firmware Capabilities */ -static void me_print_fwcaps(mbp_fw_caps *caps_section) +static void me_print_fwcaps(mbp_mefwcaps *cap) { - mefwcaps_sku *cap = &caps_section->fw_capabilities; - if (!caps_section->available) { + mbp_mefwcaps local_caps; + if (!cap) { + cap = &local_caps; printk(BIOS_ERR, "ME: mbp missing fwcaps report\n"); if (mkhi_get_fwcaps(cap)) return; @@ -705,6 +706,8 @@ static void intel_me_init(device_t dev) intel_me_extend_valid(dev); } + memset(&mbp_data, 0, sizeof(mbp_data)); + /* * According to the ME9 BWG, BIOS is required to fetch MBP data in * all boot flows except S3 Resume. @@ -718,8 +721,8 @@ static void intel_me_init(device_t dev) return; #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) - me_print_fw_version(&mbp_data.fw_version_name); - me_print_fwcaps(&mbp_data.fw_caps_sku); + me_print_fw_version(mbp_data.fw_version_name); + me_print_fwcaps(mbp_data.fw_capabilities); #endif /* @@ -754,7 +757,7 @@ static struct device_operations device_ops = { static const struct pci_driver intel_me __pci_driver = { .ops = &device_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1e3a, + .device = 0x8c3a, }; /****************************************************************************** @@ -802,6 +805,11 @@ static void intel_me_mbp_give_up(device_t dev) write_host_csr(&csr); } +struct mbp_payload { + mbp_header header; + u32 data[0]; +}; + /* * mbp seems to be following its own flow, let's retrieve it in a dedicated * function. @@ -809,12 +817,12 @@ static void intel_me_mbp_give_up(device_t dev) static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev) { mbp_header mbp_hdr; - mbp_item_header mbp_item_hdr; u32 me2host_pending; - u32 mbp_ident; struct mei_csr host; struct me_hfs2 hfs2; int count; + struct mbp_payload *mbp; + int i; pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2); @@ -840,103 +848,88 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev) me2host_pending); goto mbp_failure; } + mbp = malloc(mbp_hdr.mbp_size * sizeof(u32)); + if (!mbp) + goto mbp_failure; + mbp->header = mbp_hdr; me2host_pending--; - memset(mbp_data, 0, sizeof(*mbp_data)); - - while (mbp_hdr.num_entries--) { - u32* copy_addr; - u32 copy_size, buffer_room; - void *p; - - if (!me2host_pending) { - printk(BIOS_ERR, "ME: no mbp data %d entries to go!\n", - mbp_hdr.num_entries + 1); - goto mbp_failure; - } - mei_read_dword_ptr(&mbp_item_hdr, MEI_ME_CB_RW); + i = 0; + while (i != me2host_pending) { + mei_read_dword_ptr(&mbp->data[i], MEI_ME_CB_RW); + i++; + } - if (mbp_item_hdr.length > me2host_pending) { - printk(BIOS_ERR, "ME: insufficient mbp data %d " - "entries to go!\n", - mbp_hdr.num_entries + 1); - goto mbp_failure; - } + /* Signal to the ME that the host has finished reading the MBP. */ + read_host_csr(&host); + host.interrupt_generate = 1; + write_host_csr(&host); - me2host_pending -= mbp_item_hdr.length; + /* Wait for the mbp_cleared indicator. */ + for (count = ME_RETRY; count > 0; --count) { + pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2); + if (hfs2.mbp_cleared) + break; + udelay(ME_DELAY); + } - mbp_ident = MBP_MAKE_IDENT(mbp_item_hdr.app_id, - mbp_item_hdr.item_id); + if (count == 0) { + printk(BIOS_WARNING, "ME: Timeout waiting for mbp_cleared\n"); + intel_me_mbp_give_up(dev); + } - copy_size = mbp_item_hdr.length - 1; + /* Dump out the MBP contents. */ +#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) + printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n", + mbp->header.num_entries, mbp->header.mbp_size); + for (i = 0; i < mbp->header.mbp_size - 1; i++) { + printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]); + } +#endif -#define SET_UP_COPY(field) { copy_addr = (u32 *)&mbp_data->field; \ - buffer_room = sizeof(mbp_data->field) / sizeof(u32); \ - break; \ + #define ASSIGN_FIELD_PTR(field_,val_) \ + { \ + mbp_data->field_ = (typeof(mbp_data->field_))(void *)val_; \ + break; \ } + /* Setup the pointers in the me_bios_payload structure. */ + for (i = 0; i < mbp->header.mbp_size - 1;) { + mbp_item_header *item = (void *)&mbp->data[i]; - p = &mbp_item_hdr; - printk(BIOS_INFO, "ME: MBP item header %8.8x\n", *((u32*)p)); - - switch(mbp_ident) { + switch(MBP_MAKE_IDENT(item->app_id, item->item_id)) { case MBP_IDENT(KERNEL, FW_VER): - SET_UP_COPY(fw_version_name); + ASSIGN_FIELD_PTR(fw_version_name, &mbp->data[i+1]); case MBP_IDENT(ICC, PROFILE): - SET_UP_COPY(icc_profile); + ASSIGN_FIELD_PTR(icc_profile, &mbp->data[i+1]); case MBP_IDENT(INTEL_AT, STATE): - SET_UP_COPY(at_state); + ASSIGN_FIELD_PTR(at_state, &mbp->data[i+1]); case MBP_IDENT(KERNEL, FW_CAP): - mbp_data->fw_caps_sku.available = 1; - SET_UP_COPY(fw_caps_sku.fw_capabilities); + ASSIGN_FIELD_PTR(fw_capabilities, &mbp->data[i+1]); case MBP_IDENT(KERNEL, ROM_BIST): - SET_UP_COPY(rom_bist_data); + ASSIGN_FIELD_PTR(rom_bist_data, &mbp->data[i+1]); case MBP_IDENT(KERNEL, PLAT_KEY): - SET_UP_COPY(platform_key); + ASSIGN_FIELD_PTR(platform_key, &mbp->data[i+1]); case MBP_IDENT(KERNEL, FW_TYPE): - mbp_data->fw_plat_type.available = 1; - SET_UP_COPY(fw_plat_type.rule_data); + ASSIGN_FIELD_PTR(fw_plat_type, &mbp->data[i+1]); case MBP_IDENT(KERNEL, MFS_FAILURE): - SET_UP_COPY(mfsintegrity); + ASSIGN_FIELD_PTR(mfsintegrity, &mbp->data[i+1]); default: - printk(BIOS_ERR, "ME: unknown mbp item id 0x%x!!!\n", - mbp_ident); - goto mbp_failure; - } - - if (buffer_room != copy_size) { - printk(BIOS_ERR, "ME: buffer room %d != %d copy size" - " for item 0x%x!!!\n", - buffer_room, copy_size, mbp_ident); - goto mbp_failure; - } - while(copy_size--) - *copy_addr++ = read_cb(); - } - - read_host_csr(&host); - host.interrupt_generate = 1; - write_host_csr(&host); - - for (count = ME_RETRY; count > 0; --count) { - pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2); - if (hfs2.mbp_cleared) + printk(BIOS_ERR, "ME MBP: unknown item 0x%x @ dw offset 0x%x\n", + mbp->data[i], i); break; - udelay(ME_DELAY); - } - - if (count == 0) { - printk(BIOS_WARNING, "ME: Timeout waiting for mbp_cleared\n"); - intel_me_mbp_give_up(dev); + } + i += item->length; } + #undef ASSIGN_FIELD_PTR return 0;

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New patch to review for coreboot: 651e7ec lynx point: add new ME status information
by Stefan Reinauer 12 Mar '13

12 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2640 -gerrit commit 651e7ec465e0a3d4c2e7b50a4125c74422e18aa9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Dec 11 17:17:38 2012 -0600 lynx point: add new ME status information According to the 0.8.0 ME BWG this is a new state. It's not very clear what exactly it entails, but the Basking Ridge CRB was tripping it when MRC_DEBUG was enabled (presumably because of a DID timeout). Instead of 0x17 one can now see the proper message for this state. Change-Id: I5bda1de7d3d957d38a4760a02dcd170ec48782e9 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/intel/lynxpoint/me.h | 1 + src/southbridge/intel/lynxpoint/me_status.c | 1 + 2 files changed, 2 insertions(+) diff --git a/src/southbridge/intel/lynxpoint/me.h b/src/southbridge/intel/lynxpoint/me.h index 57c4f24..a57f779 100644 --- a/src/southbridge/intel/lynxpoint/me.h +++ b/src/southbridge/intel/lynxpoint/me.h @@ -136,6 +136,7 @@ struct me_did { #define ME_HFS2_STATE_BUP_M0 0x12 #define ME_HFS2_STATE_BUP_FLOW_DET_ERR 0x13 #define ME_HFS2_STATE_BUP_M3_CLK_ERR 0x15 +#define ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING 0x17 #define ME_HFS2_STATE_BUP_M3_KERN_LOAD 0x18 #define ME_HFS2_STATE_BUP_T32_MISSING 0x1c #define ME_HFS2_STATE_BUP_WAIT_DID 0x1f diff --git a/src/southbridge/intel/lynxpoint/me_status.c b/src/southbridge/intel/lynxpoint/me_status.c index 1feaf7d..d09be7b 100644 --- a/src/southbridge/intel/lynxpoint/me_status.c +++ b/src/southbridge/intel/lynxpoint/me_status.c @@ -109,6 +109,7 @@ static const char *me_progress_bup_values[] = { [ME_HFS2_STATE_BUP_M0] = "Bringup in M0", [ME_HFS2_STATE_BUP_FLOW_DET_ERR] = "Flow detection error", [ME_HFS2_STATE_BUP_M3_CLK_ERR] = "M3 clock switching error", + [ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING] = "Host error - CPU reset timeout, DID timeout, memory missing", [ME_HFS2_STATE_BUP_M3_KERN_LOAD] = "M3 kernel load", [ME_HFS2_STATE_BUP_T32_MISSING] = "T34 missing - cannot program ICC", [ME_HFS2_STATE_BUP_WAIT_DID] = "Waiting for DID BIOS message",

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coreboot March 2013