coreboot March 2013

coreboot@coreboot.org

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782 discussions

Re: [coreboot] Could some one please give me parameters for QEMU for running Coreboot with Linux payload
by ron minnich 12 Mar '13

12 Mar '13

have you tested with coreboot&seabios and a rom size of 4M? ron

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New patch to review for coreboot: bcc2ee8 AMD CIMx SB800: Enable AHCI mode for SATA controller by default
by Paul Menzel 12 Mar '13

12 Mar '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2661 -gerrit commit bcc2ee8178e4151346872bbe53927fbd28dd0e11 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Mar 12 12:41:40 2013 +0100 AMD CIMx SB800: Enable AHCI mode for SATA controller by default The current default is IDE mode which is slower compared to AHCI mode. Therefore use AHCI mode by default. A similar change was made for AMD Persimmon in commit »Enable SATA AHCI for faster boot with SeaBIOS.« (96be74c7) [1] but was indirectly reverted by »sb800: Add sata ahci/raid mode kconfig option« (d4a0e7d0) [2]. [1] http://review.coreboot.org/220 [2] http://review.coreboot.org/225 Change-Id: I4fa31b0a3280891e7a3f37675ae8415205818947 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/amd/cimx/sb800/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 2c9ab18..53fad3c 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -46,7 +46,7 @@ config IDE_COMBINED_MODE choice prompt "SATA Mode" - default SB800_SATA_IDE + default SB800_SATA_AHCI help Select the mode in which SATA should be driven. NATIVE AHCI, or RAID. The default is NATIVE.

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Patch merged into coreboot/master: 5021209 watchdog.h: Fix compile time error on disabling watchdog handling
by gerrit＠coreboot.org 12 Mar '13

12 Mar '13

the following patch was just integrated into master: commit 5021209f5a94e862c6b2915e4e6993b4931364fe Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Mar 11 18:32:50 2013 +0100 watchdog.h: Fix compile time error on disabling watchdog handling There's a compile time error that we didn't catch since the board defaults as used by the build bot won't expose it. Just make watchdog_off() a no-op statement so there aren't any stray semicolons in the preprocessor output. Change-Id: Ib5595e7e8aa91ca54bc8ca30a39b72875c961464 Reported-by: 'lautriv' on irc.freenode.net/#coreboot Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/2627 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/2627 for details. -gerrit

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Patch set updated for coreboot: a2456e1 OT200: reset MFGTP7 (backlight pwm)
by Christian Gmeiner 12 Mar '13

12 Mar '13

Christian Gmeiner (christian.gmeiner(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2527 -gerrit commit a2456e189efc5f861a8459b6913f34e0dbf1411f Author: Christian Gmeiner <christian.gmeiner(a)gmail.com> Date: Tue Mar 12 11:07:07 2013 +0100 OT200: reset MFGTP7 (backlight pwm) The CS5536 companion device has three different power domains. * working domain * standby domain * RTC domain When the system is "off" only the standby domain is powered. MFGPT[7:6] are member of the standby power domain. MFGPT7 is used to control the backlight of the device and so the timer gets used and configured during system boot. If the system does a reboot the timer stays configured and the Linux driver can not use it: "ot200-backlight: ot200-backlight.0: MFGPT 7 not availale" The cs5535-mfgpt has a function to hard-reset all MFGPTs but the system hangs after the first access to a MFGPT register - cause unknown. /* * This is a sledgehammer that resets all MFGPT timers. This is required by * some broken BIOSes which leave the system in an unstable state * (TinyBIOS 0.98, for example; fixed in 0.99). It's uncertain as to * whether or not this secret MSR can be used to release individual timers. * Jordan tells me that he and Mitch once played w/ it, but it's unclear * what the results of that were (and they experienced some instability). */ static void reset_all_timers(void) { uint32_t val, dummy; /* The following undocumented bit resets the MFGPT timers */ val = 0xFF; dummy = 0; wrmsr(MSR_MFGPT_SETUP, val, dummy); } After playing around with this undocumented MSR it looks like I only need to set bit 7 to free the MFGPT7. BTW, all MFGPT[0:5] will be reset during pll_reset(). Change-Id: I54a8d479ce495b0fc2f54db766a8d793bbb5d704 Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> --- src/mainboard/bachmann/ot200/mainboard.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/mainboard/bachmann/ot200/mainboard.c b/src/mainboard/bachmann/ot200/mainboard.c index ac6855a..0ea053a 100644 --- a/src/mainboard/bachmann/ot200/mainboard.c +++ b/src/mainboard/bachmann/ot200/mainboard.c @@ -21,6 +21,7 @@ #include <device/smbus.h> #include <smbios.h> #include <console/console.h> +#include <cpu/x86/msr.h> /* overwrite a weak function to fill SMBIOS table with a custom value */ static u8 hw_rev = 0; @@ -43,6 +44,7 @@ static void init(struct device *dev) unsigned int i; u32 chksum = 0; char block[20]; + msr_t reset; device_t eeprom_dev = dev_find_slot_on_smbus(1, 0x52); if (eeprom_dev == 0) { @@ -63,6 +65,12 @@ static void init(struct device *dev) hw_rev = block[5]; printk(BIOS_DEBUG, "hw revision: %u\n", hw_rev); + + /* Reset MFGPT7 (standby power domain) - this is done via + * an undocumented register */ + reset = rdmsr(0x5140002b); + reset.lo |= 1 << 7; + wrmsr(0x5140002b, reset); } static void mainboard_enable(struct device *dev)

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Patch merged into coreboot/master: db2e3aa libpayload: Fix reading x86 CBFS images from RAM
by gerrit＠coreboot.org 12 Mar '13

12 Mar '13

the following patch was just integrated into master: commit db2e3aa2578a931924f5bd269b0279bd403263ea Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Mar 9 10:52:50 2013 +0100 libpayload: Fix reading x86 CBFS images from RAM Three issues: 1. the hardcoded dereferenced pointer at 0xfffffffc 2. "RAM media" has no idea about ROM relative addresses 3. off-by-one in RAM media: it's legal to request 4 bytes from 0xfffffffc Change-Id: I671ac12d412c71dc8e8e6114f2ea13f58dd99c1d Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/2624 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> See http://review.coreboot.org/2624 for details. -gerrit

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Patch merged into coreboot/master: 6e7abcd Fix 'git describe' invocation
by gerrit＠coreboot.org 12 Mar '13

12 Mar '13

the following patch was just integrated into master: commit 6e7abcd4b58326dc2ea45f1523968d5a099bf6e1 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Mon Dec 10 15:47:23 2012 -0800 Fix 'git describe' invocation The 'git describe' command is used to obtain the source tree status information when building coreboot. As used this command expects git tags to be defined, so it can report the discrepancy between the current state of the tree and the latest tag. The problem is that the coreboot source tree does not have any git tags defined, so when 'git describe' is invoked, it reports "fatal: No names found, cannot describe anything.". This scary message can be seen on the console during coreboot builds. The solution is to add --always to the `git describe' invocation, which causes it to report the discrepancy with the latest sha1, if any, which is better than nothing. $ rm -rf /tmp/li && mkdir /tmp/li $ cp configs/config.link .config $ make obj=/tmp/li oldconfig $ make obj=/tmp/li $ grep COREBOOT_VERSION /tmp/li/build.h #define COREBOOT_VERSION "1623c06" $ echo '#' >> Makefile.inc $ grep COREBOOT_VERSION /tmp/li/build.h $ make obj=/tmp/li #define COREBOOT_VERSION "1623c06-dirty" $ git checkout Makefile.inc Change-Id: Ia77428b7cd765cbbd59bdbf8251b7bef489d47a5 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Reviewed-on: http://review.coreboot.org/2637 Tested-by: build bot (Jenkins) See http://review.coreboot.org/2637 for details. -gerrit

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Patch set updated for coreboot: 1104688 OT200: reset MFGTP7 (backlight pwm)
by Christian Gmeiner 12 Mar '13

12 Mar '13

Christian Gmeiner (christian.gmeiner(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2527 -gerrit commit 110468840b1f8bb92943bd20f625b23935694786 Author: Christian Gmeiner <christian.gmeiner(a)gmail.com> Date: Tue Mar 12 09:45:50 2013 +0100 OT200: reset MFGTP7 (backlight pwm) The CS5536 companion device has three different power domains. * working domain * standby domain * RTC domain When the system is "off" only the standby domain is powered. MFGPT[7:6] are member of the standby power domain. MFGPT7 is used to control the backlight of the device and so the timer gets used and configured during system boot. If the system does a reboot the timer stays configured and the Linux driver can not use it: "ot200-backlight: ot200-backlight.0: MFGPT 7 not availale" The cs5535-mfgpt has a function to hard-reset all MFGPTs but the system hangs after the first access to a MFGPT register - cause unknown. /* * This is a sledgehammer that resets all MFGPT timers. This is required by * some broken BIOSes which leave the system in an unstable state * (TinyBIOS 0.98, for example; fixed in 0.99). It's uncertain as to * whether or not this secret MSR can be used to release individual timers. * Jordan tells me that he and Mitch once played w/ it, but it's unclear * what the results of that were (and they experienced some instability). */ static void reset_all_timers(void) { uint32_t val, dummy; /* The following undocumented bit resets the MFGPT timers */ val = 0xFF; dummy = 0; wrmsr(MSR_MFGPT_SETUP, val, dummy); } After playing around with this undocumented MSR it looks like I only need to set bit 7 to free the MFGPT7. BTW, all MFGPT[0:5] will be reset during pll_reset(). Change-Id: I54a8d479ce495b0fc2f54db766a8d793bbb5d704 Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> --- src/mainboard/bachmann/ot200/mainboard.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/mainboard/bachmann/ot200/mainboard.c b/src/mainboard/bachmann/ot200/mainboard.c index ac6855a..6845f02 100644 --- a/src/mainboard/bachmann/ot200/mainboard.c +++ b/src/mainboard/bachmann/ot200/mainboard.c @@ -21,6 +21,7 @@ #include <device/smbus.h> #include <smbios.h> #include <console/console.h> +#include <cpu/x86/msr.h> /* overwrite a weak function to fill SMBIOS table with a custom value */ static u8 hw_rev = 0; @@ -43,6 +44,7 @@ static void init(struct device *dev) unsigned int i; u32 chksum = 0; char block[20]; + msr_t reset; device_t eeprom_dev = dev_find_slot_on_smbus(1, 0x52); if (eeprom_dev == 0) { @@ -63,6 +65,12 @@ static void init(struct device *dev) hw_rev = block[5]; printk(BIOS_DEBUG, "hw revision: %u\n", hw_rev); + + /* Reset MFGPT7 (standby power domain) - this is done via + * an undocumented register */ + reset = rdmsr(0x5140002b); + reset.lo = 1 << 7; + wrmsr(0x5140002b, reset); } static void mainboard_enable(struct device *dev)

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Please verify if disable CONFIG_WRITE_HIGH_TABLES is still needed
by Pankaj Chhabra 12 Mar '13

12 Mar '13

Hello, Documentation at http://www.coreboot.org/QEMU_Build_Tutorial#Building_or_finding_a_Linux_ker… mentions *Note: disable CONFIG_WRITE_HIGH_TABLES. Building coreboot with this option enabled crashes during elf image execution.* *pankaj@ubuntu:~/LDev/coreboot$ grep --recursive CONFIG_WRITE_HIGH_TABLES * * pankaj@ubuntu:~/LDev/coreboot$ There is CONFIG_WRITE_HIGH_TABLES in the code /configuration, please tell if this is still needed. Thanks, Pankaj

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Patch set updated for coreboot: b68b853 AMD hudson & SB800 - Fix issues with mawk
by Martin Roth 12 Mar '13

12 Mar '13

Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2628 -gerrit commit b68b8539d852a47fa8465ffcc1631ea4557724da Author: Martin Roth <martin.roth(a)se-eng.com> Date: Mon Mar 11 13:17:27 2013 -0600 AMD hudson & SB800 - Fix issues with mawk When calculating the offsets of the various binary blobs within the coreboot.rom file, we noticed that using mawk as the awk tool instead of using gawk led to build issues. This was finally traced to the maximum value of the unsigned long variables within mawk - 0x7fff_ffff. Because we were doing calculations on values up in the 0xfffcxxxx range, these numbers would either be turned into floating point values and printed using scientific notation, or truncated at 0x7fff_ffff. I see two solutions to this issue - we can either check for mawk and warn the user that it's not supported in a fashion similar to what is already being done for the solaris awk and suggest that everyone use gawk instead, or we can work around the issue. I tried to work around it by getting rid of the top 0xF000_0000 when doing the calculations in awk, then adding it back when the final values are loaded into the final variables for the make. The downside to this approach is that we could run into this error again in the future for anyone who uses mawk. Change-Id: I7b6b821c8ab13ad11f72e674ac726a98e8678710 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/southbridge/amd/agesa/hudson/Makefile.inc | 21 +++++++++++++++------ src/southbridge/amd/cimx/sb800/Makefile.inc | 9 +++++++-- 2 files changed, 22 insertions(+), 8 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 18a0ffb..ce0675d 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -22,10 +22,17 @@ ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c # EC ROM should be 64K aligned. HUDSON_FWM_POSITION=$(shell printf %u $(CONFIG_HUDSON_FWM_POSITION)) +# MAWK's limit for unsigned long is 0x7FFF_FFFF. To work around this, remove +# the top 0xF000_0000 (4026531840) from the calculation and add it back later +# in the print statements when assigning the positions. +HUDSON_FWM_POS__TRUNC=$(shell echo $(HUDSON_FWM_POSITION) \ + | awk '{print $$1 - 4026531840}') + #assume the cbfs header is less than 128 bytes. ROMSIG_SIZE=16 ifeq ($(CONFIG_HUDSON_XHCI_FWM), y) -HUDSON_XHCI_POSITION=$(shell echo $(HUDSON_FWM_POSITION) $(ROMSIG_SIZE) 128 | awk '{print $$1 + $$2 + $$3}') +HUDSON_XHCI_POSITION=$(shell echo $(HUDSON_FWM_POS__TRUNC) $(ROMSIG_SIZE) 128 \ + | awk '{printf("0xF%X", $$1 + $$2 + $$3)}') XHCI_FWM_SIZE=$(word 5,$(shell ls -l $(CONFIG_HUDSON_XHCI_FWM_FILE))) else HUDSON_XHCI_POSITION=0 @@ -33,8 +40,9 @@ XHCI_FWM_SIZE=0 endif ifeq ($(CONFIG_HUDSON_GEC_FWM), y) -HUDSON_GEC_POSITION=$(shell echo $(HUDSON_FWM_POSITION) $(ROMSIG_SIZE) 128 \ - $(XHCI_FWM_SIZE) 128 | awk '{print $$1 + $$2 + $$3 + $$4 + $$5}') +HUDSON_GEC_POSITION=$(shell echo $(HUDSON_FWM_POS__TRUNC) $(ROMSIG_SIZE) 128 \ + $(XHCI_FWM_SIZE) 128 | \ + awk '{printf("0xF%X", $$1 + $$2 + $$3 + $$4 + $$5)}') GEC_FWM_SIZE=$(word 5,$(shell ls -l $(CONFIG_HUDSON_GEC_FWM_FILE))) else HUDSON_GEC_POSITION=0 @@ -42,10 +50,11 @@ GEC_FWM_SIZE=0 endif ifeq ($(CONFIG_HUDSON_IMC_FWM), y) -HUDSON_IMC_POSITION_UNALIGN=$(shell echo $(HUDSON_FWM_POSITION) $(ROMSIG_SIZE) 128 \ - $(XHCI_FWM_SIZE) 128 \ +HUDSON_IMC_POSITION_UNALIGN=$(shell echo $(HUDSON_FWM_POS__TRUNC) \ + $(ROMSIG_SIZE) 128 $(XHCI_FWM_SIZE) 128 \ $(GEC_FWM_SIZE) 128 65535 | awk '{print $$1 + $$2 + $$3 + $$4 + $$5 + $$6 + $$7 + $$8}') -HUDSON_IMC_POSITION=$(shell echo $(HUDSON_IMC_POSITION_UNALIGN) | awk '{print $$1 - $$1 % 65536}') +HUDSON_IMC_POSITION=$(shell echo $(HUDSON_IMC_POSITION_UNALIGN) \ + | awk '{printf("0xF%X", $$1 - $$1 % 65536)}') else HUDSON_IMC_POSITION=0 endif diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index 4041b22..05937e7 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -70,8 +70,13 @@ SB800_FWM_POSITION=$(shell printf %u $(CONFIG_SB800_FWM_POSITION)) #assume the cbfs header is less than 128 bytes. ROMSIG_SIZE=16 -SB800_IMC_POSITION_UNALIGN=$(shell echo $(SB800_FWM_POSITION) $(ROMSIG_SIZE) 128 65535 | awk '{print $$1 + $$2 + $$3 + $$4}') -SB800_IMC_POSITION=$(shell echo $(SB800_IMC_POSITION_UNALIGN) | awk '{print $$1 - $$1 % 65536}') +# MAWK's limit for unsigned long is 0x7FFF_FFFF. To work around this, remove +# the top 0xF000_0000 (4026531840) from the calculation and add it back in the +# printf later. +SB800_IMC_POSITION_UNALIGN=$(shell echo $(SB800_FWM_POSITION) $(ROMSIG_SIZE) \ + 128 65535 | awk '{print $$1 - 4026531840 + $$2 + $$3 + $$4}') +SB800_IMC_POSITION=$(shell echo $(SB800_IMC_POSITION_UNALIGN) \ + | awk '{printf ("0xF%X", $$1 - $$1 % 65536)}') $(obj)/coreboot_SB800_romsig.bin: \ $(call strip_quotes, $(CONFIG_SB800_IMC_FWM_FILE)) \

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New patch to review for coreboot: ed253df libpayload: If there's no IO address space, don't try to use it for serial
by Stefan Reinauer 12 Mar '13

12 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2660 -gerrit commit ed253df995db52f738f10966d4e143bc1f16d311 Author: Gabe Black <gabeblack(a)google.com> Date: Fri Jan 18 18:37:29 2013 -0800 libpayload: If there's no IO address space, don't try to use it for serial Change-Id: I01b1fa42139af925716cd5d57f96dc24da6df5a7 Signed-off-by: Gabe Black <gabeblack(a)google.com> --- payloads/libpayload/drivers/serial.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/payloads/libpayload/drivers/serial.c b/payloads/libpayload/drivers/serial.c index 4ae3e26..df0f2e3 100644 --- a/payloads/libpayload/drivers/serial.c +++ b/payloads/libpayload/drivers/serial.c @@ -39,18 +39,22 @@ static int serial_is_mem_mapped = 0; static uint8_t serial_read_reg(int offset) { - if (serial_is_mem_mapped) - return readb(MEMBASE + offset); - else +#ifdef CONFIG_IO_ADDRESS_SPACE + if (!serial_is_mem_mapped) return inb(IOBASE + offset); + else +#endif + return readb(MEMBASE + offset); } static void serial_write_reg(uint8_t val, int offset) { - if (serial_is_mem_mapped) - writeb(val, MEMBASE + offset); - else +#ifdef CONFIG_IO_ADDRESS_SPACE + if (!serial_is_mem_mapped) outb(val, IOBASE + offset); + else +#endif + writeb(val, MEMBASE + offset); } #ifdef CONFIG_SERIAL_SET_SPEED

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coreboot March 2013