coreboot March 2013

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New patch to review for coreboot: 4a063b4 lynxpoint: Move a bit of generic RCBA into early_pch
by Stefan Reinauer 12 Mar '13

12 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2683 -gerrit commit 4a063b48551e286f5421a533f8b4ce36d46b0017 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Dec 19 13:17:06 2012 -0800 lynxpoint: Move a bit of generic RCBA into early_pch Rather than have to repeat this bit in every mainboard. Also, remove the reset of the RTC power status from here. We had done this in TOT for current platforms but did not carry it back to emeraldlake2 where this branched from. If we clear the status here then we don't get an event logged later which can be important for the devices that do not have a CMOS battery. Change-Id: Ia7131e9d9e7cf86228a285df652a96bcabf05260 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/intel/baskingridge/romstage.c | 5 ----- src/southbridge/intel/lynxpoint/early_pch.c | 20 +++++++++++++------- 2 files changed, 13 insertions(+), 12 deletions(-) diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index 9561456..d47fbf1 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -79,11 +79,6 @@ const struct rcba_config_instruction rcba_config[] = { /* Disable unused devices (board specific) */ RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), - /* Enable IOAPIC (generic) */ - RCBA_SET_REG_16(OIC, 0x0100), - /* PCH BWG says to read back the IOAPIC enable register */ - RCBA_READ_REG_16(OIC), - RCBA_END_CONFIG, }; diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 9757d8a..c87da27 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -31,6 +31,15 @@ #include "gpio.h" #endif +const struct rcba_config_instruction pch_early_config[] = { + /* Enable IOAPIC */ + RCBA_SET_REG_16(OIC, 0x0100), + /* PCH BWG says to read back the IOAPIC enable register */ + RCBA_READ_REG_16(OIC), + + RCBA_END_CONFIG, +}; + static void pch_enable_bars(void) { /* Setting up Southbridge. In the northbridge code. */ @@ -48,17 +57,10 @@ static void pch_enable_bars(void) static void pch_generic_setup(void) { - u8 reg8; - printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ printk(BIOS_DEBUG, " done.\n"); - - // reset rtc power status - reg8 = pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3); - reg8 &= ~(1 << 2); - pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, reg8); } static int sleep_type_s3(void) @@ -158,6 +160,10 @@ int early_pch_init(const void *gpio_map, /* Enable SMBus for reading SPDs. */ enable_smbus(); + /* Early PCH RCBA settings */ + pch_config_rcba(pch_early_config); + + /* Mainboard RCBA settings */ pch_config_rcba(rcba_config); wake_from_s3 = sleep_type_s3();

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New patch to review for coreboot: 58b355f lynxpoint: lpc resource reservations
by Stefan Reinauer 12 Mar '13

12 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2682 -gerrit commit 58b355faa757643845bd320a773e7dd8be32894f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Dec 19 14:38:01 2012 -0600 lynxpoint: lpc resource reservations This commit updates the Lynx Point resource reservations before the coreboot allocator assigns resources. There is no need to mark anything as subtractive decode because there are no devices/buses linked to the LPC device. The I/O range reservations consists of claiming the first 4KiB of I/O space. The PMBASE, GPIOBASE, and LPC generic I/O decode ranges are checked against the default claimed range. If those ranges overlap or fall outside of the default range then those resources are added. The MMIO range reservations consist of claiming everything from the I/O APIC to 4GiB. The RCBA and the LPC Generic Memory range register are then conditionally added if they fall outside of the default MMIO range. Change-Id: I0f560a03814a2b15961fdbe61e4164cd54cff7a5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/intel/lynxpoint/lpc.c | 167 +++++++++++++++++++++++----------- src/southbridge/intel/lynxpoint/pch.h | 1 + 2 files changed, 113 insertions(+), 55 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index a44d80f..facea7c 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -574,74 +574,131 @@ static void lpc_init(struct device *dev) pch_fixups(dev); } -static void pch_lpc_read_resources(device_t dev) +static void pch_lpc_add_mmio_resources(device_t dev) { + u32 reg; struct resource *res; - config_t *config = dev->chip_info; - u8 io_index = 0; - - /* Get the normal PCI resources of this device. */ - pci_dev_read_resources(dev); - - /* Add an extra subtractive resource for both memory and I/O. */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); - res->base = 0; - res->size = 0x1000; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + const u32 default_decode_base = IO_APIC_ADDR; - /* GPIOBASE */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); - res->base = DEFAULT_GPIOBASE; - res->size = DEFAULT_GPIOSIZE; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); - res->base = 0xff800000; - res->size = 0x00800000; /* 8 MB for flash */ - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, io_index++); /* IOAPIC */ - res->base = IO_APIC_ADDR; - res->size = 0x00001000; + /* + * Just report all resources from IO-APIC base to 4GiB. Don't mark + * them reserved as that may upset the OS if this range is marked + * as reserved in the e820. + */ + res = new_resource(dev, OIC); + res->base = default_decode_base; + res->size = 0 - default_decode_base; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - /* Set PCH IO decode ranges if required.*/ - if ((config->gen1_dec & 0xFFFC) > 0x1000) { - res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); - res->base = config->gen1_dec & 0xFFFC; - res->size = (config->gen1_dec >> 16) & 0xFC; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + /* RCBA */ + if (DEFAULT_RCBA < default_decode_base) { + res = new_resource(dev, RCBA); + res->base = DEFAULT_RCBA; + res->size = 16 * 1024; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | + IORESOURCE_FIXED | IORESOURCE_RESERVE; } - if ((config->gen2_dec & 0xFFFC) > 0x1000) { - res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); - res->base = config->gen2_dec & 0xFFFC; - res->size = (config->gen2_dec >> 16) & 0xFC; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + /* Check LPC Memory Decode register. */ + reg = pci_read_config32(dev, LGMR); + if (reg & 1) { + reg &= ~0xffff; + if (reg < default_decode_base) { + res = new_resource(dev, LGMR); + res->base = reg; + res->size = 16 * 1024; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | + IORESOURCE_FIXED | IORESOURCE_RESERVE; + } } +} - if ((config->gen3_dec & 0xFFFC) > 0x1000) { - res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); - res->base = config->gen3_dec & 0xFFFC; - res->size = (config->gen3_dec >> 16) & 0xFC; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - } +/* Default IO range claimed by the LPC device. The upper bound is exclusive. */ +#define LPC_DEFAULT_IO_RANGE_LOWER 0 +#define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 + +static inline int pch_io_range_in_default(u16 base, u16 size) +{ + /* Does it start above the range? */ + if (base >= LPC_DEFAULT_IO_RANGE_UPPER) + return 0; + + /* Is it entirely contained? */ + if (base >= LPC_DEFAULT_IO_RANGE_LOWER && + (base + size) < LPC_DEFAULT_IO_RANGE_UPPER) + return 1; + + /* This will return not in range for partial overlaps. */ + return 0; +} + +/* + * Note: this function assumes there is no overlap with the default LPC device's + * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. + */ +static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index) +{ + struct resource *res; + + if (pch_io_range_in_default(base, size)) + return; - if ((config->gen4_dec & 0xFFFC) > 0x1000) { - res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); - res->base = config->gen4_dec & 0xFFFC; - res->size = (config->gen4_dec >> 16) & 0xFC; - res->flags = IORESOURCE_IO| IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res = new_resource(dev, index); + res->base = base; + res->size = size; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index) +{ + /* + * Check if the register is enabled. If so and the base exceeds the + * device's deafult claim range add the resoure. + */ + if (reg_value & 1) { + u16 base = reg_value & 0xfffc; + u16 size = (0x3 | ((reg_value >> 16) & 0xfc)) + 1; + pch_lpc_add_io_resource(dev, base, size, index); } } +static void pch_lpc_add_io_resources(device_t dev) +{ + struct resource *res; + config_t *config = dev->chip_info; + + /* Add the default claimed IO range for the LPC device. */ + res = new_resource(dev, 0); + res->base = LPC_DEFAULT_IO_RANGE_LOWER; + res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + /* GPIOBASE */ + pch_lpc_add_io_resource(dev, DEFAULT_GPIOBASE, DEFAULT_GPIOSIZE, + GPIO_BASE); + + /* PMBASE */ + pch_lpc_add_io_resource(dev, DEFAULT_PMBASE, 128, PMBASE); + + /* LPC Generic IO Decode range. */ + pch_lpc_add_gen_io_resources(dev, config->gen1_dec, LPC_GEN1_DEC); + pch_lpc_add_gen_io_resources(dev, config->gen2_dec, LPC_GEN2_DEC); + pch_lpc_add_gen_io_resources(dev, config->gen3_dec, LPC_GEN3_DEC); + pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC); +} + +static void pch_lpc_read_resources(device_t dev) +{ + /* Get the normal PCI resources of this device. */ + pci_dev_read_resources(dev); + + /* Add non-standard MMIO resources. */ + pch_lpc_add_mmio_resources(dev); + + /* Add IO resources. */ + pch_lpc_add_io_resources(dev); +} + static void pch_lpc_enable_resources(device_t dev) { pch_decode_init(dev); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 4da2c62..eea3465 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -227,6 +227,7 @@ unsigned get_gpios(const int *gpio_num_array); #define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ +#define LGMR 0x98 /* LPC Generic Memory Range */ /* PCI Configuration Space (D31:F1): IDE */ #define PCH_IDE_DEV PCI_DEV(0, 0x1f, 1)

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New patch to review for coreboot: 69971c9 haswell platforms: restructure romstage main
by Stefan Reinauer 12 Mar '13

12 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2681 -gerrit commit 69971c91c53ea10570fed317fa2e30a888833915 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Dec 19 11:31:17 2012 -0600 haswell platforms: restructure romstage main There was a mix of setup code sprinkled across the various components: southbridge code in the northbridge, etc. This commit reorganizes the code so that northbridge code doesn't initialize southbridge components. Additionally, the calling dram initialization no longer calls out to ME code. The main() function in the mainboard calls the necessary ME functions before and after dram initialization. The biggest change is the addition of an early_pch_init() function which initializes the BARs, GPIOs, and RCBA configuration. It is also responsible for reporting back to the caller if the board is being woken up from S3. The one sequence difference is that the RCBA config is performed before claling the reference code. Lastly the rcba configuration was changed to be table driven so that different board/configurations can use the same code. It should be possible to have board/configuration specific gpio and rcba configuration while reusing the romstage code. Change-Id: I830e41b426261dd686a2701ce054fc39f296dffa Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/intel/baskingridge/romstage.c | 136 +++++---------------- src/northbridge/intel/haswell/early_init.c | 22 ---- src/northbridge/intel/haswell/raminit.c | 17 +-- src/southbridge/intel/lynxpoint/Makefile.inc | 2 +- src/southbridge/intel/lynxpoint/early_pch.c | 172 +++++++++++++++++++++++++++ src/southbridge/intel/lynxpoint/pch.h | 48 +++++++- 6 files changed, 256 insertions(+), 141 deletions(-) diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index 2a8e910..9561456 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -33,7 +33,7 @@ #include "northbridge/intel/haswell/haswell.h" #include "northbridge/intel/haswell/raminit.h" #include "southbridge/intel/lynxpoint/pch.h" -#include "southbridge/intel/lynxpoint/gpio.h" +#include "southbridge/intel/lynxpoint/me.h" #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> @@ -42,22 +42,7 @@ #include <vendorcode/google/chromeos/chromeos.h> #endif -static void pch_enable_lpc(void) -{ - device_t dev = PCH_LPC_DEV; - - /* Set COM1/COM2 decode range */ - pci_write_config16(dev, LPC_IO_DEC, 0x0010); - - /* Enable SuperIO + COM1 + PS/2 Keyboard/Mouse */ - u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN | KBC_LPC_EN; - pci_write_config16(dev, LPC_EN, lpc_config); -} - -static void rcba_config(void) -{ - u32 reg32; - +const struct rcba_config_instruction rcba_config[] = { /* * GFX INTA -> PIRQA (MSI) * D28IP_P1IP WLAN INTA -> PIRQB @@ -71,55 +56,42 @@ static void rcba_config(void) */ /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D30IP) = (NOINT << D30IP_PIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P4IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), + RCBA_SET_REG_32(D30IP, (NOINT << D30IP_PIP)), + RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), + RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | + (INTB << D28IP_P4IP)), + RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), + RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), + RCBA_SET_REG_32(D25IP, (NOINT << D25IP_LIP)), + RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQF, PIRQG, PIRQH, PIRQA); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); - DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); - DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB); - DIR_ROUTE(D26IR, PIRQE, PIRQF, PIRQG, PIRQH); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQF, PIRQG, PIRQH, PIRQA)), + RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG)), + RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE)), + RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQH, PIRQA, PIRQB)), + RCBA_SET_REG_32(D26IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), + RCBA_SET_REG_32(D25IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), + RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), /* Disable unused devices (board specific) */ - reg32 = RCBA32(FD); - reg32 |= PCH_DISABLE_ALWAYS; - RCBA32(FD) = reg32; -} + RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), -// FIXME, this function is generic code that should go to sb/... or -// nb/../early_init.c -static void early_pch_init(void) -{ - u8 reg8; + /* Enable IOAPIC (generic) */ + RCBA_SET_REG_16(OIC, 0x0100), + /* PCH BWG says to read back the IOAPIC enable register */ + RCBA_READ_REG_16(OIC), - // reset rtc power status - reg8 = pci_read_config8(PCH_LPC_DEV, 0xa4); - reg8 &= ~(1 << 2); - pci_write_config8(PCH_LPC_DEV, 0xa4, reg8); -} + RCBA_END_CONFIG, +}; void main(unsigned long bist) { int boot_mode = 0; + int wake_from_s3; int cbmem_was_initted; - u32 pm1_cnt; - u16 pm1_sts; #if CONFIG_COLLECT_TIMESTAMPS tsc_t start_romstage_time; @@ -180,64 +152,26 @@ void main(unsigned long bist) if (bist == 0) enable_lapic(); - pch_enable_lpc(); - - /* Enable GPIOs */ - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); - pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); - setup_pch_gpios(&mainboard_gpio_map); - - /* Early Console setup */ - console_init(); + wake_from_s3 = early_pch_init(&mainboard_gpio_map, &rcba_config[0]); /* Halt if there was a built in self test failure */ report_bist_failure(bist); - /* - * FIXME: MCHBAR isn't setup yet. It's setup in - * haswell_early_initialization(). - */ - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected\n"); - boot_mode = 1; - - /* System is not happy after keyboard reset... */ - printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); - outb(0x6, 0xcf9); - while (1) { - hlt(); - } - } - /* Perform some early chipset initialization required * before RAM initialization can work */ haswell_early_initialization(HASWELL_MOBILE); printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n"); - /* Check PM1_STS[15] to see if we are waking from Sx */ - pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); - - /* Read PM1_CNT[12:10] to determine which Sx state */ - pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); - - if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { + if (wake_from_s3) { #if CONFIG_HAVE_ACPI_RESUME printk(BIOS_DEBUG, "Resume from S3 detected.\n"); boot_mode = 2; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); #else printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); #endif } - post_code(0x38); - /* Enable SPD ROMs and DDR-III DRAM */ - enable_smbus(); - /* Prepare USB controller early in S3 resume */ if (boot_mode == 2) enable_usb_bar(); @@ -247,21 +181,17 @@ void main(unsigned long bist) #if CONFIG_COLLECT_TIMESTAMPS before_dram_time = rdtsc(); #endif + + report_platform_info(); + sdram_initialize(&pei_data); #if CONFIG_COLLECT_TIMESTAMPS after_dram_time = rdtsc(); #endif post_code(0x3b); - /* Perform some initialization that must run before stage2 */ - early_pch_init(); - post_code(0x3c); - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - post_code(0x3d); + intel_early_me_status(); quick_ram_check(); post_code(0x3e); diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index 505fbf1..681af42 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -29,20 +29,6 @@ static void haswell_setup_bars(void) { - /* Setting up Southbridge. In the northbridge code. */ - printk(BIOS_DEBUG, "Setting up static southbridge registers..."); - pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1); - - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */ - - printk(BIOS_DEBUG, " done.\n"); - - printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); - RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ - outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ - printk(BIOS_DEBUG, " done.\n"); - printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); @@ -62,14 +48,6 @@ static void haswell_setup_bars(void) pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); printk(BIOS_DEBUG, " done.\n"); - -#if CONFIG_ELOG_BOOT_COUNT - /* Increment Boot Counter except when resuming from S3 */ - if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && - ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) - return; - boot_count_increment(); -#endif } static void haswell_setup_graphics(void) diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 0c68e60..e2b085b 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -32,8 +32,6 @@ #include "pei_data.h" #include "haswell.h" -/* Management Engine is in the southbridge */ -#include "southbridge/intel/lynxpoint/me.h" #if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/chromeos.h> #else @@ -152,12 +150,6 @@ void sdram_initialize(struct pei_data *pei_data) struct sys_info sysinfo; unsigned long entry; - report_platform_info(); - - /* Wait for ME to be ready */ - intel_early_me_init(); - intel_early_me_uma_size(); - printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n"); memset(&sysinfo, 0, sizeof(sysinfo)); @@ -216,8 +208,6 @@ void sdram_initialize(struct pei_data *pei_data) version >> 24 , (version >> 16) & 0xff, (version >> 8) & 0xff, version & 0xff); - intel_early_me_status(); - report_memory_config(); /* S3 resume: don't save scrambler seed or MRC data */ @@ -232,7 +222,10 @@ struct cbmem_entry *get_cbmem_toc(void) unsigned long get_top_of_ram(void) { - /* Base of TSEG is top of usable DRAM */ + /* + * Base of TSEG is top of usable DRAM below 4GiB. The register has + * 1 MiB alignement. + */ u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); - return (unsigned long) tom; + return (unsigned long) tom & ~((1 << 20) - 1); } diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index c14a538..6e84ce6 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -45,7 +45,7 @@ smm-$(CONFIG_SPI_FLASH_SMM) += spi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c finalize.c -romstage-y += early_usb.c early_smbus.c early_me.c me_status.c +romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c romstage-$(CONFIG_USBDEBUG) += usb_debug.c romstage-y += reset.c early_spi.c diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c new file mode 100644 index 0000000..9757d8a --- /dev/null +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -0,0 +1,172 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 ChromeOS Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <console/console.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> +#include <elog.h> +#include "pch.h" + +#if CONFIG_INTEL_LYNXPOINT_LP +#include "lp_gpio.h" +#else +#include "gpio.h" +#endif + +static void pch_enable_bars(void) +{ + /* Setting up Southbridge. In the northbridge code. */ + pci_write_config32(PCH_LPC_DEV, RCBA, DEFAULT_RCBA | 1); + + pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); + /* Enable ACPI BAR */ + pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80); + + pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); + + /* Enable GPIO functionality. */ + pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); +} + +static void pch_generic_setup(void) +{ + u8 reg8; + + printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); + RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ + outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ + printk(BIOS_DEBUG, " done.\n"); + + // reset rtc power status + reg8 = pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3); + reg8 &= ~(1 << 2); + pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, reg8); +} + +static int sleep_type_s3(void) +{ + u32 pm1_cnt; + u16 pm1_sts; + int is_s3 = 0; + + /* Check PM1_STS[15] to see if we are waking from Sx */ + pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); + if (pm1_sts & WAK_STS) { + /* Read PM1_CNT[12:10] to determine which Sx state */ + pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); + if (((pm1_cnt >> 10) & 7) == SLP_TYP_S3) { + /* Clear SLP_TYPE. */ + outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); + is_s3 = 1; + } + } + return is_s3; +} + +static void pch_enable_lpc(void) +{ + device_t dev = PCH_LPC_DEV; + + /* Set COM1/COM2 decode range */ + pci_write_config16(dev, LPC_IO_DEC, 0x0010); + + /* Enable SuperIO + COM1 + PS/2 Keyboard/Mouse */ + u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN | KBC_LPC_EN; + pci_write_config16(dev, LPC_EN, lpc_config); +} + +static void pch_config_rcba(const struct rcba_config_instruction *rcba_config) +{ + const struct rcba_config_instruction *rc; + u32 value; + + rc = rcba_config; + while (rc->command != RCBA_COMMAND_END) + { + if ((rc->command & RCBA_REG_SIZE_MASK) == RCBA_REG_SIZE_16) { + switch (rc->command & RCBA_COMMAND_MASK) { + case RCBA_COMMAND_SET: + RCBA16(rc->reg) = (u16)rc->or_value; + break; + case RCBA_COMMAND_READ: + (void)RCBA16(rc->reg); + break; + case RCBA_COMMAND_RMW: + value = RCBA16(rc->reg); + value &= rc->mask; + value |= rc->or_value; + RCBA16(rc->reg) = (u16)value; + break; + } + } else { + switch (rc->command & RCBA_COMMAND_MASK) { + case RCBA_COMMAND_SET: + RCBA32(rc->reg) = rc->or_value; + break; + case RCBA_COMMAND_READ: + (void)RCBA32(rc->reg); + break; + case RCBA_COMMAND_RMW: + value = RCBA32(rc->reg); + value &= rc->mask; + value |= rc->or_value; + RCBA32(rc->reg) = value; + break; + } + } + rc++; + } +} + +int early_pch_init(const void *gpio_map, + const struct rcba_config_instruction *rcba_config) +{ + int wake_from_s3; + + pch_enable_lpc(); + + pch_enable_bars(); + +#if CONFIG_INTEL_LYNXPOINT_LP + setup_pch_lp_gpios(gpio_map); +#else + setup_pch_gpios(gpio_map); +#endif + + console_init(); + + pch_generic_setup(); + + /* Enable SMBus for reading SPDs. */ + enable_smbus(); + + pch_config_rcba(rcba_config); + + wake_from_s3 = sleep_type_s3(); + +#if CONFIG_ELOG_BOOT_COUNT + if (!wake_from_s3) + boot_count_increment(); +#endif + + /* Report if we are waking from s3. */ + return wake_from_s3; +} diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 1de1080..4da2c62 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -102,6 +102,48 @@ void enable_smbus(void); void enable_usb_bar(void); int smbus_read_byte(unsigned device, unsigned address); int early_spi_read(u32 offset, u32 size, u8 *buffer); + +/* State Machine configuration. */ +#define RCBA_REG_SIZE_MASK 0x8000 +#define RCBA_REG_SIZE_16 0x8000 +#define RCBA_REG_SIZE_32 0x0000 +#define RCBA_COMMAND_MASK 0x000f +#define RCBA_COMMAND_SET 0x0001 +#define RCBA_COMMAND_READ 0x0002 +#define RCBA_COMMAND_RMW 0x0003 +#define RCBA_COMMAND_END 0x0007 + +#define RCBA_ENCODE_COMMAND(command_, reg_, mask_, or_value_) \ + { .command = command_, \ + .reg = reg_, \ + .mask = mask_, \ + .or_value = or_value_ \ + } +#define RCBA_SET_REG_32(reg_, value_) \ + RCBA_ENCODE_COMMAND(RCBA_REG_SIZE_32|RCBA_COMMAND_SET, reg_, 0, value_) +#define RCBA_READ_REG_32(reg_) \ + RCBA_ENCODE_COMMAND(RCBA_REG_SIZE_32|RCBA_COMMAND_READ, reg_, 0, 0) +#define RCBA_RMW_REG_32(reg_, mask_, or_) \ + RCBA_ENCODE_COMMAND(RCBA_REG_SIZE_32|RCBA_COMMAND_RMW, reg_, mask_, or_) +#define RCBA_SET_REG_16(reg_, value_) \ + RCBA_ENCODE_COMMAND(RCBA_REG_SIZE_16|RCBA_COMMAND_SET, reg_, 0, value_) +#define RCBA_READ_REG_16(reg_) \ + RCBA_ENCODE_COMMAND(RCBA_REG_SIZE_16|RCBA_COMMAND_READ, reg_, 0, 0) +#define RCBA_RMW_REG_16(reg_, mask_, or_) \ + RCBA_ENCODE_COMMAND(RCBA_REG_SIZE_16|RCBA_COMMAND_RMW, reg_, mask_, or_) +#define RCBA_END_CONFIG \ + RCBA_ENCODE_COMMAND(RCBA_COMMAND_END, 0, 0, 0) + +struct rcba_config_instruction +{ + u16 command; + u16 reg; + u32 mask; + u32 or_value; +}; + +int early_pch_init(const void *gpio_map, + const struct rcba_config_instruction *rcba_config); #endif /* * get GPIO pin value @@ -421,9 +463,9 @@ unsigned get_gpios(const int *gpio_num_array); #define SOFT_RESET_CTRL 0x38f4 #define SOFT_RESET_DATA 0x38f8 -#define DIR_ROUTE(x,a,b,c,d) \ - RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ - ((b) << DIR_IBR) | ((a) << DIR_IAR)) +#define DIR_ROUTE(a,b,c,d) \ + (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ + ((b) << DIR_IBR) | ((a) << DIR_IAR)) #define RC 0x3400 /* 32bit */ #define HPTC 0x3404 /* 32bit */

1 0

New patch to review for coreboot: 63031aa haswell: more ULT/LP support and minor tweaks
by Stefan Reinauer 12 Mar '13

12 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2680 -gerrit commit 63031aa7867a8019529434bfbe7136f80d38ede1 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Dec 19 09:12:31 2012 -0800 haswell: more ULT/LP support and minor tweaks - Add ME device ID for Lynxpoint LP - Add GPU device IDs for ULT - SATA init tweaks from checking against DXE reference code - Remove the ICH7 from the SPI driver so it works on all lynxpoint without having to add more LPC device ID checks - Add function disable for audio dsp and xhci, remove PCI bridge - Add interrupt route registers for new devices (needs romstage setup) Change-Id: Idb48f50d0bacb6bf90531c3834542b9abb54fb8a Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/northbridge/intel/haswell/gma.c | 3 + src/southbridge/intel/lynxpoint/me_9.x.c | 8 ++- src/southbridge/intel/lynxpoint/pch.c | 11 ++-- src/southbridge/intel/lynxpoint/pch.h | 11 +++- src/southbridge/intel/lynxpoint/sata.c | 35 ++++++++-- src/southbridge/intel/lynxpoint/spi.c | 110 ++++--------------------------- 6 files changed, 70 insertions(+), 108 deletions(-) diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index f791c2b..38fe78a 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -315,14 +315,17 @@ u32 map_oprom_vendev(u32 vendev) case 0x80860402: /* GT1 Desktop */ case 0x80860406: /* GT1 Mobile */ case 0x8086040a: /* GT1 Server */ + case 0x80860a06: /* GT1 ULT */ case 0x80860412: /* GT2 Desktop */ case 0x80860416: /* GT2 Mobile */ case 0x8086041a: /* GT2 Server */ + case 0x80860a16: /* GT2 ULT */ case 0x80860422: /* GT3 Desktop */ case 0x80860426: /* GT3 Mobile */ case 0x8086042a: /* GT3 Server */ + case 0x80860a26: /* GT3 ULT */ new_vendev=0x80860406; /* GT1 Mobile */ break; diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index f2e928a..63b5205 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -754,10 +754,16 @@ static struct device_operations device_ops = { .ops_pci = &pci_ops, }; +static const unsigned short pci_device_ids[] = { + 0x8c3a, /* Mobile */ + 0x9c3a, /* Low Power */ + 0 +}; + static const struct pci_driver intel_me __pci_driver = { .ops = &device_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x8c3a, + .devices= pci_device_ids, }; /****************************************************************************** diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index c4a3acf..e992fb2 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -55,6 +55,12 @@ int pch_silicon_supported(int type, int rev) static void pch_hide_devfn(unsigned devfn) { switch (devfn) { + case PCI_DEVFN(19, 0): /* Audio DSP */ + RCBA32_OR(FD, PCH_DISABLE_ADSPD); + break; + case PCI_DEVFN(20, 0): /* XHCI */ + RCBA32_OR(FD, PCH_DISABLE_XHCI); + break; case PCI_DEVFN(22, 0): /* MEI #1 */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); break; @@ -89,9 +95,6 @@ static void pch_hide_devfn(unsigned devfn) case PCI_DEVFN(29, 0): /* EHCI #1 */ RCBA32_OR(FD, PCH_DISABLE_EHCI1); break; - case PCI_DEVFN(30, 0): /* PCI-to-PCI Bridge */ - RCBA32_OR(FD, PCH_DISABLE_P2P); - break; case PCI_DEVFN(31, 0): /* LPC */ RCBA32_OR(FD, PCH_DISABLE_LPC); break; @@ -101,7 +104,7 @@ static void pch_hide_devfn(unsigned devfn) case PCI_DEVFN(31, 3): /* SMBUS */ RCBA32_OR(FD, PCH_DISABLE_SMBUS); break; - case PCI_DEVFN(31, 5): /* SATA #22 */ + case PCI_DEVFN(31, 5): /* SATA #2 */ RCBA32_OR(FD, PCH_DISABLE_SATA2); break; case PCI_DEVFN(31, 6): /* Thermal Subsystem */ diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index fa8d75f..1de1080 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -403,6 +403,8 @@ unsigned get_gpios(const int *gpio_num_array); #define D22IP_IDERIP 8 /* IDE-R Pin */ #define D22IP_MEI2IP 4 /* MEI #2 Pin */ #define D22IP_MEI1IP 0 /* MEI #1 Pin */ +#define D20IP 0x3128 /* 32bit */ +#define D20IP_XHCI 0 /* XHCI Pin */ #define D31IR 0x3140 /* 16bit */ #define D30IR 0x3142 /* 16bit */ #define D29IR 0x3144 /* 16bit */ @@ -410,7 +412,11 @@ unsigned get_gpios(const int *gpio_num_array); #define D27IR 0x3148 /* 16bit */ #define D26IR 0x314c /* 16bit */ #define D25IR 0x3150 /* 16bit */ +#define D23IR 0x3158 /* 16bit */ #define D22IR 0x315c /* 16bit */ +#define D20IR 0x3160 /* 16bit */ +#define D21IR 0x3164 /* 16bit */ +#define D19IR 0x3168 /* 16bit */ #define OIC 0x31fe /* 16bit */ #define SOFT_RESET_CTRL 0x38f4 #define SOFT_RESET_DATA 0x38f8 @@ -430,8 +436,8 @@ unsigned get_gpios(const int *gpio_num_array); #define CG 0x341c /* 32bit */ /* Function Disable 1 RCBA 0x3418 */ -#define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26)|(1 << 27)) -#define PCH_DISABLE_P2P (1 << 1) +#define PCH_DISABLE_ALWAYS (1 << 0) +#define PCH_DISABLE_ADSPD (1 << 1) #define PCH_DISABLE_SATA1 (1 << 2) #define PCH_DISABLE_SMBUS (1 << 3) #define PCH_DISABLE_HD_AUDIO (1 << 4) @@ -441,6 +447,7 @@ unsigned get_gpios(const int *gpio_num_array); #define PCH_DISABLE_PCIE(x) (1 << (16 + x)) #define PCH_DISABLE_THERMAL (1 << 24) #define PCH_DISABLE_SATA2 (1 << 25) +#define PCH_DISABLE_XHCI (1 << 27) /* Function Disable 2 RCBA 0x3428 */ #define PCH_DISABLE_KT (1 << 4) diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 81d4a1d..25eb94f 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -23,6 +23,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <delay.h> #include "pch.h" typedef struct southbridge_intel_lynxpoint_config config_t; @@ -123,6 +124,7 @@ static void sata_init(struct device *dev) reg16 &= ~0x3f; reg16 |= 0x8000 | config->sata_port_map; pci_write_config16(dev, 0x92, reg16); + udelay(2); /* Setup register 98h */ reg32 = pci_read_config16(dev, 0x98); @@ -138,6 +140,7 @@ static void sata_init(struct device *dev) #if CONFIG_INTEL_LYNXPOINT_LP reg32 &= ~((1 << 31) | (1 << 30)); reg32 |= 1 << 23; + reg32 |= 1 << 24; /* Disable listen mode (hotplug) */ #endif pci_write_config32(dev, 0x98, reg32); @@ -159,6 +162,9 @@ static void sata_init(struct device *dev) reg32 = read32(abar + 0x00); reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS reg32 &= ~0x00020060; // clear SXS+EMS+PMS +#if CONFIG_INTEL_LYNXPOINT_LP + reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY +#endif write32(abar + 0x00, reg32); /* PI (Ports implemented) */ write32(abar + 0x0c, config->sata_port_map); @@ -166,12 +172,13 @@ static void sata_init(struct device *dev) (void) read32(abar + 0x0c); /* Read back 2 */ /* CAP2 (HBA Capabilities Extended)*/ reg32 = read32(abar + 0x24); +#if CONFIG_INTEL_LYNXPOINT_LP + /* Enable DEVSLP */ + reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2); +#else reg32 &= ~0x00000002; +#endif write32(abar + 0x24, reg32); - /* VSP (Vendor Specific Register */ - reg32 = read32(abar + 0xa0); - reg32 &= ~0x00000005; - write32(abar + 0xa0, reg32); } else { printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); @@ -230,15 +237,33 @@ static void sata_init(struct device *dev) /* Additional Programming Requirements */ /* Power Optimizer */ + + /* Step 1 */ +#if CONFIG_INTEL_LYNXPOINT_LP + sir_write(dev, 0x64, 0x883c9003); +#else sir_write(dev, 0x64, 0x883c9001); +#endif + /* Step 2: SIR 68h[15:0] = 880Ah */ reg32 = sir_read(dev, 0x68); reg32 &= 0xffff0000; reg32 |= 0x880a; sir_write(dev, 0x68, reg32); + /* Step 3: SIR 60h[3] = 1 */ + reg32 = sir_read(dev, 0x60); + reg32 |= (1 << 3); + sir_write(dev, 0x60, reg32); + + /* Step 4: SIR 60h[0] = 1 */ + reg32 = sir_read(dev, 0x60); + reg32 |= (1 << 0); + sir_write(dev, 0x60, reg32); + + /* Step 5: SIR 60h[1] = 1 */ reg32 = sir_read(dev, 0x60); - reg32 |= (1 << 0) | (1 << 1) | (1 << 3); + reg32 |= (1 << 1); sir_write(dev, 0x60, reg32); /* Clock Gating */ diff --git a/src/southbridge/intel/lynxpoint/spi.c b/src/southbridge/intel/lynxpoint/spi.c index ec7c862..123c6a9 100644 --- a/src/southbridge/intel/lynxpoint/spi.c +++ b/src/southbridge/intel/lynxpoint/spi.c @@ -68,18 +68,6 @@ typedef struct spi_slave ich_spi_slave; static int ichspi_lock = 0; -typedef struct ich7_spi_regs { - uint16_t spis; - uint16_t spic; - uint32_t spia; - uint64_t spid[8]; - uint64_t _pad; - uint32_t bbar; - uint16_t preop; - uint16_t optype; - uint8_t opmenu[8]; -} __attribute__((packed)) ich7_spi_regs; - typedef struct ich9_spi_regs { uint32_t bfpr; uint16_t hsfs; @@ -302,110 +290,40 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, return slave; } -/* - * Check if this device ID matches one of supported Intel PCH devices. - * - * Return the ICH version if there is a match, or zero otherwise. - */ -static inline int get_ich_version(uint16_t device_id) -{ - if (device_id >= PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_MIN && - device_id <= PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_MAX) - return 9; - - return 0; -} - void spi_init(void) { - int ich_version = 0; - uint8_t *rcrb; /* Root Complex Register Block */ uint32_t rcba; /* Root Complex Base Address */ uint8_t bios_cntl; device_t dev; - uint32_t ids; - uint16_t vendor_id, device_id; + ich9_spi_regs *ich9_spi; #ifdef __SMM__ dev = PCI_DEV(0, 31, 0); #else dev = dev_find_slot(0, PCI_DEVFN(31, 0)); #endif - pci_read_config_dword(dev, 0, &ids); - vendor_id = ids; - device_id = (ids >> 16); - - if (vendor_id != PCI_VENDOR_ID_INTEL) { - printk(BIOS_DEBUG, "ICH SPI: No ICH found.\n"); - return; - } - - ich_version = get_ich_version(device_id); - - if (!ich_version) { - printk(BIOS_DEBUG, "ICH SPI: No known ICH found.\n"); - return; - } pci_read_config_dword(dev, 0xf0, &rcba); /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ rcrb = (uint8_t *)(rcba & 0xffffc000); - switch (ich_version) { - case 7: - { - const uint16_t ich7_spibar_offset = 0x3020; - ich7_spi_regs *ich7_spi = - (ich7_spi_regs *)(rcrb + ich7_spibar_offset); - - ichspi_lock = readw_(&ich7_spi->spis) & SPIS_LOCK; - cntlr.opmenu = ich7_spi->opmenu; - cntlr.menubytes = sizeof(ich7_spi->opmenu); - cntlr.optype = &ich7_spi->optype; - cntlr.addr = &ich7_spi->spia; - cntlr.data = (uint8_t *)ich7_spi->spid; - cntlr.databytes = sizeof(ich7_spi->spid); - cntlr.status = (uint8_t *)&ich7_spi->spis; - cntlr.control = &ich7_spi->spic; - cntlr.bbar = &ich7_spi->bbar; - cntlr.preop = &ich7_spi->preop; - break; - } - case 9: - { - const uint16_t ich9_spibar_offset = 0x3800; - ich9_spi_regs *ich9_spi = - (ich9_spi_regs *)(rcrb + ich9_spibar_offset); - ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN; - cntlr.opmenu = ich9_spi->opmenu; - cntlr.menubytes = sizeof(ich9_spi->opmenu); - cntlr.optype = &ich9_spi->optype; - cntlr.addr = &ich9_spi->faddr; - cntlr.data = (uint8_t *)ich9_spi->fdata; - cntlr.databytes = sizeof(ich9_spi->fdata); - cntlr.status = &ich9_spi->ssfs; - cntlr.control = (uint16_t *)ich9_spi->ssfc; - cntlr.bbar = &ich9_spi->bbar; - cntlr.preop = &ich9_spi->preop; - break; - } - default: - printk(BIOS_DEBUG, "ICH SPI: Unrecognized ICH version %d.\n", ich_version); - } - + ich9_spi = (ich9_spi_regs *)(rcrb + 0x3800); + ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN; + cntlr.opmenu = ich9_spi->opmenu; + cntlr.menubytes = sizeof(ich9_spi->opmenu); + cntlr.optype = &ich9_spi->optype; + cntlr.addr = &ich9_spi->faddr; + cntlr.data = (uint8_t *)ich9_spi->fdata; + cntlr.databytes = sizeof(ich9_spi->fdata); + cntlr.status = &ich9_spi->ssfs; + cntlr.control = (uint16_t *)ich9_spi->ssfc; + cntlr.bbar = &ich9_spi->bbar; + cntlr.preop = &ich9_spi->preop; ich_set_bbar(0); /* Disable the BIOS write protect so write commands are allowed. */ pci_read_config_byte(dev, 0xdc, &bios_cntl); - switch (ich_version) { - case 9: - /* Deassert SMM BIOS Write Protect Disable. */ - bios_cntl &= ~(1 << 5); - break; - - default: - break; - } + bios_cntl &= ~(1 << 5); pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1); }

1 0

New patch to review for coreboot: caa65b0 baskingridge: Report static temperature in _TMP
by Stefan Reinauer 12 Mar '13

12 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2679 -gerrit commit caa65b0324f83ff4e82cfe34ed9526d2d4886dd3 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Dec 19 09:14:10 2012 -0800 baskingridge: Report static temperature in _TMP The current code is attempting to convert from an invalid starting temperature. Since we aren't sure where the temperature will come from yet just return a static value. This stops the kernel from going to S5 on boot because it thinks the temperature is too high. Change-Id: I433fa407e545458344af5842b353df5bc71bfdad Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/intel/baskingridge/acpi/thermal.asl | 21 +-------------------- 1 file changed, 1 insertion(+), 20 deletions(-) diff --git a/src/mainboard/intel/baskingridge/acpi/thermal.asl b/src/mainboard/intel/baskingridge/acpi/thermal.asl index f8e9d97..39dabe3 100644 --- a/src/mainboard/intel/baskingridge/acpi/thermal.asl +++ b/src/mainboard/intel/baskingridge/acpi/thermal.asl @@ -63,26 +63,7 @@ Scope (\_TZ) Method (_TMP, 0, Serialized) { - // Get CPU Temperature from PECI via SuperIO TMPIN3 - // FIXME: figure out how to read temp on this board. - Store (30, Local0) - - // Check for invalid readings - If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { - Return (CTOK (\F2ON)) - } - - // PECI raw value is an offset from Tj_max - Subtract (255, Local0, Local1) - - // Handle values greater than Tj_max - If (LGreaterEqual (Local1, \TMAX)) { - Return (CTOK (\TMAX)) - } - - // Subtract from Tj_max to get temperature - Subtract (\TMAX, Local1, Local0) - Return (CTOK (Local0)) + Return (CTOK (50)) } Method (_AC0) {

1 0

New patch to review for coreboot: 2a64201 haswell: remove CONFIG_GFXUMA
by Stefan Reinauer 12 Mar '13

12 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2678 -gerrit commit 2a64201c7c774af821c7c14d58fcfffaf80dd391 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Dec 18 14:18:53 2012 -0600 haswell: remove CONFIG_GFXUMA This option is not required for haswell. Enabling the option doesn't do anything aside from complicate mtrr calculation. Therefore, remove it. Change-Id: I897523ff7d3606eb89961674c2eb3d384e584857 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/intel/baskingridge/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index a8478a8..830c650 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MAINBOARD_RESOURCES select MMCONF_SUPPORT select HAVE_SMI_HANDLER - select GFXUMA select CHROMEOS select EXTERNAL_MRC_BLOB

1 0

New patch to review for coreboot: c8b8ef9 baskingridge: fix CHIP_NAME to identify the mainboard properly
by Stefan Reinauer 12 Mar '13

12 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2677 -gerrit commit c8b8ef9f26908f56373bc537a21f7eb12df879ec Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Mar 12 14:39:39 2013 -0700 baskingridge: fix CHIP_NAME to identify the mainboard properly Change-Id: Ib6c031fddcdba4eea4485c3d83715690a5f02cb0 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/intel/baskingridge/mainboard.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/intel/baskingridge/mainboard.c b/src/mainboard/intel/baskingridge/mainboard.c index 8ac538b..e763a49 100644 --- a/src/mainboard/intel/baskingridge/mainboard.c +++ b/src/mainboard/intel/baskingridge/mainboard.c @@ -238,7 +238,7 @@ static void mainboard_enable(device_t dev) } struct chip_operations mainboard_ops = { - CHIP_NAME("Compal Link ChromeBox") + CHIP_NAME("Intel Basking Ridge") .enable_dev = mainboard_enable, };

1 0

New patch to review for coreboot: 1d785fa baskingridge: dev, recovery, and WP switch support
by Stefan Reinauer 12 Mar '13

12 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2676 -gerrit commit 1d785fa32a0cc07f16748ab2eab3f3e1749ae4eb Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Dec 13 16:51:41 2012 -0600 baskingridge: dev, recovery, and WP switch support This commit adds support for the deveveloper, recovery, and write protect querying. It just uses jumpers on the Basking Ridge board. Noted ability to togggle jumpers results in toggling the respective modes. Change-Id: Iac189a1fa0245654591e2e9075380db422a329a0 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/intel/baskingridge/chromeos.c | 45 +++++++++++++++++------------ 1 file changed, 26 insertions(+), 19 deletions(-) diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 4ee9d62..6a1bc26 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -27,6 +27,7 @@ #include <device/pci.h> #endif #include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/lynxpoint/gpio.h> #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> @@ -44,30 +45,30 @@ void fill_lb_gpios(struct lb_gpios *gpios) if (!gpio_base) return; - u32 gp_lvl = inl(gpio_base + 0x0c); - u32 gp_lvl2 = inl(gpio_base + 0x38); - /* u32 gp_lvl3 = inl(gpio_base + 0x48); */ + u32 gp_lvl = inl(gpio_base + GP_LVL); + u32 gp_lvl2 = inl(gpio_base + GP_LVL2); + u32 gp_lvl3 = inl(gpio_base + GP_LVL3); gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); gpios->count = GPIO_COUNT; - /* Write Protect: GPIO48 */ - gpios->gpios[0].port = 48; + /* Write Protect: GPIO22 */ + gpios->gpios[0].port = 0; gpios->gpios[0].polarity = ACTIVE_LOW; - gpios->gpios[0].value = (gp_lvl2 >> (48-32)) & 1; + gpios->gpios[0].value = (gp_lvl >> 22) & 1; strncpy((char *)gpios->gpios[0].name,"write protect", GPIO_MAX_NAME_LENGTH); - /* Recovery: GPIO22 */ - gpios->gpios[1].port = 22; - gpios->gpios[1].polarity = ACTIVE_LOW; - gpios->gpios[1].value = (gp_lvl >> 22) & 1; + /* Recovery: GPIO69 - SV_DETECT - J8E3 (silkscreen: J8E2) */ + gpios->gpios[1].port = 69; + gpios->gpios[1].polarity = ACTIVE_HIGH; + gpios->gpios[1].value = (gp_lvl3 >> (69-64)) & 1; strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); - /* Developer: GPIO57 */ - gpios->gpios[2].port = 57; + /* Developer: GPIO48 - BIOS_RESP - J8E4 (silkscreen: J8E3) */ + gpios->gpios[2].port = 48; gpios->gpios[2].polarity = ACTIVE_LOW; - gpios->gpios[2].value = (gp_lvl2 >> (57-32)) & 1; + gpios->gpios[2].value = (gp_lvl2 >> (48-32)) & 1; strncpy((char *)gpios->gpios[2].name,"developer", GPIO_MAX_NAME_LENGTH); /* Hard code the lid switch GPIO to open. */ @@ -99,10 +100,13 @@ int get_developer_mode_switch(void) dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); #endif u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe; - u32 gp_lvl2 = inl(gpio_base + 0x38); + u32 gp_lvl2 = inl(gpio_base + GP_LVL2); - /* Developer: GPIO17, active high */ - return (gp_lvl2 >> (57-32)) & 1; + /* + * Developer: GPIO48, Connected to J8E4, however the silkscreen says + * J8E3. The jumper is active low. + */ + return !((gp_lvl2 >> (48-32)) & 1); } int get_recovery_mode_switch(void) @@ -114,9 +118,12 @@ int get_recovery_mode_switch(void) dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); #endif u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe; - u32 gp_lvl = inl(gpio_base + 0x0c); + u32 gp_lvl3 = inl(gpio_base + GP_LVL3); - /* Recovery: GPIO22, active low */ - return !((gp_lvl >> 22) & 1); + /* + * Recovery: GPIO69, Connected to J8E3, however the silkscreen says + * J8E2. The jump is active high. + */ + return (gp_lvl3 >> (69-64)) & 1; }

1 0

New patch to review for coreboot: 076887b baskingridge: update gpio map documentation
by Stefan Reinauer 12 Mar '13

12 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2675 -gerrit commit 076887b20e48de1ad3c4fe3a19bca2c27d2a6775 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Dec 13 16:50:10 2012 -0600 baskingridge: update gpio map documentation While looking at the Basking Ridge schematic I noticed some changes and wanted to make sure they were reflected in the GPIO map. Change-Id: I686653c164314ae9f68c42331d2f950751411d4a Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/intel/baskingridge/gpio.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/intel/baskingridge/gpio.h b/src/mainboard/intel/baskingridge/gpio.h index 13126bf..d271644 100644 --- a/src/mainboard/intel/baskingridge/gpio.h +++ b/src/mainboard/intel/baskingridge/gpio.h @@ -23,7 +23,7 @@ #include "southbridge/intel/lynxpoint/gpio.h" const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_GPIO, /* PCH_GPIO0_R -> S_GPIO -> J9F5 */ + .gpio0 = GPIO_MODE_GPIO, /* PCH_GPIO0_R -> S_GPIO -> J9F4 */ .gpio1 = GPIO_MODE_GPIO, /* SMC_EXTSMI_N */ .gpio2 = GPIO_MODE_GPIO, /* TP_RSVD_TESTMODE - float */ .gpio3 = GPIO_MODE_NATIVE, /* PCH_PCI_IRQ_N -> SIO GPIO12/SMI# */ @@ -121,7 +121,7 @@ const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio45 = GPIO_MODE_NATIVE, /* CK_PCIE_LAN_REQ_N */ .gpio46 = GPIO_MODE_GPIO, /* PCH_GPIO46_R -> DDR Voltage Select Bit 1 */ .gpio47 = GPIO_MODE_NATIVE, /* PEGA_CKREQ_N */ - .gpio48 = GPIO_MODE_GPIO, /* BIOS_RESP -> J8E6 */ + .gpio48 = GPIO_MODE_GPIO, /* BIOS_RESP -> J8E3 */ .gpio49 = GPIO_MODE_GPIO, /* PCH_GP_49 -> CRIT_TEMP_REP_N */ .gpio50 = GPIO_MODE_GPIO, /* DGPU_HOLD_RST_N */ .gpio51 = GPIO_MODE_GPIO, /* BBS_BIT1 Strap */ @@ -195,7 +195,7 @@ const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio66 = GPIO_MODE_GPIO, /* CK_FLEX2 */ .gpio67 = GPIO_MODE_GPIO, /* DGPU_PRSNT_N -> PEG_RSVD3 */ .gpio68 = GPIO_MODE_GPIO, /* SATA_ODD_PWRGT */ - .gpio69 = GPIO_MODE_GPIO, /* SV_DET -> J8E5 */ + .gpio69 = GPIO_MODE_GPIO, /* SV_DET -> J8E2 */ .gpio70 = GPIO_MODE_GPIO, /* USB3_DET_P2_N */ .gpio71 = GPIO_MODE_GPIO, /* USB3_DET_P3_N */ .gpio72 = GPIO_MODE_NATIVE, /* PM_BATLOW_R_N */

1 0

New patch to review for coreboot: 9d46634 haswell: Add VGA PCI ID mappings
by Stefan Reinauer 12 Mar '13

12 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2674 -gerrit commit 9d46634fb0f25c8c32c683fcbdcfe3be1c155bfb Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Dec 13 16:43:32 2012 -0600 haswell: Add VGA PCI ID mappings Needed to map VGA OPROM IDs to actual device IDs Change-Id: I6743905c3db52519bf18f4bcc1a972aec43d3e9d Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/northbridge/intel/haswell/gma.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 03a8e79..f791c2b 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -312,14 +312,19 @@ u32 map_oprom_vendev(u32 vendev) u32 new_vendev=vendev; switch (vendev) { - case 0x80860102: /* GT1 Desktop */ - case 0x8086010a: /* GT1 Server */ - case 0x80860112: /* GT2 Desktop */ - case 0x80860116: /* GT2 Mobile */ - case 0x80860122: /* GT2 Desktop >=1.3GHz */ - case 0x80860126: /* GT2 Mobile >=1.3GHz */ - case 0x80860166: /* IVB */ - new_vendev=0x80860106; /* GT1 Mobile */ + case 0x80860402: /* GT1 Desktop */ + case 0x80860406: /* GT1 Mobile */ + case 0x8086040a: /* GT1 Server */ + + case 0x80860412: /* GT2 Desktop */ + case 0x80860416: /* GT2 Mobile */ + case 0x8086041a: /* GT2 Server */ + + case 0x80860422: /* GT3 Desktop */ + case 0x80860426: /* GT3 Mobile */ + case 0x8086042a: /* GT3 Server */ + + new_vendev=0x80860406; /* GT1 Mobile */ break; }

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coreboot March 2013