coreboot March 2013

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New patch to review for coreboot: 501fcc6 haswell: reserve default SMRAM space
by Stefan Reinauer 13 Mar '13

13 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2688 -gerrit commit 501fcc6192792fc85aaed40598c05612f127f3df Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Dec 19 17:15:43 2012 -0600 haswell: reserve default SMRAM space Currently the OS is free to use the memory located at the default SMRAM space because it is not marked reserved in the e820. This can lead to memory corruption on S3 resume because SMM setup doesn't save this range before using it to relocate SMRAM. Resulting tables: coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000002ffff: RAM 2. 0000000000030000-000000000003ffff: RESERVED 3. 0000000000040000-000000000009ffff: RAM 4. 00000000000a0000-00000000000fffff: RESERVED 5. 0000000000100000-0000000000efffff: RAM 6. 0000000000f00000-0000000000ffffff: RESERVED 7. 0000000001000000-00000000acebffff: RAM 8. 00000000acec0000-00000000acffffff: CONFIGURATION TABLES 9. 00000000ad000000-00000000af9fffff: RESERVED 10. 00000000f0000000-00000000f3ffffff: RESERVED 11. 00000000fed10000-00000000fed19fff: RESERVED 12. 00000000fed84000-00000000fed84fff: RESERVED 13. 0000000100000000-000000018f5fffff: RAM e820 map has 13 items: 0: 0000000000000000 - 0000000000030000 = 1 RAM 1: 0000000000030000 - 0000000000040000 = 2 RESERVED 2: 0000000000040000 - 000000000009f400 = 1 RAM 3: 000000000009f400 - 00000000000a0000 = 2 RESERVED 4: 00000000000f0000 - 0000000000100000 = 2 RESERVED 5: 0000000000100000 - 0000000000f00000 = 1 RAM 6: 0000000000f00000 - 0000000001000000 = 2 RESERVED 7: 0000000001000000 - 00000000acec0000 = 1 RAM 8: 00000000acec0000 - 00000000afa00000 = 2 RESERVED 9: 00000000f0000000 - 00000000f4000000 = 2 RESERVED 10: 00000000fed10000 - 00000000fed1a000 = 2 RESERVED 11: 00000000fed84000 - 00000000fed85000 = 2 RESERVED 12: 0000000100000000 - 000000018f600000 = 1 RAM Booted and checked e820 as well as coreboot table information. Change-Id: Ie4985c748b591bf8c0d6a2b59549b698c9ad6cfe Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/cpu/x86/smm.h | 3 +++ src/northbridge/intel/haswell/northbridge.c | 40 ++++++++++++++++++++++++----- 2 files changed, 36 insertions(+), 7 deletions(-) diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 00a8c7a..698ddaf 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -24,6 +24,9 @@ #ifndef CPU_X86_SMM_H #define CPU_X86_SMM_H +#define SMM_DEFAULT_BASE 0x30000 +#define SMM_DEFAULT_SIZE 0x10000 + /* used only by C programs so far */ #define SMM_BASE 0xa0000 diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index e97ef55..7059e2c 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -32,6 +32,7 @@ #include <stdlib.h> #include <string.h> #include <cpu/cpu.h> +#include <cpu/x86/smm.h> #include <boot/tables.h> #include <cbmem.h> #include "chip.h" @@ -333,29 +334,54 @@ static void mc_add_dram_resources(device_t dev) mc_report_map_entries(dev, &mc_values[0]); /* - * There are 4 host memory ranges that should be added: - * - 0 -> 0xa0000 : cacheable + * These are the host memory ranges that should be added: + * - 0 -> SMM_DEFAULT_BASE : cacheable + * - SMM_DEFAULT_BASE -> SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE : + * cacheable and reserved + * - SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE -> 0xa0000 : cacheable * - 0xc0000 -> TSEG : cacheable * - TESG -> TOLUD: not cacheable with standard MTRRs and reserved * - 4GiB -> TOUUD: cacheable * + * The default SMRAM space is reserved so that the range doesn't + * have to be saved during S3 Resume. Once marked reserved the OS + * cannot use the memory. This is a bit of an odd place to reserve + * the region, but the CPU devices don't have dev_ops->read_resources() + * called on them. + * * The range 0xa0000 -> 0xc0000 does not have any resources * associated with it to handle legacy VGA memory. If this range * is not omitted the mtrr code will setup the area as cacheable * causing VGA access to not work. * + * It should be noted that cacheable entry types need to be added in + * order. The reason is that the current MTRR code assumes this and + * falls over itself if it isn't. + * * The resource index starts low and should not meet or exceed - * PCI_BASE_ADDRESS_0. In this case there are only 3 entries so there - * are no conflicts in the index space. + * PCI_BASE_ADDRESS_0. */ index = 0; - /* 0 - > 0xa0000 */ + /* 0 - > SMM_DEFAULT_BASE */ base_k = 0; - size_k = 0xa0000 >> 10; + size_k = SMM_DEFAULT_BASE >> 10; + ram_resource(dev, index++, base_k, size_k); + + /* SMM_DEFAULT_BASE -> SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE */ + resource = new_resource(dev, index++); + resource->base = SMM_DEFAULT_BASE; + resource->size = SMM_DEFAULT_SIZE; + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_CACHEABLE | IORESOURCE_STORED | + IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; + + /* SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE -> 0xa0000 */ + base_k = (SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE) >> 10; + size_k = (0xa0000 >> 10) - base_k; ram_resource(dev, index++, base_k, size_k); - /* 0xa0000 -> TSEG */ + /* 0xc0000 -> TSEG */ base_k = 0xc0000 >> 10; size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - base_k; ram_resource(dev, index++, base_k, size_k);

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Patch set updated for coreboot: 64433e7 haswell: remove CONFIG_GFXUMA
by Stefan Reinauer 13 Mar '13

13 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2678 -gerrit commit 64433e74a50e3d08441d9566dba65708ea364f01 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Dec 18 14:18:53 2012 -0600 haswell: remove CONFIG_GFXUMA This option is not required for haswell. Enabling the option doesn't do anything aside from complicate mtrr calculation. Therefore, remove it. Change-Id: I897523ff7d3606eb89961674c2eb3d384e584857 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/intel/baskingridge/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index a8478a8..830c650 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MAINBOARD_RESOURCES select MMCONF_SUPPORT select HAVE_SMI_HANDLER - select GFXUMA select CHROMEOS select EXTERNAL_MRC_BLOB

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New patch to review for coreboot: 653c1c6 haswell: resource allocation
by Stefan Reinauer 13 Mar '13

13 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2687 -gerrit commit 653c1c6674e1e426fd78a09834becefa2ad891e1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Dec 18 14:22:49 2012 -0600 haswell: resource allocation The previous code w.r.t. resource allocation was getting lucky based on the way fixed mmio resources on the system were being chosen. Namely, PCIEXBAR was the lowest mmio space and the other fixed non-standar BARs were above it. The resource allocator would then start allocating standard BARs below that. On top of that other resources were being added when dev_ops->set_resources() was being called on the PCI domain. At that point the PCI range limit were already picked for where to start allocating from. To ensure we no longer get lucky during resource allocation add the fixed resources in the host bridge and add the memory controller cacheable memory areas. With those resources added the range limit for standard PCI BARs is chosen properly. Depending on haswell board configurations we may need to adjust and pass in the size of physical address space needed for PCI resources to the reference code. For the time being the CRBs appear to be OK. Lastly, remove the SNB workaround for reserving 2MiB at 1GiB and 512MiB. Output from 6GiB memory configuration: MC MAP: TOM: 0x140000000 MC MAP: TOUUD: 0x18f600000 MC MAP: MESEG_BASE: 0x13f000000 MC MAP: MESEG_LIMIT: 0x7fff0fffff MC MAP: REMAP_BASE: 0x13f000000 MC MAP: REMAP_LIMIT: 0x18f5fffff MC MAP: TOLUD: 0xafa00000 MC MAP: BDSM: 0xada00000 MC MAP: BGSM: 0xad800000 MC MAP: TESGMB: 0xad000000 MC MAP: GGC: 0x209 coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000a0000-00000000000fffff: RESERVED 3. 0000000000100000-0000000000efffff: RAM 4. 0000000000f00000-0000000000ffffff: RESERVED 5. 0000000001000000-00000000acebffff: RAM 6. 00000000acec0000-00000000acffffff: CONFIGURATION TABLES 7. 00000000ad000000-00000000af9fffff: RESERVED 8. 00000000f0000000-00000000f3ffffff: RESERVED 9. 00000000fed10000-00000000fed17fff: RESERVED 10. 00000000fed18000-00000000fed18fff: RESERVED 11. 00000000fed19000-00000000fed19fff: RESERVED 12. 00000000fed84000-00000000fed84fff: RESERVED 13. 0000000100000000-000000018f5fffff: RAM e820 map has 11 items: 0: 0000000000000000 - 000000000009fc00 = 1 RAM 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED 3: 0000000000100000 - 0000000000f00000 = 1 RAM 4: 0000000000f00000 - 0000000001000000 = 2 RESERVED 5: 0000000001000000 - 00000000acec0000 = 1 RAM 6: 00000000acec0000 - 00000000afa00000 = 2 RESERVED 7: 00000000f0000000 - 00000000f4000000 = 2 RESERVED 8: 00000000fed10000 - 00000000fed1a000 = 2 RESERVED 9: 00000000fed84000 - 00000000fed85000 = 2 RESERVED 10: 0000000100000000 - 000000018f600000 = 1 RAM Output from 4GiB memory configuration: MC MAP: TOM: 0x100000000 MC MAP: TOUUD: 0x14f600000 MC MAP: MESEG_BASE: 0xff000000 MC MAP: MESEG_LIMIT: 0x7fff0fffff MC MAP: REMAP_BASE: 0x100000000 MC MAP: REMAP_LIMIT: 0x14f5fffff MC MAP: TOLUD: 0xafa00000 MC MAP: BDSM: 0xada00000 MC MAP: BGSM: 0xad800000 MC MAP: TESGMB: 0xad000000 MC MAP: GGC: 0x209 coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000a0000-00000000000fffff: RESERVED 3. 0000000000100000-0000000000efffff: RAM 4. 0000000000f00000-0000000000ffffff: RESERVED 5. 0000000001000000-00000000acebffff: RAM 6. 00000000acec0000-00000000acffffff: CONFIGURATION TABLES 7. 00000000ad000000-00000000af9fffff: RESERVED 8. 00000000f0000000-00000000f3ffffff: RESERVED 9. 00000000fed10000-00000000fed17fff: RESERVED 10. 00000000fed18000-00000000fed18fff: RESERVED 11. 00000000fed19000-00000000fed19fff: RESERVED 12. 00000000fed84000-00000000fed84fff: RESERVED 13. 0000000100000000-000000014f5fffff: RAM e820 map has 11 items: 0: 0000000000000000 - 000000000009fc00 = 1 RAM 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED 3: 0000000000100000 - 0000000000f00000 = 1 RAM 4: 0000000000f00000 - 0000000001000000 = 2 RESERVED 5: 0000000001000000 - 00000000acec0000 = 1 RAM 6: 00000000acec0000 - 00000000afa00000 = 2 RESERVED 7: 00000000f0000000 - 00000000f4000000 = 2 RESERVED 8: 00000000fed10000 - 00000000fed1a000 = 2 RESERVED 9: 00000000fed84000 - 00000000fed85000 = 2 RESERVED 10: 0000000100000000 - 000000014f600000 = 1 RAM Output from 2GiB memory configuration: MC MAP: TOM: 0x40000000 MC MAP: TOUUD: 0x100600000 MC MAP: MESEG_BASE: 0x3f000000 MC MAP: MESEG_LIMIT: 0x7fff0fffff MC MAP: REMAP_BASE: 0x100000000 MC MAP: REMAP_LIMIT: 0x1005fffff MC MAP: TOLUD: 0x3ea00000 MC MAP: BDSM: 0x3ca00000 MC MAP: BGSM: 0x3c800000 MC MAP: TESGMB: 0x3c000000 MC MAP: GGC: 0x209 coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000a0000-00000000000fffff: RESERVED 3. 0000000000100000-0000000000efffff: RAM 4. 0000000000f00000-0000000000ffffff: RESERVED 5. 0000000001000000-000000003bebffff: RAM 6. 000000003bec0000-000000003bffffff: CONFIGURATION TABLES 7. 000000003c000000-000000003e9fffff: RESERVED 8. 00000000f0000000-00000000f3ffffff: RESERVED 9. 00000000fed10000-00000000fed17fff: RESERVED 10. 00000000fed18000-00000000fed18fff: RESERVED 11. 00000000fed19000-00000000fed19fff: RESERVED 12. 00000000fed84000-00000000fed84fff: RESERVED 13. 0000000100000000-00000001005fffff: RAM e820 map has 11 items: 0: 0000000000000000 - 000000000009fc00 = 1 RAM 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED 3: 0000000000100000 - 0000000000f00000 = 1 RAM 4: 0000000000f00000 - 0000000001000000 = 2 RESERVED 5: 0000000001000000 - 000000003bec0000 = 1 RAM 6: 000000003bec0000 - 000000003ea00000 = 2 RESERVED 7: 00000000f0000000 - 00000000f4000000 = 2 RESERVED 8: 00000000fed10000 - 00000000fed1a000 = 2 RESERVED 9: 00000000fed84000 - 00000000fed85000 = 2 RESERVED 10: 0000000100000000 - 0000000100600000 = 1 RAM Verified through debug messages that range limits as well as resources were being properly honored. Change-Id: I2faa7d8a2a34a6a411a2885afb3b5c3fa1ad9c23 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/northbridge/intel/haswell/haswell.h | 9 +- src/northbridge/intel/haswell/northbridge.c | 457 ++++++++++++++++------------ 2 files changed, 275 insertions(+), 191 deletions(-) diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 967a186..bbb51aa 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -63,7 +63,6 @@ #define MCHBAR 0x48 #define PCIEXBAR 0x60 #define DMIBAR 0x68 -#define X60BAR 0x60 #define GGC 0x50 /* GMCH Graphics Control */ @@ -91,8 +90,14 @@ #define G_SMRAME (1 << 3) #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) -#define TOM 0xa0 +#define MESEG_BASE 0x70 /* Management Engine Base. */ +#define MESEG_LIMIT 0x78 /* Management Engine Limit. */ +#define REMAPBASE 0x90 /* Remap base. */ +#define REMAPLIMIT 0x98 /* Remap limit. */ +#define TOM 0xa0 /* Top of DRAM in memory controller space. */ #define TOUUD 0xa8 /* Top of Upper Usable DRAM */ +#define BDSM 0xb0 /* Base Data Stolen Memory */ +#define BGSM 0xb4 /* Base GTT Stolen Memory */ #define TSEG 0xb8 /* TSEG base */ #define TOLUD 0xbc /* Top of Low Used Memory */ diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 5731077..e97ef55 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -65,19 +65,14 @@ void cbmem_post_handling(void) update_mrc_cache(); } -static int get_pcie_bar(u32 *base, u32 *len) +static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) { - device_t dev; u32 pciexbar_reg; *base = 0; *len = 0; - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); - if (!dev) - return 0; - - pciexbar_reg = pci_read_config32(dev, PCIEXBAR); + pciexbar_reg = pci_read_config32(dev, index); if (!(pciexbar_reg & (1 << 0))) return 0; @@ -100,221 +95,305 @@ static int get_pcie_bar(u32 *base, u32 *len) return 0; } -static void add_fixed_resources(struct device *dev, int index) +static void pci_domain_set_resources(device_t dev) { - struct resource *resource; - u32 pcie_config_base, pcie_config_size; - - printk(BIOS_DEBUG, "Adding UMA memory area base=0x%llx " - "size=0x%llx\n", uma_memory_base, uma_memory_size); - resource = new_resource(dev, index); - resource->base = (resource_t) uma_memory_base; - resource->size = (resource_t) uma_memory_size; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - /* Clear these values here so they don't get used by MTRR code */ - uma_memory_base = 0; - uma_memory_size = 0; - - if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { - printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " - "size=0x%x\n", pcie_config_base, pcie_config_size); - resource = new_resource(dev, index+1); - resource->base = (resource_t) pcie_config_base; - resource->size = (resource_t) pcie_config_size; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - } - - mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k); + assign_resources(dev->link_list); +} -#if CONFIG_CHROMEOS_RAMOOPS - mmio_resource(dev, index++, CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, - CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); + /* TODO We could determine how many PCIe busses we need in + * the bar. For now that number is hardcoded to a max of 64. + * See e7525/northbridge.c for an example. + */ +static struct device_operations pci_domain_ops = { + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = pci_domain_scan_bus, +#if CONFIG_MMCONF_SUPPORT_DEFAULT + .ops_pci_bus = &pci_ops_mmconf, +#else + .ops_pci_bus = &pci_cf8_conf1, #endif +}; - /* Required for SandyBridge sighting 3715511 */ - bad_ram_resource(dev, index++, 0x20000000 >> 10, 0x00200000 >> 10); - bad_ram_resource(dev, index++, 0x40000000 >> 10, 0x00200000 >> 10); +static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) +{ + u32 bar; + + bar = pci_read_config32(dev, index); + + /* If not enabled don't report it. */ + if (!(bar & 0x1)) + return 0; + + /* Knock down the enable bit. */ + *base = bar & ~1; + + return 1; } -static void pci_domain_set_resources(device_t dev) +/* There are special BARs that actually are programmed in the MCHBAR. These + * Intel special features, but they do consume resources that need to be + * accounted for. */ +static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, + u32 *len) { - uint64_t tom, me_base, touud; - uint32_t tseg_base, uma_size, tolud; - uint16_t ggc; - unsigned long long tomk; + u32 bar; - /* Total Memory 2GB example: - * - * 00000000 0000MB-1992MB 1992MB RAM (writeback) - * 7c800000 1992MB-2000MB 8MB TSEG (SMRR) - * 7d000000 2000MB-2002MB 2MB GFX GTT (uncached) - * 7d200000 2002MB-2034MB 32MB GFX UMA (uncached) - * 7f200000 2034MB TOLUD - * 7f800000 2040MB MEBASE - * 7f800000 2040MB-2048MB 8MB ME UMA (uncached) - * 80000000 2048MB TOM - * 100000000 4096MB-4102MB 6MB RAM (writeback) - * - * Total Memory 4GB example: - * - * 00000000 0000MB-2768MB 2768MB RAM (writeback) - * ad000000 2768MB-2776MB 8MB TSEG (SMRR) - * ad800000 2776MB-2778MB 2MB GFX GTT (uncached) - * ada00000 2778MB-2810MB 32MB GFX UMA (uncached) - * afa00000 2810MB TOLUD - * ff800000 4088MB MEBASE - * ff800000 4088MB-4096MB 8MB ME UMA (uncached) - * 100000000 4096MB TOM - * 100000000 4096MB-5374MB 1278MB RAM (writeback) - * 14fe00000 5368MB TOUUD - */ + bar = MCHBAR32(index); - /* Top of Upper Usable DRAM, including remap */ - touud = pci_read_config32(dev, TOUUD+4); - touud <<= 32; - touud |= pci_read_config32(dev, TOUUD) & ~1; - - /* Top of Lower Usable DRAM */ - tolud = pci_read_config32(dev, TOLUD) & ~1; - - /* Top of Memory - does not account for any UMA */ - tom = pci_read_config32(dev, 0xa4); - tom <<= 32; - tom |= pci_read_config32(dev, 0xa0) & ~1; - - printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", - touud, tolud, tom); - - /* ME UMA needs excluding if total memory <4GB */ - me_base = pci_read_config32(dev, 0x74); - me_base <<= 32; - me_base |= pci_read_config32(dev, 0x70); - - printk(BIOS_DEBUG, "MEBASE 0x%llx\n", me_base); - - tomk = tolud >> 10; - if (me_base == tolud) { - /* ME is from MEBASE-TOM */ - uma_size = (tom - me_base) >> 10; - /* Increment TOLUD to account for ME as RAM */ - tolud += uma_size << 10; - /* UMA starts at old TOLUD */ - uma_memory_base = tomk * 1024ULL; - uma_memory_size = uma_size * 1024ULL; - printk(BIOS_DEBUG, "ME UMA base 0x%llx size %uM\n", - me_base, uma_size >> 10); - } + /* If not enabled don't report it. */ + if (!(bar & 0x1)) + return 0; + + /* Knock down the enable bit. */ + *base = bar & ~1; - /* Graphics memory comes next */ - ggc = pci_read_config16(dev, GGC); - if (!(ggc & 2)) { - printk(BIOS_DEBUG, "IGD decoded, subtracting "); - - /* Graphics memory */ - uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL; - printk(BIOS_DEBUG, "%uM UMA", uma_size >> 10); - tomk -= uma_size; - uma_memory_base = tomk * 1024ULL; - uma_memory_size += uma_size * 1024ULL; - - /* GTT Graphics Stolen Memory Size (GGMS) */ - uma_size = ((ggc >> 8) & 0x3) * 1024ULL; - tomk -= uma_size; - uma_memory_base = tomk * 1024ULL; - uma_memory_size += uma_size * 1024ULL; - printk(BIOS_DEBUG, " and %uM GTT\n", uma_size >> 10); + return 1; +} + +struct fixed_mmio_descriptor { + unsigned int index; + u32 size; + int (*get_resource)(device_t dev, unsigned int index, + u32 *base, u32 *size); + const char *description; +}; + +#define SIZE_KB(x) ((x)*1024) +struct fixed_mmio_descriptor mc_fixed_resources[] = { + { PCIEXBAR, SIZE_KB(0), get_pcie_bar, "PCIEXBAR" }, + { MCHBAR, SIZE_KB(32), get_bar, "MCHBAR" }, + { DMIBAR, SIZE_KB(4), get_bar, "DMIBAR" }, + { EPBAR, SIZE_KB(4), get_bar, "EPBAR" }, + { 0x5420, SIZE_KB(4), get_bar_in_mchbar, "GDXCBAR" }, + { 0x5408, SIZE_KB(16), get_bar_in_mchbar, "EDRAMBAR" }, +}; +#undef SIZE_KB + +/* + * Add all known fixed MMIO ranges that hang off the host bridge/memory + * controller device. + */ +static void mc_add_fixed_mmio_resources(device_t dev) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(mc_fixed_resources); i++) { + u32 base; + u32 size; + struct resource *resource; + unsigned int index; + + size = mc_fixed_resources[i].size; + index = mc_fixed_resources[i].index; + if (!mc_fixed_resources[i].get_resource(dev, index, + &base, &size)) + continue; + + resource = new_resource(dev, mc_fixed_resources[i].index); + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_STORED | IORESOURCE_RESERVE | + IORESOURCE_ASSIGNED; + resource->base = base; + resource->size = size; + printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n", + __func__, mc_fixed_resources[i].description, index, + (unsigned long)base, (unsigned long)(base + size - 1)); } +} - /* Calculate TSEG size from its base which must be below GTT */ - tseg_base = pci_read_config32(dev, 0xb8); - uma_size = (uma_memory_base - tseg_base) >> 10; - tomk -= uma_size; - uma_memory_base = tomk * 1024ULL; - uma_memory_size += uma_size * 1024ULL; - printk(BIOS_DEBUG, "TSEG base 0x%08x size %uM\n", - tseg_base, uma_size >> 10); +/* Host Memory Map: + * + * +--------------------------+ TOUUD + * | | + * +--------------------------+ 4GiB + * | PCI Address Space | + * +--------------------------+ TOLUD (also maps into MC address space) + * | iGD | + * +--------------------------+ BDSM + * | GTT | + * +--------------------------+ BGSM + * | TSEG | + * +--------------------------+ TSEGMB + * | Usage DRAM | + * +--------------------------+ 0 + * + * Some of the base registers above can be equal making the size of those + * regions 0. The reason is because the memory controller internally subtracts + * the base registers from each other to determine sizes of the regions. In + * other words, the memory map is in a fixed order no matter what. + */ - printk(BIOS_INFO, "Available memory below 4GB: %lluM\n", tomk >> 10); +struct map_entry { + int reg; + int is_64_bit; + int is_limit; + const char *description; +}; - /* Report the memory regions */ - ram_resource(dev, 3, 0, legacy_hole_base_k); - ram_resource(dev, 4, legacy_hole_base_k + legacy_hole_size_k, - (tomk - (legacy_hole_base_k + legacy_hole_size_k))); +static void read_map_entry(device_t dev, struct map_entry *entry, + uint64_t *result) +{ + uint64_t value; + uint64_t mask; - /* - * If >= 4GB installed then memory from TOLUD to 4GB - * is remapped above TOM, TOUUD will account for both - */ - touud >>= 10; /* Convert to KB */ - if (touud > 4096 * 1024) { - ram_resource(dev, 5, 4096 * 1024, touud - (4096 * 1024)); - printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", - (touud >> 10) - 4096); + /* All registers are on a 1MiB granularity. */ + mask = ((1ULL<<20)-1); + mask = ~mask; + + value = 0; + + if (entry->is_64_bit) { + value = pci_read_config32(dev, entry->reg + 4); + value <<= 32; } - add_fixed_resources(dev, 6); + value |= pci_read_config32(dev, entry->reg); + value &= mask; - assign_resources(dev->link_list); + if (entry->is_limit) + value |= ~mask; - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + *result = value; } - /* TODO We could determine how many PCIe busses we need in - * the bar. For now that number is hardcoded to a max of 64. - * See e7525/northbridge.c for an example. - */ -static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .enable_resources = NULL, - .init = NULL, - .scan_bus = pci_domain_scan_bus, -#if CONFIG_MMCONF_SUPPORT_DEFAULT - .ops_pci_bus = &pci_ops_mmconf, -#else - .ops_pci_bus = &pci_cf8_conf1, -#endif +#define MAP_ENTRY(reg_, is_64_, is_limit_, desc_) \ + { \ + .reg = reg_, \ + .is_64_bit = is_64_, \ + .is_limit = is_limit_, \ + .description = desc_, \ + } + +#define MAP_ENTRY_BASE_64(reg_, desc_) \ + MAP_ENTRY(reg_, 1, 0, desc_) +#define MAP_ENTRY_LIMIT_64(reg_, desc_) \ + MAP_ENTRY(reg_, 1, 1, desc_) +#define MAP_ENTRY_BASE_32(reg_, desc_) \ + MAP_ENTRY(reg_, 0, 0, desc_) + +enum { + TOM_REG, + TOUUD_REG, + MESEG_BASE_REG, + MESEG_LIMIT_REG, + REMAP_BASE_REG, + REMAP_LIMIT_REG, + TOLUD_REG, + BGSM_REG, + BDSM_REG, + TSEG_REG, + // Must be last. + NUM_MAP_ENTRIES }; -static void mc_read_resources(device_t dev) +static struct map_entry memory_map[NUM_MAP_ENTRIES] = { + [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"), + [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"), + [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"), + [MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"), + [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"), + [REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"), + [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"), + [BGSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"), + [BDSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"), + [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), +}; + +static void mc_read_map_entries(device_t dev, uint64_t *values) { + int i; + for (i = 0; i < NUM_MAP_ENTRIES; i++) { + read_map_entry(dev, &memory_map[i], &values[i]); + } +} + +static void mc_report_map_entries(device_t dev, uint64_t *values) +{ + int i; + for (i = 0; i < NUM_MAP_ENTRIES; i++) { + printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n", + memory_map[i].description, values[i]); + } + /* One can validate the BDSM and BGSM against the GGC. */ + printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); +} + +static void mc_add_dram_resources(device_t dev) +{ + unsigned long base_k, size_k; + unsigned long index; struct resource *resource; + uint64_t mc_values[NUM_MAP_ENTRIES]; - pci_dev_read_resources(dev); + /* Read in the MAP registers and report their values. */ + mc_read_map_entries(dev, &mc_values[0]); + mc_report_map_entries(dev, &mc_values[0]); - /* So, this is one of the big mysteries in the coreboot resource - * allocator. This resource should make sure that the address space - * of the PCIe memory mapped config space bar. But it does not. + /* + * There are 4 host memory ranges that should be added: + * - 0 -> 0xa0000 : cacheable + * - 0xc0000 -> TSEG : cacheable + * - TESG -> TOLUD: not cacheable with standard MTRRs and reserved + * - 4GiB -> TOUUD: cacheable + * + * The range 0xa0000 -> 0xc0000 does not have any resources + * associated with it to handle legacy VGA memory. If this range + * is not omitted the mtrr code will setup the area as cacheable + * causing VGA access to not work. + * + * The resource index starts low and should not meet or exceed + * PCI_BASE_ADDRESS_0. In this case there are only 3 entries so there + * are no conflicts in the index space. */ + index = 0; + + /* 0 - > 0xa0000 */ + base_k = 0; + size_k = 0xa0000 >> 10; + ram_resource(dev, index++, base_k, size_k); + + /* 0xa0000 -> TSEG */ + base_k = 0xc0000 >> 10; + size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - base_k; + ram_resource(dev, index++, base_k, size_k); + + /* TSEG -> TOLUD */ + resource = new_resource(dev, index++); + resource->base = mc_values[TSEG_REG]; + resource->size = mc_values[TOLUD_REG] - resource->base; + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_STORED | IORESOURCE_RESERVE | + IORESOURCE_ASSIGNED; + + /* 4GiB -> TOUUD */ + base_k = 4096 * 1024; /* 4GiB */ + size_k = (unsigned long)(mc_values[TOUUD_REG] >> 10) - base_k; + ram_resource(dev, index++, base_k, size_k); + + mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k); +#if CONFIG_CHROMEOS_RAMOOPS + mmio_resource(dev, index++, CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, + CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); +#endif - /* We use 0xcf as an unused index for our PCIe bar so that we find it again */ - resource = new_resource(dev, 0xcf); - resource->base = DEFAULT_PCIEXBAR; - resource->size = 64 * 1024 * 1024; /* 64MB hard coded PCIe config space */ - resource->flags = - IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | - IORESOURCE_ASSIGNED; - printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n", - (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_size = HIGH_MEMORY_SIZE; + high_tables_base = mc_values[TSEG_REG] - high_tables_size; } -static void mc_set_resources(device_t dev) +static void mc_read_resources(device_t dev) { - struct resource *resource; + /* Read standard PCI resources. */ + pci_dev_read_resources(dev); - /* Report the PCIe BAR */ - resource = find_resource(dev, 0xcf); - if (resource) { - report_resource_stored(dev, resource, "<mmconfig>"); - } + /* Add all fixed MMIO resources. */ + mc_add_fixed_mmio_resources(dev); - /* And call the normal set_resources */ - pci_dev_set_resources(dev); + /* Calculate and add DRAM resources. */ + mc_add_dram_resources(dev); } static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) @@ -453,7 +532,7 @@ static struct pci_operations intel_pci_ops = { static struct device_operations mc_ops = { .read_resources = mc_read_resources, - .set_resources = mc_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, .enable = northbridge_enable,

1 0

New patch to review for coreboot: ae3731f cbfstool: Add internal cbfs_find_file()
by Stefan Reinauer 13 Mar '13

13 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2686 -gerrit commit ae3731f6aea3404c48c3d26885b52f30431fa2e2 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Dec 14 17:14:15 2012 -0600 cbfstool: Add internal cbfs_find_file() Future work will require the ability to locate a named file. Add cbfs_find_file() to find the named file and return a struct cbfs_file. Change-Id: I3998c5e76c75de5672bef3f5e04a098e5e1778ed Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- util/cbfstool/common.c | 21 +++++++++++++++++++++ util/cbfstool/common.h | 2 ++ 2 files changed, 23 insertions(+) diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c index 3c8dca5..0517d9a 100644 --- a/util/cbfstool/common.c +++ b/util/cbfstool/common.c @@ -870,3 +870,24 @@ uint32_t cbfs_find_location(const char *romfile, uint32_t filesize, free(rom); return ret; } + +struct cbfs_file *cbfs_find_file(const char *name) +{ + uint32_t current = phys_start; + while (current < phys_end) { + if (!cbfs_file_header(current)) { + current += align; + continue; + } + struct cbfs_file *thisfile = + (struct cbfs_file *)phys_to_virt(current); + uint32_t length = ntohl(thisfile->len); + char *fname = (char *)(phys_to_virt(current) + sizeof(struct cbfs_file)); + if (!strcmp(fname, name)) + return thisfile; + current = + ALIGN(current + ntohl(thisfile->len) + + ntohl(thisfile->offset), align); + } + return NULL; +} diff --git a/util/cbfstool/common.h b/util/cbfstool/common.h index e197143..2a18d9c 100644 --- a/util/cbfstool/common.h +++ b/util/cbfstool/common.h @@ -130,4 +130,6 @@ void print_supported_filetypes(void); #define ARRAY_SIZE(a) (int)(sizeof(a) / sizeof((a)[0])) +struct cbfs_file; +struct cbfs_file *cbfs_find_file(const char *name); #endif

1 0

New patch to review for coreboot: 63ea128 cbfstool: Add file alignment for add operations
by Stefan Reinauer 13 Mar '13

13 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2685 -gerrit commit 63ea12810584e94927a38b86c289d3c64f81a4bd Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Dec 14 16:54:34 2012 -0600 cbfstool: Add file alignment for add operations Some CBFS files have alignment requirements because of how that data is used at runtime. For example, microcode updates need to be 16 byte aligned. Therefore, an alignment option is needed. Instead of adding another option for data alignment the -b (base address) option is utilizied to provide the alignment. If a base address is supplied for a file and the address <= 1024 the address is treated as an alignment requirement. The data is then aligned accordingly. Since this alignment requirement is not carried through into picking the final location it is possible that a large alignment requirement may add unnecessary padding between the header and the data. Change-Id: I84075f2cf90794b0a97f0d0e5dbf7633925c21aa Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- util/cbfstool/common.c | 32 +++++++++++++++++++++++--------- 1 file changed, 23 insertions(+), 9 deletions(-) diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c index aa98696..3c8dca5 100644 --- a/util/cbfstool/common.c +++ b/util/cbfstool/common.c @@ -632,17 +632,31 @@ void *create_cbfs_file(const char *filename, void *data, uint32_t * datasize, { uint32_t filename_len = ALIGN(strlen(filename) + 1, 16); uint32_t headersize = sizeof(struct cbfs_file) + filename_len; - if ((location != 0) && (*location != 0)) { - uint32_t offset = *location % align; - /* If offset >= (headersize % align), we can stuff the header into the offset. - Otherwise the header has to be aligned itself, and put before the offset data */ - if (offset >= (headersize % align)) { - offset -= (headersize % align); + + if (location != NULL && *location != 0) { + /* + * A location of less than or equal 1024 is considered the data + * alignement. The location is then zero'd out so that cbfs + * can place it where ever it finds. + */ + if (*location <= 1024) { + uint32_t data_start = (headersize + align - 1) % align; + uint32_t alignment = *location; + if ((data_start % alignment) != 0) + headersize += (data_start % alignment); + *location = 0; } else { - offset += align - (headersize % align); + uint32_t offset = *location % align; + /* If offset >= (headersize % align), we can stuff the header into the offset. + Otherwise the header has to be aligned itself, and put before the offset data */ + if (offset >= (headersize % align)) { + offset -= (headersize % align); + } else { + offset += align - (headersize % align); + } + headersize += offset; + *location -= headersize; } - headersize += offset; - *location -= headersize; } void *newdata = malloc(*datasize + headersize); if (!newdata) {

1 0

Patch set updated for coreboot: 3584a9b haswell: more ULT/LP support and minor tweaks
by Stefan Reinauer 13 Mar '13

13 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2680 -gerrit commit 3584a9b36e56bf2c3dcb6365c146c5fa1db141ee Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Dec 19 09:12:31 2012 -0800 haswell: more ULT/LP support and minor tweaks - Add ME device ID for Lynxpoint LP - Add GPU device IDs for ULT - SATA init tweaks from checking against DXE reference code - Remove the ICH7 from the SPI driver so it works on all lynxpoint without having to add more LPC device ID checks - Add function disable for audio dsp and xhci, remove PCI bridge - Add interrupt route registers for new devices (needs romstage setup) Change-Id: Idb48f50d0bacb6bf90531c3834542b9abb54fb8a Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/northbridge/intel/haswell/gma.c | 3 + src/southbridge/intel/lynxpoint/me_9.x.c | 8 ++- src/southbridge/intel/lynxpoint/pch.c | 11 ++-- src/southbridge/intel/lynxpoint/pch.h | 11 +++- src/southbridge/intel/lynxpoint/sata.c | 35 ++++++++-- src/southbridge/intel/lynxpoint/spi.c | 110 ++++--------------------------- 6 files changed, 70 insertions(+), 108 deletions(-) diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index f791c2b..38fe78a 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -315,14 +315,17 @@ u32 map_oprom_vendev(u32 vendev) case 0x80860402: /* GT1 Desktop */ case 0x80860406: /* GT1 Mobile */ case 0x8086040a: /* GT1 Server */ + case 0x80860a06: /* GT1 ULT */ case 0x80860412: /* GT2 Desktop */ case 0x80860416: /* GT2 Mobile */ case 0x8086041a: /* GT2 Server */ + case 0x80860a16: /* GT2 ULT */ case 0x80860422: /* GT3 Desktop */ case 0x80860426: /* GT3 Mobile */ case 0x8086042a: /* GT3 Server */ + case 0x80860a26: /* GT3 ULT */ new_vendev=0x80860406; /* GT1 Mobile */ break; diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index f2e928a..63b5205 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -754,10 +754,16 @@ static struct device_operations device_ops = { .ops_pci = &pci_ops, }; +static const unsigned short pci_device_ids[] = { + 0x8c3a, /* Mobile */ + 0x9c3a, /* Low Power */ + 0 +}; + static const struct pci_driver intel_me __pci_driver = { .ops = &device_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x8c3a, + .devices= pci_device_ids, }; /****************************************************************************** diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index c4a3acf..e992fb2 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -55,6 +55,12 @@ int pch_silicon_supported(int type, int rev) static void pch_hide_devfn(unsigned devfn) { switch (devfn) { + case PCI_DEVFN(19, 0): /* Audio DSP */ + RCBA32_OR(FD, PCH_DISABLE_ADSPD); + break; + case PCI_DEVFN(20, 0): /* XHCI */ + RCBA32_OR(FD, PCH_DISABLE_XHCI); + break; case PCI_DEVFN(22, 0): /* MEI #1 */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); break; @@ -89,9 +95,6 @@ static void pch_hide_devfn(unsigned devfn) case PCI_DEVFN(29, 0): /* EHCI #1 */ RCBA32_OR(FD, PCH_DISABLE_EHCI1); break; - case PCI_DEVFN(30, 0): /* PCI-to-PCI Bridge */ - RCBA32_OR(FD, PCH_DISABLE_P2P); - break; case PCI_DEVFN(31, 0): /* LPC */ RCBA32_OR(FD, PCH_DISABLE_LPC); break; @@ -101,7 +104,7 @@ static void pch_hide_devfn(unsigned devfn) case PCI_DEVFN(31, 3): /* SMBUS */ RCBA32_OR(FD, PCH_DISABLE_SMBUS); break; - case PCI_DEVFN(31, 5): /* SATA #22 */ + case PCI_DEVFN(31, 5): /* SATA #2 */ RCBA32_OR(FD, PCH_DISABLE_SATA2); break; case PCI_DEVFN(31, 6): /* Thermal Subsystem */ diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index fa8d75f..1de1080 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -403,6 +403,8 @@ unsigned get_gpios(const int *gpio_num_array); #define D22IP_IDERIP 8 /* IDE-R Pin */ #define D22IP_MEI2IP 4 /* MEI #2 Pin */ #define D22IP_MEI1IP 0 /* MEI #1 Pin */ +#define D20IP 0x3128 /* 32bit */ +#define D20IP_XHCI 0 /* XHCI Pin */ #define D31IR 0x3140 /* 16bit */ #define D30IR 0x3142 /* 16bit */ #define D29IR 0x3144 /* 16bit */ @@ -410,7 +412,11 @@ unsigned get_gpios(const int *gpio_num_array); #define D27IR 0x3148 /* 16bit */ #define D26IR 0x314c /* 16bit */ #define D25IR 0x3150 /* 16bit */ +#define D23IR 0x3158 /* 16bit */ #define D22IR 0x315c /* 16bit */ +#define D20IR 0x3160 /* 16bit */ +#define D21IR 0x3164 /* 16bit */ +#define D19IR 0x3168 /* 16bit */ #define OIC 0x31fe /* 16bit */ #define SOFT_RESET_CTRL 0x38f4 #define SOFT_RESET_DATA 0x38f8 @@ -430,8 +436,8 @@ unsigned get_gpios(const int *gpio_num_array); #define CG 0x341c /* 32bit */ /* Function Disable 1 RCBA 0x3418 */ -#define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26)|(1 << 27)) -#define PCH_DISABLE_P2P (1 << 1) +#define PCH_DISABLE_ALWAYS (1 << 0) +#define PCH_DISABLE_ADSPD (1 << 1) #define PCH_DISABLE_SATA1 (1 << 2) #define PCH_DISABLE_SMBUS (1 << 3) #define PCH_DISABLE_HD_AUDIO (1 << 4) @@ -441,6 +447,7 @@ unsigned get_gpios(const int *gpio_num_array); #define PCH_DISABLE_PCIE(x) (1 << (16 + x)) #define PCH_DISABLE_THERMAL (1 << 24) #define PCH_DISABLE_SATA2 (1 << 25) +#define PCH_DISABLE_XHCI (1 << 27) /* Function Disable 2 RCBA 0x3428 */ #define PCH_DISABLE_KT (1 << 4) diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 81d4a1d..25eb94f 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -23,6 +23,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <delay.h> #include "pch.h" typedef struct southbridge_intel_lynxpoint_config config_t; @@ -123,6 +124,7 @@ static void sata_init(struct device *dev) reg16 &= ~0x3f; reg16 |= 0x8000 | config->sata_port_map; pci_write_config16(dev, 0x92, reg16); + udelay(2); /* Setup register 98h */ reg32 = pci_read_config16(dev, 0x98); @@ -138,6 +140,7 @@ static void sata_init(struct device *dev) #if CONFIG_INTEL_LYNXPOINT_LP reg32 &= ~((1 << 31) | (1 << 30)); reg32 |= 1 << 23; + reg32 |= 1 << 24; /* Disable listen mode (hotplug) */ #endif pci_write_config32(dev, 0x98, reg32); @@ -159,6 +162,9 @@ static void sata_init(struct device *dev) reg32 = read32(abar + 0x00); reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS reg32 &= ~0x00020060; // clear SXS+EMS+PMS +#if CONFIG_INTEL_LYNXPOINT_LP + reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY +#endif write32(abar + 0x00, reg32); /* PI (Ports implemented) */ write32(abar + 0x0c, config->sata_port_map); @@ -166,12 +172,13 @@ static void sata_init(struct device *dev) (void) read32(abar + 0x0c); /* Read back 2 */ /* CAP2 (HBA Capabilities Extended)*/ reg32 = read32(abar + 0x24); +#if CONFIG_INTEL_LYNXPOINT_LP + /* Enable DEVSLP */ + reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2); +#else reg32 &= ~0x00000002; +#endif write32(abar + 0x24, reg32); - /* VSP (Vendor Specific Register */ - reg32 = read32(abar + 0xa0); - reg32 &= ~0x00000005; - write32(abar + 0xa0, reg32); } else { printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); @@ -230,15 +237,33 @@ static void sata_init(struct device *dev) /* Additional Programming Requirements */ /* Power Optimizer */ + + /* Step 1 */ +#if CONFIG_INTEL_LYNXPOINT_LP + sir_write(dev, 0x64, 0x883c9003); +#else sir_write(dev, 0x64, 0x883c9001); +#endif + /* Step 2: SIR 68h[15:0] = 880Ah */ reg32 = sir_read(dev, 0x68); reg32 &= 0xffff0000; reg32 |= 0x880a; sir_write(dev, 0x68, reg32); + /* Step 3: SIR 60h[3] = 1 */ + reg32 = sir_read(dev, 0x60); + reg32 |= (1 << 3); + sir_write(dev, 0x60, reg32); + + /* Step 4: SIR 60h[0] = 1 */ + reg32 = sir_read(dev, 0x60); + reg32 |= (1 << 0); + sir_write(dev, 0x60, reg32); + + /* Step 5: SIR 60h[1] = 1 */ reg32 = sir_read(dev, 0x60); - reg32 |= (1 << 0) | (1 << 1) | (1 << 3); + reg32 |= (1 << 1); sir_write(dev, 0x60, reg32); /* Clock Gating */ diff --git a/src/southbridge/intel/lynxpoint/spi.c b/src/southbridge/intel/lynxpoint/spi.c index ec7c862..123c6a9 100644 --- a/src/southbridge/intel/lynxpoint/spi.c +++ b/src/southbridge/intel/lynxpoint/spi.c @@ -68,18 +68,6 @@ typedef struct spi_slave ich_spi_slave; static int ichspi_lock = 0; -typedef struct ich7_spi_regs { - uint16_t spis; - uint16_t spic; - uint32_t spia; - uint64_t spid[8]; - uint64_t _pad; - uint32_t bbar; - uint16_t preop; - uint16_t optype; - uint8_t opmenu[8]; -} __attribute__((packed)) ich7_spi_regs; - typedef struct ich9_spi_regs { uint32_t bfpr; uint16_t hsfs; @@ -302,110 +290,40 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, return slave; } -/* - * Check if this device ID matches one of supported Intel PCH devices. - * - * Return the ICH version if there is a match, or zero otherwise. - */ -static inline int get_ich_version(uint16_t device_id) -{ - if (device_id >= PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_MIN && - device_id <= PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_MAX) - return 9; - - return 0; -} - void spi_init(void) { - int ich_version = 0; - uint8_t *rcrb; /* Root Complex Register Block */ uint32_t rcba; /* Root Complex Base Address */ uint8_t bios_cntl; device_t dev; - uint32_t ids; - uint16_t vendor_id, device_id; + ich9_spi_regs *ich9_spi; #ifdef __SMM__ dev = PCI_DEV(0, 31, 0); #else dev = dev_find_slot(0, PCI_DEVFN(31, 0)); #endif - pci_read_config_dword(dev, 0, &ids); - vendor_id = ids; - device_id = (ids >> 16); - - if (vendor_id != PCI_VENDOR_ID_INTEL) { - printk(BIOS_DEBUG, "ICH SPI: No ICH found.\n"); - return; - } - - ich_version = get_ich_version(device_id); - - if (!ich_version) { - printk(BIOS_DEBUG, "ICH SPI: No known ICH found.\n"); - return; - } pci_read_config_dword(dev, 0xf0, &rcba); /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ rcrb = (uint8_t *)(rcba & 0xffffc000); - switch (ich_version) { - case 7: - { - const uint16_t ich7_spibar_offset = 0x3020; - ich7_spi_regs *ich7_spi = - (ich7_spi_regs *)(rcrb + ich7_spibar_offset); - - ichspi_lock = readw_(&ich7_spi->spis) & SPIS_LOCK; - cntlr.opmenu = ich7_spi->opmenu; - cntlr.menubytes = sizeof(ich7_spi->opmenu); - cntlr.optype = &ich7_spi->optype; - cntlr.addr = &ich7_spi->spia; - cntlr.data = (uint8_t *)ich7_spi->spid; - cntlr.databytes = sizeof(ich7_spi->spid); - cntlr.status = (uint8_t *)&ich7_spi->spis; - cntlr.control = &ich7_spi->spic; - cntlr.bbar = &ich7_spi->bbar; - cntlr.preop = &ich7_spi->preop; - break; - } - case 9: - { - const uint16_t ich9_spibar_offset = 0x3800; - ich9_spi_regs *ich9_spi = - (ich9_spi_regs *)(rcrb + ich9_spibar_offset); - ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN; - cntlr.opmenu = ich9_spi->opmenu; - cntlr.menubytes = sizeof(ich9_spi->opmenu); - cntlr.optype = &ich9_spi->optype; - cntlr.addr = &ich9_spi->faddr; - cntlr.data = (uint8_t *)ich9_spi->fdata; - cntlr.databytes = sizeof(ich9_spi->fdata); - cntlr.status = &ich9_spi->ssfs; - cntlr.control = (uint16_t *)ich9_spi->ssfc; - cntlr.bbar = &ich9_spi->bbar; - cntlr.preop = &ich9_spi->preop; - break; - } - default: - printk(BIOS_DEBUG, "ICH SPI: Unrecognized ICH version %d.\n", ich_version); - } - + ich9_spi = (ich9_spi_regs *)(rcrb + 0x3800); + ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN; + cntlr.opmenu = ich9_spi->opmenu; + cntlr.menubytes = sizeof(ich9_spi->opmenu); + cntlr.optype = &ich9_spi->optype; + cntlr.addr = &ich9_spi->faddr; + cntlr.data = (uint8_t *)ich9_spi->fdata; + cntlr.databytes = sizeof(ich9_spi->fdata); + cntlr.status = &ich9_spi->ssfs; + cntlr.control = (uint16_t *)ich9_spi->ssfc; + cntlr.bbar = &ich9_spi->bbar; + cntlr.preop = &ich9_spi->preop; ich_set_bbar(0); /* Disable the BIOS write protect so write commands are allowed. */ pci_read_config_byte(dev, 0xdc, &bios_cntl); - switch (ich_version) { - case 9: - /* Deassert SMM BIOS Write Protect Disable. */ - bios_cntl &= ~(1 << 5); - break; - - default: - break; - } + bios_cntl &= ~(1 << 5); pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1); }

1 0

Patch set updated for coreboot: f2bbdf6 haswell platforms: restructure romstage main
by Stefan Reinauer 13 Mar '13

13 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2681 -gerrit commit f2bbdf64035eb0011e4565f3d8146da9d7c2e22c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Dec 19 11:31:17 2012 -0600 haswell platforms: restructure romstage main There was a mix of setup code sprinkled across the various components: southbridge code in the northbridge, etc. This commit reorganizes the code so that northbridge code doesn't initialize southbridge components. Additionally, the calling dram initialization no longer calls out to ME code. The main() function in the mainboard calls the necessary ME functions before and after dram initialization. The biggest change is the addition of an early_pch_init() function which initializes the BARs, GPIOs, and RCBA configuration. It is also responsible for reporting back to the caller if the board is being woken up from S3. The one sequence difference is that the RCBA config is performed before claling the reference code. Lastly the rcba configuration was changed to be table driven so that different board/configurations can use the same code. It should be possible to have board/configuration specific gpio and rcba configuration while reusing the romstage code. Change-Id: I830e41b426261dd686a2701ce054fc39f296dffa Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/intel/baskingridge/romstage.c | 136 +++++---------------- src/northbridge/intel/haswell/early_init.c | 22 ---- src/northbridge/intel/haswell/raminit.c | 17 +-- src/southbridge/intel/lynxpoint/Makefile.inc | 2 +- src/southbridge/intel/lynxpoint/early_pch.c | 172 +++++++++++++++++++++++++++ src/southbridge/intel/lynxpoint/pch.h | 48 +++++++- 6 files changed, 256 insertions(+), 141 deletions(-) diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index 2a8e910..9561456 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -33,7 +33,7 @@ #include "northbridge/intel/haswell/haswell.h" #include "northbridge/intel/haswell/raminit.h" #include "southbridge/intel/lynxpoint/pch.h" -#include "southbridge/intel/lynxpoint/gpio.h" +#include "southbridge/intel/lynxpoint/me.h" #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> @@ -42,22 +42,7 @@ #include <vendorcode/google/chromeos/chromeos.h> #endif -static void pch_enable_lpc(void) -{ - device_t dev = PCH_LPC_DEV; - - /* Set COM1/COM2 decode range */ - pci_write_config16(dev, LPC_IO_DEC, 0x0010); - - /* Enable SuperIO + COM1 + PS/2 Keyboard/Mouse */ - u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN | KBC_LPC_EN; - pci_write_config16(dev, LPC_EN, lpc_config); -} - -static void rcba_config(void) -{ - u32 reg32; - +const struct rcba_config_instruction rcba_config[] = { /* * GFX INTA -> PIRQA (MSI) * D28IP_P1IP WLAN INTA -> PIRQB @@ -71,55 +56,42 @@ static void rcba_config(void) */ /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D30IP) = (NOINT << D30IP_PIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P4IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), + RCBA_SET_REG_32(D30IP, (NOINT << D30IP_PIP)), + RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), + RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | + (INTB << D28IP_P4IP)), + RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), + RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), + RCBA_SET_REG_32(D25IP, (NOINT << D25IP_LIP)), + RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQF, PIRQG, PIRQH, PIRQA); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); - DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); - DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB); - DIR_ROUTE(D26IR, PIRQE, PIRQF, PIRQG, PIRQH); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQF, PIRQG, PIRQH, PIRQA)), + RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG)), + RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE)), + RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQH, PIRQA, PIRQB)), + RCBA_SET_REG_32(D26IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), + RCBA_SET_REG_32(D25IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), + RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), /* Disable unused devices (board specific) */ - reg32 = RCBA32(FD); - reg32 |= PCH_DISABLE_ALWAYS; - RCBA32(FD) = reg32; -} + RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), -// FIXME, this function is generic code that should go to sb/... or -// nb/../early_init.c -static void early_pch_init(void) -{ - u8 reg8; + /* Enable IOAPIC (generic) */ + RCBA_SET_REG_16(OIC, 0x0100), + /* PCH BWG says to read back the IOAPIC enable register */ + RCBA_READ_REG_16(OIC), - // reset rtc power status - reg8 = pci_read_config8(PCH_LPC_DEV, 0xa4); - reg8 &= ~(1 << 2); - pci_write_config8(PCH_LPC_DEV, 0xa4, reg8); -} + RCBA_END_CONFIG, +}; void main(unsigned long bist) { int boot_mode = 0; + int wake_from_s3; int cbmem_was_initted; - u32 pm1_cnt; - u16 pm1_sts; #if CONFIG_COLLECT_TIMESTAMPS tsc_t start_romstage_time; @@ -180,64 +152,26 @@ void main(unsigned long bist) if (bist == 0) enable_lapic(); - pch_enable_lpc(); - - /* Enable GPIOs */ - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); - pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); - setup_pch_gpios(&mainboard_gpio_map); - - /* Early Console setup */ - console_init(); + wake_from_s3 = early_pch_init(&mainboard_gpio_map, &rcba_config[0]); /* Halt if there was a built in self test failure */ report_bist_failure(bist); - /* - * FIXME: MCHBAR isn't setup yet. It's setup in - * haswell_early_initialization(). - */ - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected\n"); - boot_mode = 1; - - /* System is not happy after keyboard reset... */ - printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); - outb(0x6, 0xcf9); - while (1) { - hlt(); - } - } - /* Perform some early chipset initialization required * before RAM initialization can work */ haswell_early_initialization(HASWELL_MOBILE); printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n"); - /* Check PM1_STS[15] to see if we are waking from Sx */ - pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); - - /* Read PM1_CNT[12:10] to determine which Sx state */ - pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); - - if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { + if (wake_from_s3) { #if CONFIG_HAVE_ACPI_RESUME printk(BIOS_DEBUG, "Resume from S3 detected.\n"); boot_mode = 2; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); #else printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); #endif } - post_code(0x38); - /* Enable SPD ROMs and DDR-III DRAM */ - enable_smbus(); - /* Prepare USB controller early in S3 resume */ if (boot_mode == 2) enable_usb_bar(); @@ -247,21 +181,17 @@ void main(unsigned long bist) #if CONFIG_COLLECT_TIMESTAMPS before_dram_time = rdtsc(); #endif + + report_platform_info(); + sdram_initialize(&pei_data); #if CONFIG_COLLECT_TIMESTAMPS after_dram_time = rdtsc(); #endif post_code(0x3b); - /* Perform some initialization that must run before stage2 */ - early_pch_init(); - post_code(0x3c); - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - post_code(0x3d); + intel_early_me_status(); quick_ram_check(); post_code(0x3e); diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index 505fbf1..681af42 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -29,20 +29,6 @@ static void haswell_setup_bars(void) { - /* Setting up Southbridge. In the northbridge code. */ - printk(BIOS_DEBUG, "Setting up static southbridge registers..."); - pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1); - - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */ - - printk(BIOS_DEBUG, " done.\n"); - - printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); - RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ - outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ - printk(BIOS_DEBUG, " done.\n"); - printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); @@ -62,14 +48,6 @@ static void haswell_setup_bars(void) pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); printk(BIOS_DEBUG, " done.\n"); - -#if CONFIG_ELOG_BOOT_COUNT - /* Increment Boot Counter except when resuming from S3 */ - if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && - ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) - return; - boot_count_increment(); -#endif } static void haswell_setup_graphics(void) diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 0c68e60..e2b085b 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -32,8 +32,6 @@ #include "pei_data.h" #include "haswell.h" -/* Management Engine is in the southbridge */ -#include "southbridge/intel/lynxpoint/me.h" #if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/chromeos.h> #else @@ -152,12 +150,6 @@ void sdram_initialize(struct pei_data *pei_data) struct sys_info sysinfo; unsigned long entry; - report_platform_info(); - - /* Wait for ME to be ready */ - intel_early_me_init(); - intel_early_me_uma_size(); - printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n"); memset(&sysinfo, 0, sizeof(sysinfo)); @@ -216,8 +208,6 @@ void sdram_initialize(struct pei_data *pei_data) version >> 24 , (version >> 16) & 0xff, (version >> 8) & 0xff, version & 0xff); - intel_early_me_status(); - report_memory_config(); /* S3 resume: don't save scrambler seed or MRC data */ @@ -232,7 +222,10 @@ struct cbmem_entry *get_cbmem_toc(void) unsigned long get_top_of_ram(void) { - /* Base of TSEG is top of usable DRAM */ + /* + * Base of TSEG is top of usable DRAM below 4GiB. The register has + * 1 MiB alignement. + */ u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); - return (unsigned long) tom; + return (unsigned long) tom & ~((1 << 20) - 1); } diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index c14a538..6e84ce6 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -45,7 +45,7 @@ smm-$(CONFIG_SPI_FLASH_SMM) += spi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c finalize.c -romstage-y += early_usb.c early_smbus.c early_me.c me_status.c +romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c romstage-$(CONFIG_USBDEBUG) += usb_debug.c romstage-y += reset.c early_spi.c diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c new file mode 100644 index 0000000..9757d8a --- /dev/null +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -0,0 +1,172 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 ChromeOS Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <console/console.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> +#include <elog.h> +#include "pch.h" + +#if CONFIG_INTEL_LYNXPOINT_LP +#include "lp_gpio.h" +#else +#include "gpio.h" +#endif + +static void pch_enable_bars(void) +{ + /* Setting up Southbridge. In the northbridge code. */ + pci_write_config32(PCH_LPC_DEV, RCBA, DEFAULT_RCBA | 1); + + pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); + /* Enable ACPI BAR */ + pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80); + + pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); + + /* Enable GPIO functionality. */ + pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); +} + +static void pch_generic_setup(void) +{ + u8 reg8; + + printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); + RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ + outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ + printk(BIOS_DEBUG, " done.\n"); + + // reset rtc power status + reg8 = pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3); + reg8 &= ~(1 << 2); + pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, reg8); +} + +static int sleep_type_s3(void) +{ + u32 pm1_cnt; + u16 pm1_sts; + int is_s3 = 0; + + /* Check PM1_STS[15] to see if we are waking from Sx */ + pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); + if (pm1_sts & WAK_STS) { + /* Read PM1_CNT[12:10] to determine which Sx state */ + pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); + if (((pm1_cnt >> 10) & 7) == SLP_TYP_S3) { + /* Clear SLP_TYPE. */ + outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); + is_s3 = 1; + } + } + return is_s3; +} + +static void pch_enable_lpc(void) +{ + device_t dev = PCH_LPC_DEV; + + /* Set COM1/COM2 decode range */ + pci_write_config16(dev, LPC_IO_DEC, 0x0010); + + /* Enable SuperIO + COM1 + PS/2 Keyboard/Mouse */ + u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN | KBC_LPC_EN; + pci_write_config16(dev, LPC_EN, lpc_config); +} + +static void pch_config_rcba(const struct rcba_config_instruction *rcba_config) +{ + const struct rcba_config_instruction *rc; + u32 value; + + rc = rcba_config; + while (rc->command != RCBA_COMMAND_END) + { + if ((rc->command & RCBA_REG_SIZE_MASK) == RCBA_REG_SIZE_16) { + switch (rc->command & RCBA_COMMAND_MASK) { + case RCBA_COMMAND_SET: + RCBA16(rc->reg) = (u16)rc->or_value; + break; + case RCBA_COMMAND_READ: + (void)RCBA16(rc->reg); + break; + case RCBA_COMMAND_RMW: + value = RCBA16(rc->reg); + value &= rc->mask; + value |= rc->or_value; + RCBA16(rc->reg) = (u16)value; + break; + } + } else { + switch (rc->command & RCBA_COMMAND_MASK) { + case RCBA_COMMAND_SET: + RCBA32(rc->reg) = rc->or_value; + break; + case RCBA_COMMAND_READ: + (void)RCBA32(rc->reg); + break; + case RCBA_COMMAND_RMW: + value = RCBA32(rc->reg); + value &= rc->mask; + value |= rc->or_value; + RCBA32(rc->reg) = value; + break; + } + } + rc++; + } +} + +int early_pch_init(const void *gpio_map, + const struct rcba_config_instruction *rcba_config) +{ + int wake_from_s3; + + pch_enable_lpc(); + + pch_enable_bars(); + +#if CONFIG_INTEL_LYNXPOINT_LP + setup_pch_lp_gpios(gpio_map); +#else + setup_pch_gpios(gpio_map); +#endif + + console_init(); + + pch_generic_setup(); + + /* Enable SMBus for reading SPDs. */ + enable_smbus(); + + pch_config_rcba(rcba_config); + + wake_from_s3 = sleep_type_s3(); + +#if CONFIG_ELOG_BOOT_COUNT + if (!wake_from_s3) + boot_count_increment(); +#endif + + /* Report if we are waking from s3. */ + return wake_from_s3; +} diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 1de1080..4da2c62 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -102,6 +102,48 @@ void enable_smbus(void); void enable_usb_bar(void); int smbus_read_byte(unsigned device, unsigned address); int early_spi_read(u32 offset, u32 size, u8 *buffer); + +/* State Machine configuration. */ +#define RCBA_REG_SIZE_MASK 0x8000 +#define RCBA_REG_SIZE_16 0x8000 +#define RCBA_REG_SIZE_32 0x0000 +#define RCBA_COMMAND_MASK 0x000f +#define RCBA_COMMAND_SET 0x0001 +#define RCBA_COMMAND_READ 0x0002 +#define RCBA_COMMAND_RMW 0x0003 +#define RCBA_COMMAND_END 0x0007 + +#define RCBA_ENCODE_COMMAND(command_, reg_, mask_, or_value_) \ + { .command = command_, \ + .reg = reg_, \ + .mask = mask_, \ + .or_value = or_value_ \ + } +#define RCBA_SET_REG_32(reg_, value_) \ + RCBA_ENCODE_COMMAND(RCBA_REG_SIZE_32|RCBA_COMMAND_SET, reg_, 0, value_) +#define RCBA_READ_REG_32(reg_) \ + RCBA_ENCODE_COMMAND(RCBA_REG_SIZE_32|RCBA_COMMAND_READ, reg_, 0, 0) +#define RCBA_RMW_REG_32(reg_, mask_, or_) \ + RCBA_ENCODE_COMMAND(RCBA_REG_SIZE_32|RCBA_COMMAND_RMW, reg_, mask_, or_) +#define RCBA_SET_REG_16(reg_, value_) \ + RCBA_ENCODE_COMMAND(RCBA_REG_SIZE_16|RCBA_COMMAND_SET, reg_, 0, value_) +#define RCBA_READ_REG_16(reg_) \ + RCBA_ENCODE_COMMAND(RCBA_REG_SIZE_16|RCBA_COMMAND_READ, reg_, 0, 0) +#define RCBA_RMW_REG_16(reg_, mask_, or_) \ + RCBA_ENCODE_COMMAND(RCBA_REG_SIZE_16|RCBA_COMMAND_RMW, reg_, mask_, or_) +#define RCBA_END_CONFIG \ + RCBA_ENCODE_COMMAND(RCBA_COMMAND_END, 0, 0, 0) + +struct rcba_config_instruction +{ + u16 command; + u16 reg; + u32 mask; + u32 or_value; +}; + +int early_pch_init(const void *gpio_map, + const struct rcba_config_instruction *rcba_config); #endif /* * get GPIO pin value @@ -421,9 +463,9 @@ unsigned get_gpios(const int *gpio_num_array); #define SOFT_RESET_CTRL 0x38f4 #define SOFT_RESET_DATA 0x38f8 -#define DIR_ROUTE(x,a,b,c,d) \ - RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ - ((b) << DIR_IBR) | ((a) << DIR_IAR)) +#define DIR_ROUTE(a,b,c,d) \ + (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ + ((b) << DIR_IBR) | ((a) << DIR_IAR)) #define RC 0x3400 /* 32bit */ #define HPTC 0x3404 /* 32bit */

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Patch set updated for coreboot: f7b7845 lynxpoint: lpc resource reservations
by Stefan Reinauer 13 Mar '13

13 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2682 -gerrit commit f7b78458911d5179642c80356f5615c0ab5d2848 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Dec 19 14:38:01 2012 -0600 lynxpoint: lpc resource reservations This commit updates the Lynx Point resource reservations before the coreboot allocator assigns resources. There is no need to mark anything as subtractive decode because there are no devices/buses linked to the LPC device. The I/O range reservations consists of claiming the first 4KiB of I/O space. The PMBASE, GPIOBASE, and LPC generic I/O decode ranges are checked against the default claimed range. If those ranges overlap or fall outside of the default range then those resources are added. The MMIO range reservations consist of claiming everything from the I/O APIC to 4GiB. The RCBA and the LPC Generic Memory range register are then conditionally added if they fall outside of the default MMIO range. Change-Id: I0f560a03814a2b15961fdbe61e4164cd54cff7a5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/intel/lynxpoint/lpc.c | 167 +++++++++++++++++++++++----------- src/southbridge/intel/lynxpoint/pch.h | 1 + 2 files changed, 113 insertions(+), 55 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index a44d80f..facea7c 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -574,74 +574,131 @@ static void lpc_init(struct device *dev) pch_fixups(dev); } -static void pch_lpc_read_resources(device_t dev) +static void pch_lpc_add_mmio_resources(device_t dev) { + u32 reg; struct resource *res; - config_t *config = dev->chip_info; - u8 io_index = 0; - - /* Get the normal PCI resources of this device. */ - pci_dev_read_resources(dev); - - /* Add an extra subtractive resource for both memory and I/O. */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); - res->base = 0; - res->size = 0x1000; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + const u32 default_decode_base = IO_APIC_ADDR; - /* GPIOBASE */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); - res->base = DEFAULT_GPIOBASE; - res->size = DEFAULT_GPIOSIZE; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); - res->base = 0xff800000; - res->size = 0x00800000; /* 8 MB for flash */ - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, io_index++); /* IOAPIC */ - res->base = IO_APIC_ADDR; - res->size = 0x00001000; + /* + * Just report all resources from IO-APIC base to 4GiB. Don't mark + * them reserved as that may upset the OS if this range is marked + * as reserved in the e820. + */ + res = new_resource(dev, OIC); + res->base = default_decode_base; + res->size = 0 - default_decode_base; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - /* Set PCH IO decode ranges if required.*/ - if ((config->gen1_dec & 0xFFFC) > 0x1000) { - res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); - res->base = config->gen1_dec & 0xFFFC; - res->size = (config->gen1_dec >> 16) & 0xFC; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + /* RCBA */ + if (DEFAULT_RCBA < default_decode_base) { + res = new_resource(dev, RCBA); + res->base = DEFAULT_RCBA; + res->size = 16 * 1024; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | + IORESOURCE_FIXED | IORESOURCE_RESERVE; } - if ((config->gen2_dec & 0xFFFC) > 0x1000) { - res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); - res->base = config->gen2_dec & 0xFFFC; - res->size = (config->gen2_dec >> 16) & 0xFC; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + /* Check LPC Memory Decode register. */ + reg = pci_read_config32(dev, LGMR); + if (reg & 1) { + reg &= ~0xffff; + if (reg < default_decode_base) { + res = new_resource(dev, LGMR); + res->base = reg; + res->size = 16 * 1024; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | + IORESOURCE_FIXED | IORESOURCE_RESERVE; + } } +} - if ((config->gen3_dec & 0xFFFC) > 0x1000) { - res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); - res->base = config->gen3_dec & 0xFFFC; - res->size = (config->gen3_dec >> 16) & 0xFC; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - } +/* Default IO range claimed by the LPC device. The upper bound is exclusive. */ +#define LPC_DEFAULT_IO_RANGE_LOWER 0 +#define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 + +static inline int pch_io_range_in_default(u16 base, u16 size) +{ + /* Does it start above the range? */ + if (base >= LPC_DEFAULT_IO_RANGE_UPPER) + return 0; + + /* Is it entirely contained? */ + if (base >= LPC_DEFAULT_IO_RANGE_LOWER && + (base + size) < LPC_DEFAULT_IO_RANGE_UPPER) + return 1; + + /* This will return not in range for partial overlaps. */ + return 0; +} + +/* + * Note: this function assumes there is no overlap with the default LPC device's + * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. + */ +static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index) +{ + struct resource *res; + + if (pch_io_range_in_default(base, size)) + return; - if ((config->gen4_dec & 0xFFFC) > 0x1000) { - res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); - res->base = config->gen4_dec & 0xFFFC; - res->size = (config->gen4_dec >> 16) & 0xFC; - res->flags = IORESOURCE_IO| IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res = new_resource(dev, index); + res->base = base; + res->size = size; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index) +{ + /* + * Check if the register is enabled. If so and the base exceeds the + * device's deafult claim range add the resoure. + */ + if (reg_value & 1) { + u16 base = reg_value & 0xfffc; + u16 size = (0x3 | ((reg_value >> 16) & 0xfc)) + 1; + pch_lpc_add_io_resource(dev, base, size, index); } } +static void pch_lpc_add_io_resources(device_t dev) +{ + struct resource *res; + config_t *config = dev->chip_info; + + /* Add the default claimed IO range for the LPC device. */ + res = new_resource(dev, 0); + res->base = LPC_DEFAULT_IO_RANGE_LOWER; + res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + /* GPIOBASE */ + pch_lpc_add_io_resource(dev, DEFAULT_GPIOBASE, DEFAULT_GPIOSIZE, + GPIO_BASE); + + /* PMBASE */ + pch_lpc_add_io_resource(dev, DEFAULT_PMBASE, 128, PMBASE); + + /* LPC Generic IO Decode range. */ + pch_lpc_add_gen_io_resources(dev, config->gen1_dec, LPC_GEN1_DEC); + pch_lpc_add_gen_io_resources(dev, config->gen2_dec, LPC_GEN2_DEC); + pch_lpc_add_gen_io_resources(dev, config->gen3_dec, LPC_GEN3_DEC); + pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC); +} + +static void pch_lpc_read_resources(device_t dev) +{ + /* Get the normal PCI resources of this device. */ + pci_dev_read_resources(dev); + + /* Add non-standard MMIO resources. */ + pch_lpc_add_mmio_resources(dev); + + /* Add IO resources. */ + pch_lpc_add_io_resources(dev); +} + static void pch_lpc_enable_resources(device_t dev) { pch_decode_init(dev); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 4da2c62..eea3465 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -227,6 +227,7 @@ unsigned get_gpios(const int *gpio_num_array); #define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ +#define LGMR 0x98 /* LPC Generic Memory Range */ /* PCI Configuration Space (D31:F1): IDE */ #define PCH_IDE_DEV PCI_DEV(0, 0x1f, 1)

1 0

Patch set updated for coreboot: 1427523 lynxpoint: Move a bit of generic RCBA into early_pch
by Stefan Reinauer 13 Mar '13

13 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2683 -gerrit commit 1427523f2c1e7f87c3ca7ae193254513ae3c2144 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Dec 19 13:17:06 2012 -0800 lynxpoint: Move a bit of generic RCBA into early_pch Rather than have to repeat this bit in every mainboard. Also, remove the reset of the RTC power status from here. We had done this in TOT for current platforms but did not carry it back to emeraldlake2 where this branched from. If we clear the status here then we don't get an event logged later which can be important for the devices that do not have a CMOS battery. Change-Id: Ia7131e9d9e7cf86228a285df652a96bcabf05260 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/intel/baskingridge/romstage.c | 5 ----- src/southbridge/intel/lynxpoint/early_pch.c | 20 +++++++++++++------- 2 files changed, 13 insertions(+), 12 deletions(-) diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index 9561456..d47fbf1 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -79,11 +79,6 @@ const struct rcba_config_instruction rcba_config[] = { /* Disable unused devices (board specific) */ RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), - /* Enable IOAPIC (generic) */ - RCBA_SET_REG_16(OIC, 0x0100), - /* PCH BWG says to read back the IOAPIC enable register */ - RCBA_READ_REG_16(OIC), - RCBA_END_CONFIG, }; diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 9757d8a..c87da27 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -31,6 +31,15 @@ #include "gpio.h" #endif +const struct rcba_config_instruction pch_early_config[] = { + /* Enable IOAPIC */ + RCBA_SET_REG_16(OIC, 0x0100), + /* PCH BWG says to read back the IOAPIC enable register */ + RCBA_READ_REG_16(OIC), + + RCBA_END_CONFIG, +}; + static void pch_enable_bars(void) { /* Setting up Southbridge. In the northbridge code. */ @@ -48,17 +57,10 @@ static void pch_enable_bars(void) static void pch_generic_setup(void) { - u8 reg8; - printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ printk(BIOS_DEBUG, " done.\n"); - - // reset rtc power status - reg8 = pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3); - reg8 &= ~(1 << 2); - pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, reg8); } static int sleep_type_s3(void) @@ -158,6 +160,10 @@ int early_pch_init(const void *gpio_map, /* Enable SMBus for reading SPDs. */ enable_smbus(); + /* Early PCH RCBA settings */ + pch_config_rcba(pch_early_config); + + /* Mainboard RCBA settings */ pch_config_rcba(rcba_config); wake_from_s3 = sleep_type_s3();

1 0

Patch set updated for coreboot: 67a9cfd haswell: remove CONFIG_GFXUMA
by Stefan Reinauer 13 Mar '13

13 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2678 -gerrit commit 67a9cfdf7ef352a95861bfa4f19ed41c985a7cd9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Dec 18 14:18:53 2012 -0600 haswell: remove CONFIG_GFXUMA This option is not required for haswell. Enabling the option doesn't do anything aside from complicate mtrr calculation. Therefore, remove it. Change-Id: I897523ff7d3606eb89961674c2eb3d384e584857 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/intel/baskingridge/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index a8478a8..830c650 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MAINBOARD_RESOURCES select MMCONF_SUPPORT select HAVE_SMI_HANDLER - select GFXUMA select CHROMEOS select EXTERNAL_MRC_BLOB

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coreboot March 2013