coreboot March 2013

coreboot@coreboot.org

46 participants
782 discussions

Running into error building Filo
by Pankaj Chhabra 10 Mar '13

10 Mar '13

Hello, I am building Filo on Ubuntu 12.04.1, I am see the error in building FILO, here is the snippet of the error nkaj/LDev/coreboot/payloads/external/FILO/filo/build/util/kconfig/mconf.o: In function `main': mconf.c:(.text+0x1807): undefined reference to `stdscr' mconf.c:(.text+0x1810): undefined reference to `stdscr' mconf.c:(.text+0x1824): undefined reference to `stdscr' mconf.c:(.text+0x182d): undefined reference to `stdscr' /home/pankaj/LDev/coreboot/payloads/external/FILO/filo/build/util/kconfig/lxdialog/checklist.o: In function `print_item': checklist.c:(.text+0x2e): undefined reference to `wmove' checklist.c:(.text+0x4a): undefined reference to `waddch' checklist.c:(.text+0x73): undefined reference to `wmove' checklist.c:(.text+0xc4): undefined reference to `wprintw' checklist.c:(.text+0xfd): undefined reference to `wmove' checklist.c:(.text+0x11c): undefined reference to `waddch' checklist.c:(.text+0x159): undefined reference to `waddnstr' checklist.c:(.text+0x17d): undefined reference to `wmove' checklist.c:(.text+0x188): undefined reference to `wrefresh' /home/pankaj/LDev/coreboot/payloads/external/FILO/filo/build/util/kconfig/lxdialog/checklist.o: In function `print_arrows': checklist.c:(.text+0x1a9): undefined reference to `wmove' It seems like ncurses is not included. Could you please let me know how to fix this issue? Thanks. Regards, Pankaj

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Patch set updated for coreboot: 0996b48 pci.h: Drop unused `mainboard_pci_subsystem*` prototypes
by Paul Menzel 09 Mar '13

09 Mar '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2625 -gerrit commit 0996b48bf2a693103fdc8b5b3085ae602486abc8 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Mar 9 13:24:43 2013 +0100 pci.h: Drop unused `mainboard_pci_subsystem*` prototypes We used to allow mainboards to override subsystems using mainboard_pci_subsystem_vendor_id and mainboard_pci_subsystem_device_id. Mechanisms have changed and the only occurrence of these names is in the header. Change-Id: Ic2ab13201a2740c98868fdf580140b7758b62263 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/include/device/pci.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/include/device/pci.h b/src/include/device/pci.h index a215a2a..132c48c 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -106,8 +106,5 @@ static inline const struct pci_bus_operations *ops_pci_bus(struct bus *bus) return bops; } -unsigned mainboard_pci_subsystem_vendor_id(struct device *dev); -unsigned mainboard_pci_subsystem_device_id(struct device *dev); - #endif #endif /* PCI_H */

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ASRock E350M1 : lspci
by Alvaro G. [Andor] 09 Mar '13

09 Mar '13

Hi there! First of all, I just got into the mailing list, this is my first message. So, hi everyone. Second, Paul told me on IRC somebody was in need of the lspci output for an E350M1 with vendor BIOS. It's a E350M1, with no aditional pci/pci express cards plugged in, and last vendor BIOS version (at least it was the last two weeks ago). It's Ubuntu 12.10 with kernel 3.5.0-24-generic. So here we go: sudo lspci -H1 00:00.0 Host bridge: Advanced Micro Devices [AMD] Family 14h Processor Root Complex 00:01.0 VGA compatible controller: Advanced Micro Devices [AMD] nee ATI Wrestler [Radeon HD 6310] 00:01.1 Audio device: Advanced Micro Devices [AMD] nee ATI Wrestler HDMI Audio [Radeon HD 6250/6310] 00:04.0 PCI bridge: Advanced Micro Devices [AMD] Family 14h Processor Root Port 00:11.0 SATA controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 SATA Controller [AHCI mode] (rev 40) 00:12.0 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller 00:12.2 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller 00:13.0 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller 00:13.2 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller 00:14.0 SMBus: Advanced Micro Devices [AMD] nee ATI SBx00 SMBus Controller (rev 42) 00:14.2 Audio device: Advanced Micro Devices [AMD] nee ATI SBx00 Azalia (Intel HDA) (rev 40) 00:14.3 ISA bridge: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 LPC host controller (rev 40) 00:14.4 PCI bridge: Advanced Micro Devices [AMD] nee ATI SBx00 PCI to PCI Bridge (rev 40) 00:14.5 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI2 Controller 00:15.0 PCI bridge: Advanced Micro Devices [AMD] nee ATI SB700/SB800/SB900 PCI to PCI bridge (PCIE port 0) 00:15.1 PCI bridge: Advanced Micro Devices [AMD] nee ATI SB700/SB800/SB900 PCI to PCI bridge (PCIE port 1) 00:15.2 PCI bridge: Advanced Micro Devices [AMD] nee ATI SB900 PCI to PCI bridge (PCIE port 2) 00:16.0 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI0 Controller 00:16.2 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB EHCI Controller 00:18.0 Host bridge: Advanced Micro Devices [AMD] Family 12h/14h Processor Function 0 (rev 43) 00:18.1 Host bridge: Advanced Micro Devices [AMD] Family 12h/14h Processor Function 1 00:18.2 Host bridge: Advanced Micro Devices [AMD] Family 12h/14h Processor Function 2 00:18.3 Host bridge: Advanced Micro Devices [AMD] Family 12h/14h Processor Function 3 00:18.4 Host bridge: Advanced Micro Devices [AMD] Family 12h/14h Processor Function 4 00:18.5 Host bridge: Advanced Micro Devices [AMD] Family 12h/14h Processor Function 6 00:18.6 Host bridge: Advanced Micro Devices [AMD] Family 12h/14h Processor Function 5 00:18.7 Host bridge: Advanced Micro Devices [AMD] Family 12h/14h Processor Function 7 04:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller (rev 06) 05:00.0 USB controller: Etron Technology, Inc. EJ168 USB 3.0 Host Controller (rev 01) sudo lspci -tnvv -[0000:00]-+-00.0 1022:1510 +-01.0 1002:9802 +-01.1 1002:1314 +-04.0-[01]-- +-11.0 1002:4391 +-12.0 1002:4397 +-12.2 1002:4396 +-13.0 1002:4397 +-13.2 1002:4396 +-14.0 1002:4385 +-14.2 1002:4383 +-14.3 1002:439d +-14.4-[02]-- +-14.5 1002:4399 +-15.0-[03]-- +-15.1-[04]----00.0 10ec:8168 +-15.2-[05]----00.0 1b6f:7023 +-16.0 1002:4397 +-16.2 1002:4396 +-18.0 1022:1700 +-18.1 1022:1701 +-18.2 1022:1702 +-18.3 1022:1703 +-18.4 1022:1704 +-18.5 1022:1718 +-18.6 1022:1716 \-18.7 1022:1719 Have a nice day!

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New patch to review for coreboot: b1e52e2 Drop prototypes that aren't used anymore
by Patrick Georgi 09 Mar '13

09 Mar '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2625 -gerrit commit b1e52e21a3e836d893db2a1919bfd132b89201d9 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Mar 9 13:24:43 2013 +0100 Drop prototypes that aren't used anymore We used to allow mainboards to override setting subsystems using mainboard_pci_subsystem_vendor_id and mainboard_pci_subsystem_device_id Mechanisms have changed and the only occurrence of these names is in the header. Change-Id: Ic2ab13201a2740c98868fdf580140b7758b62263 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/include/device/pci.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/include/device/pci.h b/src/include/device/pci.h index a215a2a..132c48c 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -106,8 +106,5 @@ static inline const struct pci_bus_operations *ops_pci_bus(struct bus *bus) return bops; } -unsigned mainboard_pci_subsystem_vendor_id(struct device *dev); -unsigned mainboard_pci_subsystem_device_id(struct device *dev); - #endif #endif /* PCI_H */

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New patch to review for coreboot: f8a02be libpayload: Fix reading x86 CBFS images from RAM
by Patrick Georgi 09 Mar '13

09 Mar '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2624 -gerrit commit f8a02be2efbd93a8b88bd48efdbf46de073dd635 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Mar 9 10:52:50 2013 +0100 libpayload: Fix reading x86 CBFS images from RAM Three issues: 1. the hardcoded dereferenced pointer at 0xfffffffc 2. "RAM media" has no idea about ROM relative addresses 3. off-by-one in RAM media: it's legal to request 4 bytes from 0xfffffffc Change-Id: I671ac12d412c71dc8e8e6114f2ea13f58dd99c1d Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- payloads/libpayload/libcbfs/cbfs.c | 10 ++++++++-- payloads/libpayload/libcbfs/ram_media.c | 6 +++++- 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/payloads/libpayload/libcbfs/cbfs.c b/payloads/libpayload/libcbfs/cbfs.c index 35e48dd..2fb91bf 100644 --- a/payloads/libpayload/libcbfs/cbfs.c +++ b/payloads/libpayload/libcbfs/cbfs.c @@ -65,8 +65,14 @@ #if defined(CONFIG_CBFS_HEADER_ROM_OFFSET) && (CONFIG_CBFS_HEADER_ROM_OFFSET) # define CBFS_HEADER_ROM_ADDRESS (CONFIG_CBFS_HEADER_ROM_OFFSET) #else -// Indirect address: only works on 32bit top-aligned systems. -# define CBFS_HEADER_ROM_ADDRESS (*(uint32_t*)0xfffffffc) +/* ugly hack: this assumes that "media" exists + in the scope where the macro is used. */ +static uint32_t fetch_x86_header(struct cbfs_media *media) +{ + uint32_t *header_ptr = media->map(media, 0xfffffffc, 4); + return *header_ptr; +} +# define CBFS_HEADER_ROM_ADDRESS fetch_x86_header(media) #endif #include "cbfs_core.c" diff --git a/payloads/libpayload/libcbfs/ram_media.c b/payloads/libpayload/libcbfs/ram_media.c index 87b5292..1a0500e 100644 --- a/payloads/libpayload/libcbfs/ram_media.c +++ b/payloads/libpayload/libcbfs/ram_media.c @@ -43,7 +43,11 @@ static int ram_open(struct cbfs_media *media) { static void *ram_map(struct cbfs_media *media, size_t offset, size_t count) { struct ram_media *m = (struct ram_media*)media->context; - if (offset + count >= m->size) { + /* assume addressing from top of image in this case */ + if (offset > 0xf0000000) { + offset = m->size + offset; + } + if (offset + count > m->size) { printf("ERROR: ram_map: request out of range (0x%x+0x%x)\n", offset, count); return NULL;

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New patch to review for coreboot: 61f3782 libpayload: initial test case + tiny "framework"
by Patrick Georgi 09 Mar '13

09 Mar '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2623 -gerrit commit 61f3782d76feb2ffba79066cd8eec38ff1c2ca69 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Mar 9 10:36:10 2013 +0100 libpayload: initial test case + tiny "framework" This adds a test case for using CBFS images that reside in RAM and a Makefile to run it (and maybe other tests in the future). The test concerns an issue in libcbfs when using x86 style CBFS images in non-canonical locations (eg. when loading CBFS images for processing). Use with "make run" inside the tests directory. Change-Id: I1af3792a1451728ff9594ba7f0410027cdecb59d Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- payloads/libpayload/tests/Makefile | 13 ++++++++++ payloads/libpayload/tests/cbfs-x86-test.c | 34 ++++++++++++++++++++++++++ payloads/libpayload/tests/data/cbfs-x86.bin | Bin 0 -> 200 bytes payloads/libpayload/tests/libpayload-config.h | 30 +++++++++++++++++++++++ 4 files changed, 77 insertions(+) diff --git a/payloads/libpayload/tests/Makefile b/payloads/libpayload/tests/Makefile new file mode 100644 index 0000000..9728722 --- /dev/null +++ b/payloads/libpayload/tests/Makefile @@ -0,0 +1,13 @@ +CC=gcc -g -m32 +INCLUDES=-I. -I../include -I../include/x86 +TARGETS=cbfs-x86-test + +cbfs-x86-test: cbfs-x86-test.c ../arch/x86/rom_media.c ../libcbfs/ram_media.c ../libcbfs/cbfs.c + $(CC) -o $@ $^ $(INCLUDES) + + +all: $(TARGETS) + +run: all + for i in $(TARGETS); do ./$$i; done + diff --git a/payloads/libpayload/tests/cbfs-x86-test.c b/payloads/libpayload/tests/cbfs-x86-test.c new file mode 100644 index 0000000..8102965 --- /dev/null +++ b/payloads/libpayload/tests/cbfs-x86-test.c @@ -0,0 +1,34 @@ +/* system headers */ +#include <stdlib.h> +#include <stdio.h> + +/* libpayload headers */ +#include "cbfs.h" + +int fail(const char* str) +{ + fprintf(stderr, "%s", str); + exit(1); +} + +int main(int argc, char** argv) +{ + FILE *cbfs = fopen("data/cbfs-x86.bin", "rb"); + if (!cbfs) fail("could not open test file\n"); + if (fseek(cbfs, 0, SEEK_END) != 0) fail("seek to end failed\n"); + + long size = ftell(cbfs); + if (size == -1) fail("could not determine file size\n"); + if (fseek(cbfs, 0, SEEK_SET) != 0) fail("seek to start failed\n"); + + void *data = malloc(size); + if (!data) fail("could not allocate buffer\n"); + + if (fread(data, size, 1, cbfs) != 1) fail("could not read data\n"); + if (fclose(cbfs)) fail("could not close file\n"); + + if (setup_cbfs_from_ram(data, size) != 0) fail("could not setup CBFS in RAM\n"); + struct cbfs_file *file = cbfs_find("foo"); + if (file == NULL) fail("could not find file in CBFS\n"); + exit(0); +} diff --git a/payloads/libpayload/tests/data/cbfs-x86.bin b/payloads/libpayload/tests/data/cbfs-x86.bin new file mode 100644 index 0000000..b217b50 Binary files /dev/null and b/payloads/libpayload/tests/data/cbfs-x86.bin differ diff --git a/payloads/libpayload/tests/libpayload-config.h b/payloads/libpayload/tests/libpayload-config.h new file mode 100644 index 0000000..6fe99a9 --- /dev/null +++ b/payloads/libpayload/tests/libpayload-config.h @@ -0,0 +1,30 @@ +/* + * Automatically generated C config: don't edit + * libpayload version: 0.2.0 + * Sat Mar 9 10:22:45 2013 + */ +#define AUTOCONF_INCLUDED +#define CONFIG_SPEAKER 1 +#define CONFIG_STORAGE 1 +#define CONFIG_LIBC 1 +#define CONFIG_CBFS 1 +#define CONFIG_VGA_VIDEO_CONSOLE 1 +#define CONFIG_SERIAL_CONSOLE 1 +#define CONFIG_PC_KEYBOARD 1 +#define CONFIG_ARCH_X86 1 +#define CONFIG_STORAGE_ATA 1 +#define CONFIG_ARCH_SPECIFIC_OPTIONS 1 +#define CONFIG_STORAGE_AHCI_ONLY_TESTED 1 +#define CONFIG_X86_SERIAL_CONSOLE 1 +#define CONFIG_PDCURSES 1 +#define CONFIG_NVRAM 1 +#define CONFIG_PC_KEYBOARD_LAYOUT_US 1 +#define CONFIG_STORAGE_AHCI 1 +#define CONFIG_MULTIBOOT 1 +#define CONFIG_SERIAL_IOBASE 0x3f8 +#define CONFIG_CURSES 1 +#define CONFIG_CBMEM_CONSOLE 1 +#define CONFIG_LITTLE_ENDIAN 1 +#define CONFIG_PCI 1 +#define CONFIG_STORAGE_ATAPI 1 +#define CONFIG_VIDEO_CONSOLE 1

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New patch to review for coreboot: b396229 graysreef: update platform information
by Stefan Reinauer 09 Mar '13

09 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2622 -gerrit commit b396229423356a84629cffc394c3263032119905 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Nov 2 09:19:43 2012 -0500 graysreef: update platform information Some of the Lynx Point ids were off. Correct those and make the pei data BAR fields consistent with the others. Change-Id: I4102439588362cdb94643bd1ce69c9fa4278329e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/intel/graysreef/romstage.c | 2 +- src/northbridge/intel/haswell/report_platform.c | 9 +++++---- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/mainboard/intel/graysreef/romstage.c b/src/mainboard/intel/graysreef/romstage.c index 6e35d51..25c17fe 100644 --- a/src/mainboard/intel/graysreef/romstage.c +++ b/src/mainboard/intel/graysreef/romstage.c @@ -135,7 +135,7 @@ void main(unsigned long bist) mchbar: DEFAULT_MCHBAR, dmibar: DEFAULT_DMIBAR, epbar: DEFAULT_EPBAR, - pciexbar: CONFIG_MMCONF_BASE_ADDRESS, + pciexbar: DEFAULT_PCIEXBAR, smbusbar: SMBUS_IO_BASE, wdbbar: 0x4000000, wdbsize: 0x1000, diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c index 95133a5..b194027 100644 --- a/src/northbridge/intel/haswell/report_platform.c +++ b/src/northbridge/intel/haswell/report_platform.c @@ -74,10 +74,11 @@ static struct { } pch_table [] = { {0x8c41, "Mobile Engineering Sample"}, {0x8c42, "Desktop Engineering Sample"}, - {0x8c46, "Z87"}, - {0x8c49, "Z85"}, - {0x8c4a, "HM86"}, - {0x8c4b, "H87"}, + {0x8c44, "Z87"}, + {0x8c46, "Z85"}, + {0x8c49, "HM86"}, + {0x8c4a, "H87"}, + {0x8c4b, "HM87"}, {0x8c4c, "Q85"}, {0x8c4e, "Q87"}, {0x8c4f, "QM87"},

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New patch to review for coreboot: eea2ce9 Mainboard: Add support for Grays Reef
by Stefan Reinauer 09 Mar '13

09 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2621 -gerrit commit eea2ce9b48f8c94a358b67421614494db6cb46a9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Oct 30 09:09:39 2012 -0500 Mainboard: Add support for Grays Reef Grays Reef is one of Intel's CRBs for the Haswell processor. The platform is named Shark Bay. GPIOs were the main focus so IRQ routing and ACPI still needs to be further looked at. Change-Id: Ie94b7af66f772714992a92612c76ca93b9b27088 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/intel/Kconfig | 3 + src/mainboard/intel/graysreef/Kconfig | 45 +++ src/mainboard/intel/graysreef/Makefile.inc | 23 ++ src/mainboard/intel/graysreef/acpi/chromeos.asl | 24 ++ src/mainboard/intel/graysreef/acpi/ec.asl | 0 .../intel/graysreef/acpi/haswell_pci_irqs.asl | 69 +++++ src/mainboard/intel/graysreef/acpi/mainboard.asl | 28 ++ src/mainboard/intel/graysreef/acpi/platform.asl | 86 ++++++ src/mainboard/intel/graysreef/acpi/superio.asl | 35 +++ src/mainboard/intel/graysreef/acpi/thermal.asl | 275 ++++++++++++++++++ src/mainboard/intel/graysreef/acpi/video.asl | 43 +++ src/mainboard/intel/graysreef/acpi_tables.c | 284 ++++++++++++++++++ src/mainboard/intel/graysreef/chromeos.c | 122 ++++++++ src/mainboard/intel/graysreef/cmos.layout | 139 +++++++++ src/mainboard/intel/graysreef/devicetree.cb | 84 ++++++ src/mainboard/intel/graysreef/dsdt.asl | 56 ++++ src/mainboard/intel/graysreef/fadt.c | 156 ++++++++++ src/mainboard/intel/graysreef/gpio.h | 246 ++++++++++++++++ src/mainboard/intel/graysreef/hda_verb.h | 99 +++++++ src/mainboard/intel/graysreef/mainboard.c | 249 ++++++++++++++++ src/mainboard/intel/graysreef/mainboard_smi.c | 97 +++++++ src/mainboard/intel/graysreef/onboard.h | 37 +++ src/mainboard/intel/graysreef/romstage.c | 319 +++++++++++++++++++++ src/mainboard/intel/graysreef/thermal.h | 57 ++++ 24 files changed, 2576 insertions(+) diff --git a/src/mainboard/intel/Kconfig b/src/mainboard/intel/Kconfig index 68f178b..9426242 100644 --- a/src/mainboard/intel/Kconfig +++ b/src/mainboard/intel/Kconfig @@ -19,6 +19,8 @@ config BOARD_INTEL_TRUXTON bool "EP80579 devkit (Truxton)" config BOARD_INTEL_XE7501DEVKIT bool "XE7501devkit" +config BOARD_INTEL_GRAYSREEF + bool "Grays Reef CRB" endchoice @@ -26,6 +28,7 @@ source "src/mainboard/intel/d810e2cb/Kconfig" source "src/mainboard/intel/d945gclf/Kconfig" source "src/mainboard/intel/eagleheights/Kconfig" source "src/mainboard/intel/emeraldlake2/Kconfig" +source "src/mainboard/intel/graysreef/Kconfig" source "src/mainboard/intel/jarrell/Kconfig" source "src/mainboard/intel/mtarvon/Kconfig" source "src/mainboard/intel/truxton/Kconfig" diff --git a/src/mainboard/intel/graysreef/Kconfig b/src/mainboard/intel/graysreef/Kconfig new file mode 100644 index 0000000..52f859d --- /dev/null +++ b/src/mainboard/intel/graysreef/Kconfig @@ -0,0 +1,45 @@ +if BOARD_INTEL_GRAYSREEF + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_RPGA989 + select NORTHBRIDGE_INTEL_HASWELL + select SOUTHBRIDGE_INTEL_LYNXPOINT + select BOARD_ROMSIZE_KB_8192 + select BOARD_HAS_FADT + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_ACPI_RESUME + select HAVE_MAINBOARD_RESOURCES + select MMCONF_SUPPORT + select HAVE_SMI_HANDLER + select GFXUMA + select CHROMEOS + select EXTERNAL_MRC_BLOB + +config MAINBOARD_DIR + string + default intel/graysreef + +config MAINBOARD_PART_NUMBER + string + default "GRAYS REEF" + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 16 + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +endif # BOARD_INTEL_GRAYSREEF diff --git a/src/mainboard/intel/graysreef/Makefile.inc b/src/mainboard/intel/graysreef/Makefile.inc new file mode 100644 index 0000000..80385d6 --- /dev/null +++ b/src/mainboard/intel/graysreef/Makefile.inc @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c diff --git a/src/mainboard/intel/graysreef/acpi/chromeos.asl b/src/mainboard/intel/graysreef/acpi/chromeos.asl new file mode 100644 index 0000000..307e2e2 --- /dev/null +++ b/src/mainboard/intel/graysreef/acpi/chromeos.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Name(OIPG, Package() { + Package() { 0x001, 0, 22, "CougarPoint" }, // recovery button + Package() { 0x002, 1, 57, "CougarPoint" }, // developer switch + Package() { 0x003, 0, 48, "CougarPoint" }, // firmware write protect +}) diff --git a/src/mainboard/intel/graysreef/acpi/ec.asl b/src/mainboard/intel/graysreef/acpi/ec.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/intel/graysreef/acpi/haswell_pci_irqs.asl b/src/mainboard/intel/graysreef/acpi/haswell_pci_irqs.asl new file mode 100644 index 0000000..6f2d3e9 --- /dev/null +++ b/src/mainboard/intel/graysreef/acpi/haswell_pci_irqs.asl @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for IvyBridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 22 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 17 }, + Package() { 0x001cffff, 1, 0, 18 }, + Package() { 0x001cffff, 2, 0, 19 }, + Package() { 0x001cffff, 3, 0, 20 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 20 }, + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 21 }, + Package() { 0x001fffff, 1, 0, 22 }, + Package() { 0x001fffff, 2, 0, 23 }, + Package() { 0x001fffff, 3, 0, 16 }, + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + }) + } +} + diff --git a/src/mainboard/intel/graysreef/acpi/mainboard.asl b/src/mainboard/intel/graysreef/acpi/mainboard.asl new file mode 100644 index 0000000..6b15331 --- /dev/null +++ b/src/mainboard/intel/graysreef/acpi/mainboard.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device (PWRB) +{ + Name(_HID, EisaId("PNP0C0C")) + + // Wake + Name(_PRW, Package(){0x1d, 0x05}) +} diff --git a/src/mainboard/intel/graysreef/acpi/platform.asl b/src/mainboard/intel/graysreef/acpi/platform.asl new file mode 100644 index 0000000..fea92d0 --- /dev/null +++ b/src/mainboard/intel/graysreef/acpi/platform.asl @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + // NVS has a flag to determine USB policy in S3 + if (S3U0) { + Store (One, GP47) // Enable USB0 + } Else { + Store (Zero, GP47) // Disable USB0 + } + + // NVS has a flag to determine USB policy in S3 + if (S3U1) { + Store (One, GP56) // Enable USB1 + } Else { + Store (Zero, GP56) // Disable USB1 + } +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + diff --git a/src/mainboard/intel/graysreef/acpi/superio.asl b/src/mainboard/intel/graysreef/acpi/superio.asl new file mode 100644 index 0000000..a50c4b3 --- /dev/null +++ b/src/mainboard/intel/graysreef/acpi/superio.asl @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Values should match those defined in devicetree.cb */ + +#undef SIO_ENABLE_FDC0 // pnp 2e.0: Disable Floppy Controller +#undef SIO_ENABLE_INFR // pnp 2e.a: Disable Consumer IR + +#define SIO_ENABLE_PS2K // pnp 2e.5: Enable PS/2 Keyboard +#define SIO_ENABLE_PS2M // pnp 2e.6: Enable PS/2 Mouse +#define SIO_ENABLE_COM1 // pnp 2e.1: Enable Serial Port 1 +#define SIO_ENABLE_ENVC // pnp 2e.4: Enable Environmental Controller +#define SIO_ENVC_IO0 0x700 // pnp 2e.4: io 0x60 +#define SIO_ENVC_IO1 0x710 // pnp 2e.4: io 0x62 +#define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO +#define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60 +#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60 + +#include "superio/smsc/sio1007/acpi/superio.asl" diff --git a/src/mainboard/intel/graysreef/acpi/thermal.asl b/src/mainboard/intel/graysreef/acpi/thermal.asl new file mode 100644 index 0000000..f8e9d97 --- /dev/null +++ b/src/mainboard/intel/graysreef/acpi/thermal.asl @@ -0,0 +1,275 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Thermal Zone + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + Name (_TC1, 0x02) + Name (_TC2, 0x05) + + // Thermal zone polling frequency: 0 seconds + Name (_TZP, 0) + + // Thermal sampling period for passive cooling: 2 seconds + Name (_TSP, 20) + + // Convert from Degrees C to 1/10 Kelvin for ACPI + Method (CTOK, 1) { + // 10th of Degrees C + Multiply (Arg0, 10, Local0) + + // Convert to Kelvin + Add (Local0, 2732, Local0) + + Return (Local0) + } + + // Threshold for OS to shutdown + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + // Threshold for passive cooling + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + // Processors used for passive cooling + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } + + Method (_TMP, 0, Serialized) + { + // Get CPU Temperature from PECI via SuperIO TMPIN3 + // FIXME: figure out how to read temp on this board. + Store (30, Local0) + + // Check for invalid readings + If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { + Return (CTOK (\F2ON)) + } + + // PECI raw value is an offset from Tj_max + Subtract (255, Local0, Local1) + + // Handle values greater than Tj_max + If (LGreaterEqual (Local1, \TMAX)) { + Return (CTOK (\TMAX)) + } + + // Subtract from Tj_max to get temperature + Subtract (\TMAX, Local1, Local0) + Return (CTOK (Local0)) + } + + Method (_AC0) { + If (LLessEqual (\FLVL, 0)) { + Return (CTOK (\F0OF)) + } Else { + Return (CTOK (\F0ON)) + } + } + + Method (_AC1) { + If (LLessEqual (\FLVL, 1)) { + Return (CTOK (\F1OF)) + } Else { + Return (CTOK (\F1ON)) + } + } + + Method (_AC2) { + If (LLessEqual (\FLVL, 2)) { + Return (CTOK (\F2OF)) + } Else { + Return (CTOK (\F2ON)) + } + } + + Method (_AC3) { + If (LLessEqual (\FLVL, 3)) { + Return (CTOK (\F3OF)) + } Else { + Return (CTOK (\F3ON)) + } + } + + Method (_AC4) { + If (LLessEqual (\FLVL, 4)) { + Return (CTOK (\F4OF)) + } Else { + Return (CTOK (\F4ON)) + } + } + + Name (_AL0, Package () { FAN0 }) + Name (_AL1, Package () { FAN1 }) + Name (_AL2, Package () { FAN2 }) + Name (_AL3, Package () { FAN3 }) + Name (_AL4, Package () { FAN4 }) + + PowerResource (FNP0, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 0)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + Store (0, \FLVL) + Store (\F0PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + Notify (\_TZ.THRM, 0x81) + } + Method (_OFF) { + Store (1, \FLVL) + Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + Notify (\_TZ.THRM, 0x81) + } + } + + PowerResource (FNP1, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 1)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + Store (1, \FLVL) + Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + Notify (\_TZ.THRM, 0x81) + } + Method (_OFF) { + Store (2, \FLVL) + Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + Notify (\_TZ.THRM, 0x81) + } + } + + PowerResource (FNP2, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 2)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + Store (2, \FLVL) + Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + Notify (\_TZ.THRM, 0x81) + } + Method (_OFF) { + Store (3, \FLVL) + Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + Notify (\_TZ.THRM, 0x81) + } + } + + PowerResource (FNP3, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 3)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + Store (3, \FLVL) + Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + Notify (\_TZ.THRM, 0x81) + } + Method (_OFF) { + Store (4, \FLVL) + Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + Notify (\_TZ.THRM, 0x81) + } + } + + PowerResource (FNP4, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 4)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + Store (4, \FLVL) + Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + Notify (\_TZ.THRM, 0x81) + } + Method (_OFF) { + Store (4, \FLVL) + Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + Notify (\_TZ.THRM, 0x81) + } + } + + Device (FAN0) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 0) + Name (_PR0, Package () { FNP0 }) + } + + Device (FAN1) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 1) + Name (_PR0, Package () { FNP1 }) + } + + Device (FAN2) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 2) + Name (_PR0, Package () { FNP2 }) + } + + Device (FAN3) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 3) + Name (_PR0, Package () { FNP3 }) + } + + Device (FAN4) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 4) + Name (_PR0, Package () { FNP4 }) + } + } +} + diff --git a/src/mainboard/intel/graysreef/acpi/video.asl b/src/mainboard/intel/graysreef/acpi/video.asl new file mode 100644 index 0000000..3ececa9 --- /dev/null +++ b/src/mainboard/intel/graysreef/acpi/video.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Brightness write +Method (BRTW, 1, Serialized) +{ + // TODO +} + +// Hot Key Display Switch +Method (HKDS, 1, Serialized) +{ + // TODO +} + +// Lid Switch Display Switch +Method (LSDS, 1, Serialized) +{ + // TODO +} + +// Brightness Notification +Method(BRTN,1,Serialized) +{ + // TODO (no displays defined yet) +} + diff --git a/src/mainboard/intel/graysreef/acpi_tables.c b/src/mainboard/intel/graysreef/acpi_tables.c new file mode 100644 index 0000000..cd0025d --- /dev/null +++ b/src/mainboard/intel/graysreef/acpi_tables.c @@ -0,0 +1,284 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <cbmem.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <vendorcode/google/chromeos/gnvs.h> + +#if CONFIG_HAVE_ACPI_SLIC +unsigned long acpi_create_slic(unsigned long current); +#endif + +#include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/lynxpoint/nvs.h> +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->f4of = FAN4_THRESHOLD_OFF; + gnvs->f4on = FAN4_THRESHOLD_ON; + gnvs->f4pw = FAN4_PWM; + + gnvs->f3of = FAN3_THRESHOLD_OFF; + gnvs->f3on = FAN3_THRESHOLD_ON; + gnvs->f3pw = FAN3_PWM; + + gnvs->f2of = FAN2_THRESHOLD_OFF; + gnvs->f2on = FAN2_THRESHOLD_ON; + gnvs->f2pw = FAN2_PWM; + + gnvs->f1of = FAN1_THRESHOLD_OFF; + gnvs->f1on = FAN1_THRESHOLD_ON; + gnvs->f1pw = FAN1_PWM; + + gnvs->f0of = FAN0_THRESHOLD_OFF; + gnvs->f0on = FAN0_THRESHOLD_ON; + gnvs->f0pw = FAN0_PWM; + + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tmax = MAX_TEMPERATURE; +} + +static void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + gnvs->apic = 1; + gnvs->mpen = 1; /* Enable Multi Processing */ + gnvs->pcnt = dev_count_cpu(); + + /* Enable USB ports in S3 */ + gnvs->s3u0 = 1; + gnvs->s3u1 = 1; + + /* + * Enable Front USB ports in S5 by default + * to be consistent with back port behavior + */ + gnvs->s5u0 = 1; + gnvs->s5u1 = 1; + + /* CBMEM TOC */ + gnvs->cmem = (u32)get_cbmem_toc(); + + /* IGD Displays */ + gnvs->ndid = 3; + gnvs->did[0] = 0x80000100; + gnvs->did[1] = 0x80000240; + gnvs->did[2] = 0x80000410; + gnvs->did[3] = 0x80000410; + gnvs->did[4] = 0x00000005; + +#if CONFIG_CHROMEOS + // TODO(reinauer) this could move elsewhere? + chromeos_init_vboot(&(gnvs->chromeos)); + /* Emerald Lake has no EC (?) */ + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; +#endif + + acpi_update_thermal_table(gnvs); +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, + const char *oem_table_id) +{ + generate_cpu_entries(); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +#define ALIGN_CURRENT current = (ALIGN(current, 16)) +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + int i; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_xsdt_t *xsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; +#if CONFIG_HAVE_ACPI_SLIC + acpi_header_t *slic; +#endif + acpi_header_t *ssdt; + acpi_header_t *dsdt; + + current = start; + + /* Align ACPI tables to 16byte */ + ALIGN_CURRENT; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + ALIGN_CURRENT; + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + ALIGN_CURRENT; + xsdt = (acpi_xsdt_t *) current; + current += sizeof(acpi_xsdt_t); + ALIGN_CURRENT; + + /* clear all table memory */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, xsdt); + acpi_write_rsdt(rsdt); + acpi_write_xsdt(xsdt); + + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + ALIGN_CURRENT; + acpi_create_facs(facs); + + printk(BIOS_DEBUG, "ACPI: * DSDT\n"); + dsdt = (acpi_header_t *) current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + ALIGN_CURRENT; + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* + * We explicitly add these tables later on: + */ + printk(BIOS_DEBUG, "ACPI: * HPET\n"); + + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + ALIGN_CURRENT; + acpi_create_intel_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, madt); + + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, mcfg); + + /* Pack GNVS into the ACPI table area */ + for (i=0; i < dsdt->length; i++) { + if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { + printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " + "DSDT at offset 0x%04x -> 0x%08lx\n", i, current); + *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes + acpi_save_gnvs(current); + break; + } + } + + /* And fill it */ + acpi_create_gnvs((global_nvs_t *)current); + + /* And tell SMI about it */ + smm_setup_structures((void *)current, NULL, NULL); + + current += sizeof(global_nvs_t); + ALIGN_CURRENT; + + /* We patched up the DSDT, so we need to recalculate the checksum */ + dsdt->checksum = 0; + dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); + + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + +#if CONFIG_HAVE_ACPI_SLIC + printk(BIOS_DEBUG, "ACPI: * SLIC\n"); + slic = (acpi_header_t *)current; + current += acpi_create_slic(current); + ALIGN_CURRENT; + acpi_add_table(rsdp, slic); +#endif + + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "current = %lx\n", current); + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/intel/graysreef/chromeos.c b/src/mainboard/intel/graysreef/chromeos.c new file mode 100644 index 0000000..4ee9d62 --- /dev/null +++ b/src/mainboard/intel/graysreef/chromeos.c @@ -0,0 +1,122 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <arch/io.h> +#ifdef __PRE_RAM__ +#include <arch/romcc_io.h> +#else +#include <device/device.h> +#include <device/pci.h> +#endif +#include <southbridge/intel/lynxpoint/pch.h> + +#ifndef __PRE_RAM__ +#include <boot/coreboot_tables.h> +#include <arch/coreboot_tables.h> + +#define GPIO_COUNT 6 +#define ACTIVE_LOW 0 +#define ACTIVE_HIGH 1 + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); + u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe; + + if (!gpio_base) + return; + + u32 gp_lvl = inl(gpio_base + 0x0c); + u32 gp_lvl2 = inl(gpio_base + 0x38); + /* u32 gp_lvl3 = inl(gpio_base + 0x48); */ + + gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); + gpios->count = GPIO_COUNT; + + /* Write Protect: GPIO48 */ + gpios->gpios[0].port = 48; + gpios->gpios[0].polarity = ACTIVE_LOW; + gpios->gpios[0].value = (gp_lvl2 >> (48-32)) & 1; + strncpy((char *)gpios->gpios[0].name,"write protect", + GPIO_MAX_NAME_LENGTH); + + /* Recovery: GPIO22 */ + gpios->gpios[1].port = 22; + gpios->gpios[1].polarity = ACTIVE_LOW; + gpios->gpios[1].value = (gp_lvl >> 22) & 1; + strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); + + /* Developer: GPIO57 */ + gpios->gpios[2].port = 57; + gpios->gpios[2].polarity = ACTIVE_LOW; + gpios->gpios[2].value = (gp_lvl2 >> (57-32)) & 1; + strncpy((char *)gpios->gpios[2].name,"developer", GPIO_MAX_NAME_LENGTH); + + /* Hard code the lid switch GPIO to open. */ + gpios->gpios[3].port = -1; + gpios->gpios[3].polarity = ACTIVE_HIGH; + gpios->gpios[3].value = 1; + strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH); + + /* Power Button */ + gpios->gpios[4].port = -1; + gpios->gpios[4].polarity = ACTIVE_HIGH; + gpios->gpios[4].value = 0; + strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH); + + /* Did we load the VGA option ROM? */ + gpios->gpios[5].port = -1; + gpios->gpios[5].polarity = ACTIVE_HIGH; + gpios->gpios[5].value = oprom_is_loaded; + strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH); +} +#endif + +int get_developer_mode_switch(void) +{ + device_t dev; +#ifdef __PRE_RAM__ + dev = PCI_DEV(0, 0x1f, 0); +#else + dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); +#endif + u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe; + u32 gp_lvl2 = inl(gpio_base + 0x38); + + /* Developer: GPIO17, active high */ + return (gp_lvl2 >> (57-32)) & 1; +} + +int get_recovery_mode_switch(void) +{ + device_t dev; +#ifdef __PRE_RAM__ + dev = PCI_DEV(0, 0x1f, 0); +#else + dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); +#endif + u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe; + u32 gp_lvl = inl(gpio_base + 0x0c); + + /* Recovery: GPIO22, active low */ + return !((gp_lvl >> 22) & 1); +} + diff --git a/src/mainboard/intel/graysreef/cmos.layout b/src/mainboard/intel/graysreef/cmos.layout new file mode 100644 index 0000000..afdd3c6 --- /dev/null +++ b/src/mainboard/intel/graysreef/cmos.layout @@ -0,0 +1,139 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 + + diff --git a/src/mainboard/intel/graysreef/devicetree.cb b/src/mainboard/intel/graysreef/devicetree.cb new file mode 100644 index 0000000..70d1300 --- /dev/null +++ b/src/mainboard/intel/graysreef/devicetree.cb @@ -0,0 +1,84 @@ +chip northbridge/intel/haswell + + # Enable DisplayPort 1 Hotplug with 6ms pulse + register "gpu_dp_d_hotplug" = "0x06" + + # Enable DisplayPort 0 Hotplug with 6ms pulse + register "gpu_dp_c_hotplug" = "0x06" + + # Enable DVI Hotplug with 6ms pulse + register "gpu_dp_b_hotplug" = "0x06" + + device lapic_cluster 0 on + chip cpu/intel/socket_rPGA989 + device lapic 0 on end + end + chip cpu/intel/haswell + # Magic APIC ID to locate this chip + device lapic 0xACAC off end + + register "c1_battery" = "3" # ACPI(C1) = MWAIT(C3) + register "c2_battery" = "4" # ACPI(C2) = MWAIT(C6) + register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + + register "c1_acpower" = "3" # ACPI(C1) = MWAIT(C3) + register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C6) + register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) + end + end + + device pci_domain 0 on + device pci 00.0 on end # host bridge + device pci 02.0 on end # vga controller + + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x8b" + register "pirqd_routing" = "0x8b" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x80" + + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "gpi1_routing" = "1" + register "gpi14_routing" = "2" + register "alt_gp_smi_en" = "0x0002" + register "gpe0_en" = "0x4000" + + register "ide_legacy_combined" = "0x0" + register "sata_ahci" = "0x1" + register "sata_port_map" = "0x3f" + + # SuperIO range is 0x700-0x73f + register "gen2_dec" = "0x003c0701" + + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 (WLAN) + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 (Debug) + device pci 1c.3 on end # PCIe Port #4 (LAN) + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 on end # Thermal + end + end +end diff --git a/src/mainboard/intel/graysreef/dsdt.asl b/src/mainboard/intel/graysreef/dsdt.asl new file mode 100644 index 0000000..79bb8f3 --- /dev/null +++ b/src/mainboard/intel/graysreef/dsdt.asl @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + + // General Purpose Events + //#include "acpi/gpe.asl" + + #include "acpi/thermal.asl" + + #include "../../../cpu/intel/haswell/acpi/cpu.asl" + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/haswell/acpi/haswell.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } + } + + #include "acpi/chromeos.asl" + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + /* Chipset specific sleep states */ + #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl> +} diff --git a/src/mainboard/intel/graysreef/fadt.c b/src/mainboard/intel/graysreef/fadt.c new file mode 100644 index 0000000..315cb58 --- /dev/null +++ b/src/mainboard/intel/graysreef/fadt.c @@ -0,0 +1,156 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <device/pci.h> +#include <arch/acpi.h> +#include <cpu/x86/smm.h> + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), + 0x40) & 0xfffe; + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_DESKTOP; + + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x50; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x20; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 16; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 87; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + fadt->duty_width = 0; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 64; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = pmbase + 0x20; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/intel/graysreef/gpio.h b/src/mainboard/intel/graysreef/gpio.h new file mode 100644 index 0000000..44f1efd --- /dev/null +++ b/src/mainboard/intel/graysreef/gpio.h @@ -0,0 +1,246 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef GRAYSREEF_GPIO_H +#define GRAYSREEF_GPIO_H + +#include "southbridge/intel/lynxpoint/gpio.h" + +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, /* PCH_GPIO0_R -> S_GPIO -> J9F5 */ + .gpio1 = GPIO_MODE_GPIO, /* SMC_EXTSMI_N */ + .gpio2 = GPIO_MODE_GPIO, /* TP_RSVD_TESTMODE - float */ + .gpio3 = GPIO_MODE_NATIVE, /* SATA_ODD_DA_N -> PIRQF# */ + .gpio4 = GPIO_MODE_GPIO, /* EXTTS_SNI_DRV0_PCH - float */ + .gpio5 = GPIO_MODE_GPIO, /* EXTTS_SNI_DRV1_PCH - float */ + .gpio6 = GPIO_MODE_GPIO, /* DGPU_HPD_INTR_N */ + .gpio7 = GPIO_MODE_GPIO, /* SMC_RUNTIME_SCI_N */ + .gpio8 = GPIO_MODE_GPIO, /* PCH_GPIO8 -> DDR Voltage Select Bit 0 */ + .gpio9 = GPIO_MODE_NATIVE, /* USB_OC_10_11_R_N */ + .gpio10 = GPIO_MODE_NATIVE, /* USB_OC_12_13_R_N */ + .gpio11 = GPIO_MODE_GPIO, /* PCH_GPIO11 -> HOST_ALERT2_N -> PCIE_RSVD_2_N (3GIO_X1) slot 4 */ + .gpio12 = GPIO_MODE_GPIO, /* PM_LANPHY_ENABLE */ + .gpio13 = GPIO_MODE_NATIVE, /* HDA_DOCK_RST_N */ + .gpio14 = GPIO_MODE_GPIO, /* SMC_WAKE_SCI_R_N */ + .gpio15 = GPIO_MODE_GPIO, /* Always GPIO: HOST_ALERT1_R_N -> PCIE_RSV_1_N */ + .gpio16 = GPIO_MODE_NATIVE, /* SATA_DET4_R_N */ + .gpio17 = GPIO_MODE_GPIO, /* DGPU_PWROK */ + .gpio18 = GPIO_MODE_NATIVE, /* CK_SLOT1_OE_N_R */ + .gpio19 = GPIO_MODE_GPIO, /* BBS_BIT0_R - STRAP */ + .gpio20 = GPIO_MODE_GPIO, /* CK_SLOT2_OE_N_R */ + .gpio21 = GPIO_MODE_GPIO, /* SATA_DET0_R_N -> J9H4 */ + .gpio22 = GPIO_MODE_GPIO, /* BIOS_REC -> J8G1 */ + .gpio23 = GPIO_MODE_NATIVE, /* PCH_DRQ1_N */ + .gpio24 = GPIO_MODE_GPIO, /* Always GPIO: PCH_GPIO24_R1 -> DDR Voltage Select Bit 2 */ + .gpio25 = GPIO_MODE_NATIVE, /* CK_SLOT3_OE_N */ + .gpio26 = GPIO_MODE_NATIVE, /* CK_SLOT4_OE_N */ + .gpio27 = GPIO_MODE_GPIO, /* Always GPIO: PCH_GPIO_27 -> SMC_WAKE_SCI_N & LANWAKE_N */ + .gpio28 = GPIO_MODE_GPIO, /* Always GPIO: PLL_ODVR_EN */ + .gpio29 = GPIO_MODE_NATIVE, /* PCH_SLP_WLAN_N */ + .gpio30 = GPIO_MODE_NATIVE, /* SUS_PWR_ACK_R */ + .gpio31 = GPIO_MODE_NATIVE, /* AC_PRESENT_R */ +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_OUTPUT, + /* .gpio3 NATIVE */ + .gpio4 = GPIO_DIR_OUTPUT, + .gpio5 = GPIO_DIR_OUTPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio9 = GPIO_DIR_INPUT, + /* .gpio10 NATIVE */ + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + /* .gpio13 NATIVE */ + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + /* .gpio16 NATIVE */ + .gpio17 = GPIO_DIR_INPUT, + /* .gpio18 NATIVE */ + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + /* .gpio23 NATIVE */ + .gpio24 = GPIO_DIR_OUTPUT, + /* .gpio25 NATIVE */ + /* .gpio26 NATIVE */ + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + /* .gpio29 NATIVE */ + /* .gpio30 NATIVE */ + /* .gpio31 NATIVE */ +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio2 = GPIO_LEVEL_HIGH, + .gpio4 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_HIGH, + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, /* Always GPIO on desktop. Mobile Native. PM_CLKRUN_N */ + .gpio33 = GPIO_MODE_NATIVE, /* HDADOCKEN_R_N */ + .gpio34 = GPIO_MODE_GPIO, /* PCH_GPIO34 -> SATA_PWR_EN0_N */ + .gpio35 = GPIO_MODE_GPIO, /* Always GPIO. SATA_PWR_EN1_R_N */ + .gpio36 = GPIO_MODE_NATIVE, /* SATA_ODD_PRSNT_R_N */ + .gpio37 = GPIO_MODE_GPIO, /* FDI_OVRVLTG */ + .gpio38 = GPIO_MODE_GPIO, /* MFG_MODE */ + .gpio39 = GPIO_MODE_GPIO, /* GFX_CRB_DET */ + .gpio40 = GPIO_MODE_NATIVE, /* USB_OC_2_R_N */ + .gpio41 = GPIO_MODE_NATIVE, /* USB_OC_5_R_N */ + .gpio42 = GPIO_MODE_NATIVE, /* USB_OC_6_7_R_N */ + .gpio43 = GPIO_MODE_NATIVE, /* USB_OSC_8_9_R_N */ + .gpio44 = GPIO_MODE_NATIVE, /* CK_SLOT5_OE_N */ + .gpio45 = GPIO_MODE_NATIVE, /* CK_PCIE_LAN_REQ_N */ + .gpio46 = GPIO_MODE_GPIO, /* PCH_GPIO46_R -> DDR Voltage Select Bit 1 */ + .gpio47 = GPIO_MODE_NATIVE, /* PEGA_CKREQ_N */ + .gpio48 = GPIO_MODE_GPIO, /* BIOS_RESP -> J8E6 */ + .gpio49 = GPIO_MODE_GPIO, /* PCH_GP_49 -> CRIT_TEMP_REP_N */ + .gpio50 = GPIO_MODE_GPIO, /* DGPU_HOLD_RST_N */ + .gpio51 = GPIO_MODE_GPIO, /* BBS_BIT1 Strap */ + .gpio52 = GPIO_MODE_GPIO, /* DGPU_SELECT_N */ + .gpio53 = GPIO_MODE_GPIO, /* DGPU_PWM_SELECT_N -> PEG_JTAG5 */ + .gpio54 = GPIO_MODE_GPIO, /* DGPU_PWR_EN_N -> PEG_RSVD5 */ + .gpio55 = GPIO_MODE_GPIO, /* STP_A16OVR Strap */ + .gpio56 = GPIO_MODE_NATIVE, /* MC_CKREQ_N */ + .gpio57 = GPIO_MODE_GPIO, /* Always GPIO. NFC_IRQ_R */ + .gpio58 = GPIO_MODE_NATIVE, /* SML1_CK */ + .gpio59 = GPIO_MODE_NATIVE, /* USB_OC_0_1_R_N */ + .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */ + .gpio61 = GPIO_MODE_NATIVE, /* PM_SUS_STAT_N */ + .gpio62 = GPIO_MODE_NATIVE, /* SUS_CK */ + .gpio63 = GPIO_MODE_NATIVE, /* SLP_S5_R_N */ +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + /* .gpio32 NATIVE */ + /* .gpio33 NATIVE */ + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + /* .gpio36 NATIVE */ + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + /* .gpio40 NATIVE */ + /* .gpio41 NATIVE */ + /* .gpio42 NATIVE */ + /* .gpio43 NATIVE */ + /* .gpio44 NATIVE */ + /* .gpio45 NATIVE */ + .gpio46 = GPIO_DIR_OUTPUT, + /* .gpio47 NATIVE */ + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_OUTPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + /* .gpio56 NATIVE */ + .gpio57 = GPIO_DIR_INPUT, + /* .gpio58 NATIVE */ + /* .gpio59 NATIVE */ + .gpio60 = GPIO_DIR_OUTPUT, + /* .gpio61 NATIVE */ + /* .gpio62 NATIVE */ + /* .gpio63 NATIVE */ +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_LOW, + .gpio52 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_LOW, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, /* CK_PCH_SIO_DOCK_R -> TP_CK_PCI_SIO_DOCK */ + .gpio65 = GPIO_MODE_NATIVE, /* CK_FLEX1 */ + .gpio66 = GPIO_MODE_GPIO, /* TP_CK_FLEX2 */ + .gpio67 = GPIO_MODE_GPIO, /* DGPU_PRSNT_N -> PEG_RSVD3 */ + .gpio68 = GPIO_MODE_GPIO, /* SATA_ODD_PWRGT */ + .gpio69 = GPIO_MODE_GPIO, /* SV_DET -> J8E5 */ + .gpio70 = GPIO_MODE_GPIO, /* USB3_DET_P2_N */ + .gpio71 = GPIO_MODE_GPIO, /* USB3_DET_P3_N */ + .gpio72 = GPIO_MODE_NATIVE, /* PM_BATLOW_R_N */ + .gpio73 = GPIO_MODE_NATIVE, /* CK_REQ_DOCK_N */ + .gpio74 = GPIO_MODE_NATIVE, /* PCH_GPIO74_R -> AMB_THM2_R_N */ + .gpio75 = GPIO_MODE_NATIVE, /* SM1_DATA */ +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + /* .gpio65 NATIVE */ + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + /* .gpio72 NATIVE */ + /* .gpio73 NATIVE */ + /* .gpio74 NATIVE */ + /* .gpio75 NATIVE */ +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_LOW, + .gpio66 = GPIO_LEVEL_LOW, + .gpio68 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map graysreef_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; + +#endif diff --git a/src/mainboard/intel/graysreef/hda_verb.h b/src/mainboard/intel/graysreef/hda_verb.h new file mode 100644 index 0000000..9a4a740 --- /dev/null +++ b/src/mainboard/intel/graysreef/hda_verb.h @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +static const u32 mainboard_cim_verb_data[] = { + /* coreboot specific header */ + 0x10134210, // Codec Vendor / Device ID: Cirrus Logic CS4210 + 0x10134210, // Subsystem ID + 0x00000007, // Number of jacks + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10134210 */ + 0x00172010, + 0x00172142, + 0x00172213, + 0x00172310, + + /* Pin Widget Verb Table */ + + /* Pin Complex (NID 0x05) 1/8 Gray HP Out at Ext Front */ + 0x00571cf0, + 0x00571d20, + 0x00571e21, + 0x00571f02, + + /* Pin Complex (NID 0x06) Analog Unknown Speaker at Int N/A */ + 0x00671c10, + 0x00671d00, + 0x00671e17, + 0x00671f90, + + /* Pin Complex (NID 0x07) 1/8 Grey Line In at Ext Front */ + 0x00771cf0, + 0x00771d20, + 0x00771ea1, + 0x00771f02, + + /* Pin Complex (NID 0x08) Analog Unknown Mic at Oth Mobile-In */ + 0x00871c37, + 0x00871d00, + 0x00871ea7, + 0x00871f77, + + /* Pin Complex (NID 0x09) Digital Unknown Mic at Oth Mobile-In */ + 0x00971c3e, + 0x00971d00, + 0x00971ea6, + 0x00971f77, + + /* Pin Complex (NID 0x0a) Optical Black SPDIF Out at Ext N/A */ + 0x00a71cf0, + 0x00a71d10, + 0x00a71e45, + 0x00a71f43, + + /* coreboot specific header */ + 0x80862805, // Codec Vendor / Device ID: Intel CougarPoint HDMI + 0x80860101, // Subsystem ID + 0x00000004, // Number of jacks + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ + 0x00172001, + 0x00172101, + 0x00172286, + 0x00172380, + + /* Pin Complex (NID 0x05) Digital Out at Int HDMI */ + 0x30571c10, + 0x30571d00, + 0x30571e56, + 0x30571f18, + + /* Pin Complex (NID 0x06) Digital Out at Int HDMI */ + 0x30671c20, + 0x30671d00, + 0x30671e56, + 0x30671f18, + + /* Pin Complex (NID 0x07) Digital Out at Int HDMI */ + 0x30771c30, + 0x30771d00, + 0x30771e56, + 0x30771f18 +}; + diff --git a/src/mainboard/intel/graysreef/mainboard.c b/src/mainboard/intel/graysreef/mainboard.c new file mode 100644 index 0000000..ff8828e --- /dev/null +++ b/src/mainboard/intel/graysreef/mainboard.c @@ -0,0 +1,249 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <console/console.h> +#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL +#include <x86emu/x86emu.h> +#endif +#include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <arch/coreboot_tables.h> +#include "hda_verb.h" +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_suspend_resume(void) +{ + /* Call SMM finalize() handlers before resume */ + outb(0xcb, 0xb2); +} + +int add_mainboard_resources(struct lb_memory *mem) +{ + return add_northbridge_resources(mem); +} + +#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE +static int int15_handler(struct eregs *regs) +{ + int res=-1; + + printk(BIOS_DEBUG, "%s: INT15 function %04x!\n", + __func__, regs->eax & 0xffff); + + switch(regs->eax & 0xffff) { + case 0x5f34: + /* + * Set Panel Fitting Hook: + * bit 2 = Graphics Stretching + * bit 1 = Text Stretching + * bit 0 = Centering (do not set with bit1 or bit2) + * 0 = video bios default + */ + regs->eax &= 0xffff0000; + regs->eax |= 0x005f; + regs->ecx &= 0xffffff00; + regs->ecx |= 0x01; + res = 0; + break; + case 0x5f35: + /* + * Boot Display Device Hook: + * bit 0 = CRT + * bit 1 = TV (eDP) * + * bit 2 = EFP * + * bit 3 = LFP + * bit 4 = CRT2 + * bit 5 = TV2 (eDP) * + * bit 6 = EFP2 * + * bit 7 = LFP2 + */ + regs->eax &= 0xffff0000; + regs->eax |= 0x005f; + regs->ecx &= 0xffff0000; + regs->ecx |= 0x0000; + res = 0; + break; + case 0x5f51: + /* + * Hook to select active LFP configuration: + * 00h = No LVDS, VBIOS does not enable LVDS + * 01h = Int-LVDS, LFP driven by integrated LVDS decoder + * 02h = SVDO-LVDS, LFP driven by SVDO decoder + * 03h = eDP, LFP Driven by Int-DisplayPort encoder + */ + regs->eax &= 0xffff0000; + regs->eax |= 0x005f; + regs->ecx &= 0xffff0000; + regs->ecx |= 0x0003; + res = 0; + break; + case 0x5f70: + switch ((regs->ecx >> 8) & 0xff) { + case 0: + /* Get Mux */ + regs->eax &= 0xffff0000; + regs->eax |= 0x005f; + regs->ecx &= 0xffff0000; + regs->ecx |= 0x0000; + res = 0; + break; + case 1: + /* Set Mux */ + regs->eax &= 0xffff0000; + regs->eax |= 0x005f; + regs->ecx &= 0xffff0000; + regs->ecx |= 0x0000; + res = 0; + break; + case 2: + /* Get SG/Non-SG mode */ + regs->eax &= 0xffff0000; + regs->eax |= 0x005f; + regs->ecx &= 0xffff0000; + regs->ecx |= 0x0000; + res = 0; + break; + default: + /* Interrupt was not handled */ + printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n", + ((regs->ecx >> 8) & 0xff)); + return 0; + } + break; + + default: + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", + regs->eax & 0xffff); + break; + } + return res; +} +#endif + +#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL +static int int15_handler(void) +{ + printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", + __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX); + + switch (M.x86.R_AX) { + case 0x5f34: + /* + * Set Panel Fitting Hook: + * bit 2 = Graphics Stretching + * bit 1 = Text Stretching + * bit 0 = Centering (do not set with bit1 or bit2) + */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = 0x0001; + break; + case 0x5f35: + /* + * Boot Display Device Hook: + * bit 0 = CRT + * bit 1 = TV (eDP) * + * bit 2 = EFP * + * bit 3 = LFP + * bit 4 = CRT2 + * bit 5 = TV2 (eDP) * + * bit 6 = EFP2 * + * bit 7 = LFP2 + */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = 0x0000; + break; + case 0x5f51: + /* + * Hook to select active LFP configuration: + * 00h = No LVDS, VBIOS does not enable LVDS + * 01h = Int-LVDS, LFP driven by integrated LVDS decoder + * 02h = SVDO-LVDS, LFP driven by SVDO decoder + * 03h = eDP, LFP Driven by Int-DisplayPort encoder + */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = 3; + break; + case 0x5f70: + /* Unknown */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = 0; + break; + default: + /* Interrupt was not handled */ + printk(BIOS_DEBUG, "Unknown INT15 function: 0x%04x\n", + M.x86.R_AX); + return 0; + } + + /* Interrupt handled */ + return 1; +} +#endif + +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE +static void int15_install(void) +{ +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL + typedef int (* yabel_handleIntFunc)(void); + extern yabel_handleIntFunc yabel_intFuncArray[256]; + yabel_intFuncArray[0x15] = int15_handler; +#endif +#ifdef CONFIG_PCI_OPTION_ROM_RUN_REALMODE + mainboard_interrupt_handlers(0x15, &int15_handler); +#endif +} +#endif + +/* Audio Setup */ + +extern const u32 * cim_verb_data; +extern u32 cim_verb_data_size; + +static void verb_setup(void) +{ + cim_verb_data = mainboard_cim_verb_data; + cim_verb_data_size = sizeof(mainboard_cim_verb_data); +} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(device_t dev) +{ +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE + /* Install custom int15 handler for VGA OPROM */ + int15_install(); +#endif + verb_setup(); +} + +struct chip_operations mainboard_ops = { + CHIP_NAME("Compal Link ChromeBox") + .enable_dev = mainboard_enable, +}; + diff --git a/src/mainboard/intel/graysreef/mainboard_smi.c b/src/mainboard/intel/graysreef/mainboard_smi.c new file mode 100644 index 0000000..ecfc385 --- /dev/null +++ b/src/mainboard/intel/graysreef/mainboard_smi.c @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <southbridge/intel/lynxpoint/nvs.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/lynxpoint/me.h> +#include <northbridge/intel/haswell/haswell.h> +#include <cpu/intel/haswell/haswell.h> + +int mainboard_io_trap_handler(int smif) +{ + switch (smif) { + case 0x99: + printk(BIOS_DEBUG, "Sample\n"); + smm_get_gnvs()->smif = 0; + break; + default: + return 0; + } + + /* On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + * + * For now, we force the return value to 0 and log all traps to + * see what's going on. + */ + //gnvs->smif = 0; + return 1; +} + +/* + * Change LED_POWER# (SIO GPIO 45) state based on sleep type. + * The IO address is hardcoded as we don't have device path in SMM. + */ +#define SIO_GPIO_BASE_SET4 (0x730 + 3) +#define SIO_GPIO_BLINK_GPIO45 0x25 +void mainboard_smi_sleep(u8 slp_typ) +{ + u8 reg8; + + switch (slp_typ) { + case SLP_TYP_S3: + case SLP_TYP_S4: + break; + + case SLP_TYP_S5: + /* Turn off LED */ + reg8 = inb(SIO_GPIO_BASE_SET4); + reg8 |= (1 << 5); + outb(reg8, SIO_GPIO_BASE_SET4); + break; + } +} + +#define APMC_FINALIZE 0xcb + +static int mainboard_finalized = 0; + +int mainboard_smi_apmc(u8 apmc) +{ + switch (apmc) { + case APMC_FINALIZE: + if (mainboard_finalized) { + printk(BIOS_DEBUG, "SMI#: Already finalized\n"); + return 0; + } + + intel_me_finalize_smm(); + intel_pch_finalize_smm(); + intel_northbridge_haswell_finalize_smm(); + intel_cpu_haswell_finalize_smm(); + + mainboard_finalized = 1; + break; + } + return 0; +} diff --git a/src/mainboard/intel/graysreef/onboard.h b/src/mainboard/intel/graysreef/onboard.h new file mode 100644 index 0000000..52f53e0 --- /dev/null +++ b/src/mainboard/intel/graysreef/onboard.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef LUMPY_ONBOARD_H +#define LUMPY_ONBOARD_H + +#include <arch/smp/mpspec.h> + +#define LUMPY_LIGHTSENSOR_NAME "lightsensor" +#define LUMPY_LIGHTSENSOR_I2C_ADDR 0x44 +#define LUMPY_LIGHTSENSOR_GSI 20 +#define LUMPY_LIGHTSENSOR_IRQ 14 +#define LUMPY_LIGHTSENSOR_IRQ_MODE (MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_LOW) + +#define LUMPY_TRACKPAD_NAME "trackpad" +#define LUMPY_TRACKPAD_I2C_ADDR 0x67 +#define LUMPY_TRACKPAD_GSI 21 +#define LUMPY_TRACKPAD_IRQ 15 +#define LUMPY_TRACKPAD_IRQ_MODE (MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_LOW) + +#endif diff --git a/src/mainboard/intel/graysreef/romstage.c b/src/mainboard/intel/graysreef/romstage.c new file mode 100644 index 0000000..6e35d51 --- /dev/null +++ b/src/mainboard/intel/graysreef/romstage.c @@ -0,0 +1,319 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <lib.h> +#include <timestamp.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <pc80/mc146818rtc.h> +#include <cbmem.h> +#include <console/console.h> +#include "northbridge/intel/haswell/haswell.h" +#include "northbridge/intel/haswell/raminit.h" +#include "southbridge/intel/lynxpoint/pch.h" +#include "southbridge/intel/lynxpoint/gpio.h" +#include <arch/cpu.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> +#include "gpio.h" +#if CONFIG_CHROMEOS +#include <vendorcode/google/chromeos/chromeos.h> +#endif + +static void pch_enable_lpc(void) +{ + device_t dev = PCH_LPC_DEV; + + /* Set COM1/COM2 decode range */ + pci_write_config16(dev, LPC_IO_DEC, 0x0010); + + /* Enable SuperIO + COM1 + PS/2 Keyboard/Mouse */ + u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN | KBC_LPC_EN; + pci_write_config16(dev, LPC_EN, lpc_config); +} + +static void rcba_config(void) +{ + u32 reg32; + + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P1IP WLAN INTA -> PIRQB + * D28IP_P4IP ETH0 INTB -> PIRQC + * D29IP_E1P EHCI1 INTA -> PIRQD + * D26IP_E2P EHCI2 INTA -> PIRQE + * D31IP_SIP SATA INTA -> PIRQF (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQG + * D31IP_TTIP THRT INTC -> PIRQH + * D27IP_ZIP HDA INTA -> PIRQG (MSI) + */ + + /* Device interrupt pin register (board specific) */ + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D30IP) = (NOINT << D30IP_PIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | + (INTB << D28IP_P4IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (NOINT << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + + /* Device interrupt route registers */ + DIR_ROUTE(D31IR, PIRQF, PIRQG, PIRQH, PIRQA); + DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); + DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); + DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB); + DIR_ROUTE(D26IR, PIRQE, PIRQF, PIRQG, PIRQH); + DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + + /* Enable IOAPIC (generic) */ + RCBA16(OIC) = 0x0100; + /* PCH BWG says to read back the IOAPIC enable register */ + (void) RCBA16(OIC); + + /* Disable unused devices (board specific) */ + reg32 = RCBA32(FD); + reg32 |= PCH_DISABLE_ALWAYS; + RCBA32(FD) = reg32; +} + +// FIXME, this function is generic code that should go to sb/... or +// nb/../early_init.c +static void early_pch_init(void) +{ + u8 reg8; + + // reset rtc power status + reg8 = pci_read_config8(PCH_LPC_DEV, 0xa4); + reg8 &= ~(1 << 2); + pci_write_config8(PCH_LPC_DEV, 0xa4, reg8); +} + +void main(unsigned long bist) +{ + int boot_mode = 0; + int cbmem_was_initted; + u32 pm1_cnt; + u16 pm1_sts; + +#if CONFIG_COLLECT_TIMESTAMPS + tsc_t start_romstage_time; + tsc_t before_dram_time; + tsc_t after_dram_time; + tsc_t base_time = { + .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), + .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) + }; +#endif + struct pei_data pei_data = { + pei_version: PEI_VERSION, + mchbar: DEFAULT_MCHBAR, + dmibar: DEFAULT_DMIBAR, + epbar: DEFAULT_EPBAR, + pciexbar: CONFIG_MMCONF_BASE_ADDRESS, + smbusbar: SMBUS_IO_BASE, + wdbbar: 0x4000000, + wdbsize: 0x1000, + hpet_address: HPET_ADDR, + rcba: DEFAULT_RCBA, + pmbase: DEFAULT_PMBASE, + gpiobase: DEFAULT_GPIOBASE, + thermalbase: 0xfed08000, + system_type: 0, // 0 Mobile, 1 Desktop/Server + tseg_size: CONFIG_SMM_TSEG_SIZE, + spd_addresses: { 0xa0, 0x00, 0xa4, 0x00 }, + ts_addresses: { 0x00, 0x00, 0x00, 0x00 }, + ec_present: 0, + // 0 = leave channel enabled + // 1 = disable dimm 0 on channel + // 2 = disable dimm 1 on channel + // 3 = disable dimm 0+1 on channel + dimm_channel0_disabled: 2, + dimm_channel1_disabled: 2, + max_ddr3_freq: 1600, + usb_port_config: { + { 1, 0, 0x0040 }, /* P0: Front port (OC0) */ + { 1, 1, 0x0040 }, /* P1: Back port (OC1) */ + { 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */ + { 1, 0, 0x0040 }, /* P3: MMC (no OC) */ + { 1, 2, 0x0040 }, /* P4: Front port (OC2) */ + { 0, 0, 0x0000 }, /* P5: Empty */ + { 0, 0, 0x0000 }, /* P6: Empty */ + { 0, 0, 0x0000 }, /* P7: Empty */ + { 1, 4, 0x0040 }, /* P8: Back port (OC4) */ + { 1, 4, 0x0040 }, /* P9: MINIPCIE3 (no OC) */ + { 1, 4, 0x0040 }, /* P10: BLUETOOTH (no OC) */ + { 0, 4, 0x0000 }, /* P11: Empty */ + { 1, 6, 0x0040 }, /* P12: Back port (OC6) */ + { 1, 5, 0x0040 }, /* P13: Back port (OC5) */ + }, + }; + +#if CONFIG_COLLECT_TIMESTAMPS + start_romstage_time = rdtsc(); +#endif + + if (bist == 0) + enable_lapic(); + + pch_enable_lpc(); + + /* Enable GPIOs */ + pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); + pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); + setup_pch_gpios(&graysreef_gpio_map); + + /* Early Console setup */ + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + if (MCHBAR16(SSKPD) == 0xCAFE) { + printk(BIOS_DEBUG, "soft reset detected\n"); + boot_mode = 1; + + /* System is not happy after keyboard reset... */ + printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); + outb(0x6, 0xcf9); + while (1) { + hlt(); + } + } + + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + haswell_early_initialization(HASWELL_MOBILE); + printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n"); + + /* Check PM1_STS[15] to see if we are waking from Sx */ + pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); + + /* Read PM1_CNT[12:10] to determine which Sx state */ + pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); + + if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { +#if CONFIG_HAVE_ACPI_RESUME + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + boot_mode = 2; + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); +#else + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); +#endif + } + + post_code(0x38); + /* Enable SPD ROMs and DDR-III DRAM */ + enable_smbus(); + + /* Prepare USB controller early in S3 resume */ + if (boot_mode == 2) + enable_usb_bar(); + + post_code(0x3a); + pei_data.boot_mode = boot_mode; +#if CONFIG_COLLECT_TIMESTAMPS + before_dram_time = rdtsc(); +#endif + sdram_initialize(&pei_data); + + while (1) { + asm("hlt\n"); + } + +#if CONFIG_COLLECT_TIMESTAMPS + after_dram_time = rdtsc(); +#endif + post_code(0x3b); + /* Perform some initialization that must run before stage2 */ + early_pch_init(); + post_code(0x3c); + + /* This should probably go away. Until now it is required + * and mainboard specific + */ + rcba_config(); + post_code(0x3d); + + quick_ram_check(); + post_code(0x3e); + + MCHBAR16(SSKPD) = 0xCAFE; +#if CONFIG_EARLY_CBMEM_INIT + cbmem_was_initted = !cbmem_initialize(); +#else + cbmem_was_initted = cbmem_reinit((uint64_t) (get_top_of_ram() + - HIGH_MEMORY_SIZE)); +#endif + +#if CONFIG_HAVE_ACPI_RESUME + /* If there is no high memory area, we didn't boot before, so + * this is not a resume. In that case we just create the cbmem toc. + */ + + *(u32 *)CBMEM_BOOT_MODE = 0; + *(u32 *)CBMEM_RESUME_BACKUP = 0; + + if ((boot_mode == 2) && cbmem_was_initted) { + void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + if (resume_backup_memory) { + *(u32 *)CBMEM_BOOT_MODE = boot_mode; + *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; + } + /* Magic for S3 resume */ + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); + } else if (boot_mode == 2) { + /* Failed S3 resume, reset to come up cleanly */ + outb(0x6, 0xcf9); + while (1) { + hlt(); + } + } else { + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); + } +#endif + post_code(0x3f); +#if CONFIG_CHROMEOS + init_chromeos(boot_mode); +#endif +#if CONFIG_COLLECT_TIMESTAMPS + timestamp_init(base_time); + timestamp_add(TS_START_ROMSTAGE, start_romstage_time ); + timestamp_add(TS_BEFORE_INITRAM, before_dram_time ); + timestamp_add(TS_AFTER_INITRAM, after_dram_time ); + timestamp_add_now(TS_END_ROMSTAGE); +#endif +#if CONFIG_CONSOLE_CBMEM + /* Keep this the last thing this function does. */ + cbmemc_reinit(); +#endif +} diff --git a/src/mainboard/intel/graysreef/thermal.h b/src/mainboard/intel/graysreef/thermal.h new file mode 100644 index 0000000..2068686 --- /dev/null +++ b/src/mainboard/intel/graysreef/thermal.h @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef GRAYSREEF_THERMAL_H +#define GRAYSREEF_THERMAL_H + +/* Fan is OFF */ +#define FAN4_THRESHOLD_OFF 0 +#define FAN4_THRESHOLD_ON 0 +#define FAN4_PWM 0x00 + +/* Fan is at LOW speed */ +#define FAN3_THRESHOLD_OFF 48 +#define FAN3_THRESHOLD_ON 55 +#define FAN3_PWM 0x40 + +/* Fan is at MEDIUM speed */ +#define FAN2_THRESHOLD_OFF 52 +#define FAN2_THRESHOLD_ON 64 +#define FAN2_PWM 0x80 + +/* Fan is at HIGH speed */ +#define FAN1_THRESHOLD_OFF 60 +#define FAN1_THRESHOLD_ON 68 +#define FAN1_PWM 0xb0 + +/* Fan is at FULL speed */ +#define FAN0_THRESHOLD_OFF 66 +#define FAN0_THRESHOLD_ON 78 +#define FAN0_PWM 0xff + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +/* Tj_max value for calculating PECI CPU temperature */ +#define MAX_TEMPERATURE 100 + +#endif

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New patch to review for coreboot: 3050fca lynxpoint: Management Engine Updates
by Stefan Reinauer 09 Mar '13

09 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2620 -gerrit commit 3050fcafa5cc5b13e80c5f9a81c83824c8223b62 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Nov 2 09:16:46 2012 -0500 lynxpoint: Management Engine Updates The ME9 requirements have added some registers and changed some of the MBP state machine. Implement the changes found so far in the ME9 BWG. There were a couple of reigster renames, but the majority of th churn in the me.h header file is just introducing the data structures in the same order as the ME9 BWG. Change-Id: I51b0bb6620eff4979674ea99992ddab65a8abc18 Signed-Off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/intel/lynxpoint/early_me.c | 18 +- src/southbridge/intel/lynxpoint/me.h | 262 +++++++++++++++++++--------- src/southbridge/intel/lynxpoint/me_9.x.c | 167 ++++++++++-------- src/southbridge/intel/lynxpoint/me_status.c | 167 +++++++++--------- 4 files changed, 369 insertions(+), 245 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c index 3e3c08d..e41b801 100644 --- a/src/southbridge/intel/lynxpoint/early_me.c +++ b/src/southbridge/intel/lynxpoint/early_me.c @@ -56,12 +56,12 @@ static inline void pci_write_dword_ptr(void *ptr, int offset) void intel_early_me_status(void) { struct me_hfs hfs; - struct me_gmes gmes; + struct me_hfs2 hfs2; pci_read_dword_ptr(&hfs, PCI_ME_HFS); - pci_read_dword_ptr(&gmes, PCI_ME_GMES); + pci_read_dword_ptr(&hfs2, PCI_ME_HFS2); - intel_me_status(&hfs, &gmes); + intel_me_status(&hfs, &hfs2); } int intel_early_me_init(void) @@ -73,6 +73,7 @@ int intel_early_me_init(void) printk(BIOS_INFO, "Intel ME early init\n"); /* Wait for ME UMA SIZE VALID bit to be set */ + /* FIXME: ME9 BGW indicates a 5 sec poll timeout. */ for (count = ME_RETRY; count > 0; --count) { pci_read_dword_ptr(&uma, PCI_ME_UMA); if (uma.valid) @@ -144,6 +145,13 @@ int intel_early_me_init_done(u8 status) pci_write_dword_ptr(&did, PCI_ME_H_GS); + /* + * The ME firmware does not respond with an ACK when NOMEM or ERROR + * are sent. + */ + if (status == ME_INIT_STATUS_NOMEM || status == ME_INIT_STATUS_ERROR) + return 0; + /* Must wait for ME acknowledgement */ for (count = ME_RETRY; count > 0; --count) { pci_read_dword_ptr(&hfs, PCI_ME_HFS); @@ -192,7 +200,9 @@ int intel_early_me_init_done(u8 status) /* Perform the requested reset */ if (reset) { outb(reset, 0xcf9); - hlt(); + while (1) { + hlt(); + } } return -1; } diff --git a/src/southbridge/intel/lynxpoint/me.h b/src/southbridge/intel/lynxpoint/me.h index aaeb24d..57c4f24 100644 --- a/src/southbridge/intel/lynxpoint/me.h +++ b/src/southbridge/intel/lynxpoint/me.h @@ -97,40 +97,111 @@ struct me_uma { #define ME_INIT_STATUS_SUCCESS 0 #define ME_INIT_STATUS_NOMEM 1 #define ME_INIT_STATUS_ERROR 2 +#define ME_INIT_STATUS_SUCCESS_OTHER 3 /* SEE ME9 BWG */ struct me_did { u32 uma_base: 16; - u32 reserved: 8; + u32 reserved: 7; + u32 rapid_start: 1; u32 status: 4; u32 init_done: 4; } __attribute__ ((packed)); -#define PCI_ME_GMES 0x48 -#define ME_GMES_PHASE_ROM 0 -#define ME_GMES_PHASE_BUP 1 -#define ME_GMES_PHASE_UKERNEL 2 -#define ME_GMES_PHASE_POLICY 3 -#define ME_GMES_PHASE_MODULE 4 -#define ME_GMES_PHASE_UNKNOWN 5 -#define ME_GMES_PHASE_HOST 6 - -struct me_gmes { - u32 bist_in_prog : 1; - u32 icc_prog_sts : 2; - u32 invoke_mebx : 1; - u32 cpu_replaced_sts : 1; - u32 mbp_rdy : 1; - u32 mfs_failure : 1; - u32 warm_rst_req_for_df : 1; - u32 cpu_replaced_valid : 1; - u32 reserved_1 : 2; - u32 fw_upd_ipu : 1; - u32 reserved_2 : 4; +/* + * Apparently the GMES register is renamed to HFS2 (or HFSTS2 according + * to ME9 BWG). Sadly the PCH EDS and the ME BWG do not match on nomenclature. + */ +#define PCI_ME_HFS2 0x48 +/* Infrastructure Progress Values */ +#define ME_HFS2_PHASE_ROM 0 +#define ME_HFS2_PHASE_BUP 1 +#define ME_HFS2_PHASE_UKERNEL 2 +#define ME_HFS2_PHASE_POLICY 3 +#define ME_HFS2_PHASE_MODULE_LOAD 4 +#define ME_HFS2_PHASE_UNKNOWN 5 +#define ME_HFS2_PHASE_HOST_COMM 6 +/* Current State - Based on Infra Progress values. */ +/* ROM State */ +#define ME_HFS2_STATE_ROM_BEGIN 0 +#define ME_HFS2_STATE_ROM_DISABLE 6 +/* BUP State */ +#define ME_HFS2_STATE_BUP_INIT 0 +#define ME_HFS2_STATE_BUP_DIS_HOST_WAKE 1 +#define ME_HFS2_STATE_BUP_FLOW_DET 4 +#define ME_HFS2_STATE_BUP_VSCC_ERR 8 +#define ME_HFS2_STATE_BUP_CHECK_STRAP 0xa +#define ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT 0xb +#define ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP 0xd +#define ME_HFS2_STATE_BUP_M3 0x11 +#define ME_HFS2_STATE_BUP_M0 0x12 +#define ME_HFS2_STATE_BUP_FLOW_DET_ERR 0x13 +#define ME_HFS2_STATE_BUP_M3_CLK_ERR 0x15 +#define ME_HFS2_STATE_BUP_M3_KERN_LOAD 0x18 +#define ME_HFS2_STATE_BUP_T32_MISSING 0x1c +#define ME_HFS2_STATE_BUP_WAIT_DID 0x1f +#define ME_HFS2_STATE_BUP_WAIT_DID_FAIL 0x20 +#define ME_HFS2_STATE_BUP_DID_NO_FAIL 0x21 +#define ME_HFS2_STATE_BUP_ENABLE_UMA 0x22 +#define ME_HFS2_STATE_BUP_ENABLE_UMA_ERR 0x23 +#define ME_HFS2_STATE_BUP_SEND_DID_ACK 0x24 +#define ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR 0x25 +#define ME_HFS2_STATE_BUP_M0_CLK 0x26 +#define ME_HFS2_STATE_BUP_M0_CLK_ERR 0x27 +#define ME_HFS2_STATE_BUP_TEMP_DIS 0x28 +#define ME_HFS2_STATE_BUP_M0_KERN_LOAD 0x32 +/* Policy Module State */ +#define ME_HFS2_STATE_POLICY_ENTRY 0 +#define ME_HFS2_STATE_POLICY_RCVD_S3 3 +#define ME_HFS2_STATE_POLICY_RCVD_S4 4 +#define ME_HFS2_STATE_POLICY_RCVD_S5 5 +#define ME_HFS2_STATE_POLICY_RCVD_UPD 6 +#define ME_HFS2_STATE_POLICY_RCVD_PCR 7 +#define ME_HFS2_STATE_POLICY_RCVD_NPCR 8 +#define ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE 9 +#define ME_HFS2_STATE_POLICY_RCVD_AC_DC 0xa +#define ME_HFS2_STATE_POLICY_RCVD_DID 0xb +#define ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND 0xc +#define ME_HFS2_STATE_POLICY_VSCC_INVALID 0xd +#define ME_HFS2_STATE_POLICY_FPB_ERR 0xe +#define ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR 0xf +#define ME_HFS2_STATE_POLICY_VSCC_NO_MATCH 0x10 +/* Current PM Event Values */ +#define ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE 0 +#define ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR 1 +#define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET 2 +#define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR 3 +#define ME_HFS2_PMEVENT_CLEAN_ME_RESET 4 +#define ME_HFS2_PMEVENT_ME_RESET_EXCEPTION 5 +#define ME_HFS2_PMEVENT_PSEUDO_ME_RESET 6 +#define ME_HFS2_PMEVENT_S0MO_SXM3 7 +#define ME_HFS2_PMEVENT_SXM3_S0M0 8 +#define ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET 9 +#define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3 0xa +#define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF 0xb +#define ME_HFS2_PMEVENT_SXMX_SXMOFF 0xc + +struct me_hfs2 { + u32 bist_in_progress: 1; + u32 reserved1: 2; + u32 invoke_mebx: 1; + u32 cpu_replaced_sts: 1; + u32 mbp_rdy: 1; + u32 mfs_failure: 1; + u32 warm_reset_request: 1; + u32 cpu_replaced_valid: 1; + u32 reserved2: 4; + u32 mbp_cleared: 1; + u32 reserved3: 2; u32 current_state: 8; u32 current_pmevent: 4; u32 progress_code: 4; } __attribute__ ((packed)); +#define PCI_ME_H_GS2 0x70 +#define PCI_ME_MBP_GIVE_UP 0x01 + +#define PCI_ME_H_GS3 0x74 + #define PCI_ME_HERES 0xbc #define PCI_ME_EXT_SHA1 0x00 #define PCI_ME_EXT_SHA256 0x02 @@ -241,7 +312,7 @@ typedef enum { } me_bios_path; /* Defined in me_status.c for both romstage and ramstage */ -void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes); +void intel_me_status(struct me_hfs *hfs, struct me_hfs2 *hfs2); #ifdef __PRE_RAM__ void intel_early_me_status(void); @@ -254,6 +325,47 @@ int intel_early_me_init_done(u8 status); void intel_me_finalize_smm(void); void intel_me8_finalize_smm(void); #endif + +/* + * ME to BIOS Payload Datastructures and definitions. The ordering of the + * structures follows the ordering in the ME9 BWG. + */ + +#define MBP_APPID_KERNEL 1 +#define MBP_APPID_INTEL_AT 3 +#define MBP_APPID_HWA 4 +#define MBP_APPID_ICC 5 +/* Kernel items: */ +#define MBP_KERNEL_FW_VER_ITEM 1 +#define MBP_KERNEL_FW_CAP_ITEM 2 +#define MBP_KERNEL_ROM_BIST_ITEM 3 +#define MBP_KERNEL_PLAT_KEY_ITEM 4 +#define MBP_KERNEL_FW_TYPE_ITEM 5 +#define MBP_KERNEL_MFS_FAILURE_ITEM 6 +/* Intel AT items: */ +#define MBP_INTEL_AT_STATE_ITEM 1 +/* ICC Items: */ +#define MBP_ICC_PROFILE_ITEM 1 +/* HWA Items: */ +#define MBP_HWA_REQUEST_ITEM 1 + +#define MBP_MAKE_IDENT(appid, item) ((appid << 8) | item) +#define MBP_IDENT(appid, item) \ + MBP_MAKE_IDENT(MBP_APPID_##appid, MBP_##appid##_##item##_ITEM) + +typedef struct { + u32 mbp_size : 8; + u32 num_entries : 8; + u32 rsvd : 16; +} __attribute__ ((packed)) mbp_header; + +typedef struct { + u32 app_id : 8; + u32 item_id : 8; + u32 length : 8; + u32 rsvd : 8; +} __attribute__ ((packed)) mbp_item_header; + typedef struct { u32 major_version : 16; u32 minor_version : 16; @@ -262,19 +374,10 @@ typedef struct { } __attribute__ ((packed)) mbp_fw_version_name; typedef struct { - u8 num_icc_profiles; - u8 icc_profile_soft_strap; - u8 icc_profile_index; - u8 reserved; - u32 register_lock_mask[3]; -} __attribute__ ((packed)) mbp_icc_profile; - -typedef struct { u32 full_net : 1; u32 std_net : 1; u32 manageability : 1; - u32 small_business : 1; - u32 l3manageability : 1; + u32 reserved_2 : 2; u32 intel_at : 1; u32 intel_cls : 1; u32 reserved : 3; @@ -293,33 +396,6 @@ typedef struct { } __attribute__ ((packed)) mefwcaps_sku; typedef struct { - u16 lock_state : 1; - u16 authenticate_module : 1; - u16 s3authentication : 1; - u16 flash_wear_out : 1; - u16 flash_variable_security : 1; - u16 wwan3gpresent : 1; - u16 wwan3goob : 1; - u16 reserved : 9; -} __attribute__ ((packed)) tdt_state_flag; - -typedef struct { - u8 state; - u8 last_theft_trigger; - tdt_state_flag flags; -} __attribute__ ((packed)) tdt_state_info; - -typedef struct { - u32 platform_target_usage_type : 4; - u32 platform_target_market_type : 2; - u32 super_sku : 1; - u32 reserved : 1; - u32 intel_me_fw_image_type : 4; - u32 platform_brand : 4; - u32 reserved_1 : 16; -} __attribute__ ((packed)) platform_type_rule_data; - -typedef struct { mefwcaps_sku fw_capabilities; u8 available; } mbp_fw_caps; @@ -335,33 +411,57 @@ typedef struct { } mbp_platform_key; typedef struct { - platform_type_rule_data rule_data; - u8 available; + u32 mobile: 1; + u32 desktop: 1; + u32 server: 1; + u32 workstation: 1; + u32 corporate: 1; + u32 consumer: 1; + u32 regular_super_sku: 1; + u32 rsvd: 1; + u32 image_type: 4; + u32 brand: 4; + u32 rsvd1: 16; +} __attribute__ ((packed)) mbp_me_firmware_type; + +typedef struct { + mbp_me_firmware_type rule_data; + u8 available; } mbp_plat_type; typedef struct { - mbp_fw_version_name fw_version_name; - mbp_fw_caps fw_caps_sku; - mbp_rom_bist_data rom_bist_data; - mbp_platform_key platform_key; - mbp_plat_type fw_plat_type; - mbp_icc_profile icc_profile; - tdt_state_info at_state; - u32 mfsintegrity; -} me_bios_payload; + u8 num_icc_profiles; + u8 icc_profile_soft_strap; + u8 icc_profile_index; + u8 reserved; + u32 register_lock_mask[3]; +} __attribute__ ((packed)) mbp_icc_profile; -typedef struct { - u32 mbp_size : 8; - u32 num_entries : 8; - u32 rsvd : 16; -} __attribute__ ((packed)) mbp_header; +typedef struct { + u16 lock_state : 1; + u16 authenticate_module : 1; + u16 s3authentication : 1; + u16 flash_wear_out : 1; + u16 flash_variable_security : 1; + u16 reserved : 11; +} __attribute__ ((packed)) tdt_state_flag; typedef struct { - u32 app_id : 8; - u32 item_id : 8; - u32 length : 8; - u32 rsvd : 8; -} __attribute__ ((packed)) mbp_item_header; + u8 state; + u8 last_theft_trigger; + tdt_state_flag flags; +} __attribute__ ((packed)) tdt_state_info; + +typedef struct { + mbp_fw_version_name fw_version_name; + mbp_fw_caps fw_caps_sku; + mbp_rom_bist_data rom_bist_data; + mbp_platform_key platform_key; + mbp_plat_type fw_plat_type; + mbp_icc_profile icc_profile; + tdt_state_info at_state; + u32 mfsintegrity; +} me_bios_payload; struct me_fwcaps { u32 id; diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index e9e5cec..12f7ab7 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -62,7 +62,7 @@ static const char *me_bios_path_values[] = { [ME_DISABLE_BIOS_PATH] = "Disable", [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", }; -static int intel_me_read_mbp(me_bios_payload *mbp_data); +static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev); #endif /* MMIO base address for MEI interface */ @@ -414,8 +414,6 @@ static void me_print_fwcaps(mbp_fw_caps *caps_section) print_cap("Full Network manageability", cap->full_net); print_cap("Regular Network manageability", cap->std_net); print_cap("Manageability", cap->manageability); - print_cap("Small business technology", cap->small_business); - print_cap("Level III manageability", cap->l3manageability); print_cap("IntelR Anti-Theft (AT)", cap->intel_at); print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls); print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc); @@ -533,7 +531,7 @@ static me_bios_path intel_me_path(device_t dev) { me_bios_path path = ME_DISABLE_BIOS_PATH; struct me_hfs hfs; - struct me_gmes gmes; + struct me_hfs2 hfs2; #if CONFIG_HAVE_ACPI_RESUME /* S3 wake skips all MKHI messages */ @@ -543,10 +541,10 @@ static me_bios_path intel_me_path(device_t dev) #endif pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS); - pci_read_dword_ptr(dev, &gmes, PCI_ME_GMES); + pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2); /* Check and dump status */ - intel_me_status(&hfs, &gmes); + intel_me_status(&hfs, &hfs2); /* Check Current Working State */ switch (hfs.working_state) { @@ -579,7 +577,7 @@ static me_bios_path intel_me_path(device_t dev) path = ME_ERROR_BIOS_PATH; /* Check if the MBP is ready */ - if (!gmes.mbp_rdy) { + if (!hfs2.mbp_rdy) { printk(BIOS_CRIT, "%s: mbp is not ready!\n", __FUNCTION__); path = ME_ERROR_BIOS_PATH; @@ -592,9 +590,9 @@ static me_bios_path intel_me_path(device_t dev) .operation_state = hfs.operation_state, .operation_mode = hfs.operation_mode, .error_code = hfs.error_code, - .progress_code = gmes.progress_code, - .current_pmevent = gmes.current_pmevent, - .current_state = gmes.current_state, + .progress_code = hfs2.progress_code, + .current_pmevent = hfs2.current_pmevent, + .current_state = hfs2.current_state, }; elog_add_event_byte(ELOG_TYPE_MANAGEMENT_ENGINE, path); elog_add_event_raw(ELOG_TYPE_MANAGEMENT_ENGINE_EXT, @@ -698,54 +696,35 @@ static void intel_me_init(device_t dev) /* Do initial setup and determine the BIOS path */ printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_bios_path_values[path]); - switch (path) { - case ME_S3WAKE_BIOS_PATH: + if (path == ME_S3WAKE_BIOS_PATH) { intel_me_hide(dev); - break; - - case ME_NORMAL_BIOS_PATH: + return; + } else if (path == ME_NORMAL_BIOS_PATH) { /* Validate the extend register */ - if (intel_me_extend_valid(dev) < 0) - break; /* TODO: force recovery mode */ + /* FIXME: force recovery mode on failure. */ + intel_me_extend_valid(dev); + } - /* Prepare MEI MMIO interface */ - if (intel_mei_setup(dev) < 0) - break; + /* + * According to the ME9 BWG, BIOS is required to fetch MBP data in + * all boot flows except S3 Resume. + */ - if(intel_me_read_mbp(&mbp_data)) - break; + /* Prepare MEI MMIO interface */ + if (intel_mei_setup(dev) < 0) + return; -#if CONFIG_CHROMEOS && 0 /* DISABLED */ - /* - * Unlock ME in recovery mode. - */ - if (recovery_mode_enabled()) { - /* Unlock ME flash region */ - mkhi_hmrfpo_enable(); - - /* Issue global reset */ - mkhi_global_reset(); - return; - } -#endif + if(intel_me_read_mbp(&mbp_data, dev)) + return; #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) - me_print_fw_version(&mbp_data.fw_version_name); - me_print_fwcaps(&mbp_data.fw_caps_sku); + me_print_fw_version(&mbp_data.fw_version_name); + me_print_fwcaps(&mbp_data.fw_caps_sku); #endif - /* - * Leave the ME unlocked in this path. - * It will be locked via SMI command later. - */ - break; - - case ME_ERROR_BIOS_PATH: - case ME_RECOVERY_BIOS_PATH: - case ME_DISABLE_BIOS_PATH: - case ME_FIRMWARE_UPDATE_BIOS_PATH: - break; - } + /* + * Leave the ME unlocked. It will be locked via SMI command later. + */ } static void set_subsystem(device_t dev, unsigned vendor, unsigned device) @@ -805,22 +784,49 @@ static u32 host_to_me_words_room(void) (csr.buffer_depth - 1); } #endif + +/* + * mbp give up routine. This path is taken if hfs.mpb_rdy is 0 or the read + * state machine on the BIOS end doesn't match the ME's state machine. + */ +static void intel_me_mbp_give_up(device_t dev) +{ + u32 reg32; + struct mei_csr csr; + + reg32 = PCI_ME_MBP_GIVE_UP; + pci_write_config32(dev, PCI_ME_H_GS3, reg32); + read_host_csr(&csr); + csr.reset = 1; + csr.interrupt_generate = 1; + write_host_csr(&csr); +} + /* * mbp seems to be following its own flow, let's retrieve it in a dedicated * function. */ -static int intel_me_read_mbp(me_bios_payload *mbp_data) +static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev) { mbp_header mbp_hdr; mbp_item_header mbp_item_hdr; u32 me2host_pending; - u32 mbp_item_id; + u32 mbp_ident; struct mei_csr host; + struct me_hfs2 hfs2; + int count; + + pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2); + + if (!hfs2.mbp_rdy) { + printk(BIOS_ERR, "ME: MBP not ready\n"); + goto mbp_failure; + } me2host_pending = me_to_host_words_pending(); if (!me2host_pending) { printk(BIOS_ERR, "ME: no mbp data!\n"); - return -1; + goto mbp_failure; } /* we know for sure that at least the header is there */ @@ -832,7 +838,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data) " buffer contains %d words\n", mbp_hdr.num_entries, mbp_hdr.mbp_size, me2host_pending); - return -1; + goto mbp_failure; } me2host_pending--; @@ -846,7 +852,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data) if (!me2host_pending) { printk(BIOS_ERR, "ME: no mbp data %d entries to go!\n", mbp_hdr.num_entries + 1); - return -1; + goto mbp_failure; } mei_read_dword_ptr(&mbp_item_hdr, MEI_ME_CB_RW); @@ -855,13 +861,13 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data) printk(BIOS_ERR, "ME: insufficient mbp data %d " "entries to go!\n", mbp_hdr.num_entries + 1); - return -1; + goto mbp_failure; } me2host_pending -= mbp_item_hdr.length; - mbp_item_id = (((u32)mbp_item_hdr.item_id) << 8) + - mbp_item_hdr.app_id; + mbp_ident = MBP_MAKE_IDENT(mbp_item_hdr.app_id, + mbp_item_hdr.item_id); copy_size = mbp_item_hdr.length - 1; @@ -873,44 +879,44 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data) p = &mbp_item_hdr; printk(BIOS_INFO, "ME: MBP item header %8.8x\n", *((u32*)p)); - switch(mbp_item_id) { - case 0x101: + switch(mbp_ident) { + case MBP_IDENT(KERNEL, FW_VER): SET_UP_COPY(fw_version_name); - case 0x102: + case MBP_IDENT(ICC, PROFILE): SET_UP_COPY(icc_profile); - case 0x103: + case MBP_IDENT(INTEL_AT, STATE): SET_UP_COPY(at_state); - case 0x201: + case MBP_IDENT(KERNEL, FW_CAP): mbp_data->fw_caps_sku.available = 1; SET_UP_COPY(fw_caps_sku.fw_capabilities); - case 0x301: + case MBP_IDENT(KERNEL, ROM_BIST): SET_UP_COPY(rom_bist_data); - case 0x401: + case MBP_IDENT(KERNEL, PLAT_KEY): SET_UP_COPY(platform_key); - case 0x501: + case MBP_IDENT(KERNEL, FW_TYPE): mbp_data->fw_plat_type.available = 1; SET_UP_COPY(fw_plat_type.rule_data); - case 0x601: + case MBP_IDENT(KERNEL, MFS_FAILURE): SET_UP_COPY(mfsintegrity); default: printk(BIOS_ERR, "ME: unknown mbp item id 0x%x!!!\n", - mbp_item_id); - return -1; + mbp_ident); + goto mbp_failure; } if (buffer_room != copy_size) { printk(BIOS_ERR, "ME: buffer room %d != %d copy size" " for item 0x%x!!!\n", - buffer_room, copy_size, mbp_item_id); - return -1; + buffer_room, copy_size, mbp_ident); + goto mbp_failure; } while(copy_size--) *copy_addr++ = read_cb(); @@ -920,16 +926,23 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data) host.interrupt_generate = 1; write_host_csr(&host); - { - int cntr = 0; - while(host.interrupt_generate) { - read_host_csr(&host); - cntr++; - } - printk(BIOS_SPEW, "ME: mbp read OK after %d cycles\n", cntr); + for (count = ME_RETRY; count > 0; --count) { + pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2); + if (hfs2.mbp_cleared) + break; + udelay(ME_DELAY); + } + + if (count == 0) { + printk(BIOS_WARNING, "ME: Timeout waiting for mbp_cleared\n"); + intel_me_mbp_give_up(dev); } return 0; + +mbp_failure: + intel_me_mbp_give_up(dev); + return -1; } #endif /* !__SMM__ */ diff --git a/src/southbridge/intel/lynxpoint/me_status.c b/src/southbridge/intel/lynxpoint/me_status.c index b2f38d6..1feaf7d 100644 --- a/src/southbridge/intel/lynxpoint/me_status.c +++ b/src/southbridge/intel/lynxpoint/me_status.c @@ -62,89 +62,89 @@ static const char *me_error_values[] = { [ME_HFS_ERROR_DEBUG] = "Debug Failure" }; -/* GMES[31:28] ME Progress Code */ +/* HFS2[31:28] ME Progress Code */ static const char *me_progress_values[] = { - [ME_GMES_PHASE_ROM] = "ROM Phase", - [ME_GMES_PHASE_BUP] = "BUP Phase", - [ME_GMES_PHASE_UKERNEL] = "uKernel Phase", - [ME_GMES_PHASE_POLICY] = "Policy Module", - [ME_GMES_PHASE_MODULE] = "Module Loading", - [ME_GMES_PHASE_UNKNOWN] = "Unknown", - [ME_GMES_PHASE_HOST] = "Host Communication" + [ME_HFS2_PHASE_ROM] = "ROM Phase", + [ME_HFS2_PHASE_BUP] = "BUP Phase", + [ME_HFS2_PHASE_UKERNEL] = "uKernel Phase", + [ME_HFS2_PHASE_POLICY] = "Policy Module", + [ME_HFS2_PHASE_MODULE_LOAD] = "Module Loading", + [ME_HFS2_PHASE_UNKNOWN] = "Unknown", + [ME_HFS2_PHASE_HOST_COMM] = "Host Communication" }; -/* GMES[27:24] Power Management Event */ +/* HFS2[27:24] Power Management Event */ static const char *me_pmevent_values[] = { - [0x00] = "Clean Moff->Mx wake", - [0x01] = "Moff->Mx wake after an error", - [0x02] = "Clean global reset", - [0x03] = "Global reset after an error", - [0x04] = "Clean Intel ME reset", - [0x05] = "Intel ME reset due to exception", - [0x06] = "Pseudo-global reset", - [0x07] = "S0/M0->Sx/M3", - [0x08] = "Sx/M3->S0/M0", - [0x09] = "Non-power cycle reset", - [0x0a] = "Power cycle reset through M3", - [0x0b] = "Power cycle reset through Moff", - [0x0c] = "Sx/Mx->Sx/Moff" + [ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE] = "Clean Moff->Mx wake", + [ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR] = "Moff->Mx wake after an error", + [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET] = "Clean global reset", + [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR] = "Global reset after an error", + [ME_HFS2_PMEVENT_CLEAN_ME_RESET] = "Clean Intel ME reset", + [ME_HFS2_PMEVENT_ME_RESET_EXCEPTION] = "Intel ME reset due to exception", + [ME_HFS2_PMEVENT_PSEUDO_ME_RESET] = "Pseudo-global reset", + [ME_HFS2_PMEVENT_S0MO_SXM3] = "S0/M0->Sx/M3", + [ME_HFS2_PMEVENT_SXM3_S0M0] = "Sx/M3->S0/M0", + [ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET] = "Non-power cycle reset", + [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3] = "Power cycle reset through M3", + [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF] = "Power cycle reset through Moff", + [ME_HFS2_PMEVENT_SXMX_SXMOFF] = "Sx/Mx->Sx/Moff" }; /* Progress Code 0 states */ static const char *me_progress_rom_values[] = { - [0x00] = "BEGIN", - [0x06] = "DISABLE" + [ME_HFS2_STATE_ROM_BEGIN] = "BEGIN", + [ME_HFS2_STATE_ROM_DISABLE] = "DISABLE" }; /* Progress Code 1 states */ static const char *me_progress_bup_values[] = { - [0x00] = "Initialization starts", - [0x01] = "Disable the host wake event", - [0x04] = "Flow determination start process", - [0x08] = "Error reading/matching the VSCC table in the descriptor", - [0x0a] = "Check to see if straps say ME DISABLED", - [0x0b] = "Timeout waiting for PWROK", - [0x0d] = "Possibly handle BUP manufacturing override strap", - [0x11] = "Bringup in M3", - [0x12] = "Bringup in M0", - [0x13] = "Flow detection error", - [0x15] = "M3 clock switching error", - [0x18] = "M3 kernel load", - [0x1c] = "T34 missing - cannot program ICC", - [0x1f] = "Waiting for DID BIOS message", - [0x20] = "Waiting for DID BIOS message failure", - [0x21] = "DID reported an error", - [0x22] = "Enabling UMA", - [0x23] = "Enabling UMA error", - [0x24] = "Sending DID Ack to BIOS", - [0x25] = "Sending DID Ack to BIOS error", - [0x26] = "Switching clocks in M0", - [0x27] = "Switching clocks in M0 error", - [0x28] = "ME in temp disable", - [0x32] = "M0 kernel load", + [ME_HFS2_STATE_BUP_INIT] = "Initialization starts", + [ME_HFS2_STATE_BUP_DIS_HOST_WAKE] = "Disable the host wake event", + [ME_HFS2_STATE_BUP_FLOW_DET] = "Flow determination start process", + [ME_HFS2_STATE_BUP_VSCC_ERR] = "Error reading/matching the VSCC table in the descriptor", + [ME_HFS2_STATE_BUP_CHECK_STRAP] = "Check to see if straps say ME DISABLED", + [ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT] = "Timeout waiting for PWROK", + [ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP] = "Possibly handle BUP manufacturing override strap", + [ME_HFS2_STATE_BUP_M3] = "Bringup in M3", + [ME_HFS2_STATE_BUP_M0] = "Bringup in M0", + [ME_HFS2_STATE_BUP_FLOW_DET_ERR] = "Flow detection error", + [ME_HFS2_STATE_BUP_M3_CLK_ERR] = "M3 clock switching error", + [ME_HFS2_STATE_BUP_M3_KERN_LOAD] = "M3 kernel load", + [ME_HFS2_STATE_BUP_T32_MISSING] = "T34 missing - cannot program ICC", + [ME_HFS2_STATE_BUP_WAIT_DID] = "Waiting for DID BIOS message", + [ME_HFS2_STATE_BUP_WAIT_DID_FAIL] = "Waiting for DID BIOS message failure", + [ME_HFS2_STATE_BUP_DID_NO_FAIL] = "DID reported no error", + [ME_HFS2_STATE_BUP_ENABLE_UMA] = "Enabling UMA", + [ME_HFS2_STATE_BUP_ENABLE_UMA_ERR] = "Enabling UMA error", + [ME_HFS2_STATE_BUP_SEND_DID_ACK] = "Sending DID Ack to BIOS", + [ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR] = "Sending DID Ack to BIOS error", + [ME_HFS2_STATE_BUP_M0_CLK] = "Switching clocks in M0", + [ME_HFS2_STATE_BUP_M0_CLK_ERR] = "Switching clocks in M0 error", + [ME_HFS2_STATE_BUP_TEMP_DIS] = "ME in temp disable", + [ME_HFS2_STATE_BUP_M0_KERN_LOAD] = "M0 kernel load", }; /* Progress Code 3 states */ static const char *me_progress_policy_values[] = { - [0x00] = "Entery into Policy Module", - [0x03] = "Received S3 entry", - [0x04] = "Received S4 entry", - [0x05] = "Received S5 entry", - [0x06] = "Received UPD entry", - [0x07] = "Received PCR entry", - [0x08] = "Received NPCR entry", - [0x09] = "Received host wake", - [0x0a] = "Received AC<>DC switch", - [0x0b] = "Received DRAM Init Done", - [0x0c] = "VSCC Data not found for flash device", - [0x0d] = "VSCC Table is not valid", - [0x0e] = "Flash Partition Boundary is outside address space", - [0x0f] = "ME cannot access the chipset descriptor region", - [0x10] = "Required VSCC values for flash parts do not match", + [ME_HFS2_STATE_POLICY_ENTRY] = "Entery into Policy Module", + [ME_HFS2_STATE_POLICY_RCVD_S3] = "Received S3 entry", + [ME_HFS2_STATE_POLICY_RCVD_S4] = "Received S4 entry", + [ME_HFS2_STATE_POLICY_RCVD_S5] = "Received S5 entry", + [ME_HFS2_STATE_POLICY_RCVD_UPD] = "Received UPD entry", + [ME_HFS2_STATE_POLICY_RCVD_PCR] = "Received PCR entry", + [ME_HFS2_STATE_POLICY_RCVD_NPCR] = "Received NPCR entry", + [ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE] = "Received host wake", + [ME_HFS2_STATE_POLICY_RCVD_AC_DC] = "Received AC<>DC switch", + [ME_HFS2_STATE_POLICY_RCVD_DID] = "Received DRAM Init Done", + [ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND] = "VSCC Data not found for flash device", + [ME_HFS2_STATE_POLICY_VSCC_INVALID] = "VSCC Table is not valid", + [ME_HFS2_STATE_POLICY_FPB_ERR] = "Flash Partition Boundary is outside address space", + [ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR] = "ME cannot access the chipset descriptor region", + [ME_HFS2_STATE_POLICY_VSCC_NO_MATCH] = "Required VSCC values for flash parts do not match", }; #endif -void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes) +void intel_me_status(struct me_hfs *hfs, struct me_hfs2 *hfs2) { #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) /* Check Current States */ @@ -169,44 +169,45 @@ void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes) printk(BIOS_DEBUG, "ME: Error Code : %s\n", me_error_values[hfs->error_code]); printk(BIOS_DEBUG, "ME: Progress Phase : %s\n", - me_progress_values[gmes->progress_code]); + me_progress_values[hfs2->progress_code]); printk(BIOS_DEBUG, "ME: Power Management Event : %s\n", - me_pmevent_values[gmes->current_pmevent]); + me_pmevent_values[hfs2->current_pmevent]); printk(BIOS_DEBUG, "ME: Progress Phase State : "); - switch (gmes->progress_code) { - case ME_GMES_PHASE_ROM: /* ROM Phase */ + switch (hfs2->progress_code) { + case ME_HFS2_PHASE_ROM: /* ROM Phase */ printk(BIOS_DEBUG, "%s", - me_progress_rom_values[gmes->current_state]); + me_progress_rom_values[hfs2->current_state]); break; - case ME_GMES_PHASE_BUP: /* Bringup Phase */ - if (gmes->current_state < ARRAY_SIZE(me_progress_bup_values) - && me_progress_bup_values[gmes->current_state]) + case ME_HFS2_PHASE_BUP: /* Bringup Phase */ + if (hfs2->current_state < ARRAY_SIZE(me_progress_bup_values) + && me_progress_bup_values[hfs2->current_state]) printk(BIOS_DEBUG, "%s", - me_progress_bup_values[gmes->current_state]); + me_progress_bup_values[hfs2->current_state]); else - printk(BIOS_DEBUG, "0x%02x", gmes->current_state); + printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); break; - case ME_GMES_PHASE_POLICY: /* Policy Module Phase */ - if (gmes->current_state < ARRAY_SIZE(me_progress_policy_values) - && me_progress_policy_values[gmes->current_state]) + case ME_HFS2_PHASE_POLICY: /* Policy Module Phase */ + if (hfs2->current_state < ARRAY_SIZE(me_progress_policy_values) + && me_progress_policy_values[hfs2->current_state]) printk(BIOS_DEBUG, "%s", - me_progress_policy_values[gmes->current_state]); + me_progress_policy_values[hfs2->current_state]); else - printk(BIOS_DEBUG, "0x%02x", gmes->current_state); + printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); break; - case ME_GMES_PHASE_HOST: /* Host Communication Phase */ - if (!gmes->current_state) + case ME_HFS2_PHASE_HOST_COMM: /* Host Communication Phase */ + if (!hfs2->current_state) printk(BIOS_DEBUG, "Host communication established"); else - printk(BIOS_DEBUG, "0x%02x", gmes->current_state); + printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); break; default: - printk(BIOS_DEBUG, "Unknown 0x%02x", gmes->current_state); + printk(BIOS_DEBUG, "Unknown phase: 0x%02x sate: 0x%02x", + hfs2->progress_code, hfs2->current_state); } printk(BIOS_DEBUG, "\n"); #endif

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New patch to review for coreboot: c6739e8 lynxpoint: PMIR register rename
by Stefan Reinauer 09 Mar '13

09 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2619 -gerrit commit c6739e8eb9a4961ac54223c8946d53e24d349142 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Nov 2 09:10:30 2012 -0500 lynxpoint: PMIR register rename The register that controls global reset is named the Power Mangement Initialization Regiser (PMIR). Update the defines to reflect the documentation. Additionally, there is no core well reset control according to the EDS. There is, however, a CF9 lock field to lock this register down. Change-Id: I773c33bec63a06cdb869eb9f94553d476e492798 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/intel/lynxpoint/early_me.c | 11 ++++------- src/southbridge/intel/lynxpoint/pch.h | 6 +++--- 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c index 5b266cc..3e3c08d 100644 --- a/src/southbridge/intel/lynxpoint/early_me.c +++ b/src/southbridge/intel/lynxpoint/early_me.c @@ -111,18 +111,15 @@ int intel_early_me_uma_size(void) static inline void set_global_reset(int enable) { - u32 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3); - - /* Clear CF9 Without Resume Well Reset Enable */ - etr3 &= ~ETR3_CWORWRE; + u32 pmir = pci_read_config32(PCH_LPC_DEV, PMIR); /* CF9GR indicates a Global Reset */ if (enable) - etr3 |= ETR3_CF9GR; + pmir |= PMIR_CF9GR; else - etr3 &= ~ETR3_CF9GR; + pmir &= ~PMIR_CF9GR; - pci_write_config32(PCH_LPC_DEV, ETR3, etr3); + pci_write_config32(PCH_LPC_DEV, PMIR, pmir); } int intel_early_me_init_done(u8 status) diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index d508214..0847956 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -129,9 +129,9 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define GEN_PMCON_1 0xa0 #define GEN_PMCON_2 0xa2 #define GEN_PMCON_3 0xa4 -#define ETR3 0xac -#define ETR3_CWORWRE (1 << 18) -#define ETR3_CF9GR (1 << 20) +#define PMIR 0xac +#define PMIR_CF9LOCK (1 << 31) +#define PMIR_CF9GR (1 << 20) /* GEN_PMCON_3 bits */ #define RTC_BATTERY_DEAD (1 << 2)

1 0

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coreboot March 2013