coreboot March 2013

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New patch to review for coreboot: db7c2e5 x86: Add alignment requirement for cbfs microcode
by Stefan Reinauer 13 Mar '13

13 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2711 -gerrit commit db7c2e529785f46163c57b824e9f31fa59c697bb Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Dec 14 17:11:20 2012 -0600 x86: Add alignment requirement for cbfs microcode There is a requirement that microcode updates be aligned on a 16 byte boundary. Inform cbfstool to align the microcode blob in cbfs to a 16-byte boundary. Noted that when alignment requirement is added the microcode is properly aligned. Change-Id: I84edb8ae98ab06858228e0ccba9e914131a14379 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index b48a803..09ca2eb 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -16,12 +16,14 @@ ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL), y) cbfs-files-y += cpu_microcode_blob.bin cpu_microcode_blob.bin-type = 0x53 cpu_microcode_blob.bin-file = $(call strip_quotes,$(CONFIG_CPU_MICROCODE_FILE)) +cpu_microcode_blob.bin-position = 0x10 endif ifeq ($(CONFIG_CPU_MICROCODE_CBFS_GENERATE), y) cbfs-files-y += cpu_microcode_blob.bin cpu_microcode_blob.bin-type = 0x53 cpu_microcode_blob.bin-file = $(obj)/cpu_microcode_blob.bin +cpu_microcode_blob.bin-position = 0x10 endif # In case we have more than one "source" (cough) files containing microcode, we

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Patch merged into coreboot/master: ba949d3 libpayload: Start using only internal and compiler headers.
by gerrit＠coreboot.org 13 Mar '13

13 Mar '13

the following patch was just integrated into master: commit ba949d32ba97d96422510967df33532dd39e47c0 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Mar 13 13:42:55 2013 -0700 libpayload: Start using only internal and compiler headers. When building other payloads with lpgcc the -nostdinc flag was injected into CFLAGS, but when building libpayload itself some headers were being used from the host system. This change puts -nostdinc into the Makefile and xcompile script, fixes up one include path in include/inttypes.h, adds the compiler provided include directory to the include search path, and deletes the two now redundant stdint.h files. BUG=None TEST=With this and other changes, built libpayload and depthcharge for Daisy, Link, and Fox. BRANCH=None Change-Id: Ia7817fceab5297cd82ccc0d392330de0df61980e Signed-off-by: Gabe Black <gabeblack(a)google.com> Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: http://review.coreboot.org/2710 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Wed Mar 13 21:59:46 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Wed Mar 13 22:04:37 2013, giving +2 See http://review.coreboot.org/2710 for details. -gerrit

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New patch to review for coreboot: 98cc6c0 libpayload: Start using only internal and compiler headers.
by Ronald G. Minnich 13 Mar '13

13 Mar '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2710 -gerrit commit 98cc6c0c446f9ebbb94ef6ede24169d5fe06f06b Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Mar 13 13:42:55 2013 -0700 libpayload: Start using only internal and compiler headers. When building other payloads with lpgcc the -nostdinc flag was injected into CFLAGS, but when building libpayload itself some headers were being used from the host system. This change puts -nostdinc into the Makefile and xcompile script, fixes up one include path in include/inttypes.h, adds the compiler provided include directory to the include search path, and deletes the two now redundant stdint.h files. BUG=None TEST=With this and other changes, built libpayload and depthcharge for Daisy, Link, and Fox. BRANCH=None Change-Id: Ia7817fceab5297cd82ccc0d392330de0df61980e Signed-off-by: Gabe Black <gabeblack(a)google.com> Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- payloads/libpayload/Makefile.inc | 6 +- payloads/libpayload/include/inttypes.h | 2 +- payloads/libpayload/include/sys/stdint.h | 185 ----------------------------- payloads/libpayload/util/xcompile/xcompile | 2 +- 4 files changed, 6 insertions(+), 189 deletions(-) diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc index 4c434a3..b06288b 100644 --- a/payloads/libpayload/Makefile.inc +++ b/payloads/libpayload/Makefile.inc @@ -58,8 +58,10 @@ subdirs-$(CONFIG_CURSES) += curses subdirs-$(CONFIG_CBFS) += libcbfs subdirs-$(CONFIG_LZMA) += liblzma -INCLUDES := -Iinclude -Iinclude/$(ARCHDIR-y) -I$(obj) -CFLAGS = $(EXTRA_CFLAGS) $(INCLUDES) -Os -pipe +CC_INCLUDE = $(shell $(CC) -print-search-dirs | head -n 1 | cut -d' ' -f2)include + +INCLUDES := -Iinclude -Iinclude/$(ARCHDIR-y) -I$(obj) -I$(CC_INCLUDE) +CFLAGS = $(EXTRA_CFLAGS) $(INCLUDES) -Os -pipe -nostdinc CFLAGS += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs CFLAGS += -Wstrict-aliasing -Wshadow -fno-builtin diff --git a/payloads/libpayload/include/inttypes.h b/payloads/libpayload/include/inttypes.h index 922f08a..357dbf4 100644 --- a/payloads/libpayload/include/inttypes.h +++ b/payloads/libpayload/include/inttypes.h @@ -19,7 +19,7 @@ #ifndef _INTTYPES_H_ #define _INTTYPES_H_ -#include <sys/stdint.h> +#include <stdint.h> #ifdef __cplusplus #define __wchar_t wchar_t diff --git a/payloads/libpayload/include/sys/stdint.h b/payloads/libpayload/include/sys/stdint.h deleted file mode 100644 index c1b1044..0000000 --- a/payloads/libpayload/include/sys/stdint.h +++ /dev/null @@ -1,185 +0,0 @@ -/* $OpenBSD: stdint.h,v 1.4 2006/12/10 22:17:55 deraadt Exp $ */ - -/* - * Copyright (c) 1997, 2005 Todd C. Miller <Todd.Miller(a)courtesan.com> - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _SYS_STDINT_H_ -#define _SYS_STDINT_H_ - -#include <arch/types.h> -//#include <sys/cdefs.h> -//#include <machine/_types.h> - -#ifndef __BIT_TYPES_DEFINED__ -#define __BIT_TYPES_DEFINED__ -#endif - -/* 7.18.1.2 Minimum-width integer types */ -typedef int8_t int_least8_t; -typedef uint8_t uint_least8_t; -typedef int16_t int_least16_t; -typedef uint16_t uint_least16_t; -typedef int32_t int_least32_t; -typedef uint32_t uint_least32_t; -typedef int64_t int_least64_t; -typedef uint64_t uint_least64_t; - -/* 7.18.1.3 Fastest minimum-width integer types */ -typedef int8_t int_fast8_t; -typedef uint8_t uint_fast8_t; -typedef int16_t int_fast16_t; -typedef uint16_t uint_fast16_t; -typedef int32_t int_fast32_t; -typedef uint32_t uint_fast32_t; -typedef int64_t int_fast64_t; -typedef uint64_t uint_fast64_t; - -/* 7.18.1.5 Greatest-width integer types */ -typedef int64_t intmax_t; -typedef uint64_t uintmax_t; - -#if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) -/* - * 7.18.2 Limits of specified-width integer types. - * - * The following object-like macros specify the minimum and maximum limits - * of integer types corresponding to the typedef names defined above. - */ - -/* 7.18.2.1 Limits of exact-width integer types */ -#define INT8_MIN (-0x7f - 1) -#define INT16_MIN (-0x7fff - 1) -#define INT32_MIN (-0x7fffffff - 1) -#define INT64_MIN (-0x7fffffffffffffffLL - 1) - -#define INT8_MAX 0x7f -#define INT16_MAX 0x7fff -#define INT32_MAX 0x7fffffff -#define INT64_MAX 0x7fffffffffffffffLL - -#define UINT8_MAX 0xff -#define UINT16_MAX 0xffff -#define UINT32_MAX 0xffffffffU -#define UINT64_MAX 0xffffffffffffffffULL - -/* 7.18.2.2 Limits of minimum-width integer types */ -#define INT_LEAST8_MIN INT8_MIN -#define INT_LEAST16_MIN INT16_MIN -#define INT_LEAST32_MIN INT32_MIN -#define INT_LEAST64_MIN INT64_MIN - -#define INT_LEAST8_MAX INT8_MAX -#define INT_LEAST16_MAX INT16_MAX -#define INT_LEAST32_MAX INT32_MAX -#define INT_LEAST64_MAX INT64_MAX - -#define UINT_LEAST8_MAX UINT8_MAX -#define UINT_LEAST16_MAX UINT16_MAX -#define UINT_LEAST32_MAX UINT32_MAX -#define UINT_LEAST64_MAX UINT64_MAX - -/* 7.18.2.3 Limits of fastest minimum-width integer types */ -#define INT_FAST8_MIN INT8_MIN -#define INT_FAST16_MIN INT16_MIN -#define INT_FAST32_MIN INT32_MIN -#define INT_FAST64_MIN INT64_MIN - -#define INT_FAST8_MAX INT8_MAX -#define INT_FAST16_MAX INT16_MAX -#define INT_FAST32_MAX INT32_MAX -#define INT_FAST64_MAX INT64_MAX - -#define UINT_FAST8_MAX UINT8_MAX -#define UINT_FAST16_MAX UINT16_MAX -#define UINT_FAST32_MAX UINT32_MAX -#define UINT_FAST64_MAX UINT64_MAX - -/* 7.18.2.4 Limits of integer types capable of holding object pointers */ -#ifdef __LP64__ -#define INTPTR_MIN INT64_MIN -#define INTPTR_MAX INT64_MAX -#define UINTPTR_MAX UINT64_MAX -#else -#define INTPTR_MIN INT32_MIN -#define INTPTR_MAX INT32_MAX -#define UINTPTR_MAX UINT32_MAX -#endif - -/* 7.18.2.5 Limits of greatest-width integer types */ -#define INTMAX_MIN INT64_MIN -#define INTMAX_MAX INT64_MAX -#define UINTMAX_MAX UINT64_MAX - -/* - * 7.18.3 Limits of other integer types. - * - * The following object-like macros specify the minimum and maximum limits - * of integer types corresponding to types specified in other standard - * header files. - */ - -/* Limits of ptrdiff_t */ -#define PTRDIFF_MIN INTPTR_MIN -#define PTRDIFF_MAX INTPTR_MAX - -/* Limits of sig_atomic_t */ -#define SIG_ATOMIC_MIN INT32_MIN -#define SIG_ATOMIC_MAX INT32_MAX - -/* Limits of size_t (also in limits.h) */ -#ifndef SIZE_MAX -#define SIZE_MAX UINTPTR_MAX -#endif - -/* Limits of wchar_t */ -#define WCHAR_MIN INT32_MIN -#define WCHAR_MAX INT32_MAX - -/* Limits of wint_t */ -#define WINT_MIN INT32_MIN -#define WINT_MAX INT32_MAX - -#endif /* __cplusplus || __STDC_LIMIT_MACROS */ - -#if !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) -/* - * 7.18.4 Macros for integer constants. - * - * The following function-like macros expand to integer constants - * suitable for initializing objects that have integer types corresponding - * to types defined in <stdint.h>. The argument in any instance of - * these macros shall be a decimal, octal, or hexadecimal constant with - * a value that does not exceed the limits for the corresponding type. - */ - -/* 7.18.4.1 Macros for minimum-width integer constants. */ -#define INT8_C(_c) (_c) -#define INT16_C(_c) (_c) -#define INT32_C(_c) (_c) -#define INT64_C(_c) __CONCAT(_c, LL) - -#define UINT8_C(_c) (_c) -#define UINT16_C(_c) (_c) -#define UINT32_C(_c) __CONCAT(_c, U) -#define UINT64_C(_c) __CONCAT(_c, ULL) - -/* 7.18.4.2 Macros for greatest-width integer constants. */ -#define INTMAX_C(_c) __CONCAT(_c, LL) -#define UINTMAX_C(_c) __CONCAT(_c, ULL) - -#endif /* __cplusplus || __STDC_CONSTANT_MACROS */ - -#endif /* _SYS_STDINT_H_ */ diff --git a/payloads/libpayload/util/xcompile/xcompile b/payloads/libpayload/util/xcompile/xcompile index 62e7a38..58f086f 100644 --- a/payloads/libpayload/util/xcompile/xcompile +++ b/payloads/libpayload/util/xcompile/xcompile @@ -41,7 +41,7 @@ testcc() { local tmp_o="$TMPFILE.o" rm -f "$tmp_c" "$tmp_o" echo "_start(void) {}" >"$tmp_c" - "$1" -nostdlib -Werror $2 "$tmp_c" -o "$tmp_o" >/dev/null 2>&1 + "$1" -nostdinc -nostdlib -Werror $2 "$tmp_c" -o "$tmp_o" >/dev/null 2>&1 } testas() {

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New patch to review for coreboot: a2f354d Revert "Intel Sandybridge: add reserved memory as resources"
by Stefan Reinauer 13 Mar '13

13 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2709 -gerrit commit a2f354d7ffbee4d55f7fe237786538a3fa0d478d Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Mar 13 20:25:13 2013 +0100 Revert "Intel Sandybridge: add reserved memory as resources" This reverts commit 1ec5e744c63938aa75e80e8d7548d05e998660a2 This is not to be submitted, but there as a place holder for the real fix. Change-Id: I6a36b1b78423b5a79fa42b39927fbefef554aa48 --- src/cpu/x86/mtrr/mtrr.c | 4 ---- src/include/device/device.h | 12 ++--------- src/include/device/resource.h | 1 - src/northbridge/intel/sandybridge/northbridge.c | 28 +++++++++++++------------ 4 files changed, 17 insertions(+), 28 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index a061b54..fdc7aa6 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -361,10 +361,6 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res) return; } - if (res->flags & IORESOURCE_IGNORE_MTRR) { - return; - } - if (!(res->flags & IORESOURCE_CACHEABLE)) return; diff --git a/src/include/device/device.h b/src/include/device/device.h index eaf84c6..1515b45 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -173,25 +173,17 @@ unsigned int scan_static_bus(device_t bus, unsigned int max); void fixed_mem_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek, unsigned long type); - -/* It is the caller's responsibility to adjust regions such that ram_resource() - * and mmio_resource() do not overlap. - * - * Current MTRR setup creates exclusive uncacheable holes for uma_resource() - * only and these are allowed to overlap any ram_resource(). This approach - * is used for all UMA except Intel Sandy/IvyBridge. - */ #define ram_resource(dev, idx, basek, sizek) \ fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_CACHEABLE) #define bad_ram_resource(dev, idx, basek, sizek) \ - fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE | IORESOURCE_IGNORE_MTRR) + fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE | IORESOURCE_CACHEABLE ) #define uma_resource(dev, idx, basek, sizek) \ fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE | IORESOURCE_UMA_FB) #define mmio_resource(dev, idx, basek, sizek) \ - fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE | IORESOURCE_IGNORE_MTRR) + fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE) void tolm_test(void *gp, struct device *dev, struct resource *new); u32 find_pci_tolm(struct bus *bus); diff --git a/src/include/device/resource.h b/src/include/device/resource.h index c28ada5..e667f91 100644 --- a/src/include/device/resource.h +++ b/src/include/device/resource.h @@ -21,7 +21,6 @@ */ #define IORESOURCE_BRIDGE 0x00080000 /* The IO resource has a bus below it. */ #define IORESOURCE_UMA_FB 0x00100000 /* UMA framebuffer */ -#define IORESOURCE_IGNORE_MTRR 0x00200000 /* The resource does not affect MTRR setup. */ #define IORESOURCE_RESERVE 0x10000000 /* The resource needs to be reserved in the coreboot table */ #define IORESOURCE_STORED 0x20000000 /* The IO resource assignment has been stored in the device */ diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 0df85a7..bfb2166 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -63,6 +63,19 @@ static const int legacy_hole_size_k = 384; int add_northbridge_resources(struct lb_memory *mem) { + lb_add_memory_range(mem, LB_MEM_RESERVED, + legacy_hole_base_k * 1024, legacy_hole_size_k * 1024); + +#if CONFIG_CHROMEOS_RAMOOPS + lb_add_memory_range(mem, LB_MEM_RESERVED, + CONFIG_CHROMEOS_RAMOOPS_RAM_START, + CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE); +#endif + + /* Required for SandyBridge sighting 3715511 */ + lb_add_memory_range(mem, LB_MEM_RESERVED, 0x20000000, 0x00200000); + lb_add_memory_range(mem, LB_MEM_RESERVED, 0x40000000, 0x00200000); + return 0; } @@ -113,7 +126,7 @@ static void add_fixed_resources(struct device *dev, int index) printk(BIOS_DEBUG, "Adding UMA memory area base=0x%llx " "size=0x%llx\n", uma_memory_base, uma_memory_size); - resource = new_resource(dev, index++); + resource = new_resource(dev, index); resource->base = (resource_t) uma_memory_base; resource->size = (resource_t) uma_memory_size; resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | @@ -126,23 +139,12 @@ static void add_fixed_resources(struct device *dev, int index) if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " "size=0x%x\n", pcie_config_base, pcie_config_size); - resource = new_resource(dev, index++); + resource = new_resource(dev, index+1); resource->base = (resource_t) pcie_config_base; resource->size = (resource_t) pcie_config_size; resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } - - mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k); - -#if CONFIG_CHROMEOS_RAMOOPS - mmio_resource(dev, index++, CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, - CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); -#endif - - /* Required for SandyBridge sighting 3715511 */ - bad_ram_resource(dev, index++, 0x20000000 >> 10, 0x00200000 >> 10); - bad_ram_resource(dev, index++, 0x40000000 >> 10, 0x00200000 >> 10); } static void pci_domain_set_resources(device_t dev)

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Patch set updated for coreboot: 58ba41f Intel i82801gx, bd82x6x: Enable PCI-to-PCI bridge
by Paul Menzel 13 Mar '13

13 Mar '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2706 -gerrit commit 58ba41f99ebfaba5094e772256d4287d31ecc3a8 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Mar 13 11:12:56 2013 +0200 Intel i82801gx, bd82x6x: Enable PCI-to-PCI bridge Once the PCI command register is written the bridge forwards future IO and memory regions, as programmed in the respective base and limit registers, to the secondary PCI bus. Since the LPC function claims the resources for IOAPIC, ROM and low IO (0x0-0xfff) in its read_resources() call, the PCI-to-PCI configuration will not overlap those regions and does not hide the resources mentioned in the original comment. The bridge was disable in the following commit [1] commit a8e1168064b34b46494b58480411a11bc98340f6 Author: Stefan Reinauer <stepan(a)coresystems.de> Date: Wed Mar 11 14:54:18 2009 +0000 This patch contains some significant updates to the i82801gx component and will be required for a series of later patches. Roughly it contains: but unfortunately it was not noted which system this caused problems with. [1] http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=a8e1168064b34b4… Change-Id: I75128d83a344f4a0e09a3ea623c7f92a016ebfb9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/southbridge/intel/bd82x6x/pci.c | 9 --------- src/southbridge/intel/i82801gx/pci.c | 9 --------- 2 files changed, 18 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c index 306e7d5..0f5f3f6 100644 --- a/src/southbridge/intel/bd82x6x/pci.c +++ b/src/southbridge/intel/bd82x6x/pci.c @@ -63,7 +63,6 @@ static void pci_init(struct device *dev) pci_write_config16(dev, SECSTS, reg16); } -#undef PCI_BRIDGE_UPDATE_COMMAND static void ich_pci_dev_enable_resources(struct device *dev) { const struct pci_operations *ops; @@ -83,16 +82,8 @@ static void ich_pci_dev_enable_resources(struct device *dev) command = pci_read_config16(dev, PCI_COMMAND); command |= dev->command; -#ifdef PCI_BRIDGE_UPDATE_COMMAND - /* If we write to PCI_COMMAND, on some systems - * this will cause the ROM and APICs not being visible - * anymore. - */ printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command); pci_write_config16(dev, PCI_COMMAND, command); -#else - printk(BIOS_DEBUG, "%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command); -#endif } static void ich_pci_bus_enable_resources(struct device *dev) diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c index 0f372e7..5a21b21 100644 --- a/src/southbridge/intel/i82801gx/pci.c +++ b/src/southbridge/intel/i82801gx/pci.c @@ -62,7 +62,6 @@ static void pci_init(struct device *dev) pci_write_config16(dev, SECSTS, reg16); } -#undef PCI_BRIDGE_UPDATE_COMMAND static void ich_pci_dev_enable_resources(struct device *dev) { const struct pci_operations *ops; @@ -80,16 +79,8 @@ static void ich_pci_dev_enable_resources(struct device *dev) command = pci_read_config16(dev, PCI_COMMAND); command |= dev->command; -#ifdef PCI_BRIDGE_UPDATE_COMMAND - /* If we write to PCI_COMMAND, on some systems - * this will cause the ROM and APICs not being visible - * anymore. - */ printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command); pci_write_config16(dev, PCI_COMMAND, command); -#else - printk(BIOS_DEBUG, "%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command); -#endif } static void ich_pci_bus_enable_resources(struct device *dev)

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Patch merged into coreboot/master: 2def262 libpayload: Add more parenthesis to the endian conversion macros
by gerrit＠coreboot.org 13 Mar '13

13 Mar '13

the following patch was just integrated into master: commit 2def2625e0b49ea3ae85ae8b821979e5901c6638 Author: Gabe Black <gabeblack(a)google.com> Date: Thu Jan 31 04:27:39 2013 -0800 libpayload: Add more parenthesis to the endian conversion macros There weren't enough parenthesis in the macros so operations might only apply to the last part of an expression passed in as an argument. Change-Id: I5afb406f9409986e45bbbc598bcbd0dd8507ed35 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: http://review.coreboot.org/2665 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Build-Tested: build bot (Jenkins) at Tue Mar 12 22:20:48 2013, giving +1 See http://review.coreboot.org/2665 for details. -gerrit

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#190: Coreboot times out waiting waiting for P-State / Phenom XII 955
by coreboot 13 Mar '13

13 Mar '13

#190: Coreboot times out waiting waiting for P-State / Phenom XII 955 ---------------------------------------------+----------------------------- Reporter: "George Chriss' <gschriss@…> | Owner: stepan@… Type: defect | Status: new Priority: major | Milestone: Component: coreboot | Keywords: Dependencies: | Patch Status: there is no | patch ---------------------------------------------+----------------------------- Coreboot times out with the following on Gigabyte GA-MA785GMT-UD2H (rev. 1.1) + AMD Phenom XII 955 (HDZ955FBGIBOX) processor: {{{ F3xDC[PstateMaxVal] is zero. Northbridge voltage setting will fail. fixPsNbVidBeforeWR in fidvid.c needs fixing. See *** Time out waiting for P-state 1. Current P-state 0 P-state current limit MSRC001_0061=00 }}} The same Coreboot rom will boot with a AMD Athlon II X2 245 processor. Debug logs attached; it's an important fix and any patches welcome. -- Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/190> coreboot <http://www.coreboot.org/>

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#189: Coreboot times out waiting waiting for P-State / Phenom XII 955
by coreboot 13 Mar '13

13 Mar '13

#189: Coreboot times out waiting waiting for P-State / Phenom XII 955 ---------------------------------------------+----------------------------- Reporter: "George Chriss' <gschriss@…> | Owner: stepan@… Type: defect | Status: new Priority: major | Milestone: Component: coreboot | Keywords: Dependencies: | Patch Status: there is no | patch ---------------------------------------------+----------------------------- Coreboot times out with the following on Gigabyte GA-MA785GMT-UD2H (rev. 1.1) + AMD Phenom XII 955 (HDZ955FBGIBOX) processor: {{{ F3xDC[PstateMaxVal] is zero. Northbridge voltage setting will fail. fixPsNbVidBeforeWR in fidvid.c needs fixing. See *** Time out waiting for P-state 1. Current P-state 0 P-state current limit MSRC001_0061=00 }}} The same Coreboot rom will boot with a AMD Athlon II X2 245 processor. Debug logs attached; it's an important fix and any patches welcome. -- Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/189> coreboot <http://www.coreboot.org/>

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Patch merged into coreboot/master: b53a73e libpayload: Make the source for lzma decompression const
by gerrit＠coreboot.org 13 Mar '13

13 Mar '13

the following patch was just integrated into master: commit b53a73ef7726ccbaea73cb560b6f72cdb166eb50 Author: Gabe Black <gabeblack(a)google.com> Date: Mon Feb 11 20:43:45 2013 -0800 libpayload: Make the source for lzma decompression const Change-Id: I9a16331dedc97f17af94bf2cf535a9c93d1729a0 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: http://review.coreboot.org/2667 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Wed Mar 13 18:16:35 2013, giving +2 See http://review.coreboot.org/2667 for details. -gerrit

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Patch set updated for coreboot: fe487f6 Persimmon DSDT: Add OSC method
by Mike Loptien 13 Mar '13

13 Mar '13

Mike Loptien (mike.loptien(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2684 -gerrit commit fe487f638d781307de91c21178d96634407f669e Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Tue Mar 12 10:21:24 2013 -0600 Persimmon DSDT: Add OSC method The _OSC method is used to tell the OS what capabilities it can take control over from the firmware. This method is described in chapter 6.2.9 of the ACPI spec v3.0. The method takes 4 inputs (UUID, Rev ID, Input Count, and Capabilities Buffer) and returns a Capabilites Buffer the same size as the input Buffer. This Buffer is generally 3 Dwords long consisting of an Errors Dword, a Supported Capabilities Dword, and a Control Dword. The OS will request control of certain capabilities and the firmware must grant or deny control of those features. We do not want to have control over anything so let the OS control as much as it can. The _OSC method is required for PCIe devices and dmesg checks for its existence and issues an error if it is not found. Before this change, dmesg gave this message: pci0000:00: Requesting ACPI _OSC control (0x1d) pci0000:00: ACPI _OSC request failed (AE_NOT_FOUND), returned control mask: 0x1d ACPI _OSC control for PCIe not granted, disabling ASPM After this change, dmesg looks like this: pci0000:00: Requesting ACPI _OSC control (0x1d) pci0000:00: ACPI _OSC control (0x1d) granted Change-Id: I1494285def7440972f0549b7cb73eb94dafc72c2 Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com> --- src/mainboard/amd/persimmon/dsdt.asl | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/src/mainboard/amd/persimmon/dsdt.asl b/src/mainboard/amd/persimmon/dsdt.asl index 148d7b0..d29bbff 100644 --- a/src/mainboard/amd/persimmon/dsdt.asl +++ b/src/mainboard/amd/persimmon/dsdt.asl @@ -1157,8 +1157,20 @@ DefinitionBlock ( Device(PCI0) { External (TOM1) External (TOM2) - Name(_HID, EISAID("PNP0A03")) + Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ + Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + + /* Operating System Capabilities Method */ + Method(_OSC, 4) + { /* Check for proper PCI/PCIe UUID */ + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + { + /* Let OS control everything */ + Return (Arg3) + } + } + Method(_BBN, 0) { /* Bus number = 0 */ Return(0) }

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coreboot March 2013