coreboot March 2013

coreboot@coreboot.org

46 participants
782 discussions

Patch merged into coreboot/master: 00e5da6 libpayload: Don't do unaligned accesses during LZMA decompression
by gerrit＠coreboot.org 13 Mar '13

13 Mar '13

the following patch was just integrated into master: commit 00e5da6f25483f5d29aefadfff56a11dd0f3c97c Author: Gabe Black <gabeblack(a)google.com> Date: Wed Mar 6 04:46:00 2013 -0800 libpayload: Don't do unaligned accesses during LZMA decompression Use memcpy to access a uint32_t that's inherently unaligned due to the layout of the LZMA header format. Built and booted on Daisy and saw a data abort go away. Built and booted into developer mode on Link and verified that bitmaps were decompressed/displayed correctly. Change-Id: Id3ae746c04d23bcb0345cb71797bfa219479cc8f Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: http://review.coreboot.org/2670 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Mar 12 23:10:29 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed Mar 13 23:42:08 2013, giving +2 See http://review.coreboot.org/2670 for details. -gerrit

1 0

Patch merged into coreboot/master: 903f8e0 libpayload: Add size_t and ssize_t types for ARM and x86
by gerrit＠coreboot.org 13 Mar '13

13 Mar '13

the following patch was just integrated into master: commit 903f8e03307de8a689244eec5bf9aface73850b1 Author: Gabe Black <gabeblack(a)google.com> Date: Tue Feb 26 23:18:24 2013 -0800 libpayload: Add size_t and ssize_t types for ARM and x86 Some new TPM drivers in depthcharge require that type. I added it to arch/types.h which seemed appropriate, but I'm not sure that's exactly the right header to use, or in other words if you'd get that type from libpayload the same way you'd get it if you were building a standard Linux program. Also, I attempted to determine what underlying types gcc would use, and while I think I picked the right ones I'm not 100% certain of that either. Change-Id: Ic5c0b4173c8565ede3bfce8870976d596d69e51d Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: http://review.coreboot.org/2669 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Mar 12 23:00:23 2013, giving +1 Reviewed-By: Marc Jones <marc.jones(a)se-eng.com> at Wed Mar 13 06:25:20 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed Mar 13 23:41:39 2013, giving +2 See http://review.coreboot.org/2669 for details. -gerrit

1 0

Patch merged into coreboot/master: a0e2797 libpayload: Move over to the payload's stack during startup
by gerrit＠coreboot.org 13 Mar '13

13 Mar '13

the following patch was just integrated into master: commit a0e27979c06088912489633a67644254bc5a1f70 Author: Gabe Black <gabeblack(a)google.com> Date: Tue Feb 26 19:08:28 2013 -0800 libpayload: Move over to the payload's stack during startup Don't keep using the coreboot stack on ARMv7. Change-Id: I734c5d77f8584e30ee0c720d41e21e3040f56db4 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: http://review.coreboot.org/2668 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Mar 12 22:50:11 2013, giving +1 Reviewed-By: Marc Jones <marc.jones(a)se-eng.com> at Wed Mar 13 06:24:10 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed Mar 13 23:41:22 2013, giving +2 See http://review.coreboot.org/2668 for details. -gerrit

1 0

New patch to review for coreboot: cbad753 Eagleheights DSDT: Grant OS control through OSC
by Mike Loptien 13 Mar '13

13 Mar '13

Mike Loptien (mike.loptien(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2714 -gerrit commit cbad7533a804fe18ba3b19aa126374561531ece4 Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Wed Mar 13 16:28:16 2013 -0600 Eagleheights DSDT: Grant OS control through OSC Change the OSC method to actually grant control of PCIe capabilities to the OS instead of granting no control. I believe the logic was backwards in the original commit. Bits should be set when granting control and cleared when not granting control. By setting the return value to 0x00, we effectively tell the OS that it cannot control any PCIe capability. See section 6.2.9 of the ACPI spec version 3.0 for more information. This edit is a duplication of the OSC method that is in the src/southbridge/intel/bd82x6x/pch.asl file. Change-Id: Id2462ab12203afceb9033f24d06b4dfbf2236d2e Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com> --- 3rdparty | 2 +- src/mainboard/intel/eagleheights/dsdt.asl | 45 +++---------------------------- 2 files changed, 4 insertions(+), 43 deletions(-) diff --git a/3rdparty b/3rdparty index ba8caa3..dac1a18 160000 --- a/3rdparty +++ b/3rdparty @@ -1 +1 @@ -Subproject commit ba8caa30bd5ed6d89dbfd40e17c75c94d43804c6 +Subproject commit dac1a18d184976e4447b98479f0b7a172054b98f diff --git a/src/mainboard/intel/eagleheights/dsdt.asl b/src/mainboard/intel/eagleheights/dsdt.asl index 507d250..cb9ec8e 100644 --- a/src/mainboard/intel/eagleheights/dsdt.asl +++ b/src/mainboard/intel/eagleheights/dsdt.asl @@ -179,50 +179,11 @@ DefinitionBlock ("DSDT", "DSDT", 1, "EAGLE", "COREBOOT", 0x0000001) Method (_OSC, 4) { /* Check for proper GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) - { - /* Create DWORD-adressable field from the Capabilities Buffer */ - CreateDWordField (Arg3, 0, CDW1) - CreateDWordField (Arg3, 4, CDW2) - CreateDWordField (Arg3, 8, CDW3) - - /* Save Capabilities DWord 2 & 3 */ - Store (CDW2, SUPP) - Store (CDW3, CTRL) - - /* Don't care of OS capabilites */ - /* We support nothing (maybe we should add PCIe Capability Structure Control) */ - And (CTRL, 0x00, CTRL) - - /* Query flag clear ? */ - If (Not (And (CDW1, 1))) + If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { - /* Nothing to do */ + /* Let OS control everything */ + Return (Arg3) } - - /* Unknown revision ? */ - If (LNotEqual (Arg1, One)) - { - Or (CDW1, 0x08, CDW1) - } - - /* Capabilities bits masked ? */ - If (LNotEqual (CDW3, CTRL)) - { - Or (CDW1, 0x10, CDW1) - } - - /* Update DWORD3 in the buffer */ - Store (CTRL, CDW3) - - Return (Arg3) - } - Else - { - /* Unrecognized UUID */ - Or (CDW1, 4, CDW1) - Return (Arg3) - } } /* End _OSC */ Method (_PRT, 0, NotSerialized)

1 0

Patch merged into coreboot/master: 0274919 exynos5250/snow: enable branch prediction
by gerrit＠coreboot.org 13 Mar '13

13 Mar '13

the following patch was just integrated into master: commit 0274919bf6853b7a437025a8abf6624b824b3d91 Author: David Hendricks <dhendrix(a)chromium.org> Date: Tue Mar 12 22:00:43 2013 -0700 exynos5250/snow: enable branch prediction This enables branch prediction. We can probably find a better place to do this, but for now we'll do it in snow's romstage main(). Change-Id: I86c7b6bc9e897a7a432c490fb96a126e81b8ce72 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2701 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Mar 13 06:39:14 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed Mar 13 23:17:07 2013, giving +2 See http://review.coreboot.org/2701 for details. -gerrit

1 0

Patch set updated for coreboot: ac6652c exynos5250: add RAM resource beginning at physical address
by Ronald G. Minnich 13 Mar '13

13 Mar '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2698 -gerrit commit ac6652c6ac73574e1f946059171743c1a77f88e3 Author: David Hendricks <dhendrix(a)chromium.org> Date: Tue Mar 12 20:16:44 2013 -0700 exynos5250: add RAM resource beginning at physical address The original code attempted to reserve a space in RAM for coreboot to remain resident. This turns out not to be needed, and breaks things for the kernel since the exynos5250-smdk5250 kernel device tree starts RAM at 0x40000000. (This patch was originally by Gabe, I'm just uploading it) Change-Id: I4536edaf8785d81a3ea008216a2d57549ce5edfb Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/cpu/samsung/exynos5250/cpu.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index 0a49e1e..3b0ae58 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -1,9 +1,8 @@ #include <console/console.h> #include <device/device.h> -#define RAM_BASE ((CONFIG_SYS_SDRAM_BASE >> 10) + (CONFIG_COREBOOT_ROMSIZE_KB)) -#define RAM_SIZE (((CONFIG_DRAM_SIZE_MB << 10UL) * CONFIG_NR_DRAM_BANKS) \ - - CONFIG_COREBOOT_ROMSIZE_KB) +#define RAM_BASE (CONFIG_SYS_SDRAM_BASE >> 10) +#define RAM_SIZE (CONFIG_DRAM_SIZE_MB << 10UL) static void domain_read_resources(device_t dev) {

1 0

Patch merged into coreboot/master: 49ff3c5 libpayload: ARCH-$(CONFIG_ARCH_ARMV7) was defined twice, make one POWERPC
by gerrit＠coreboot.org 13 Mar '13

13 Mar '13

the following patch was just integrated into master: commit 49ff3c50dd7c4aca145f274a3346f36a2233c7d2 Author: Gabe Black <gabeblack(a)google.com> Date: Wed Jan 16 03:18:02 2013 -0800 libpayload: ARCH-$(CONFIG_ARCH_ARMV7) was defined twice, make one POWERPC Change-Id: Ia85a7cd6a0b85119cce6b2f9c42a7fc31ffd9f97 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: http://review.coreboot.org/2654 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Mar 12 04:29:48 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed Mar 13 23:09:30 2013, giving +2 See http://review.coreboot.org/2654 for details. -gerrit

1 0

Patch merged into coreboot/master: dc9e77f libpayload: Add usb_generic_(create|remove) functions for unrecognized devices
by gerrit＠coreboot.org 13 Mar '13

13 Mar '13

the following patch was just integrated into master: commit dc9e77f45135452166cdd9fb96c2234753febed6 Author: Gabe Black <gabeblack(a)google.com> Date: Fri Feb 1 20:19:27 2013 -0800 libpayload: Add usb_generic_(create|remove) functions for unrecognized devices It might be useful to provide a USB driver in the payload itself instead of in libpayload. For example there are multiple payloads being built and linked against the same libpayload, and they might not need or even want to have the same set of drivers installed. This change adds two new functions, usb_generic_create and usb_generic_remove, which behave like the usbdisk_create and usbdisk_remove functions which are defined for USB mass storage devices. If a USB device isn't recognized and claimed by one of the built in USB class drivers (currently hub, hid, and msc) and the create function is defined, then it will be called to give the payload a chance to use the device. Once it's removed, if usb_generic_remove is defined it will be called, effectively giving the payload notice. Built and booted depthcharge on Link. Built depthcharge for Daisy. Built a netbooting payload, called usb_poll() with those functions implemented, and verified that they were called and that the devices they were told about were reasonable and the same as what was reported by lsusb in the booted system. Change-Id: Ief7c0a513b60849fbf2986ef4ae5c9e7825fef16 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: http://review.coreboot.org/2666 Tested-by: build bot (Jenkins) Reviewed-by: Kimarie Hoot <kimarie.hoot(a)se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Mar 12 22:30:35 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed Mar 13 23:08:58 2013, giving +2 See http://review.coreboot.org/2666 for details. -gerrit

1 0

Patch merged into coreboot/master: 69eea7c libpayload: Split EHCI bulk transfers on packet boundaries over qTDs
by gerrit＠coreboot.org 13 Mar '13

13 Mar '13

the following patch was just integrated into master: commit 69eea7c01af0ce095aa7618eadae72e86f6eebbe Author: Julius Werner <jwerner(a)chromium.org> Date: Fri Jan 11 16:25:52 2013 -0800 libpayload: Split EHCI bulk transfers on packet boundaries over qTDs EHCI controllers see transfers as a queue of transfer descriptors (qTDs), each of which can represent an aligned area of up to 20KB. Each qTD is processed separately, which means that a single USB packet cannot span multiple qTDs. While this should not be a problem according to the specification, some USB storage devices seem to get confused when a packet in the middle of a transfer is smaller than the maximum packet size (512 bytes) due to falling on a qTD boundary. This patch aligns the total transfer length per qTD to 512 bytes to avoid that problem (any excess bytes will simply roll over to the next qTD). Change-Id: I0b5db07507699a3861b30c1a5ee774c45dda7fdd Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: http://review.coreboot.org/2651 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Tue Mar 12 10:20:11 2013, giving +1 Build-Tested: build bot (Jenkins) at Tue Mar 12 03:59:50 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed Mar 13 23:08:10 2013, giving +2 See http://review.coreboot.org/2651 for details. -gerrit

1 0

Patch merged into coreboot/master: 716375d libpayload: add support for 64-bit EHCI controllers
by gerrit＠coreboot.org 13 Mar '13

13 Mar '13

the following patch was just integrated into master: commit 716375dd3ee8ec695c38b2ab25e714a0cc116fb0 Author: Vincent Palatin <vpalatin(a)chromium.org> Date: Thu Oct 25 17:38:43 2012 -0700 libpayload: add support for 64-bit EHCI controllers Initialize the high part of the address and use 64-bit compatible descriptors. (waste a few bytes on 32-bit but should be harmless) Read USB stick on a SandyBridge system which has 64-bit EHCI. Change-Id: I59cc842459acecdde8f8bdd4795ebfeccb842c8f Signed-off-by: Vincent Palatin <vpalatin(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: http://review.coreboot.org/2650 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Kimarie Hoot <kimarie.hoot(a)se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Tue Mar 12 10:21:01 2013, giving +1 Build-Tested: build bot (Jenkins) at Tue Mar 12 03:49:21 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed Mar 13 23:07:48 2013, giving +2 See http://review.coreboot.org/2650 for details. -gerrit

1 0

← Newer
1
...
40
41
42
43
44
45
46
...
79
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot March 2013