coreboot March 2013

coreboot@coreboot.org

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Patch merged into coreboot/master: 613c0f6 libpayload: Stub out time keeping functions for ARM as well
by gerrit＠coreboot.org 13 Mar '13

13 Mar '13

the following patch was just integrated into master: commit 613c0f630a5fdcb0837d36b8a9104007f0ee7137 Author: Gabe Black <gabeblack(a)google.com> Date: Fri Jan 18 15:04:07 2013 -0800 libpayload: Stub out time keeping functions for ARM as well These were currently stubbed out for PowerPC but not for ARM. Change-Id: I08f45174877bf5751d972078b8c53d82898b7f2b Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: http://review.coreboot.org/2655 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Mar 12 04:39:58 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed Mar 13 23:06:26 2013, giving +2 See http://review.coreboot.org/2655 for details. -gerrit

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Patch merged into coreboot/master: 1617e1f libpayload: If no video drivers initialize in video_init, return 1.
by gerrit＠coreboot.org 13 Mar '13

13 Mar '13

the following patch was just integrated into master: commit 1617e1f0ab0d8e280e60caee693606ad88c37a86 Author: Gabe Black <gabeblack(a)google.com> Date: Tue Jan 15 15:48:55 2013 -0800 libpayload: If no video drivers initialize in video_init, return 1. Change-Id: I56f810dfa6654ac1e9d1696ad15e7f1b8bfe59bd Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: http://review.coreboot.org/2652 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Tue Mar 12 11:20:50 2013, giving +1 Build-Tested: build bot (Jenkins) at Tue Mar 12 04:10:06 2013, giving +1 See http://review.coreboot.org/2652 for details. -gerrit

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Patch merged into coreboot/master: b7b57d9 libpayload: If there's no IO address space, don't try to use it for serial
by gerrit＠coreboot.org 13 Mar '13

13 Mar '13

the following patch was just integrated into master: commit b7b57d97512f1a5fc9a102ae0374ff08242b6e0c Author: Gabe Black <gabeblack(a)google.com> Date: Fri Jan 18 18:37:29 2013 -0800 libpayload: If there's no IO address space, don't try to use it for serial Change-Id: I01b1fa42139af925716cd5d57f96dc24da6df5a7 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: http://review.coreboot.org/2660 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Mar 12 05:29:49 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed Mar 13 23:03:21 2013, giving +2 See http://review.coreboot.org/2660 for details. -gerrit

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Patch merged into coreboot/master: d8d4d11 libpayload: If there's no IO space, complain if the serial claims to use it
by gerrit＠coreboot.org 13 Mar '13

13 Mar '13

the following patch was just integrated into master: commit d8d4d113f005c28f3b8d9cc2c6b57627bdf35de1 Author: Gabe Black <gabeblack(a)google.com> Date: Fri Jan 18 18:24:46 2013 -0800 libpayload: If there's no IO space, complain if the serial claims to use it Change-Id: I36c750d520ff034c9ca9b9af46bd99bd49af7355 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: http://review.coreboot.org/2659 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Mar 12 05:20:07 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed Mar 13 23:02:52 2013, giving +2 See http://review.coreboot.org/2659 for details. -gerrit

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Patch merged into coreboot/master: 1c11712 libpayload: Consolidate io vs. mem mapped serial into accessor functions
by gerrit＠coreboot.org 13 Mar '13

13 Mar '13

the following patch was just integrated into master: commit 1c1171208ff9978ec45d01ade8a0836c3f93b59f Author: Gabe Black <gabeblack(a)google.com> Date: Fri Jan 18 18:04:44 2013 -0800 libpayload: Consolidate io vs. mem mapped serial into accessor functions This way we won't have two copies of the hardware init function, and three copies of the putchar, havechar, and getchar functions. Change-Id: Ifda7fec5d582244b0e163ee93ffeedeb28ce48da Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: http://review.coreboot.org/2657 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Mar 12 05:00:02 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed Mar 13 23:04:28 2013, giving +2 See http://review.coreboot.org/2657 for details. -gerrit

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Patch merged into coreboot/master: d267987 libpayload: Make whether or not there's an IO address space configurable
by gerrit＠coreboot.org 13 Mar '13

13 Mar '13

the following patch was just integrated into master: commit d267987083f84253c98d0bbfd1e46cec56aa1dcd Author: Gabe Black <gabeblack(a)google.com> Date: Fri Jan 18 15:49:00 2013 -0800 libpayload: Make whether or not there's an IO address space configurable Default it to no to be consistent with the other architecture wide options (endianness), and turn it on explicitly for x86 and PowerPC. Change-Id: Idda26d580156bbbf08ea11b28abe75cfa6b594b2 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: http://review.coreboot.org/2658 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Mar 12 05:10:04 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed Mar 13 23:02:04 2013, giving +2 See http://review.coreboot.org/2658 for details. -gerrit

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Patch merged into coreboot/master: ffc13bd Update 3rdparty mark to latest repository
by gerrit＠coreboot.org 13 Mar '13

13 Mar '13

the following patch was just integrated into master: commit ffc13bdb2a314046cf86489df88ed28c596f0c4f Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Mar 11 14:50:30 2013 -0700 Update 3rdparty mark to latest repository For google/stout binaries Change-Id: I4ef3f9cc35dfb6d27e1c9f074759f0e3ddee73c4 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/2635 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Mar 13 01:54:46 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed Mar 13 23:00:49 2013, giving +2 See http://review.coreboot.org/2635 for details. -gerrit

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Re: [coreboot] Could some one please give me parameters for QEMU for running Coreboot with Linux payload
by ron minnich 13 Mar '13

13 Mar '13

This is a qemu problem. Look at the end. It's trying to pxe boot. You need to make it not do that. ron On Tue, Mar 12, 2013 at 8:32 AM, Pankaj Chhabra <chhabra.pankaj(a)gmail.com> wrote: > Hello, > > I have tested with coreboot and seabios with ROM size of 4M and it works > fine. > > I am now running Qemu on Ubuntu 12.04 - > > Here is the coreboot+ Linux payload where the bios.bin points to > coreboot.rom, I see the following on the terminal > > please check the log below and let me know if I am making any mistake - > > > pankaj@ubuntu:/usr/share/qemu$ sudo qemu-system-i386 -serial stdio > > Could not access KVM kernel module: No such file or directory > failed to initialize KVM: No such file or directory > Back to tcg accelerator. > POST: 0x05 > > > coreboot-4.0-3625-g5021209 Tue Mar 12 08:28:42 PDT 2013 starting... > Re-Initializing CBMEM area to 0x17ee0000 > Initializing CBMEM area to 0x17ee0000 (1179648 bytes) > Loading image. > CBFS: CBFS_HEADER_ROM_ADDRESS: 0xfffffc90/0x400000 > CBFS: CBFS location: 0x0~0x3ffcb0, align: 64 > CBFS: Looking for 'fallback/coreboot_ram' starting from 0x0. > CBFS: - load entry 0x0 file name (16 bytes)... > CBFS: (unmatched file @0x0: cmos_layout.bin) > CBFS: - load entry 0x4c0 file name (32 bytes)... > CBFS: (unmatched file @0x4c0: fallback/romstage) > CBFS: - load entry 0x5000 file name (32 bytes)... > CBFS: Found file (offset=0x5038, len=42816). > CBFS: loading stage fallback/coreboot_ram @ 0x100000 (139264 bytes), entry @ > 0x100000 > CBFS: stage loaded. > Jumping to image. > POST: 0x80 > POST: 0x39 > coreboot-4.0-3625-g5021209 Tue Mar 12 08:28:42 PDT 2013 booting... > POST: 0x40 > Enumerating buses... > Show all devs...Before device enumeration. > Root Device: enabled 1 > DOMAIN: 0000: enabled 1 > PCI: 00:00.0: enabled 1 > PCI: 00:01.0: enabled 1 > PCI: 00:01.1: enabled 1 > Compare with tree... > Root Device: enabled 1 > DOMAIN: 0000: enabled 1 > PCI: 00:00.0: enabled 1 > PCI: 00:01.0: enabled 1 > PCI: 00:01.1: enabled 1 > scan_static_bus for Root Device > DOMAIN: 0000 enabled > DOMAIN: 0000 scanning... > PCI: pci_scan_bus for bus 00 > POST: 0x24 > PCI: 00:00.0 [8086/1237] ops > PCI: 00:00.0 [8086/1237] enabled > PCI: 00:01.0 [8086/7000] bus ops > PCI: 00:01.0 [8086/7000] enabled > PCI: 00:01.1 [8086/7010] ops > PCI: 00:01.1 [8086/7010] enabled > memalign Enter, boundary 8, size 152, free_mem_ptr 0011e000 > memalign 0011e000 > PCI: 00:01.3 [8086/7113] bus ops > pwrmgt_enable: gpo default missing in devicetree.cb! > Wakeup from ACPI sleep type S5 (PMCNTRL=0000) > PCI: 00:01.3 [8086/7113] enabled > memalign Enter, boundary 8, size 152, free_mem_ptr 0011e098 > memalign 0011e098 > PCI: 00:02.0 [1013/00b8] ops > PCI: 00:02.0 [1013/00b8] enabled > memalign Enter, boundary 8, size 152, free_mem_ptr 0011e130 > memalign 0011e130 > PCI: 00:03.0 [10ec/8139] enabled > POST: 0x25 > scan_static_bus for PCI: 00:01.0 > scan_static_bus for PCI: 00:01.0 done > scan_static_bus for PCI: 00:01.3 > scan_static_bus for PCI: 00:01.3 done > PCI: pci_scan_bus returning with max=000 > POST: 0x55 > scan_static_bus for Root Device done > done > POST: 0x66 > found VGA at PCI: 00:02.0 > Setting up VGA for PCI: 00:02.0 > Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 > Setting PCI_BRIDGE_CTL_VGA for bridge Root Device > Allocating resources... > Reading resources... > Root Device read_resources bus 0 link: 0 > memalign Enter, boundary 8, size 2560, free_mem_ptr 0011e1c8 > memalign 0011e1c8 > DOMAIN: 0000 read_resources bus 0 link: 0 > DOMAIN: 0000 read_resources bus 0 link: 0 done > Root Device read_resources bus 0 link: 0 done > Done reading resources. > Show resources in subtree (Root Device)...After reading. > Root Device child on link 0 DOMAIN: 0000 > DOMAIN: 0000 child on link 0 PCI: 00:00.0 > DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags > 40040100 index 10000000 > DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags > 40040200 index 10000100 > DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0 limit > ffffffff flags e0000200 index 2 > DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit > ffffffff flags e0000200 index 3 > PCI: 00:00.0 > PCI: 00:01.0 > PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags > c0000100 index 1 > PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 > flags d0000200 index 2 > PCI: 00:01.1 > PCI: 00:01.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 > index 20 > PCI: 00:01.3 > PCI: 00:01.3 resource base e400 size 40 align 0 gran 0 limit ffff flags > d0000100 index 1 > PCI: 00:01.3 resource base f00 size 10 align 0 gran 0 limit ffff flags > d0000100 index 2 > PCI: 00:02.0 > PCI: 00:02.0 resource base 0 size 2000000 align 25 gran 25 limit ffffffff > flags 1200 index 10 > PCI: 00:02.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff > flags 200 index 14 > PCI: 00:02.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff > flags 2200 index 30 > PCI: 00:03.0 > PCI: 00:03.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 > index 10 > PCI: 00:03.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags > 200 index 14 > PCI: 00:03.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff > flags 2200 index 30 > DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: > ffff > PCI: 00:03.0 10 * [0x0 - 0xff] io > PCI: 00:01.1 20 * [0x400 - 0x40f] io > DOMAIN: 0000 compute_resources_io: base: 410 size: 410 align: 8 gran: 0 > limit: ffff done > DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: > ffffffff > PCI: 00:02.0 10 * [0x0 - 0x1ffffff] prefmem > PCI: 00:02.0 30 * [0x2000000 - 0x200ffff] mem > PCI: 00:03.0 30 * [0x2010000 - 0x201ffff] mem > PCI: 00:02.0 14 * [0x2020000 - 0x2020fff] mem > PCI: 00:03.0 14 * [0x2021000 - 0x20210ff] mem > DOMAIN: 0000 compute_resources_mem: base: 2021100 size: 2021100 align: 25 > gran: 0 limit: ffffffff done > avoid_fixed_resources: DOMAIN: 0000 > avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff > avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff > constrain_resources: DOMAIN: 0000 > constrain_resources: PCI: 00:00.0 > constrain_resources: PCI: 00:01.0 > constrain_resources: PCI: 00:01.1 > constrain_resources: PCI: 00:01.3 > constrain_resources: PCI: 00:02.0 > constrain_resources: PCI: 00:03.0 > avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff > lim->base 00001000 lim->limit 0000e3ff > avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff > lim->base 00000000 lim->limit febfffff > Setting resources... > DOMAIN: 0000 allocate_resources_io: base:1000 size:410 align:8 gran:0 > limit:e3ff > Assigned: PCI: 00:03.0 10 * [0x1000 - 0x10ff] io > Assigned: PCI: 00:01.1 20 * [0x1400 - 0x140f] io > DOMAIN: 0000 allocate_resources_io: next_base: 1410 size: 410 align: 8 gran: > 0 done > DOMAIN: 0000 allocate_resources_mem: base:fc000000 size:2021100 align:25 > gran:0 limit:febfffff > Assigned: PCI: 00:02.0 10 * [0xfc000000 - 0xfdffffff] prefmem > Assigned: PCI: 00:02.0 30 * [0xfe000000 - 0xfe00ffff] mem > Assigned: PCI: 00:03.0 30 * [0xfe010000 - 0xfe01ffff] mem > Assigned: PCI: 00:02.0 14 * [0xfe020000 - 0xfe020fff] mem > Assigned: PCI: 00:03.0 14 * [0xfe021000 - 0xfe0210ff] mem > DOMAIN: 0000 allocate_resources_mem: next_base: fe021100 size: 2021100 > align: 25 gran: 0 done > Root Device assign_resources, bus 0 link: 0 > Detected 393216 Kbytes (384 MiB) RAM. > DOMAIN: 0000 assign_resources, bus 0 link: 0 > PCI: 00:01.1 20 <- [0x0000001400 - 0x000000140f] size 0x00000010 gran 0x04 > io > PCI: 00:02.0 10 <- [0x00fc000000 - 0x00fdffffff] size 0x02000000 gran 0x19 > prefmem > PCI: 00:02.0 14 <- [0x00fe020000 - 0x00fe020fff] size 0x00001000 gran 0x0c > mem > PCI: 00:02.0 30 <- [0x00fe000000 - 0x00fe00ffff] size 0x00010000 gran 0x10 > romem > PCI: 00:03.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 > io > PCI: 00:03.0 14 <- [0x00fe021000 - 0x00fe0210ff] size 0x00000100 gran 0x08 > mem > PCI: 00:03.0 30 <- [0x00fe010000 - 0x00fe01ffff] size 0x00010000 gran 0x10 > romem > DOMAIN: 0000 assign_resources, bus 0 link: 0 > Root Device assign_resources, bus 0 link: 0 > Done setting resources. > Show resources in subtree (Root Device)...After assigning values. > Root Device child on link 0 DOMAIN: 0000 > DOMAIN: 0000 child on link 0 PCI: 00:00.0 > DOMAIN: 0000 resource base 1000 size 410 align 8 gran 0 limit e3ff flags > 40040100 index 10000000 > DOMAIN: 0000 resource base fc000000 size 2021100 align 25 gran 0 limit > febfffff flags 40040200 index 10000100 > DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0 limit > ffffffff flags e0000200 index 2 > DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit > ffffffff flags e0000200 index 3 > DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags > e0004200 index a > DOMAIN: 0000 resource base c0000 size 17f40000 align 0 gran 0 limit 0 > flags e0004200 index b > PCI: 00:00.0 > PCI: 00:01.0 > PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags > c0000100 index 1 > PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 > flags d0000200 index 2 > PCI: 00:01.1 > PCI: 00:01.1 resource base 1400 size 10 align 4 gran 4 limit e3ff flags > 60000100 index 20 > PCI: 00:01.3 > PCI: 00:01.3 resource base e400 size 40 align 0 gran 0 limit ffff flags > d0000100 index 1 > PCI: 00:01.3 resource base f00 size 10 align 0 gran 0 limit ffff flags > d0000100 index 2 > PCI: 00:02.0 > PCI: 00:02.0 resource base fc000000 size 2000000 align 25 gran 25 limit > febfffff flags 60001200 index 10 > PCI: 00:02.0 resource base fe020000 size 1000 align 12 gran 12 limit > febfffff flags 60000200 index 14 > PCI: 00:02.0 resource base fe000000 size 10000 align 16 gran 16 limit > febfffff flags 60002200 index 30 > PCI: 00:03.0 > PCI: 00:03.0 resource base 1000 size 100 align 8 gran 8 limit e3ff flags > 60000100 index 10 > PCI: 00:03.0 resource base fe021000 size 100 align 8 gran 8 limit > febfffff flags 60000200 index 14 > PCI: 00:03.0 resource base fe010000 size 10000 align 16 gran 16 limit > febfffff flags 60002200 index 30 > Done allocating resources. > POST: 0x88 > Enabling resources... > PCI: 00:00.0 cmd <- 00 > PCI: 00:01.0 cmd <- 00 > PCI: 00:01.1 cmd <- 01 > PCI: 00:01.3 cmd <- 00 > PCI: 00:02.0 cmd <- 03 > PCI: 00:03.0 cmd <- 03 > done. > POST: 0x89 > Initializing devices... > Root Device init > PCI: 00:00.0 init > Keyboard init... > Setting up ethernet... > Assigning IRQ 11 to 0:3.0 > i8259_configure_irq_trigger: current interrupts are 0x0 > i8259_configure_irq_trigger: try to set interrupts 0x800 > PCI: 00:01.0 init > RTC Init > PCI: 00:01.1 init > IDE: Primary IDE interface: on > IDE: Secondary IDE interface: on > IDE: Access to legacy IDE ports: off > PCI: 00:02.0 init > CBFS: CBFS_HEADER_ROM_ADDRESS: 0xfffffc90/0x400000 > CBFS: CBFS location: 0x0~0x3ffcb0, align: 64 > CBFS: Looking for 'pci1013,00b8.rom' starting from 0x0. > CBFS: - load entry 0x0 file name (16 bytes)... > CBFS: (unmatched file @0x0: cmos_layout.bin) > CBFS: - load entry 0x4c0 file name (32 bytes)... > CBFS: (unmatched file @0x4c0: fallback/romstage) > CBFS: - load entry 0x5000 file name (32 bytes)... > CBFS: (unmatched file @0x5000: fallback/coreboot_ram) > CBFS: - load entry 0xf780 file name (32 bytes)... > CBFS: (unmatched file @0xf780: fallback/payload) > CBFS: - load entry 0x147980 file name (16 bytes)... > CBFS: (unmatched file @0x147980: config) > CBFS: - load entry 0x148500 file name (16 bytes)... > CBFS: (unmatched file @0x148500: ) > CBFS: ERROR: No file header found at 0x3ffc80 - try next aligned address: > 0x3ffcc0. > CBFS: ERROR: Not found. > CBFS: Could not find file 'pci1013,00b8.rom'. > Option ROM address for PCI: 00:02.0 = fe000000 > PCI expansion ROM, signature 0xaa55, INIT size 0x8c00, data ptr 0x010f > PCI ROM image, vendor ID 1013, device ID 00b8, > PCI ROM image, Class Code 030000, Code Type 00 > Copying VGA ROM Image from fe000000 to 0xc0000, 0x8c00 bytes > Real mode stub @00000600: 867 bytes > Calling Option ROM... > ... Option ROM returned. > PCI: 00:03.0 init > CBFS: CBFS_HEADER_ROM_ADDRESS: 0xfffffc90/0x400000 > CBFS: CBFS location: 0x0~0x3ffcb0, align: 64 > CBFS: Looking for 'pci10ec,8139.rom' starting from 0x0. > CBFS: - load entry 0x0 file name (16 bytes)... > CBFS: (unmatched file @0x0: cmos_layout.bin) > CBFS: - load entry 0x4c0 file name (32 bytes)... > CBFS: (unmatched file @0x4c0: fallback/romstage) > CBFS: - load entry 0x5000 file name (32 bytes)... > CBFS: (unmatched file @0x5000: fallback/coreboot_ram) > CBFS: - load entry 0xf780 file name (32 bytes)... > CBFS: (unmatched file @0xf780: fallback/payload) > CBFS: - load entry 0x147980 file name (16 bytes)... > CBFS: (unmatched file @0x147980: config) > CBFS: - load entry 0x148500 file name (16 bytes)... > CBFS: (unmatched file @0x148500: ) > CBFS: ERROR: No file header found at 0x3ffc80 - try next aligned address: > 0x3ffcc0. > CBFS: ERROR: Not found. > CBFS: Could not find file 'pci10ec,8139.rom'. > Option ROM address for PCI: 00:03.0 = fe010000 > PCI expansion ROM, signature 0xaa55, INIT size 0xfc00, data ptr 0x0020 > PCI ROM image, vendor ID 10ec, device ID 8139, > PCI ROM image, Class Code 000002, Code Type 00 > Class Code mismatch ROM 00000002, dev 00020000 > Copying non-VGA ROM image from fe010000 to 000d0000, 0xfc00 bytes > Real mode stub @00000600: 867 bytes > Calling Option ROM... > > > iPXE (http://ipxe.org) 00:03.0 D000 D000 > Press Ctrl-B to configure iPXE (PCI 00:03.0)... > > > > Thanks, > Pankaj > > On Tue, Mar 12, 2013 at 7:53 PM, ron minnich <rminnich(a)gmail.com> wrote: >> >> have you tested with coreboot&seabios and a rom size of 4M? >> >> ron > >

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New patch to review for coreboot: 61ca4af cbfstool: drop unused variable
by Stefan Reinauer 13 Mar '13

13 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2713 -gerrit commit 61ca4af8d47ab2e56f8908f53279eb6470acd266 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Mar 13 14:15:24 2013 -0700 cbfstool: drop unused variable This broke the build when manually compiling cbfstool in util/cbfstool. Change-Id: I57afc74f8c2723d9dc749707f8bcb6cfff477769 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- util/cbfstool/common.c | 1 - 1 file changed, 1 deletion(-) diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c index 0517d9a..11dd45b 100644 --- a/util/cbfstool/common.c +++ b/util/cbfstool/common.c @@ -881,7 +881,6 @@ struct cbfs_file *cbfs_find_file(const char *name) } struct cbfs_file *thisfile = (struct cbfs_file *)phys_to_virt(current); - uint32_t length = ntohl(thisfile->len); char *fname = (char *)(phys_to_virt(current) + sizeof(struct cbfs_file)); if (!strcmp(fname, name)) return thisfile;

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New patch to review for coreboot: 801c603 cbfstool: Add update-fit command
by Stefan Reinauer 13 Mar '13

13 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2712 -gerrit commit 801c603d6c2496b5feed6c6a1b266a7bd502e376 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Dec 14 17:16:21 2012 -0600 cbfstool: Add update-fit command This commit adds support for filling in the Firmware Interface Table. For now it only supports adding microcode entries. It takes 2 options: 1. Name of file in cbfs where the mircocode is located 2. The number of empty entries in the table. Verified with go firmware tools. Also commented out updating mircoode in the bootblock. When romstage runs, the CPUs indicate their microcode is already loaded. Change-Id: Iaccaa9c226ee24868a5f4c0ba79729015d15bbef Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- util/cbfstool/Makefile | 2 +- util/cbfstool/Makefile.inc | 1 + util/cbfstool/cbfstool.c | 40 +++++++ util/cbfstool/fit.c | 282 +++++++++++++++++++++++++++++++++++++++++++++ util/cbfstool/fit.h | 25 ++++ 5 files changed, 349 insertions(+), 1 deletion(-) diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile index a14a76f..a51e6de 100644 --- a/util/cbfstool/Makefile +++ b/util/cbfstool/Makefile @@ -7,7 +7,7 @@ CFLAGS += -D_7ZIP_ST BINARY:=$(obj)/cbfstool -COMMON:=cbfstool.o common.o cbfs_image.o compress.o +COMMON:=cbfstool.o common.o cbfs_image.o compress.o fit.o COMMON+=cbfs-mkstage.o cbfs-mkpayload.o # LZMA COMMON+=lzma/lzma.o diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index 2cee794..e3eb798 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -5,6 +5,7 @@ cbfsobj += compress.o cbfsobj += cbfs_image.o cbfsobj += cbfs-mkstage.o cbfsobj += cbfs-mkpayload.o +cbfsobj += fit.o # LZMA cbfsobj += lzma.o cbfsobj += LzFind.o diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 97fd88d..4c6933a 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -28,6 +28,7 @@ #include "common.h" #include "cbfs.h" #include "cbfs_image.h" +#include "fit.h" struct command { const char *name; @@ -52,6 +53,7 @@ static struct param { uint32_t alignment; uint32_t offset; uint32_t top_aligned; + int fit_empty_entries; comp_algo algo; } param = { /* All variables not listed are initialized as zero. */ @@ -414,6 +416,37 @@ static int cbfs_extract(void) return result; } +static int cbfs_update_fit(void) +{ + void *rom; + int ret; + + if (!param.name) { + ERROR("You need to specify -n/--name.\n"); + return 1; + } + + if (param.fit_empty_entries <= 0) { + ERROR("Invalid number of fit entries " + "(-x/--empty-fits): %d\n", param.fit_empty_entries); + return 1; + } + + rom = loadrom(param.cbfs_name); + if (rom == NULL) { + ERROR("Could not load ROM image '%s'.\n", + param.cbfs_name); + return 1; + } + + ret = fit_update_table(rom, romsize, param.fit_empty_entries, param.name); + if (!ret) + ret = writerom(param.cbfs_name, rom, romsize); + + free(rom); + return 0; +} + static const struct command commands[] = { {"add", "f:n:t:b:vh?", cbfs_add}, {"add-payload", "f:n:t:c:b:vh?", cbfs_add_payload}, @@ -424,6 +457,7 @@ static const struct command commands[] = { {"locate", "f:n:a:Tvh?", cbfs_locate}, {"print", "vh?", cbfs_print}, {"extract", "n:f:vh?", cbfs_extract}, + {"update-fit", "n:x:vh?", cbfs_update_fit}, }; static struct option long_options[] = { @@ -440,6 +474,7 @@ static struct option long_options[] = { {"offset", required_argument, 0, 'o' }, {"file", required_argument, 0, 'f' }, {"arch", required_argument, 0, 'm' }, + {"empty-fits", required_argument, 0, 'x' }, {"verbose", no_argument, 0, 'v' }, {"help", no_argument, 0, 'h' }, {NULL, 0, 0, 0 } @@ -474,6 +509,8 @@ static void usage(char *name) "Show the contents of the ROM\n" " extract -n NAME -f FILE " "Extracts a raw payload from ROM\n" + " update-fit -n MICROCODE_BLOB_NAME -x EMTPY_FIT_ENTRIES\n " + "Updates the FIT table with mircodoe entries\n" "\n" "ARCHes:\n" " armv7, x86\n" @@ -581,6 +618,9 @@ int main(int argc, char **argv) case 'T': param.top_aligned = 1; break; + case 'x': + param.fit_empty_entries = strtol(optarg, NULL, 0); + break; case 'v': verbose++; break; diff --git a/util/cbfstool/fit.c b/util/cbfstool/fit.c new file mode 100644 index 0000000..4fce1a6 --- /dev/null +++ b/util/cbfstool/fit.c @@ -0,0 +1,282 @@ +/* + * Firmware Interface Table support. + * + * Copyright (C) 2012 ChromeOS Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#include <stdint.h> +#include <stdlib.h> +#include <string.h> +#include <stdio.h> + +#include "common.h" +#include "cbfs.h" +#include "fit.h" + +/* Warning: This code assumes it is being executed on a little endian machine.*/ + +#define FIT_POINTER_LOCATION 0xffffffc0 +#define FIT_TABLE_LOWEST_ADDRESS ((uint32_t)(-(16 << 20))) +#define FIT_ENTRY_CHECKSUM_VALID 0x80 +#define FIT_TYPE_HEADER 0x0 +#define FIT_HEADER_VERSION 0x0100 +#define FIT_HEADER_ADDRESS "_FIT_ " +#define FIT_TYPE_MICROCODE 0x1 +#define FIT_MICROCODE_VERSION 0x0100 + +struct fit_entry { + uint64_t address; + uint32_t size_reserved; + uint16_t version; + uint8_t type_checksum_valid; + uint8_t checksum; +} __attribute__ ((packed)); + +struct fit_table { + struct fit_entry header; + struct fit_entry entries[0]; +} __attribute__ ((packed)); + + +struct microcode_header { + uint32_t version; + uint32_t revision; + uint32_t date; + uint32_t processor_signature; + uint32_t checksum; + uint32_t loader_revision; + uint32_t processor_flags; + uint32_t data_size; + uint32_t total_size; + uint8_t reserved[12]; +} __attribute__ ((packed)); + +struct microcode_entry { + int offset; + int size; +}; + +struct rom_image { + char *rom; + uint32_t size; +}; + +static inline void *rom_buffer_pointer(struct rom_image *image, int offset) +{ + return &image->rom[offset]; +} + +static inline int fit_entry_size_bytes(struct fit_entry *entry) +{ + return (entry->size_reserved & 0xffffff) << 4; +} + +static inline void fit_entry_update_size(struct fit_entry *entry, + int size_bytes) +{ + /* Size is multiples of 16 bytes. */ + entry->size_reserved = (size_bytes >> 4) & 0xffffff; +} + +static inline void fit_entry_add_size(struct fit_entry *entry, + int size_bytes) +{ + int size = fit_entry_size_bytes(entry); + size += size_bytes; + fit_entry_update_size(entry, size); +} + +static inline int fit_entry_type(struct fit_entry *entry) +{ + return entry->type_checksum_valid & ~FIT_ENTRY_CHECKSUM_VALID; +} + +/* + * Get an offset from a host pointer. This function assumes the ROM is located + * in the host address space at [4G - romsize -> 4G). It also assume all + * pointers have values within this address range. + */ +static inline int ptr_to_offset(uint32_t romsize, uint32_t host_ptr) +{ + return (int)(romsize + host_ptr); +} + +/* + * Get a pointer from an offset. This function assumes the ROM is located + * in the host address space at [4G - romsize -> 4G). It also assume all + * pointers have values within this address range. + */ +static inline uint32_t offset_to_ptr(uint32_t romsize, int offset) +{ + return -(romsize - (uint32_t )offset); +} + +static struct fit_table *locate_fit_table(struct rom_image *image) +{ + struct fit_table *table; + uint32_t *fit_pointer; + + fit_pointer = rom_buffer_pointer(image, + ptr_to_offset(image->size, FIT_POINTER_LOCATION)); + + /* Ensure pointer is below 4GiB and within 16MiB of 4GiB */ + if (fit_pointer[1] != 0 || fit_pointer[0] < FIT_TABLE_LOWEST_ADDRESS) + return NULL; + + table = rom_buffer_pointer(image, + ptr_to_offset(image->size, *fit_pointer)); + + /* Check that the address field has the proper signature. */ + if (strncmp((const char *)&table->header.address, FIT_HEADER_ADDRESS, + sizeof(table->header.address))) + return NULL; + + if (table->header.version != FIT_HEADER_VERSION) + return NULL; + + if (fit_entry_type(&table->header) != FIT_TYPE_HEADER) + return NULL; + + /* Assume that the FIT table only contains the header */ + if (fit_entry_size_bytes(&table->header) != sizeof(struct fit_entry)) + return NULL; + + return table; +} + +static void update_fit_checksum(struct fit_table *fit) +{ + int size_bytes; + uint8_t *buffer; + uint8_t result; + int i; + + fit->header.checksum = 0; + size_bytes = fit_entry_size_bytes(&fit->header); + result = 0; + buffer = (void *)fit; + for (i = 0; i < size_bytes; i++) + result += buffer[i]; + fit->header.checksum = -result; +} + +static void add_microcodde_entries(struct rom_image *image, + struct fit_table *fit, + struct microcode_entry *mcus, int num_mcus) +{ + int i; + + for (i = 0; i < num_mcus; i++) { + struct fit_entry *entry = &fit->entries[i]; + struct microcode_entry *mcu = &mcus[i]; + + entry->address = offset_to_ptr(image->size, mcu->offset); + fit_entry_update_size(entry, mcu->size); + entry->version = FIT_MICROCODE_VERSION; + entry->type_checksum_valid = FIT_TYPE_MICROCODE; + entry->checksum = 0; + fit_entry_add_size(&fit->header, sizeof(struct fit_entry)); + } +} + +static int parse_microcode_blob(struct rom_image *image, + struct cbfs_file *mcode_file, + struct microcode_entry *mcus, int *total_mcus) +{ + int num_mcus; + int current_offset; + int file_length; + + current_offset = (int)((char *)mcode_file - image->rom); + current_offset += ntohl(mcode_file->offset); + file_length = ntohl(mcode_file->len); + + num_mcus = 0; + while (file_length > sizeof(struct microcode_header)) + { + struct microcode_header *mcu_header; + + mcu_header = rom_buffer_pointer(image, current_offset); + + /* FIXME: Should the chcksum be validated? */ + mcus[num_mcus].offset = current_offset; + mcus[num_mcus].size = mcu_header->total_size; + + /* Proceed to next payload. */ + current_offset += mcus[num_mcus].size; + num_mcus++; + file_length -= mcus[num_mcus].size; + + /* Can't determine any more entries. */ + if (!mcu_header->total_size) + break; + + /* Reached limit of FIT entries. */ + if (num_mcus == *total_mcus) + break; + if (file_length < sizeof(struct microcode_header)) + break; + } + + /* Update how many we found. */ + *total_mcus = num_mcus; + + return 0; +} + +int fit_update_table(void *rom, uint32_t romsize, int empty_entries, + const char *microcode_blob_name) +{ + struct fit_table *fit; + struct cbfs_file *mcode_file; + struct microcode_entry *mcus; + int ret = 0; + struct rom_image image = { .rom = rom, .size = romsize, }; + + fit = locate_fit_table(&image); + + if (!fit) { + fprintf(stderr, "FIT not found.\n"); + return 1; + } + + mcode_file = cbfs_find_file(microcode_blob_name); + if (!mcode_file) { + fprintf(stderr, "File '%s' not found in cbfs\n", + microcode_blob_name); + return 1; + } + + mcus = malloc(sizeof(*mcus) * empty_entries); + + if (!mcus) { + fprintf(stderr, "Couldn't allocate memory for MCU entries.\n"); + return 1; + } + + if (parse_microcode_blob(&image, mcode_file, mcus, &empty_entries)) { + fprintf(stderr, "Couldn't parse microcode blob.\n"); + ret = 1; + goto out; + } + + add_microcodde_entries(&image, fit, mcus, empty_entries); + update_fit_checksum(fit); + +out: + free(mcus); + return ret; +} diff --git a/util/cbfstool/fit.h b/util/cbfstool/fit.h new file mode 100644 index 0000000..03183fc --- /dev/null +++ b/util/cbfstool/fit.h @@ -0,0 +1,25 @@ +/* + * Firmware Interface Table support. + * + * Copyright (C) 2012 ChromeOS Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#ifndef __CBFSTOOL_FIT_H +#define __CBFSTOOL_FIT_H + +int fit_update_table(void *rom, uint32_t romsize, + int empty_entries, const char *microcode_blob_name); +#endif

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coreboot March 2013