coreboot March 2013

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Patch merged into coreboot/master: 4412bc4 OT200: reset MFGTP7 (backlight pwm)
by gerrit＠coreboot.org 14 Mar '13

14 Mar '13

the following patch was just integrated into master: commit 4412bc4ae8f8ab33a49cdd00098754ff7c333a01 Author: Christian Gmeiner <christian.gmeiner(a)gmail.com> Date: Tue Mar 12 11:07:07 2013 +0100 OT200: reset MFGTP7 (backlight pwm) The CS5536 companion device has three different power domains. * working domain * standby domain * RTC domain When the system is "off" only the standby domain is powered. MFGPT[7:6] are member of the standby power domain. MFGPT7 is used to control the backlight of the device and so the timer gets used and configured during system boot. If the system does a reboot the timer stays configured and the Linux driver can not use it: "ot200-backlight: ot200-backlight.0: MFGPT 7 not availale" The cs5535-mfgpt has a function to hard-reset all MFGPTs but the system hangs after the first access to a MFGPT register - cause unknown. /* * This is a sledgehammer that resets all MFGPT timers. This is required by * some broken BIOSes which leave the system in an unstable state * (TinyBIOS 0.98, for example; fixed in 0.99). It's uncertain as to * whether or not this secret MSR can be used to release individual timers. * Jordan tells me that he and Mitch once played w/ it, but it's unclear * what the results of that were (and they experienced some instability). */ static void reset_all_timers(void) { uint32_t val, dummy; /* The following undocumented bit resets the MFGPT timers */ val = 0xFF; dummy = 0; wrmsr(MSR_MFGPT_SETUP, val, dummy); } After playing around with this undocumented MSR it looks like I only need to set bit 7 to free the MFGPT7. BTW, all MFGPT[0:5] will be reset during pll_reset(). Change-Id: I54a8d479ce495b0fc2f54db766a8d793bbb5d704 Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> Reviewed-on: http://review.coreboot.org/2527 Tested-by: build bot (Jenkins) Reviewed-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Build-Tested: build bot (Jenkins) at Tue Mar 12 10:56:37 2013, giving +1 Reviewed-By: Marc Jones <marc.jones(a)se-eng.com> at Thu Mar 14 16:32:45 2013, giving +2 See http://review.coreboot.org/2527 for details. -gerrit

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Patch merged into coreboot/master: 138f2ce haswell: remove GPIO60 memory reset gate on S3 transition
by gerrit＠coreboot.org 14 Mar '13

14 Mar '13

the following patch was just integrated into master: commit 138f2cede491b65cfd8c73b9185a2dc7ee10b8b3 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Dec 12 09:22:34 2012 -0800 haswell: remove GPIO60 memory reset gate on S3 transition This is no longer tied to a GPIO but has a proper chipset pin. Change-Id: Iba70338e8c67e3c3c1cb32e69bfea1282fda8cb5 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/2643 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Mar 12 02:34:50 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Mar 14 06:36:21 2013, giving +2 See http://review.coreboot.org/2643 for details. -gerrit

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Patch merged into coreboot/master: 89f79a0 haswell: remove explicit pcie config accesses
by gerrit＠coreboot.org 14 Mar '13

14 Mar '13

the following patch was just integrated into master: commit 89f79a019fd049f26ed7bf40618ff960bd9e095e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Oct 31 23:05:25 2012 -0500 haswell: remove explicit pcie config accesses Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove the pcie explicit accesses. The default config accesses use MMIO. Change-Id: I8406cec16c1ee1bc205b657a0c90beb2252df061 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2618 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Mon Mar 11 23:33:43 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Mar 14 06:35:47 2013, giving +2 See http://review.coreboot.org/2618 for details. -gerrit

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Patch merged into coreboot/master: b9ea8b3 lynxpoint: PMIR register rename
by gerrit＠coreboot.org 14 Mar '13

14 Mar '13

the following patch was just integrated into master: commit b9ea8b3fb0082840b0c9d449535f4c49c2e885ac Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Nov 2 09:10:30 2012 -0500 lynxpoint: PMIR register rename The register that controls global reset is named the Power Mangement Initialization Regiser (PMIR). Update the defines to reflect the documentation. Additionally, there is no core well reset control according to the EDS. There is, however, a CF9 lock field to lock this register down. Change-Id: I773c33bec63a06cdb869eb9f94553d476e492798 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2619 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Mon Mar 11 23:23:09 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Mar 14 06:33:32 2013, giving +2 See http://review.coreboot.org/2619 for details. -gerrit

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Patch merged into coreboot/master: 9aa031e lynxpoint: Management Engine Updates
by gerrit＠coreboot.org 14 Mar '13

14 Mar '13

the following patch was just integrated into master: commit 9aa031e47157e37e8f3cd80cbc80215e2843eaa9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Nov 2 09:16:46 2012 -0500 lynxpoint: Management Engine Updates The ME9 requirements have added some registers and changed some of the MBP state machine. Implement the changes found so far in the ME9 BWG. There were a couple of reigster renames, but the majority of th churn in the me.h header file is just introducing the data structures in the same order as the ME9 BWG. Change-Id: I51b0bb6620eff4979674ea99992ddab65a8abc18 Signed-Off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2620 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Mon Mar 11 23:13:07 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Mar 14 06:26:41 2013, giving +2 See http://review.coreboot.org/2620 for details. -gerrit

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Patch merged into coreboot/master: dc278f8 haswell: Properly Guard Engergy Policy by CPUID
by gerrit＠coreboot.org 14 Mar '13

14 Mar '13

the following patch was just integrated into master: commit dc278f8fd0318caf0c11330478dff8453bb1107d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Dec 11 17:15:13 2012 -0600 haswell: Properly Guard Engergy Policy by CPUID The IA32_ENERGY_PERFORMANCE_BIAS MSR can only be read or written to if the CPU supports it. The support is indicated by ECX[3] for cpuid(6). Without this guard, some Haswell parts would GP# fault in this routine. No more GP# while running on haswell CRBs. Change-Id: If41e1e133e5faebb3ed578cba60743ce7e1c196f Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2639 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> Build-Tested: build bot (Jenkins) at Tue Mar 12 01:53:20 2013, giving +1 See http://review.coreboot.org/2639 for details. -gerrit

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Patch merged into coreboot/master: c1989c4 haswell: add PCI id support
by gerrit＠coreboot.org 14 Mar '13

14 Mar '13

the following patch was just integrated into master: commit c1989c494e2628618067d03d9e192ac25b4f42d1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Dec 11 17:13:17 2012 -0600 haswell: add PCI id support In order for coreboot to assign resources properly the pci drivers need to have th proper device ids. Add the host controller and the LPC device ids for Lynx Point. Resource assignment works correctly now w/o odd behavior because of conflicts. Change-Id: Id33b3676616fb0c428d84e5fe5c6b8a7cc5fbb62 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2638 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> Build-Tested: build bot (Jenkins) at Tue Mar 12 01:43:03 2013, giving +1 See http://review.coreboot.org/2638 for details. -gerrit

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Patch merged into coreboot/master: b6b5aa1 haswell: Remove logic to send dram init done to ME
by gerrit＠coreboot.org 14 Mar '13

14 Mar '13

the following patch was just integrated into master: commit b6b5aa15cecf2a9226bf5c265f15bf905c90e558 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Dec 7 09:50:40 2012 -0600 haswell: Remove logic to send dram init done to ME The reference code sends the dram init done command to the ME. Therefore, there is no need for coreboot to do this. Change-Id: I6837d6c50bbb7db991f9d21fc9cdba76252c1b7b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2633 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Mar 12 00:45:15 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Mar 14 05:10:00 2013, giving +2 See http://review.coreboot.org/2633 for details. -gerrit

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Patch merged into coreboot/master: 68724fd basking ridge: update gpio, spd addresses, and OC
by gerrit＠coreboot.org 14 Mar '13

14 Mar '13

the following patch was just integrated into master: commit 68724fd1e327d3e33c93bceec56973c0a4f7f505 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Dec 7 09:47:16 2012 -0600 basking ridge: update gpio, spd addresses, and OC Even though this is under the graysreef board it really applies to the Basking Ridge board. A subsequent patch will rename graysreef to baskingridge. The GPIO pins were updated to reflect the Basking Ridge schematics as well as the DIMM spd addresses and USB over current pins. Change-Id: Ice4e05f5203de3024cd463dfccf0bcfec1e247c1 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2632 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Mar 12 00:35:32 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Mar 14 05:09:29 2013, giving +2 See http://review.coreboot.org/2632 for details. -gerrit

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Patch merged into coreboot/master: 30c3900 haswell: notes and updates.
by gerrit＠coreboot.org 14 Mar '13

14 Mar '13

the following patch was just integrated into master: commit 30c3900451756793144bb579acc59205381138ab Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Nov 29 17:21:51 2012 -0600 haswell: notes and updates. Add a FIXME about checking a MCHBAR register that isn't setup yet. Also, remove revision updating because I can't find anything in the docs that suggest this is required for haswell. Change-Id: Ia8a6e08f82e18789e31c6c2ec2c1d63740c18dc4 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2631 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Mar 12 00:25:11 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Mar 14 05:08:01 2013, giving +2 See http://review.coreboot.org/2631 for details. -gerrit

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coreboot March 2013