coreboot March 2013

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Patch merged into coreboot/master: ef8f4c7 baskingridge: zero out alt_gp_smi_en in devicetree
by gerrit＠coreboot.org 14 Mar '13

14 Mar '13

the following patch was just integrated into master: commit ef8f4c78a55bc8c2874b02177e0612c8bffb5e39 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Dec 12 12:32:43 2012 -0600 baskingridge: zero out alt_gp_smi_en in devicetree The baskingridge has a non-zero alt_gp_smi_en value in the devicetree.cb file. It has just to be determined which GPI pins should trigger an SMI on basking ridge. Without this change the board would hang during boot (presumably through a SMI flood). No more hangs once the value is zero. Change-Id: I9704071bb7966bd3d0bbbc4aafede3f42d829b17 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2673 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Mar 12 23:44:37 2013, giving +1 See http://review.coreboot.org/2673 for details. -gerrit

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Patch merged into coreboot/master: e265d20 baskingridge: rename graysreef to baskingridge
by gerrit＠coreboot.org 14 Mar '13

14 Mar '13

the following patch was just integrated into master: commit e265d209374812f103fa401be518db624b79520d Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Mar 12 14:32:26 2013 -0700 baskingridge: rename graysreef to baskingridge The Grays Reef CRB is deprecated by order of Intel. Basking Ridge is the new hotness. Therefore, rename graysreef to basking ridge. Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I203497e165d8efc99d3438c4c548140a6e9cc649 Reviewed-on: http://review.coreboot.org/2672 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Build-Tested: build bot (Jenkins) at Tue Mar 12 23:34:31 2013, giving +1 See http://review.coreboot.org/2672 for details. -gerrit

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Patch merged into coreboot/master: 74c0d05 lynxpoint: Update device IDs and clock gating setup
by gerrit＠coreboot.org 14 Mar '13

14 Mar '13

the following patch was just integrated into master: commit 74c0d05cf51e089357712b2c855f344caba680fb Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Dec 17 11:31:40 2012 -0800 lynxpoint: Update device IDs and clock gating setup - Add device IDs for lynxpoint mobile and LP variants. - Update the clock gating setup based on BWG - Update the SATA programming based on BWG - Add a DEVSLP0 mux config register Change-Id: Icf4d7bab7f3df7adef5eb7c5e310a6995227a0e5 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/2649 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Build-Tested: build bot (Jenkins) at Tue Mar 12 03:36:23 2013, giving +1 See http://review.coreboot.org/2649 for details. -gerrit

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Patch merged into coreboot/master: 045f153 lynxpoint: Add new GPIO interface for Lynxpoint-LP
by gerrit＠coreboot.org 14 Mar '13

14 Mar '13

the following patch was just integrated into master: commit 045f153a4fe2b6e1cb193db01866218d0316f253 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Dec 17 11:29:10 2012 -0800 lynxpoint: Add new GPIO interface for Lynxpoint-LP The low power variant of the chipset introduces a completely new interface to the GPIOs. This is a 1KB region and so needs to be moved as well so it does not conflict with other IO regions. Also expose the gpio_get functions to ramstage and move the prototypes to pch.h so they can be used for both GPIO interfaces. Change-Id: I20bc18669525af16de8cdf99f0ccfa9612be63ad Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/2648 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Build-Tested: build bot (Jenkins) at Tue Mar 12 03:26:02 2013, giving +1 See http://review.coreboot.org/2648 for details. -gerrit

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Patch merged into coreboot/master: 5125404 haswell: Add ULT CPUID and updated microcode
by gerrit＠coreboot.org 14 Mar '13

14 Mar '13

the following patch was just integrated into master: commit 51254049b91a816c53b5cadf72d254f11e882818 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Dec 17 11:24:45 2012 -0800 haswell: Add ULT CPUID and updated microcode This adds microcode ffff000a and the CPUIDs for ULT. Change-Id: I341c1148a355d8373b31032b9f209232bd03230a Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/2647 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Build-Tested: build bot (Jenkins) at Tue Mar 12 03:16:08 2013, giving +1 See http://review.coreboot.org/2647 for details. -gerrit

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Patch merged into coreboot/master: df7be71 haswell: Add ULT device IDs
by gerrit＠coreboot.org 14 Mar '13

14 Mar '13

the following patch was just integrated into master: commit df7be71374a8b80708c58fd13e26b9e3fc6ed54c Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Dec 17 11:22:57 2012 -0800 haswell: Add ULT device IDs Device IDs for northbridge and GPU. Also mask off the lock bit in the memory map registers. Change-Id: I9a4955d4541b938285712e82dd0b1696fa272b63 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/2646 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Build-Tested: build bot (Jenkins) at Tue Mar 12 03:05:50 2013, giving +1 See http://review.coreboot.org/2646 for details. -gerrit

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Patch merged into coreboot/master: fb9928f lynxpoint: Add Kconfig entry for Low Power chipset
by gerrit＠coreboot.org 14 Mar '13

14 Mar '13

the following patch was just integrated into master: commit fb9928f2ec240babb5d3138136c03a7a78c53cc4 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Dec 17 11:11:26 2012 -0800 lynxpoint: Add Kconfig entry for Low Power chipset There are enough subtle differences that it is useful to have a Kconfig entry to differentiate the ULT/LP chipet from the desktop/mobile versions. Change-Id: I04ca1bc6f90bcf9e6994ea7125c98347e8def898 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/2645 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Build-Tested: build bot (Jenkins) at Tue Mar 12 02:56:22 2013, giving +1 See http://review.coreboot.org/2645 for details. -gerrit

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Patch merged into coreboot/master: be98524 lynxpoint: ME to BIOS Payload Updates
by gerrit＠coreboot.org 14 Mar '13

14 Mar '13

the following patch was just integrated into master: commit be98524ab208be4764c7d79bdcc7c35162210af1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Dec 12 12:40:33 2012 -0600 lynxpoint: ME to BIOS Payload Updates This commit contains a bevy of updates: - PCI device id is updated to match Lynx Point EDS in the ME driver. - Allocate the memory to store the consumption of the MBP. - me_bios_payload structure is now a structure of pointers that point into the allocated memory. - The ICC profile structure was updated to correctly reflect the documentation. Verfied that output of MBP reading can handle unknown items. Change-Id: I43cc45e6b797444c105e7c842eb5684e9c104687 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2641 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Mar 12 02:13:47 2013, giving +1 See http://review.coreboot.org/2641 for details. -gerrit

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Patch merged into coreboot/master: 569c653 lynx point: add new ME status information
by gerrit＠coreboot.org 14 Mar '13

14 Mar '13

the following patch was just integrated into master: commit 569c653a72cce2a29688f86849d48a5f0f935cf1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Dec 11 17:17:38 2012 -0600 lynx point: add new ME status information According to the 0.8.0 ME BWG this is a new state. It's not very clear what exactly it entails, but the Basking Ridge CRB was tripping it when MRC_DEBUG was enabled (presumably because of a DID timeout). Instead of 0x17 one can now see the proper message for this state. Change-Id: I5bda1de7d3d957d38a4760a02dcd170ec48782e9 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2640 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Mar 12 02:03:22 2013, giving +1 See http://review.coreboot.org/2640 for details. -gerrit

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Patch merged into coreboot/master: f72ad02 graysreef: update platform information
by gerrit＠coreboot.org 14 Mar '13

14 Mar '13

the following patch was just integrated into master: commit f72ad02158945c0c80aedd81218fb4fc4080cf1e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Nov 2 09:19:43 2012 -0500 graysreef: update platform information Some of the Lynx Point ids were off. Correct those and make the pei data BAR fields consistent with the others. Change-Id: I4102439588362cdb94643bd1ce69c9fa4278329e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2622 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Mon Mar 11 22:52:08 2013, giving +1 See http://review.coreboot.org/2622 for details. -gerrit

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coreboot March 2013