coreboot March 2013

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Patch merged into coreboot/master: 6f561af lynxpoint: lpc resource reservations
by gerrit＠coreboot.org 14 Mar '13

14 Mar '13

the following patch was just integrated into master: commit 6f561afa4a635958dedf20ffda9a40c6f5e5699e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Dec 19 14:38:01 2012 -0600 lynxpoint: lpc resource reservations This commit updates the Lynx Point resource reservations before the coreboot allocator assigns resources. There is no need to mark anything as subtractive decode because there are no devices/buses linked to the LPC device. The I/O range reservations consists of claiming the first 4KiB of I/O space. The PMBASE, GPIOBASE, and LPC generic I/O decode ranges are checked against the default claimed range. If those ranges overlap or fall outside of the default range then those resources are added. The MMIO range reservations consist of claiming everything from the I/O APIC to 4GiB. The RCBA and the LPC Generic Memory range register are then conditionally added if they fall outside of the default MMIO range. Change-Id: I0f560a03814a2b15961fdbe61e4164cd54cff7a5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2682 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Mar 13 02:59:43 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Mar 14 20:18:57 2013, giving +2 See http://review.coreboot.org/2682 for details. -gerrit

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Patch merged into coreboot/master: 26e7dd7 haswell: more ULT/LP support and minor tweaks
by gerrit＠coreboot.org 14 Mar '13

14 Mar '13

the following patch was just integrated into master: commit 26e7dd703dea8dce30829d8bb73c1f27a2178d72 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Dec 19 09:12:31 2012 -0800 haswell: more ULT/LP support and minor tweaks - Add ME device ID for Lynxpoint LP - Add GPU device IDs for ULT - SATA init tweaks from checking against DXE reference code - Remove the ICH7 from the SPI driver so it works on all lynxpoint without having to add more LPC device ID checks - Add function disable for audio dsp and xhci, remove PCI bridge - Add interrupt route registers for new devices (needs romstage setup) Change-Id: Idb48f50d0bacb6bf90531c3834542b9abb54fb8a Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/2680 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Mar 13 03:20:37 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Mar 14 20:16:26 2013, giving +2 See http://review.coreboot.org/2680 for details. -gerrit

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Patch merged into coreboot/master: eb58bc5 baskingridge: Report static temperature in _TMP
by gerrit＠coreboot.org 14 Mar '13

14 Mar '13

the following patch was just integrated into master: commit eb58bc5af6b8bf626f38d0c07bf55db2835f53b5 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Dec 19 09:14:10 2012 -0800 baskingridge: Report static temperature in _TMP The current code is attempting to convert from an invalid starting temperature. Since we aren't sure where the temperature will come from yet just return a static value. This stops the kernel from going to S5 on boot because it thinks the temperature is too high. Change-Id: I433fa407e545458344af5842b353df5bc71bfdad Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/2679 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Mar 13 02:29:15 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Mar 14 20:15:06 2013, giving +2 See http://review.coreboot.org/2679 for details. -gerrit

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Patch merged into coreboot/master: ed7b52d haswell: remove CONFIG_GFXUMA
by gerrit＠coreboot.org 14 Mar '13

14 Mar '13

the following patch was just integrated into master: commit ed7b52d3cb4c5f3f4ecfd43d93c0c5e2d459fe23 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Dec 18 14:18:53 2012 -0600 haswell: remove CONFIG_GFXUMA This option is not required for haswell. Enabling the option doesn't do anything aside from complicate mtrr calculation. Therefore, remove it. Change-Id: I897523ff7d3606eb89961674c2eb3d384e584857 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2678 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Mar 13 04:02:11 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Mar 14 20:13:41 2013, giving +2 See http://review.coreboot.org/2678 for details. -gerrit

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Patch merged into coreboot/master: f7fa218 x86: improve lb_cleanup_memory_ranges
by gerrit＠coreboot.org 14 Mar '13

14 Mar '13

the following patch was just integrated into master: commit f7fa218359cdfa981a2e6ea8c8eba32cb0567693 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Dec 18 17:01:57 2012 -0600 x86: improve lb_cleanup_memory_ranges There are 2 issues in lb_cleanup_memory_ranges(). The first is that during sort there is a neighbor comparison that initially starts with the current entry. The second issue is that merging has an off by one comparison for adjacent entries. Before: coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000a0000-00000000000fffff: RESERVED 3. 0000000000100000-0000000000efffff: RAM 4. 0000000000f00000-0000000000ffffff: RESERVED 5. 0000000001000000-00000000acebffff: RAM 6. 00000000acec0000-00000000acffffff: CONFIGURATION TABLES 7. 00000000ad000000-00000000af9fffff: RESERVED 8. 00000000f0000000-00000000f3ffffff: RESERVED 9. 00000000fed10000-00000000fed17fff: RESERVED 10. 00000000fed18000-00000000fed18fff: RESERVED 11. 00000000fed19000-00000000fed19fff: RESERVED 12. 00000000fed84000-00000000fed84fff: RESERVED 13. 0000000100000000-000000018f5fffff: RAM After: coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000a0000-00000000000fffff: RESERVED 3. 0000000000100000-0000000000efffff: RAM 4. 0000000000f00000-0000000000ffffff: RESERVED 5. 0000000001000000-00000000acebffff: RAM 6. 00000000acec0000-00000000acffffff: CONFIGURATION TABLES 7. 00000000ad000000-00000000af9fffff: RESERVED 8. 00000000f0000000-00000000f3ffffff: RESERVED 9. 00000000fed10000-00000000fed19fff: RESERVED 10. 00000000fed84000-00000000fed84fff: RESERVED 11. 0000000100000000-000000018f5fffff: RAM Change-Id: I656aab61b0ed4711c9dceaedb81c290d040ffdec Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2671 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Mar 12 23:21:01 2013, giving +1 Reviewed-By: Marc Jones <marc.jones(a)se-eng.com> at Wed Mar 13 06:27:44 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Mar 14 20:13:19 2013, giving +2 See http://review.coreboot.org/2671 for details. -gerrit

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Re: [coreboot] "Time out waiting for P-state 1" / GA-MA785GMT-UD2H + AMD Phenom II X4 955
by Marc Jones 14 Mar '13

14 Mar '13

On Thu, Mar 14, 2013 at 11:34 AM, George Chriss <gschriss(a)gmail.com> wrote: > Hi, > > I'm attempting to use Coreboot with a Gigabyte GA-MA785GMT-UD2H (rev > 1.1) board -- listed on the 'Supported boards' list -- with an AMD > Phenom II X4 955 (HDZ955FBGIBOX) processor. Proprietary VGA BIOS > extraction, building, flashing, and DualBIOS recovery all work well. > > The board coreboots reasonably well with a Athlon II X2 245 processor. > Debug log output: > coreboot / GA-MA785GMT-UD2H / Athlon II X2 245 > http://pastebin.com/9GxVnAha > > coreboot dmesg / GA-MA785GMT-UD2H / Athlon II X2 245 > http://pastebin.com/MztWHjfv > > > However with the Phenom II X4 processor Coreboot times out with " Time > out waiting for P-state 1. Current P-state 0...": > coreboot debug log / Gigabyte GA-MA785GMT-UD2H > http://pastebin.com/zinViJ4i > > Related commit: > [coreboot] [commit] r6401 ... cpu/amd/model_10xxx > http://www.coreboot.org/pipermail/coreboot/2011-February/063903.html > > "+ /* paranoia ? I fear when we run fixPsNbVidBeforeWR we can enter a > + * P1 that is a copy of P0, therefore has the same NB DID but the > + * TSC will count twice per tick, so we have to wait for twice the > + * count to achieve the desired timeout. But I'm likely to > + * misunderstand this... > + */" > > It's OK in my case to have the processor remain in P0 indefinably. > Any patch suggestions? > > Sincerely, > George > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot Hi George, In P0, it will always run hot, but there shouldn't be a problem. It will still do suspend on halt when it is not working on a thread. You may want to instrument that section further to see what it is trying to do with other Pstates. You may also lengthen the timeout. As the comment mentions, you should look at the BKDG, there may have been a change for that version of silicon. http://www.coreboot.org/Datasheets Marc -- http://se-eng.com

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"Time out waiting for P-state 1" / GA-MA785GMT-UD2H + AMD Phenom II X4 955
by George Chriss 14 Mar '13

14 Mar '13

Hi, I'm attempting to use Coreboot with a Gigabyte GA-MA785GMT-UD2H (rev 1.1) board -- listed on the 'Supported boards' list -- with an AMD Phenom II X4 955 (HDZ955FBGIBOX) processor. Proprietary VGA BIOS extraction, building, flashing, and DualBIOS recovery all work well. The board coreboots reasonably well with a Athlon II X2 245 processor. Debug log output: coreboot / GA-MA785GMT-UD2H / Athlon II X2 245 http://pastebin.com/9GxVnAha coreboot dmesg / GA-MA785GMT-UD2H / Athlon II X2 245 http://pastebin.com/MztWHjfv However with the Phenom II X4 processor Coreboot times out with " Time out waiting for P-state 1. Current P-state 0...": coreboot debug log / Gigabyte GA-MA785GMT-UD2H http://pastebin.com/zinViJ4i Related commit: [coreboot] [commit] r6401 ... cpu/amd/model_10xxx http://www.coreboot.org/pipermail/coreboot/2011-February/063903.html "+ /* paranoia ? I fear when we run fixPsNbVidBeforeWR we can enter a + * P1 that is a copy of P0, therefore has the same NB DID but the + * TSC will count twice per tick, so we have to wait for twice the + * count to achieve the desired timeout. But I'm likely to + * misunderstand this... + */" It's OK in my case to have the processor remain in P0 indefinably. Any patch suggestions? Sincerely, George

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Patch merged into coreboot/master: 0160d76 baskingridge: dev, recovery, and WP switch support
by gerrit＠coreboot.org 14 Mar '13

14 Mar '13

the following patch was just integrated into master: commit 0160d76152ecfbcbed599bb697917b423931b92b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Dec 13 16:51:41 2012 -0600 baskingridge: dev, recovery, and WP switch support This commit adds support for the deveveloper, recovery, and write protect querying. It just uses jumpers on the Basking Ridge board. Noted ability to togggle jumpers results in toggling the respective modes. Change-Id: Iac189a1fa0245654591e2e9075380db422a329a0 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2676 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Build-Tested: build bot (Jenkins) at Wed Mar 13 00:15:53 2013, giving +1 See http://review.coreboot.org/2676 for details. -gerrit

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Patch merged into coreboot/master: bdd89d0 baskingridge: update gpio map documentation
by gerrit＠coreboot.org 14 Mar '13

14 Mar '13

the following patch was just integrated into master: commit bdd89d0dc23ab4cd2efe5fcb9f0753a09aa14dc9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Dec 13 16:50:10 2012 -0600 baskingridge: update gpio map documentation While looking at the Basking Ridge schematic I noticed some changes and wanted to make sure they were reflected in the GPIO map. Change-Id: I686653c164314ae9f68c42331d2f950751411d4a Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2675 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Build-Tested: build bot (Jenkins) at Wed Mar 13 00:05:26 2013, giving +1 See http://review.coreboot.org/2675 for details. -gerrit

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Patch merged into coreboot/master: 7116129 haswell: Add VGA PCI ID mappings
by gerrit＠coreboot.org 14 Mar '13

14 Mar '13

the following patch was just integrated into master: commit 711612989930fdb3c1d60b3fc99ccb6918c3f135 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Dec 13 16:43:32 2012 -0600 haswell: Add VGA PCI ID mappings Needed to map VGA OPROM IDs to actual device IDs Change-Id: I6743905c3db52519bf18f4bcc1a972aec43d3e9d Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2674 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Build-Tested: build bot (Jenkins) at Tue Mar 12 23:54:53 2013, giving +1 See http://review.coreboot.org/2674 for details. -gerrit

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coreboot March 2013