coreboot January 2013

coreboot@coreboot.org

32 participants
607 discussions

Patch merged into coreboot/master: 3414234 Exynos5250: change all unsigned with no type to 'unsigned int'
by gerrit＠coreboot.org 29 Jan '13

29 Jan '13

the following patch was just integrated into master: commit 3414234f5a21b23b5b6cc0d2827ccbb4d9a2ccc8 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Jan 29 14:31:33 2013 -0800 Exynos5250: change all unsigned with no type to 'unsigned int' At some point we did a lot of cleanup to replace bare 'unsigned' with 'unsigned int'. Do that work for this imported code as well. At some point, we may find we can shrink these 'int's to something smaller, thought I very much doubt it's worth the trouble. Change-Id: Ic3da491c0188c56c836f8b9c4c8f26a31b4b3573 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: http://review.coreboot.org/2223 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Build-Tested: build bot (Jenkins) at Tue Jan 29 23:51:40 2013, giving +1 Reviewed-By: David Hendricks <dhendrix(a)chromium.org> at Tue Jan 29 23:59:45 2013, giving +2 See http://review.coreboot.org/2223 for details. -gerrit

1 0

Patch merged into coreboot/master: 88e4691 Exynos5250: add debug prints to DDR3 startup code.
by gerrit＠coreboot.org 29 Jan '13

29 Jan '13

the following patch was just integrated into master: commit 88e4691ed9f580b468005fd3ffec148b6e00e9ae Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Jan 29 14:16:35 2013 -0800 Exynos5250: add debug prints to DDR3 startup code. It can be handy to have debug prints as DRAM is started up, so that in the case of failure (does that ever happen?) you've got some idea where it failed. This patch adds some DEBUG_SPEW prints to the DDR3 code. I am doing this as its own CL because we may find we want to revert it. That's unlikely but it is not impossible if we skew the timing in some way. This code works for some trivial DRAM tests. Change-Id: I57e8d2a2d8df6b8ec8cd0d414681fc513e9999e3 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: http://review.coreboot.org/2222 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Build-Tested: build bot (Jenkins) at Tue Jan 29 23:44:20 2013, giving +1 Reviewed-By: David Hendricks <dhendrix(a)chromium.org> at Tue Jan 29 23:59:34 2013, giving +2 See http://review.coreboot.org/2222 for details. -gerrit

1 0

Patch merged into coreboot/master: 770996f Exynos5250: make vendor enums in the timing array more debuggable.
by gerrit＠coreboot.org 29 Jan '13

29 Jan '13

the following patch was just integrated into master: commit 770996fd86a2dfd44b0985b898af56c9dc10244b Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Jan 29 11:52:05 2013 -0800 Exynos5250: make vendor enums in the timing array more debuggable. The timing array is crucial to proper operation of DRAM. Getting a valid pointer to it is hence very important. Unfortunately, the constants chosen for the vendor were '1', and '2', (this in a 32-bit word) which in a debug print makes it almost impossible to tell if you've got a misaligned pointer. Note: coreboot people did not choose them :-) So, give them values which are extremely unlikely to occur elsewhere in the array (or in memory, for that matter). Given the frequency with which this check occurs, i.e. once, I would much prefer strings but I expect I'd get shouted down on that one. Constants in this case are an almost useless optimization but we'll go with them for now. Note no space is saved by not using strings: there's an entire function somewhere devoted to mapping the enum to a string! Debug prints of pointers to structs in this array are now far more useful than they were. See snarky comment in the code (left there to make sure nobody gets tempted to get fancy again). Comment now less snarky. This is tested on google snow to the point that the DRAM works. Change-Id: I30bc44719f321f791fd82ded60e29393399d9e3d Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: http://review.coreboot.org/2221 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Tue Jan 29 23:36:55 2013, giving +1 Reviewed-By: David Hendricks <dhendrix(a)chromium.org> at Tue Jan 29 23:13:23 2013, giving +2 See http://review.coreboot.org/2221 for details. -gerrit

1 0

New patch to review for coreboot: 44c7efa Exynos5250: Get DDR3 working by changing what is compiled and add a function
by Ronald G. Minnich 29 Jan '13

29 Jan '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2224 -gerrit commit 44c7efade1af8fcd677f5e2065d8773cb2a2e900 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Jan 29 14:35:35 2013 -0800 Exynos5250: Get DDR3 working by changing what is compiled and add a function This is a minor set of changes to get DDR3 going. Move compilation of DDR3 startup to the romstage. Fix a prototype that was missing a void. Remove a function that is overly flexible, and even though it is overly flexible only actually can handle one type of RAM. Mainboards only support one type of DRAM, so create a function to explicitly initialize the type of DDR we have -- DDR3. With these changes, and the previous changes, google snow is ready to run the ramstage. Change-Id: I37e0ab0d2dbc1dd121fb175386a46bc2fb1285e5 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/cpu/samsung/exynos5250/Makefile.inc | 4 ++-- src/cpu/samsung/exynos5250/clock_init.c | 2 +- src/cpu/samsung/exynos5250/dmc_common.c | 21 ++------------------- src/cpu/samsung/exynos5250/setup.h | 4 +--- 4 files changed, 6 insertions(+), 25 deletions(-) diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 1b915a3..992edce 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -11,6 +11,8 @@ romstage-y += pinmux.c romstage-y += power.c romstage-y += soc.c romstage-y += uart.c +romstage-$(CONFIG_SPL_BUILD) += dmc_common.c +romstage-$(CONFIG_SPL_BUILD) += dmc_init_ddr3.c #ramstage-y += clock.c #ramstage-y += clock_init.c @@ -30,8 +32,6 @@ ramstage-y += uart.c #ramstage-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.c #ramstage-$(CONFIG_SATA_AHCI) += sata.c ramstage-$(CONFIG_SPL_BUILD) += lowlevel_init_c.c -ramstage-$(CONFIG_SPL_BUILD) += dmc_common.c -ramstage-$(CONFIG_SPL_BUILD) += dmc_init_ddr3.c exynos5250_add_bl1: $(obj)/coreboot.pre printf " DD Adding Samsung Exynos5250 BL1\n" diff --git a/src/cpu/samsung/exynos5250/clock_init.c b/src/cpu/samsung/exynos5250/clock_init.c index ea91bb4..565abe1 100644 --- a/src/cpu/samsung/exynos5250/clock_init.c +++ b/src/cpu/samsung/exynos5250/clock_init.c @@ -744,7 +744,7 @@ struct mem_timings *clock_get_mem_timings(void) return NULL; } -void system_clock_init() +void system_clock_init(void) { struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; struct exynos5_mct_regs *mct_regs = diff --git a/src/cpu/samsung/exynos5250/dmc_common.c b/src/cpu/samsung/exynos5250/dmc_common.c index 35a13ac..f91cbb3 100644 --- a/src/cpu/samsung/exynos5250/dmc_common.c +++ b/src/cpu/samsung/exynos5250/dmc_common.c @@ -26,6 +26,8 @@ #include <common.h> #include <console/console.h> #include <cpu/samsung/exynos5250/setup.h> +#include <cpu/samsung/exynos5250/dmc.h> +#include <cpu/samsung/exynos5250/clock_init.h> #include <cpu/samsung/exynos5-common/spl.h> #include <system.h> @@ -179,22 +181,3 @@ void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc) writel(DMC_MEMBASECONFIG1_VAL, &dmc->membaseconfig1); } -void mem_ctrl_init() -{ - struct spl_machine_param *param = spl_get_machine_params(); - struct mem_timings *mem; - int ret; - - mem = clock_get_mem_timings(); - - /* If there are any other memory variant, add their init call below */ - if (param->mem_type == DDR_MODE_DDR3) { - ret = ddr3_mem_ctrl_init(mem, param->mem_iv_size); - if (ret) { - printk(BIOS_ERR, "Memory controller init failed, err: %u", ret); - BUG(); - } - } else { - die("Unknown memory type"); - } -} diff --git a/src/cpu/samsung/exynos5250/setup.h b/src/cpu/samsung/exynos5250/setup.h index bb438c5..13a46c2 100644 --- a/src/cpu/samsung/exynos5250/setup.h +++ b/src/cpu/samsung/exynos5250/setup.h @@ -706,9 +706,7 @@ void mem_ctrl_init(void); */ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size); -/* FIXME(dhendrix): why is this here? commenting it out and we'll use - clock_init.h instead */ -//void system_clock_init(void); +void ddr3_init(void); void tzpc_init(void); /*

1 0

New patch to review for coreboot: 8d2fb5c Exynos5250: change all unsigned with no type to 'unsigned int'
by Ronald G. Minnich 29 Jan '13

29 Jan '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2223 -gerrit commit 8d2fb5c0c99632da1b8009f7a7d45b05a92b43a0 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Jan 29 14:31:33 2013 -0800 Exynos5250: change all unsigned with no type to 'unsigned int' At some point we did a lot of cleanup to replace bare 'unsigned' with 'unsigned int'. Do that work for this imported code as well. At some point, we may find we can shrink these 'int's to something smaller, thought I very much doubt it's worth the trouble. Change-Id: Ic3da491c0188c56c836f8b9c4c8f26a31b4b3573 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/cpu/samsung/exynos5250/clock_init.h | 66 ++++++++++++++++----------------- 1 file changed, 33 insertions(+), 33 deletions(-) diff --git a/src/cpu/samsung/exynos5250/clock_init.h b/src/cpu/samsung/exynos5250/clock_init.h index 57a0fe6..00561a0 100644 --- a/src/cpu/samsung/exynos5250/clock_init.h +++ b/src/cpu/samsung/exynos5250/clock_init.h @@ -31,27 +31,27 @@ enum { /* These are the ratio's for configuring ARM clock */ struct arm_clk_ratios { - unsigned arm_freq_mhz; /* Frequency of ARM core in MHz */ - - unsigned apll_mdiv; - unsigned apll_pdiv; - unsigned apll_sdiv; - - unsigned arm2_ratio; - unsigned apll_ratio; - unsigned pclk_dbg_ratio; - unsigned atb_ratio; - unsigned periph_ratio; - unsigned acp_ratio; - unsigned cpud_ratio; - unsigned arm_ratio; + unsigned int arm_freq_mhz; /* Frequency of ARM core in MHz */ + + unsigned int apll_mdiv; + unsigned int apll_pdiv; + unsigned int apll_sdiv; + + unsigned int arm2_ratio; + unsigned int apll_ratio; + unsigned int pclk_dbg_ratio; + unsigned int atb_ratio; + unsigned int periph_ratio; + unsigned int acp_ratio; + unsigned int cpud_ratio; + unsigned int arm_ratio; }; /* These are the memory timings for a particular memory type and speed */ struct mem_timings { enum mem_manuf mem_manuf; /* Memory manufacturer */ enum ddr_mode mem_type; /* Memory type */ - unsigned frequency_mhz; /* Frequency of memory in MHz */ + unsigned int frequency_mhz; /* Frequency of memory in MHz */ /* Here follow the timing parameters for the selected memory */ uint8_t apll_mdiv; @@ -77,18 +77,18 @@ struct mem_timings { uint8_t bpll_sdiv; uint8_t use_bpll; /* 1 to use BPLL for cdrex, 0 to use MPLL */ uint8_t pclk_cdrex_ratio; - unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT]; + unsigned int direct_cmd_msr[MEM_TIMINGS_MSR_COUNT]; - unsigned timing_ref; - unsigned timing_row; - unsigned timing_data; - unsigned timing_power; + unsigned int timing_ref; + unsigned int timing_row; + unsigned int timing_data; + unsigned int timing_power; /* DQS, DQ, DEBUG offsets */ - unsigned phy0_dqs; - unsigned phy1_dqs; - unsigned phy0_dq; - unsigned phy1_dq; + unsigned int phy0_dqs; + unsigned int phy1_dqs; + unsigned int phy0_dq; + unsigned int phy1_dq; uint8_t phy0_tFS; uint8_t phy1_tFS; uint8_t phy0_pulld_dqs; @@ -116,21 +116,21 @@ struct mem_timings { uint8_t zq_mode_term; uint8_t zq_mode_noterm; /* 1 to allow termination disable */ - unsigned memcontrol; - unsigned memconfig; + unsigned int memcontrol; + unsigned int memconfig; - unsigned membaseconfig0; - unsigned membaseconfig1; - unsigned prechconfig_tp_cnt; - unsigned dpwrdn_cyc; - unsigned dsref_cyc; - unsigned concontrol; + unsigned int membaseconfig0; + unsigned int membaseconfig1; + unsigned int prechconfig_tp_cnt; + unsigned int dpwrdn_cyc; + unsigned int dsref_cyc; + unsigned int concontrol; /* Channel and Chip Selection */ uint8_t dmc_channels; /* number of memory channels */ uint8_t chips_per_channel; /* number of chips per channel */ uint8_t chips_to_configure; /* number of chips to configure */ uint8_t send_zq_init; /* 1 to send this command */ - unsigned impedance; /* drive strength impedeance */ + unsigned int impedance; /* drive strength impedeance */ uint8_t gate_leveling_enable; /* check gate leveling is enabled */ };

1 0

New patch to review for coreboot: 58cf6e6 Exynos5250: add debug prints to DDR3 startup code.
by Ronald G. Minnich 29 Jan '13

29 Jan '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2222 -gerrit commit 58cf6e699891fca73a0382a81deb1dd94cf632f3 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Jan 29 14:16:35 2013 -0800 Exynos5250: add debug prints to DDR3 startup code. It can be handy to have debug prints as DRAM is started up, so that in the case of failure (does that ever happen?) you've got some idea where it failed. This patch adds some DEBUG_SPEW prints to the DDR3 code. I am doing this as its own CL because we may find we want to revert it. That's unlikely but it is not impossible if we skew the timing in some way. This code works for some trivial DRAM tests. Change-Id: I57e8d2a2d8df6b8ec8cd0d414681fc513e9999e3 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/cpu/samsung/exynos5250/dmc_init_ddr3.c | 31 ++++++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c index 6ef10bf..541f749 100644 --- a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c +++ b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c @@ -24,6 +24,7 @@ #include <config.h> #include <arch/io.h> +#include <console/console.h> //#include "clock.h" /* FIXME(dhendrix): untangle clock/clk ... */ #include <cpu/samsung/s5p-common/clock.h> @@ -67,28 +68,37 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size) phy0_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY0_BASE; phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE; dmc = (struct exynos5_dmc *)EXYNOS5_DMC_CTRL_BASE; - + printk(BIOS_SPEW, "ddr3_mem_ctrl_init: reset phy: "); reset_phy_ctrl(); + printk(BIOS_SPEW, "done\n"); /* Set Impedance Output Driver */ + printk(BIOS_SPEW, "ddr3_mem_ctrl_init: Set Impedance Output Driver\n"); + printk(BIOS_SPEW, "ddr3_mem_ctrl_init: mem->impedance 0x%x\n", + mem->impedance); val = (mem->impedance << CA_CK_DRVR_DS_OFFSET) | (mem->impedance << CA_CKE_DRVR_DS_OFFSET) | (mem->impedance << CA_CS_DRVR_DS_OFFSET) | (mem->impedance << CA_ADR_DRVR_DS_OFFSET); + printk(BIOS_SPEW, "ddr3_mem_ctrl_init: val 0x%x\n", val); writel(val, &phy0_ctrl->phy_con39); writel(val, &phy1_ctrl->phy_con39); /* Set Read Latency and Burst Length for PHY0 and PHY1 */ + printk(BIOS_SPEW, "ddr3_mem_ctrl_init: " + "Set Read Latency and Burst Length for PHY0 and PHY1\n"); val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) | (mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT); writel(val, &phy0_ctrl->phy_con42); writel(val, &phy1_ctrl->phy_con42); /* ZQ Calibration */ + printk(BIOS_SPEW, "ddr3_mem_ctrl_init: ZQ Calibration\n"); if (dmc_config_zq(mem, phy0_ctrl, phy1_ctrl)) return SETUP_ERR_ZQ_CALIBRATION_FAILURE; /* DQ Signal */ + printk(BIOS_SPEW, "ddr3_mem_ctrl_init: DQ Signal\n"); writel(mem->phy0_pulld_dqs, &phy0_ctrl->phy_con14); writel(mem->phy1_pulld_dqs, &phy1_ctrl->phy_con14); @@ -99,6 +109,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size) update_reset_dll(dmc, DDR_MODE_DDR3); /* DQS Signal */ + printk(BIOS_SPEW, "ddr3_mem_ctrl_init: DQS Signal\n"); writel(mem->phy0_dqs, &phy0_ctrl->phy_con4); writel(mem->phy1_dqs, &phy1_ctrl->phy_con4); @@ -116,6 +127,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size) writel(val, &phy1_ctrl->phy_con12); /* Start DLL locking */ + printk(BIOS_SPEW, "ddr3_mem_ctrl_init: Start DLL Locking\n"); writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT), &phy0_ctrl->phy_con12); writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT), @@ -127,9 +139,12 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size) &dmc->concontrol); /* Memory Channel Inteleaving Size */ + printk(BIOS_SPEW, "ddr3_mem_ctrl_init: " + "Memory Channel Inteleaving Size\n"); writel(mem->iv_size, &dmc->ivcontrol); /* Set DMC MEMCONTROL register */ + printk(BIOS_SPEW, "ddr3_mem_ctrl_init: Set DMC MEMCONTROL register\n"); val = mem->memcontrol & ~DMC_MEMCONTROL_DSREF_ENABLE; writel(val, &dmc->memcontrol); @@ -139,10 +154,13 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size) writel(mem->membaseconfig1, &dmc->membaseconfig1); /* Precharge Configuration */ + printk(BIOS_SPEW, "ddr3_mem_ctrl_init: Precharge Configuration\n"); writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT, &dmc->prechconfig); /* Power Down mode Configuration */ + printk(BIOS_SPEW, "ddr3_mem_ctrl_init: " + "Power Down mode Configuraation\n"); writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT | mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT, &dmc->pwrdnconfig); @@ -150,15 +168,19 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size) /* TimingRow, TimingData, TimingPower and Timingaref * values as per Memory AC parameters */ + printk(BIOS_SPEW, "ddr3_mem_ctrl_init: " + "TimingRow, TimingData, TimingPower and Timingaref\n"); writel(mem->timing_ref, &dmc->timingref); writel(mem->timing_row, &dmc->timingrow); writel(mem->timing_data, &dmc->timingdata); writel(mem->timing_power, &dmc->timingpower); /* Send PALL command */ + printk(BIOS_SPEW, "ddr3_mem_ctrl_init: Send PALL Command\n"); dmc_config_prech(mem, dmc); /* Send NOP, MRS and ZQINIT commands */ + printk(BIOS_SPEW, "ddr3_mem_ctrl_init: Send NOP, MRS, and ZQINIT\n"); dmc_config_mrs(mem, dmc); if (mem->gate_leveling_enable) { @@ -217,8 +239,10 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size) sdelay(100); i--; } - if (!i) + if (!i){ + printk(BIOS_SPEW, "Timeout on RDLVL. No DRAM.\n"); return SETUP_ERR_RDLV_COMPLETE_TIMEOUT; + } writel(CTRL_RDLVL_GATE_DISABLE, &dmc->rdlvl_config); writel(0, &phy0_ctrl->phy_con14); @@ -238,11 +262,14 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size) } /* Send PALL command */ + printk(BIOS_SPEW, "ddr3_mem_ctrl_init: Send PALL Command\n"); dmc_config_prech(mem, dmc); writel(mem->memcontrol, &dmc->memcontrol); /* Set DMC Concontrol and enable auto-refresh counter */ + printk(BIOS_SPEW, "ddr3_mem_ctrl_init: " + "Set DMC Concontrol and enable auto-refresh counter\n"); writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT), &dmc->concontrol); return 0;

1 0

Patch set updated for coreboot: bb30380 Exynos5250: make vendor enums in the timing array more debuggable.
by Ronald G. Minnich 29 Jan '13

29 Jan '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2221 -gerrit commit bb303803b3e7fa10a901e1fb91a98f3c2ec1c0dc Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Jan 29 11:52:05 2013 -0800 Exynos5250: make vendor enums in the timing array more debuggable. The timing array is crucial to proper operation of DRAM. Getting a valid pointer to it is hence very important. Unfortunately, the constants chosen for the vendor were '1', and '2', (this in a 32-bit word) which in a debug print makes it almost impossible to tell if you've got a misaligned pointer. Note: coreboot people did not choose them :-) So, give them values which are extremely unlikely to occur elsewhere in the array (or in memory, for that matter). Given the frequency with which this check occurs, i.e. once, I would much prefer strings but I expect I'd get shouted down on that one. Constants in this case are an almost useless optimization but we'll go with them for now. Note no space is saved by not using strings: there's an entire function somewhere devoted to mapping the enum to a string! Debug prints of pointers to structs in this array are now far more useful than they were. See snarky comment in the code (left there to make sure nobody gets tempted to get fancy again). Comment now less snarky. This is tested on google snow to the point that the DRAM works. Change-Id: I30bc44719f321f791fd82ded60e29393399d9e3d Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/cpu/samsung/exynos5250/dmc.h | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/src/cpu/samsung/exynos5250/dmc.h b/src/cpu/samsung/exynos5250/dmc.h index d1dfbb1..b778e09 100644 --- a/src/cpu/samsung/exynos5250/dmc.h +++ b/src/cpu/samsung/exynos5250/dmc.h @@ -152,12 +152,27 @@ enum ddr_mode { DDR_MODE_COUNT, }; +/* For reasons unknown, people are in the habit of taking a 32-bit + * field with 2 possible values and packing it with, say, 2 bits. A + * non-robust encoding, using only 2 bits of a 32-bit field, is + * incredibly difficult to deal with when things go wrong, because + * there are a lot of things that get expressed as 0, 1, or 2. If + * you're scanning with jtag or dumping memory it is really hard to + * tell when you've hit the beginning of the struct. So, let's be a + * bit smart here. First, while it's common to let the enum count + * entries for you, when there are two of them, we can do the + * counting. And, let's set the values to something we can easily scan + * for in memory. Since '1' and '2' are rather common, we pick + * something that's actually of some value when things go wrong. This + * setup motivated by a use case: something's going wrong and having a + * manuf name of '1' or '2' is completely useless! + */ enum mem_manuf { MEM_MANUF_AUTODETECT, - MEM_MANUF_ELPIDA, - MEM_MANUF_SAMSUNG, + MEM_MANUF_ELPIDA = 0xe7b1da, + MEM_MANUF_SAMSUNG = 0x5a5096, - MEM_MANUF_COUNT, + MEM_MANUF_COUNT = 2, // fancy that. }; /* CONCONTROL register fields */

1 0

Patch set updated for coreboot: fd0b849 Exynos5250: make vendor enums in the timing array more debuggable.
by Ronald G. Minnich 29 Jan '13

29 Jan '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2221 -gerrit commit fd0b849df28aedd943e0e96ff8ca4972372f66d1 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Jan 29 11:52:05 2013 -0800 Exynos5250: make vendor enums in the timing array more debuggable. The timing array is crucial to proper operation of DRAM. Getting a valid pointer to it is hence very important. Unfortunately, the constants chosen for the vendor were '1', and '2', (this in a 32-bit word) which in a debug print makes it almost impossible to tell if you've got a misaligned pointer. Note: coreboot people did not choose them :-) So, give them values which are extremely unlikely to occur elsewhere in the array (or in memory, for that matter). Given the frequency with which this check occurs, i.e. once, I would much prefer strings but I expect I'd get shouted down on that one. Constants in this case are an almost useless optimization but we'll go with them for now. Note no space is saved by not using strings: there's an entire function somewhere devoted to mapping the enum to a string! Debug prints of pointers to structs in this array are now far more useful than they were. See snarky comment in the code (left there to make sure nobody gets tempted to get fancy again). Comment now less snarky. This is tested on google snow to the point that the DRAM works. Change-Id: I30bc44719f321f791fd82ded60e29393399d9e3d Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/cpu/samsung/exynos5250/dmc.h | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/src/cpu/samsung/exynos5250/dmc.h b/src/cpu/samsung/exynos5250/dmc.h index d1dfbb1..b778e09 100644 --- a/src/cpu/samsung/exynos5250/dmc.h +++ b/src/cpu/samsung/exynos5250/dmc.h @@ -152,12 +152,27 @@ enum ddr_mode { DDR_MODE_COUNT, }; +/* For reasons unknown, people are in the habit of taking a 32-bit + * field with 2 possible values and packing it with, say, 2 bits. A + * non-robust encoding, using only 2 bits of a 32-bit field, is + * incredibly difficult to deal with when things go wrong, because + * there are a lot of things that get expressed as 0, 1, or 2. If + * you're scanning with jtag or dumping memory it is really hard to + * tell when you've hit the beginning of the struct. So, let's be a + * bit smart here. First, while it's common to let the enum count + * entries for you, when there are two of them, we can do the + * counting. And, let's set the values to something we can easily scan + * for in memory. Since '1' and '2' are rather common, we pick + * something that's actually of some value when things go wrong. This + * setup motivated by a use case: something's going wrong and having a + * manuf name of '1' or '2' is completely useless! + */ enum mem_manuf { MEM_MANUF_AUTODETECT, - MEM_MANUF_ELPIDA, - MEM_MANUF_SAMSUNG, + MEM_MANUF_ELPIDA = 0xe7b1da, + MEM_MANUF_SAMSUNG = 0x5a5096, - MEM_MANUF_COUNT, + MEM_MANUF_COUNT = 2, // fancy that. }; /* CONCONTROL register fields */

1 0

Help Finding BIOS Chip on Thinkpad X60
by Alex Griffin 29 Jan '13

29 Jan '13

I recently got my hands on a Thinkpad X60, one of the few laptops supported by Coreboot. Following the wiki instructions for installing on this machine, I opened up the case to find the BIOS chip model to make sure I could apply a correct patch against flashrom and avoid bricking the machine. I can't seem to identify the BIOS chip, though, and I don't see any chips on the motherboard labeled with anything present in flashrom's sources. Can anyone help me? Where is the BIOS chip located on your X60? Is there any other advice you can give me about how to identify the BIOS chip? I have a few pictures of the top and bottom of the motherboard that I can post later if that would help. Thanks! -- Alex Griffin

2 1

Patch set updated for coreboot: 34c9106 Exynos5250: make vendor enums in the timing array more debuggable.
by Ronald G. Minnich 29 Jan '13

29 Jan '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2221 -gerrit commit 34c9106f544cec0029517ae43218e0f8b2bd59d7 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Jan 29 11:52:05 2013 -0800 Exynos5250: make vendor enums in the timing array more debuggable. The timing array is crucial to proper operation of DRAM. Getting a valid pointer to it is hence very important. Unfortunately, the constants chosen for the vendor were '1', and '2', (this in a 32-bit word) which in a debug print makes it almost impossible to tell if you've got a misaligned pointer. Note: coreboot people did not choose them :-) So, give them values which are extremely unlikely to occur elsewhere in the array (or in memory, for that matter). Given the frequency with which this check occurs, i.e. once, I would much prefer strings but I expect I'd get shouted down on that one. Constants in this case are an almost useless optimization but we'll go with them for now. Note no space is saved by not using strings: there's an entire function somewhere devoted to mapping the enum to a string! Debug prints of pointers to structs in this array are now far more useful than they were. See snarky comment in the code (left there to make sure nobody gets tempted to get fancy again). Comment now less snarky. This is tested on google snow to the point that the DRAM works. Change-Id: I30bc44719f321f791fd82ded60e29393399d9e3d Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/cpu/samsung/exynos5250/dmc.h | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/src/cpu/samsung/exynos5250/dmc.h b/src/cpu/samsung/exynos5250/dmc.h index d1dfbb1..b778e09 100644 --- a/src/cpu/samsung/exynos5250/dmc.h +++ b/src/cpu/samsung/exynos5250/dmc.h @@ -152,12 +152,27 @@ enum ddr_mode { DDR_MODE_COUNT, }; +/* For reasons unknown, people are in the habit of taking a 32-bit + * field with 2 possible values and packing it with, say, 2 bits. A + * non-robust encoding, using only 2 bits of a 32-bit field, is + * incredibly difficult to deal with when things go wrong, because + * there are a lot of things that get expressed as 0, 1, or 2. If + * you're scanning with jtag or dumping memory it is really hard to + * tell when you've hit the beginning of the struct. So, let's be a + * bit smart here. First, while it's common to let the enum count + * entries for you, when there are two of them, we can do the + * counting. And, let's set the values to something we can easily scan + * for in memory. Since '1' and '2' are rather common, we pick + * something that's actually of some value when things go wrong. This + * setup motivated by a use case: something's going wrong and having a + * manuf name of '1' or '2' is completely useless! + */ enum mem_manuf { MEM_MANUF_AUTODETECT, - MEM_MANUF_ELPIDA, - MEM_MANUF_SAMSUNG, + MEM_MANUF_ELPIDA = 0xe7b1da, + MEM_MANUF_SAMSUNG = 0x5a5096, - MEM_MANUF_COUNT, + MEM_MANUF_COUNT = 2, // fancy that. }; /* CONCONTROL register fields */

1 0

← Newer
1
...
6
7
8
9
10
11
12
...
61
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot January 2013