coreboot January 2013

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Patch set updated for coreboot: 319a2ae armv7: Clean up the mmu setup a bit
by David Hendricks 28 Jan '13

28 Jan '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2204 -gerrit commit 319a2aed6ba2e14612499879836375d68da22cc3 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Mon Jan 28 09:01:26 2013 -0800 armv7: Clean up the mmu setup a bit The previous incarnation did not use all of mmu_setup, which meant we did not carefully disable things before (possibly) changing them. This code is tested and works, and it's a bit of a simplification. Change-Id: I0560f9b8e25f31cd90e34304d6ec987fc5c87699 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/include/common.h | 4 +-- src/arch/armv7/include/system.h | 2 +- src/arch/armv7/lib/cache-cp15.c | 47 ++++++------------------------- src/cpu/samsung/exynos5250/exynos_cache.c | 3 +- src/mainboard/google/snow/romstage.c | 7 +---- 5 files changed, 15 insertions(+), 48 deletions(-) diff --git a/src/arch/armv7/include/common.h b/src/arch/armv7/include/common.h index 5a27fc0..1b69e84 100644 --- a/src/arch/armv7/include/common.h +++ b/src/arch/armv7/include/common.h @@ -239,10 +239,10 @@ uint rd_dc_cst (void); void wr_dc_cst (uint); void wr_dc_adr (uint); int icache_status (void); -void icache_enable (void); +void icache_enable (unsigned long start, unsigned long size); void icache_disable(void); int dcache_status (void); -void dcache_enable (void); +void dcache_enable (unsigned long start, unsigned long size); void dcache_disable(void); void mmu_disable(void); ulong get_endaddr (void); diff --git a/src/arch/armv7/include/system.h b/src/arch/armv7/include/system.h index c74ce8c..ddbab89 100644 --- a/src/arch/armv7/include/system.h +++ b/src/arch/armv7/include/system.h @@ -106,7 +106,7 @@ void mmu_set_region_dcache(unsigned long start, int size, */ void mmu_page_table_flush(unsigned long start, unsigned long stop); -void dram_bank_mmu_setup(unsigned long start, unsigned long size); +void mmu_setup(unsigned long start, unsigned long size); void arm_init_before_mmu(void); diff --git a/src/arch/armv7/lib/cache-cp15.c b/src/arch/armv7/lib/cache-cp15.c index 221befa..f51ee48 100644 --- a/src/arch/armv7/lib/cache-cp15.c +++ b/src/arch/armv7/lib/cache-cp15.c @@ -91,32 +91,13 @@ void mmu_set_region_dcache(unsigned long start, int size, enum dcache_option opt mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]); } -#if 0 -static inline void dram_bank_mmu_setup(int bank) -{ -// bd_t *bd = gd->bd; - int i; - - debug("%s: bank: %d\n", __func__, bank); - for (i = bd->bi_dram[bank].start >> 20; - i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20; - i++) { -#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) - set_section_dcache(i, DCACHE_WRITETHROUGH); -#else - set_section_dcache(i, DCACHE_WRITEBACK); -#endif - } -} -#endif - /** * dram_bank_mmu_set - set up the data cache policy for a given dram bank * * @start: virtual address start of bank * @size: size of bank (in bytes) */ -inline void dram_bank_mmu_setup(unsigned long start, unsigned long size) +static inline void dram_bank_mmu_setup(unsigned long start, unsigned long size) { int i; @@ -133,27 +114,17 @@ inline void dram_bank_mmu_setup(unsigned long start, unsigned long size) } /* to activate the MMU we need to set up virtual memory: use 1M areas */ -static inline void mmu_setup(void) +inline void mmu_setup(unsigned long start, unsigned long size) { int i; u32 reg; arm_init_before_mmu(); + /* Set up an identity-mapping for all 4GB, rw for everyone */ for (i = 0; i < 4096; i++) set_section_dcache(i, DCACHE_OFF); - /* FIXME(dhendrix): u-boot's global data struct was used here... */ -#if 0 - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - dram_bank_mmu_setup(i); - } -#endif -#if 0 - /* comes from board's romstage.c, since we need to know which - ranges to setup */ - mainboard_setup_mmu(); -#endif dram_bank_mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB << 20); /* Copy the page table address to cp15 */ @@ -174,13 +145,13 @@ static int mmu_enabled(void) } /* cache_bit must be either CR_I or CR_C */ -static void cache_enable(uint32_t cache_bit) +static void cache_enable(unsigned long start, unsigned long size, uint32_t cache_bit) { uint32_t reg; /* The data cache is not active unless the mmu is enabled too */ if ((cache_bit == CR_C) && !mmu_enabled()) - mmu_setup(); + mmu_setup(start, size); reg = get_cr(); /* get control reg. */ cp_delay(); set_cr(reg | cache_bit); @@ -216,9 +187,9 @@ static void cache_disable(uint32_t cache_bit) set_cr(reg & ~cache_bit); } -void icache_enable(void) +void icache_enable(unsigned long start, unsigned long size) { - cache_enable(CR_I); + cache_enable(start, size, CR_I); } void icache_disable(void) @@ -231,9 +202,9 @@ int icache_status(void) return (get_cr() & CR_I) != 0; } -void dcache_enable(void) +void dcache_enable(unsigned long start, unsigned long size) { - cache_enable(CR_C); + cache_enable(start, size, CR_C); } void dcache_disable(void) diff --git a/src/cpu/samsung/exynos5250/exynos_cache.c b/src/cpu/samsung/exynos5250/exynos_cache.c index ec858d1..7f4effe 100644 --- a/src/cpu/samsung/exynos5250/exynos_cache.c +++ b/src/cpu/samsung/exynos5250/exynos_cache.c @@ -39,7 +39,8 @@ enum l2_cache_params { void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); + /* can't use it anyway -- it has dependencies we have to fix. */ + //dcache_enable(); } #endif diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 45016a5..3f3f3ec 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -37,11 +37,6 @@ #endif #include <console/console.h> -static void mmu_setup(void) -{ - dram_bank_mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024); -} - void main(void); void main(void) { @@ -54,5 +49,5 @@ void main(void) printk(BIOS_INFO, "hello from romstage\n"); // *pshold &= ~0x100; /* shut down */ - mmu_setup(); + mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024); }

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Patch merged into coreboot/master: 1fb9bfa armv7: nuke global_data.h and remove some references to gd struct
by gerrit＠coreboot.org 28 Jan '13

28 Jan '13

the following patch was just integrated into master: commit 1fb9bfa0f90c73c73bf0b9b7d9d5a2af6d7fe530 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Jan 28 12:24:54 2013 -0800 armv7: nuke global_data.h and remove some references to gd struct This begins to remove references to global data which u-boot used. There are still many commented out references to gd-> and bd-> which we'll fix once we're happy with the replacements. Change-Id: Ie1b40a997e28a118f8f3ad96a2f9a2462d32fbe3 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2210 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Mon Jan 28 21:51:05 2013, giving +1 See http://review.coreboot.org/2210 for details. -gerrit

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Patch merged into coreboot/master: 4a48420 armv7: Clean out weak symbols and unnecessary #ifdef's in cache files
by gerrit＠coreboot.org 28 Jan '13

28 Jan '13

the following patch was just integrated into master: commit 4a484203d011c6fb3dd6f0edb2fadb3f2b07220c Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Jan 28 12:11:27 2013 -0800 armv7: Clean out weak symbols and unnecessary #ifdef's in cache files This just removes unused code. If for some reason we don't want to initialize cache, then the CPU or mainboard specific init routines don't need to call these. Change-Id: Ieb7393b6cbc103e490753da4ed27114156466ded Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2209 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Mon Jan 28 21:58:14 2013, giving +1 See http://review.coreboot.org/2209 for details. -gerrit

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New patch to review: 49493f5 T60: add volume CMOS setting
by gerrit＠coreboot.org 28 Jan '13

28 Jan '13

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12 -gerrit

6 10

New patch to review for coreboot: 0b41858 Clean up the mmu setup a bit
by Ronald G. Minnich 28 Jan '13

28 Jan '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2204 -gerrit commit 0b418582644777ba74ffa86403e6a0a2e4114ee2 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Mon Jan 28 09:01:26 2013 -0800 Clean up the mmu setup a bit The previous incarnation did not use all of mmu_setup, which meant we did not carefully disable things before (possibly) changing them. This coce is tested and works, and it's a bit of a simplification. Change-Id: I0560f9b8e25f31cd90e34304d6ec987fc5c87699 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/armv7/include/common.h | 4 +-- src/arch/armv7/include/system.h | 2 +- src/arch/armv7/lib/cache-cp15.c | 51 ++++++------------------------- src/cpu/samsung/exynos5250/exynos_cache.c | 3 +- src/mainboard/google/snow/romstage.c | 7 +---- 5 files changed, 16 insertions(+), 51 deletions(-) diff --git a/src/arch/armv7/include/common.h b/src/arch/armv7/include/common.h index a2cd9ae..3bf0bba 100644 --- a/src/arch/armv7/include/common.h +++ b/src/arch/armv7/include/common.h @@ -241,10 +241,10 @@ uint rd_dc_cst (void); void wr_dc_cst (uint); void wr_dc_adr (uint); int icache_status (void); -void icache_enable (void); +void icache_enable (unsigned long start, unsigned long size); void icache_disable(void); int dcache_status (void); -void dcache_enable (void); +void dcache_enable (unsigned long start, unsigned long size); void dcache_disable(void); void mmu_disable(void); void relocate_code (ulong, gd_t *, ulong) __attribute__ ((noreturn)); diff --git a/src/arch/armv7/include/system.h b/src/arch/armv7/include/system.h index c74ce8c..ddbab89 100644 --- a/src/arch/armv7/include/system.h +++ b/src/arch/armv7/include/system.h @@ -106,7 +106,7 @@ void mmu_set_region_dcache(unsigned long start, int size, */ void mmu_page_table_flush(unsigned long start, unsigned long stop); -void dram_bank_mmu_setup(unsigned long start, unsigned long size); +void mmu_setup(unsigned long start, unsigned long size); void arm_init_before_mmu(void); diff --git a/src/arch/armv7/lib/cache-cp15.c b/src/arch/armv7/lib/cache-cp15.c index 1786725..7dbd550 100644 --- a/src/arch/armv7/lib/cache-cp15.c +++ b/src/arch/armv7/lib/cache-cp15.c @@ -111,34 +111,13 @@ void mmu_set_region_dcache(unsigned long start, int size, enum dcache_option opt mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]); } -#if 0 -static inline void dram_bank_mmu_setup(int bank) -{ -// bd_t *bd = gd->bd; - int i; - - debug("%s: bank: %d\n", __func__, bank); - for (i = bd->bi_dram[bank].start >> 20; - i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20; - i++) { -#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) - set_section_dcache(i, DCACHE_WRITETHROUGH); -#else - set_section_dcache(i, DCACHE_WRITEBACK); -#endif - } -} -#endif - -/* FIXME(dhendrix): modified to take arguments from the caller (mainboard's - romstage.c) so it doesn't rely on global data struct */ /** * dram_bank_mmu_set - set up the data cache policy for a given dram bank * * @start: virtual address start of bank * @size: size of bank (in bytes) */ -inline void dram_bank_mmu_setup(unsigned long start, unsigned long size) +static inline void dram_bank_mmu_setup(unsigned long start, unsigned long size) { int i; @@ -155,27 +134,17 @@ inline void dram_bank_mmu_setup(unsigned long start, unsigned long size) } /* to activate the MMU we need to set up virtual memory: use 1M areas */ -static inline void mmu_setup(void) +inline void mmu_setup(unsigned long start, unsigned long size) { int i; u32 reg; - arm_init_before_mmu(); + /* enough with the weak symbols already */ + //arm_init_before_mmu(); /* Set up an identity-mapping for all 4GB, rw for everyone */ for (i = 0; i < 4096; i++) set_section_dcache(i, DCACHE_OFF); - /* FIXME(dhendrix): u-boot's global data struct was used here... */ -#if 0 - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - dram_bank_mmu_setup(i); - } -#endif -#if 0 - /* comes from board's romstage.c, since we need to know which - ranges to setup */ - mainboard_setup_mmu(); -#endif dram_bank_mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB << 20); /* Copy the page table address to cp15 */ @@ -196,13 +165,13 @@ static int mmu_enabled(void) } /* cache_bit must be either CR_I or CR_C */ -static void cache_enable(uint32_t cache_bit) +static void cache_enable(unsigned long start, unsigned long size, uint32_t cache_bit) { uint32_t reg; /* The data cache is not active unless the mmu is enabled too */ if ((cache_bit == CR_C) && !mmu_enabled()) - mmu_setup(); + mmu_setup(start, size); reg = get_cr(); /* get control reg. */ cp_delay(); set_cr(reg | cache_bit); @@ -255,9 +224,9 @@ int icache_status (void) return 0; /* always off */ } #else -void icache_enable(void) +void icache_enable(unsigned long start, unsigned long size) { - cache_enable(CR_I); + cache_enable(start, size, CR_I); } void icache_disable(void) @@ -287,9 +256,9 @@ int dcache_status (void) return 0; /* always off */ } #else -void dcache_enable(void) +void dcache_enable(unsigned long start, unsigned long size) { - cache_enable(CR_C); + cache_enable(start, size, CR_C); } void dcache_disable(void) diff --git a/src/cpu/samsung/exynos5250/exynos_cache.c b/src/cpu/samsung/exynos5250/exynos_cache.c index ec858d1..7f4effe 100644 --- a/src/cpu/samsung/exynos5250/exynos_cache.c +++ b/src/cpu/samsung/exynos5250/exynos_cache.c @@ -39,7 +39,8 @@ enum l2_cache_params { void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); + /* can't use it anyway -- it has dependencies we have to fix. */ + //dcache_enable(); } #endif diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 45016a5..3f3f3ec 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -37,11 +37,6 @@ #endif #include <console/console.h> -static void mmu_setup(void) -{ - dram_bank_mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024); -} - void main(void); void main(void) { @@ -54,5 +49,5 @@ void main(void) printk(BIOS_INFO, "hello from romstage\n"); // *pshold &= ~0x100; /* shut down */ - mmu_setup(); + mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024); }

4 3

Patch set updated for coreboot: 25ba1b9 Clean up the mmu setup a bit
by David Hendricks 28 Jan '13

28 Jan '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2204 -gerrit commit 25ba1b9b58ad7300f22b92f83a57b17048171a1a Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Mon Jan 28 09:01:26 2013 -0800 Clean up the mmu setup a bit The previous incarnation did not use all of mmu_setup, which meant we did not carefully disable things before (possibly) changing them. This coce is tested and works, and it's a bit of a simplification. Change-Id: I0560f9b8e25f31cd90e34304d6ec987fc5c87699 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/include/common.h | 4 +-- src/arch/armv7/include/system.h | 2 +- src/arch/armv7/lib/cache-cp15.c | 47 ++++++------------------------- src/cpu/samsung/exynos5250/exynos_cache.c | 3 +- src/mainboard/google/snow/romstage.c | 7 +---- 5 files changed, 15 insertions(+), 48 deletions(-) diff --git a/src/arch/armv7/include/common.h b/src/arch/armv7/include/common.h index 5a27fc0..1b69e84 100644 --- a/src/arch/armv7/include/common.h +++ b/src/arch/armv7/include/common.h @@ -239,10 +239,10 @@ uint rd_dc_cst (void); void wr_dc_cst (uint); void wr_dc_adr (uint); int icache_status (void); -void icache_enable (void); +void icache_enable (unsigned long start, unsigned long size); void icache_disable(void); int dcache_status (void); -void dcache_enable (void); +void dcache_enable (unsigned long start, unsigned long size); void dcache_disable(void); void mmu_disable(void); ulong get_endaddr (void); diff --git a/src/arch/armv7/include/system.h b/src/arch/armv7/include/system.h index c74ce8c..ddbab89 100644 --- a/src/arch/armv7/include/system.h +++ b/src/arch/armv7/include/system.h @@ -106,7 +106,7 @@ void mmu_set_region_dcache(unsigned long start, int size, */ void mmu_page_table_flush(unsigned long start, unsigned long stop); -void dram_bank_mmu_setup(unsigned long start, unsigned long size); +void mmu_setup(unsigned long start, unsigned long size); void arm_init_before_mmu(void); diff --git a/src/arch/armv7/lib/cache-cp15.c b/src/arch/armv7/lib/cache-cp15.c index 221befa..f51ee48 100644 --- a/src/arch/armv7/lib/cache-cp15.c +++ b/src/arch/armv7/lib/cache-cp15.c @@ -91,32 +91,13 @@ void mmu_set_region_dcache(unsigned long start, int size, enum dcache_option opt mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]); } -#if 0 -static inline void dram_bank_mmu_setup(int bank) -{ -// bd_t *bd = gd->bd; - int i; - - debug("%s: bank: %d\n", __func__, bank); - for (i = bd->bi_dram[bank].start >> 20; - i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20; - i++) { -#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) - set_section_dcache(i, DCACHE_WRITETHROUGH); -#else - set_section_dcache(i, DCACHE_WRITEBACK); -#endif - } -} -#endif - /** * dram_bank_mmu_set - set up the data cache policy for a given dram bank * * @start: virtual address start of bank * @size: size of bank (in bytes) */ -inline void dram_bank_mmu_setup(unsigned long start, unsigned long size) +static inline void dram_bank_mmu_setup(unsigned long start, unsigned long size) { int i; @@ -133,27 +114,17 @@ inline void dram_bank_mmu_setup(unsigned long start, unsigned long size) } /* to activate the MMU we need to set up virtual memory: use 1M areas */ -static inline void mmu_setup(void) +inline void mmu_setup(unsigned long start, unsigned long size) { int i; u32 reg; arm_init_before_mmu(); + /* Set up an identity-mapping for all 4GB, rw for everyone */ for (i = 0; i < 4096; i++) set_section_dcache(i, DCACHE_OFF); - /* FIXME(dhendrix): u-boot's global data struct was used here... */ -#if 0 - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - dram_bank_mmu_setup(i); - } -#endif -#if 0 - /* comes from board's romstage.c, since we need to know which - ranges to setup */ - mainboard_setup_mmu(); -#endif dram_bank_mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB << 20); /* Copy the page table address to cp15 */ @@ -174,13 +145,13 @@ static int mmu_enabled(void) } /* cache_bit must be either CR_I or CR_C */ -static void cache_enable(uint32_t cache_bit) +static void cache_enable(unsigned long start, unsigned long size, uint32_t cache_bit) { uint32_t reg; /* The data cache is not active unless the mmu is enabled too */ if ((cache_bit == CR_C) && !mmu_enabled()) - mmu_setup(); + mmu_setup(start, size); reg = get_cr(); /* get control reg. */ cp_delay(); set_cr(reg | cache_bit); @@ -216,9 +187,9 @@ static void cache_disable(uint32_t cache_bit) set_cr(reg & ~cache_bit); } -void icache_enable(void) +void icache_enable(unsigned long start, unsigned long size) { - cache_enable(CR_I); + cache_enable(start, size, CR_I); } void icache_disable(void) @@ -231,9 +202,9 @@ int icache_status(void) return (get_cr() & CR_I) != 0; } -void dcache_enable(void) +void dcache_enable(unsigned long start, unsigned long size) { - cache_enable(CR_C); + cache_enable(start, size, CR_C); } void dcache_disable(void) diff --git a/src/cpu/samsung/exynos5250/exynos_cache.c b/src/cpu/samsung/exynos5250/exynos_cache.c index ec858d1..7f4effe 100644 --- a/src/cpu/samsung/exynos5250/exynos_cache.c +++ b/src/cpu/samsung/exynos5250/exynos_cache.c @@ -39,7 +39,8 @@ enum l2_cache_params { void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); + /* can't use it anyway -- it has dependencies we have to fix. */ + //dcache_enable(); } #endif diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 45016a5..3f3f3ec 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -37,11 +37,6 @@ #endif #include <console/console.h> -static void mmu_setup(void) -{ - dram_bank_mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024); -} - void main(void); void main(void) { @@ -54,5 +49,5 @@ void main(void) printk(BIOS_INFO, "hello from romstage\n"); // *pshold &= ~0x100; /* shut down */ - mmu_setup(); + mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024); }

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Patch set updated for coreboot: 21a9db6 Clean up the mmu setup a bit
by David Hendricks 28 Jan '13

28 Jan '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2204 -gerrit commit 21a9db6d8c82885b5fa220155e1456b78c726308 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Mon Jan 28 09:01:26 2013 -0800 Clean up the mmu setup a bit The previous incarnation did not use all of mmu_setup, which meant we did not carefully disable things before (possibly) changing them. This coce is tested and works, and it's a bit of a simplification. Change-Id: I0560f9b8e25f31cd90e34304d6ec987fc5c87699 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/include/common.h | 4 +-- src/arch/armv7/include/system.h | 2 +- src/arch/armv7/lib/cache-cp15.c | 49 +++++++------------------------ src/cpu/samsung/exynos5250/exynos_cache.c | 3 +- src/mainboard/google/snow/romstage.c | 7 +---- 5 files changed, 16 insertions(+), 49 deletions(-) diff --git a/src/arch/armv7/include/common.h b/src/arch/armv7/include/common.h index 5a27fc0..1b69e84 100644 --- a/src/arch/armv7/include/common.h +++ b/src/arch/armv7/include/common.h @@ -239,10 +239,10 @@ uint rd_dc_cst (void); void wr_dc_cst (uint); void wr_dc_adr (uint); int icache_status (void); -void icache_enable (void); +void icache_enable (unsigned long start, unsigned long size); void icache_disable(void); int dcache_status (void); -void dcache_enable (void); +void dcache_enable (unsigned long start, unsigned long size); void dcache_disable(void); void mmu_disable(void); ulong get_endaddr (void); diff --git a/src/arch/armv7/include/system.h b/src/arch/armv7/include/system.h index c74ce8c..ddbab89 100644 --- a/src/arch/armv7/include/system.h +++ b/src/arch/armv7/include/system.h @@ -106,7 +106,7 @@ void mmu_set_region_dcache(unsigned long start, int size, */ void mmu_page_table_flush(unsigned long start, unsigned long stop); -void dram_bank_mmu_setup(unsigned long start, unsigned long size); +void mmu_setup(unsigned long start, unsigned long size); void arm_init_before_mmu(void); diff --git a/src/arch/armv7/lib/cache-cp15.c b/src/arch/armv7/lib/cache-cp15.c index 221befa..79cd6eb 100644 --- a/src/arch/armv7/lib/cache-cp15.c +++ b/src/arch/armv7/lib/cache-cp15.c @@ -91,32 +91,13 @@ void mmu_set_region_dcache(unsigned long start, int size, enum dcache_option opt mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]); } -#if 0 -static inline void dram_bank_mmu_setup(int bank) -{ -// bd_t *bd = gd->bd; - int i; - - debug("%s: bank: %d\n", __func__, bank); - for (i = bd->bi_dram[bank].start >> 20; - i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20; - i++) { -#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) - set_section_dcache(i, DCACHE_WRITETHROUGH); -#else - set_section_dcache(i, DCACHE_WRITEBACK); -#endif - } -} -#endif - /** * dram_bank_mmu_set - set up the data cache policy for a given dram bank * * @start: virtual address start of bank * @size: size of bank (in bytes) */ -inline void dram_bank_mmu_setup(unsigned long start, unsigned long size) +static inline void dram_bank_mmu_setup(unsigned long start, unsigned long size) { int i; @@ -133,27 +114,17 @@ inline void dram_bank_mmu_setup(unsigned long start, unsigned long size) } /* to activate the MMU we need to set up virtual memory: use 1M areas */ -static inline void mmu_setup(void) +inline void mmu_setup(unsigned long start, unsigned long size) { int i; u32 reg; - arm_init_before_mmu(); + /* enough with the weak symbols already */ + //arm_init_before_mmu(); /* Set up an identity-mapping for all 4GB, rw for everyone */ for (i = 0; i < 4096; i++) set_section_dcache(i, DCACHE_OFF); - /* FIXME(dhendrix): u-boot's global data struct was used here... */ -#if 0 - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - dram_bank_mmu_setup(i); - } -#endif -#if 0 - /* comes from board's romstage.c, since we need to know which - ranges to setup */ - mainboard_setup_mmu(); -#endif dram_bank_mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB << 20); /* Copy the page table address to cp15 */ @@ -174,13 +145,13 @@ static int mmu_enabled(void) } /* cache_bit must be either CR_I or CR_C */ -static void cache_enable(uint32_t cache_bit) +static void cache_enable(unsigned long start, unsigned long size, uint32_t cache_bit) { uint32_t reg; /* The data cache is not active unless the mmu is enabled too */ if ((cache_bit == CR_C) && !mmu_enabled()) - mmu_setup(); + mmu_setup(start, size); reg = get_cr(); /* get control reg. */ cp_delay(); set_cr(reg | cache_bit); @@ -216,9 +187,9 @@ static void cache_disable(uint32_t cache_bit) set_cr(reg & ~cache_bit); } -void icache_enable(void) +void icache_enable(unsigned long start, unsigned long size) { - cache_enable(CR_I); + cache_enable(start, size, CR_I); } void icache_disable(void) @@ -231,9 +202,9 @@ int icache_status(void) return (get_cr() & CR_I) != 0; } -void dcache_enable(void) +void dcache_enable(unsigned long start, unsigned long size) { - cache_enable(CR_C); + cache_enable(start, size, CR_C); } void dcache_disable(void) diff --git a/src/cpu/samsung/exynos5250/exynos_cache.c b/src/cpu/samsung/exynos5250/exynos_cache.c index ec858d1..7f4effe 100644 --- a/src/cpu/samsung/exynos5250/exynos_cache.c +++ b/src/cpu/samsung/exynos5250/exynos_cache.c @@ -39,7 +39,8 @@ enum l2_cache_params { void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); + /* can't use it anyway -- it has dependencies we have to fix. */ + //dcache_enable(); } #endif diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 45016a5..3f3f3ec 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -37,11 +37,6 @@ #endif #include <console/console.h> -static void mmu_setup(void) -{ - dram_bank_mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024); -} - void main(void); void main(void) { @@ -54,5 +49,5 @@ void main(void) printk(BIOS_INFO, "hello from romstage\n"); // *pshold &= ~0x100; /* shut down */ - mmu_setup(); + mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024); }

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Patch set updated for coreboot: 23c0d24 armv7: Clean out weak symbols and unnecessary #ifdef's in cache files
by David Hendricks 28 Jan '13

28 Jan '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2209 -gerrit commit 23c0d249b7f308a39ca5f8857308b972ad8a205d Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Jan 28 12:11:27 2013 -0800 armv7: Clean out weak symbols and unnecessary #ifdef's in cache files This just removes unused code. If for some reason we don't want to initialize cache, then the CPU or mainboard specific init routines don't need to call these. Change-Id: Ieb7393b6cbc103e490753da4ed27114156466ded Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/lib/cache-cp15.c | 52 ------------------------ src/arch/armv7/lib/cache_v7.c | 88 ----------------------------------------- 2 files changed, 140 deletions(-) diff --git a/src/arch/armv7/lib/cache-cp15.c b/src/arch/armv7/lib/cache-cp15.c index 1786725..c684d65 100644 --- a/src/arch/armv7/lib/cache-cp15.c +++ b/src/arch/armv7/lib/cache-cp15.c @@ -21,25 +21,13 @@ * MA 02111-1307 USA */ -/* FIXME(dhendrix): clean-up weak symbols if it looks unlikely we'll - want to override them with anything other than what's in cache_v7. */ #include <common.h> #include <stdlib.h> #include <system.h> #include <global_data.h> -#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) - DECLARE_GLOBAL_DATA_PTR; -#if 0 -void __arm_init_before_mmu(void) -{ -} -void arm_init_before_mmu(void) - __attribute__((weak, alias("__arm_init_before_mmu"))); -#endif - static void cp_delay (void) { volatile int i; @@ -92,11 +80,6 @@ void __mmu_page_table_flush(unsigned long start, unsigned long stop) } #endif -#if 0 -void mmu_page_table_flush(unsigned long start, unsigned long stop) - __attribute__((weak, alias("__mmu_page_table_flush"))); -#endif - void mmu_set_region_dcache(unsigned long start, int size, enum dcache_option option) { u32 *page_table = (u32 *)gd->tlb_addr; @@ -237,24 +220,7 @@ static void cache_disable(uint32_t cache_bit) flush_dcache_all(); set_cr(reg & ~cache_bit); } -#endif - -#ifdef CONFIG_SYS_ICACHE_OFF -void icache_enable (void) -{ - return; -} - -void icache_disable (void) -{ - return; -} -int icache_status (void) -{ - return 0; /* always off */ -} -#else void icache_enable(void) { cache_enable(CR_I); @@ -269,24 +235,7 @@ int icache_status(void) { return (get_cr() & CR_I) != 0; } -#endif - -#ifdef CONFIG_SYS_DCACHE_OFF -void dcache_enable (void) -{ - return; -} -void dcache_disable (void) -{ - return; -} - -int dcache_status (void) -{ - return 0; /* always off */ -} -#else void dcache_enable(void) { cache_enable(CR_C); @@ -301,4 +250,3 @@ int dcache_status(void) { return (get_cr() & CR_C) != 0; } -#endif diff --git a/src/arch/armv7/lib/cache_v7.c b/src/arch/armv7/lib/cache_v7.c index 13bb59f..22c3f89 100644 --- a/src/arch/armv7/lib/cache_v7.c +++ b/src/arch/armv7/lib/cache_v7.c @@ -32,7 +32,6 @@ #define ARMV7_DCACHE_INVAL_RANGE 3 #define ARMV7_DCACHE_CLEAN_INVAL_RANGE 4 -#ifndef CONFIG_SYS_DCACHE_OFF /* * Write the level and type you want to Cache Size Selection Register(CSSELR) * to get size details from Current Cache Size ID Register(CCSIDR) @@ -319,43 +318,7 @@ void flush_cache(unsigned long start, unsigned long size) { flush_dcache_range(start, start + size); } -#else /* #ifndef CONFIG_SYS_DCACHE_OFF */ -ulong dcache_get_line_size(void) -{ - return 0; -} - -void invalidate_dcache_all(void) -{ -} - -void flush_dcache_all(void) -{ -} - -void invalidate_dcache_range(unsigned long start, unsigned long stop) -{ -} -void flush_dcache_range(unsigned long start, unsigned long stop) -{ -} - -void arm_init_before_mmu(void) -{ -} - -void flush_cache(unsigned long start, unsigned long size) -{ -} - -void mmu_page_table_flush(unsigned long start, unsigned long stop) -{ -} - -#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */ - -#ifndef CONFIG_SYS_ICACHE_OFF /* Invalidate entire I-cache and branch predictor array */ void invalidate_icache_all(void) { @@ -374,54 +337,3 @@ void invalidate_icache_all(void) /* ISB - make sure the instruction stream sees it */ CP15ISB; } -#else -void invalidate_icache_all(void) -{ -} -#endif - -/* - * FIXME(dhendrix): had unexplainable compilation failure of weak symbols - * (in spite of having prototypes and whatnot)... ron's advice is "death - * to weak symbols!" - */ -#if 0 -/* - * Stub implementations for outer cache operations - */ -void __v7_outer_cache_enable(void) -{ -} -void v7_outer_cache_enable(void) - __attribute__((weak, alias("__v7_outer_cache_enable"))); - -void __v7_outer_cache_disable(void) -{ -} -void v7_outer_cache_disable(void) - __attribute__((weak, alias("__v7_outer_cache_disable"))); - -void __v7_outer_cache_flush_all(void) -{ -} -void v7_outer_cache_flush_all(void) - __attribute__((weak, alias("__v7_outer_cache_flush_all"))); - -void __v7_outer_cache_inval_all(void) -{ -} -void v7_outer_cache_inval_all(void) - __attribute__((weak, alias("__v7_outer_cache_inval_all"))); - -void __v7_outer_cache_flush_range(u32 start, u32 end) -{ -} -void v7_outer_cache_flush_range(u32 start, u32 end) - __attribute__((weak, alias("__v7_outer_cache_flush_range"))); - -void __v7_outer_cache_inval_range(u32 start, u32 end) -{ -} -void v7_outer_cache_inval_range(u32 start, u32 end) - __attribute__((weak, alias("__v7_outer_cache_inval_range"))); -#endif

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Patch set updated for coreboot: 41ffc6d armv7: nuke global_data.h and remove some references to gd struct
by David Hendricks 28 Jan '13

28 Jan '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2210 -gerrit commit 41ffc6d3e0fb939ea3b489e74d397e615c6ea0e9 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Jan 28 12:24:54 2013 -0800 armv7: nuke global_data.h and remove some references to gd struct This begins to remove references to global data which u-boot used. There are still many commented out references to gd-> and bd-> which we'll fix once we're happy with the replacements. Change-Id: Ie1b40a997e28a118f8f3ad96a2f9a2462d32fbe3 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/include/common.h | 3 - src/arch/armv7/include/global_data.h | 108 ------------------------------ src/arch/armv7/lib/cache-cp15.c | 11 +-- src/cpu/samsung/exynos5-common/spl_boot.c | 12 ---- 4 files changed, 3 insertions(+), 131 deletions(-) diff --git a/src/arch/armv7/include/common.h b/src/arch/armv7/include/common.h index a2cd9ae..5a27fc0 100644 --- a/src/arch/armv7/include/common.h +++ b/src/arch/armv7/include/common.h @@ -83,7 +83,6 @@ void __assert_fail(const char *assertion, const char *file, unsigned line, typedef void (interrupt_handler_t)(void *); //#include <asm/u-boot.h> /* boot information for Linux kernel */ -#include <global_data.h> /* global data used for startup functions */ /* * Return the time since boot in microseconds, This is needed for bootstage @@ -152,7 +151,6 @@ void reset_cmd_timeout(void); /* arch/$(ARCH)/lib/board.c */ void board_init_f (void); -void board_init_r (gd_t *, ulong) __attribute__ ((noreturn)); int checkboard (void); int checkflash (void); int checkdram (void); @@ -247,7 +245,6 @@ int dcache_status (void); void dcache_enable (void); void dcache_disable(void); void mmu_disable(void); -void relocate_code (ulong, gd_t *, ulong) __attribute__ ((noreturn)); ulong get_endaddr (void); void trap_init (ulong); #if defined (CONFIG_4xx) || \ diff --git a/src/arch/armv7/include/global_data.h b/src/arch/armv7/include/global_data.h deleted file mode 100644 index 4ae86aa..0000000 --- a/src/arch/armv7/include/global_data.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * (C) Copyright 2002-2010 - * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_GBL_DATA_H -#define __ASM_GBL_DATA_H - -/* - * The following data structure is placed in some memory which is - * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or - * some locked parts of the data cache) to allow for a minimum set of - * global variables during system initialization (until we have set - * up the memory controller so that we can use RAM). - * - * Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t) - */ - -typedef struct global_data { -// bd_t *bd; - unsigned long flags; - unsigned long baudrate; - unsigned long have_console; /* serial_init() was called */ -#ifdef CONFIG_PRE_CONSOLE_BUFFER - unsigned long precon_buf_idx; /* Pre-Console buffer index */ -#endif - unsigned long env_addr; /* Address of Environment struct */ - unsigned long env_valid; /* Checksum of Environment valid? */ - unsigned long fb_base; /* base address of frame buffer */ -#ifdef CONFIG_FSL_ESDHC - unsigned long sdhc_clk; -#endif -#ifdef CONFIG_AT91FAMILY - /* "static data" needed by at91's clock.c */ - unsigned long cpu_clk_rate_hz; - unsigned long main_clk_rate_hz; - unsigned long mck_rate_hz; - unsigned long plla_rate_hz; - unsigned long pllb_rate_hz; - unsigned long at91_pllb_usb_init; -#endif -#ifdef CONFIG_ARM - /* "static data" needed by most of timer.c on ARM platforms */ - unsigned long timer_rate_hz; - unsigned long tbl; - unsigned long tbu; - unsigned long long timer_reset_value; - unsigned long lastinc; -#endif -#ifdef CONFIG_IXP425 - unsigned long timestamp; -#endif - unsigned long relocaddr; /* Start address of U-Boot in RAM */ - unsigned long long ram_size; /* RAM size */ - unsigned long mon_len; /* monitor len */ - unsigned long irq_sp; /* irq stack pointer */ - unsigned long start_addr_sp; /* start_addr_stackpointer */ - unsigned long reloc_off; -#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) - unsigned long tlb_addr; - unsigned long tlb_size; -#endif - const void *fdt_blob; /* Our device tree, NULL if none */ -#ifdef CONFIG_SYS_SKIP_ARM_RELOCATION - ulong malloc_end; /* End of malloc region (addr + 1) */ -#endif - void **jt; /* jump table */ - char env_buf[32]; /* buffer for getenv() before reloc. */ -#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) - unsigned long post_log_word; /* Record POST activities */ - unsigned long post_log_res; /* success of POST test */ - unsigned long post_init_f_time; /* When post_init_f started */ -#endif -} gd_t; - -/* - * Global Data Flags - */ -#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ -#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ -#define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ -#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ -#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ -#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ -#define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */ - -#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r8") - -#endif /* __ASM_GBL_DATA_H */ diff --git a/src/arch/armv7/lib/cache-cp15.c b/src/arch/armv7/lib/cache-cp15.c index c684d65..221befa 100644 --- a/src/arch/armv7/lib/cache-cp15.c +++ b/src/arch/armv7/lib/cache-cp15.c @@ -24,9 +24,8 @@ #include <common.h> #include <stdlib.h> #include <system.h> -#include <global_data.h> -DECLARE_GLOBAL_DATA_PTR; +static unsigned int tlb_addr; static void cp_delay (void) { @@ -41,9 +40,7 @@ static void cp_delay (void) static void set_section_dcache(int section, enum dcache_option option) { u32 value = section << MMU_SECTION_SHIFT | (3 << 10); -// u32 *page_table = (u32 *)gd->tlb_addr; u32 *page_table; - unsigned int tlb_addr; unsigned int tlb_size = 4096 * 4; /* @@ -82,7 +79,7 @@ void __mmu_page_table_flush(unsigned long start, unsigned long stop) void mmu_set_region_dcache(unsigned long start, int size, enum dcache_option option) { - u32 *page_table = (u32 *)gd->tlb_addr; + u32 *page_table = &tlb_addr; u32 upto, end; end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT; @@ -113,8 +110,6 @@ static inline void dram_bank_mmu_setup(int bank) } #endif -/* FIXME(dhendrix): modified to take arguments from the caller (mainboard's - romstage.c) so it doesn't rely on global data struct */ /** * dram_bank_mmu_set - set up the data cache policy for a given dram bank * @@ -163,7 +158,7 @@ static inline void mmu_setup(void) /* Copy the page table address to cp15 */ asm volatile("mcr p15, 0, %0, c2, c0, 0" - : : "r" (gd->tlb_addr) : "memory"); + : : "r" (tlb_addr) : "memory"); /* Set the access control to all-supervisor */ asm volatile("mcr p15, 0, %0, c3, c0, 0" : : "r" (~0)); diff --git a/src/cpu/samsung/exynos5-common/spl_boot.c b/src/cpu/samsung/exynos5-common/spl_boot.c index ecff871..ddf6937 100644 --- a/src/cpu/samsung/exynos5-common/spl_boot.c +++ b/src/cpu/samsung/exynos5-common/spl_boot.c @@ -55,9 +55,6 @@ #include <arch/io.h> -/* FIXME(dhendrix): clean out u-boot global data stuff */ -//DECLARE_GLOBAL_DATA_PTR; - #define OM_STAT (0x1f << 1) /** @@ -344,15 +341,6 @@ void board_init_f(void) hlt(); } -/* Place Holders */ -void board_init_r(gd_t *id, ulong dest_addr) -{ - /* Function attribute is no-return */ - /* This Function never executes */ - while (1) - ; -} - //void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) {} #if 0

1 0

New patch to review for coreboot: bd77fb9 armv7: nuke global_data.h and remove some references to gd struct
by David Hendricks 28 Jan '13

28 Jan '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2210 -gerrit commit bd77fb9e99bbbb71d8a516f2b0a8dcd257afd72c Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Jan 28 12:24:54 2013 -0800 armv7: nuke global_data.h and remove some references to gd struct This begins to remove references to global data which u-boot used. There are still many commented out references to gd-> and bd-> which we'll fix once we're happy with the replacements. Change-Id: Ie1b40a997e28a118f8f3ad96a2f9a2462d32fbe3 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/include/common.h | 3 - src/arch/armv7/include/global_data.h | 108 ------------------------------ src/arch/armv7/lib/cache-cp15.c | 11 +-- src/cpu/samsung/exynos5-common/spl_boot.c | 12 ---- 4 files changed, 3 insertions(+), 131 deletions(-) diff --git a/src/arch/armv7/include/common.h b/src/arch/armv7/include/common.h index a2cd9ae..5a27fc0 100644 --- a/src/arch/armv7/include/common.h +++ b/src/arch/armv7/include/common.h @@ -83,7 +83,6 @@ void __assert_fail(const char *assertion, const char *file, unsigned line, typedef void (interrupt_handler_t)(void *); //#include <asm/u-boot.h> /* boot information for Linux kernel */ -#include <global_data.h> /* global data used for startup functions */ /* * Return the time since boot in microseconds, This is needed for bootstage @@ -152,7 +151,6 @@ void reset_cmd_timeout(void); /* arch/$(ARCH)/lib/board.c */ void board_init_f (void); -void board_init_r (gd_t *, ulong) __attribute__ ((noreturn)); int checkboard (void); int checkflash (void); int checkdram (void); @@ -247,7 +245,6 @@ int dcache_status (void); void dcache_enable (void); void dcache_disable(void); void mmu_disable(void); -void relocate_code (ulong, gd_t *, ulong) __attribute__ ((noreturn)); ulong get_endaddr (void); void trap_init (ulong); #if defined (CONFIG_4xx) || \ diff --git a/src/arch/armv7/include/global_data.h b/src/arch/armv7/include/global_data.h deleted file mode 100644 index 4ae86aa..0000000 --- a/src/arch/armv7/include/global_data.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * (C) Copyright 2002-2010 - * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_GBL_DATA_H -#define __ASM_GBL_DATA_H - -/* - * The following data structure is placed in some memory which is - * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or - * some locked parts of the data cache) to allow for a minimum set of - * global variables during system initialization (until we have set - * up the memory controller so that we can use RAM). - * - * Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t) - */ - -typedef struct global_data { -// bd_t *bd; - unsigned long flags; - unsigned long baudrate; - unsigned long have_console; /* serial_init() was called */ -#ifdef CONFIG_PRE_CONSOLE_BUFFER - unsigned long precon_buf_idx; /* Pre-Console buffer index */ -#endif - unsigned long env_addr; /* Address of Environment struct */ - unsigned long env_valid; /* Checksum of Environment valid? */ - unsigned long fb_base; /* base address of frame buffer */ -#ifdef CONFIG_FSL_ESDHC - unsigned long sdhc_clk; -#endif -#ifdef CONFIG_AT91FAMILY - /* "static data" needed by at91's clock.c */ - unsigned long cpu_clk_rate_hz; - unsigned long main_clk_rate_hz; - unsigned long mck_rate_hz; - unsigned long plla_rate_hz; - unsigned long pllb_rate_hz; - unsigned long at91_pllb_usb_init; -#endif -#ifdef CONFIG_ARM - /* "static data" needed by most of timer.c on ARM platforms */ - unsigned long timer_rate_hz; - unsigned long tbl; - unsigned long tbu; - unsigned long long timer_reset_value; - unsigned long lastinc; -#endif -#ifdef CONFIG_IXP425 - unsigned long timestamp; -#endif - unsigned long relocaddr; /* Start address of U-Boot in RAM */ - unsigned long long ram_size; /* RAM size */ - unsigned long mon_len; /* monitor len */ - unsigned long irq_sp; /* irq stack pointer */ - unsigned long start_addr_sp; /* start_addr_stackpointer */ - unsigned long reloc_off; -#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) - unsigned long tlb_addr; - unsigned long tlb_size; -#endif - const void *fdt_blob; /* Our device tree, NULL if none */ -#ifdef CONFIG_SYS_SKIP_ARM_RELOCATION - ulong malloc_end; /* End of malloc region (addr + 1) */ -#endif - void **jt; /* jump table */ - char env_buf[32]; /* buffer for getenv() before reloc. */ -#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) - unsigned long post_log_word; /* Record POST activities */ - unsigned long post_log_res; /* success of POST test */ - unsigned long post_init_f_time; /* When post_init_f started */ -#endif -} gd_t; - -/* - * Global Data Flags - */ -#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ -#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ -#define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ -#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ -#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ -#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ -#define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */ - -#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r8") - -#endif /* __ASM_GBL_DATA_H */ diff --git a/src/arch/armv7/lib/cache-cp15.c b/src/arch/armv7/lib/cache-cp15.c index c684d65..221befa 100644 --- a/src/arch/armv7/lib/cache-cp15.c +++ b/src/arch/armv7/lib/cache-cp15.c @@ -24,9 +24,8 @@ #include <common.h> #include <stdlib.h> #include <system.h> -#include <global_data.h> -DECLARE_GLOBAL_DATA_PTR; +static unsigned int tlb_addr; static void cp_delay (void) { @@ -41,9 +40,7 @@ static void cp_delay (void) static void set_section_dcache(int section, enum dcache_option option) { u32 value = section << MMU_SECTION_SHIFT | (3 << 10); -// u32 *page_table = (u32 *)gd->tlb_addr; u32 *page_table; - unsigned int tlb_addr; unsigned int tlb_size = 4096 * 4; /* @@ -82,7 +79,7 @@ void __mmu_page_table_flush(unsigned long start, unsigned long stop) void mmu_set_region_dcache(unsigned long start, int size, enum dcache_option option) { - u32 *page_table = (u32 *)gd->tlb_addr; + u32 *page_table = &tlb_addr; u32 upto, end; end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT; @@ -113,8 +110,6 @@ static inline void dram_bank_mmu_setup(int bank) } #endif -/* FIXME(dhendrix): modified to take arguments from the caller (mainboard's - romstage.c) so it doesn't rely on global data struct */ /** * dram_bank_mmu_set - set up the data cache policy for a given dram bank * @@ -163,7 +158,7 @@ static inline void mmu_setup(void) /* Copy the page table address to cp15 */ asm volatile("mcr p15, 0, %0, c2, c0, 0" - : : "r" (gd->tlb_addr) : "memory"); + : : "r" (tlb_addr) : "memory"); /* Set the access control to all-supervisor */ asm volatile("mcr p15, 0, %0, c3, c0, 0" : : "r" (~0)); diff --git a/src/cpu/samsung/exynos5-common/spl_boot.c b/src/cpu/samsung/exynos5-common/spl_boot.c index ecff871..ddf6937 100644 --- a/src/cpu/samsung/exynos5-common/spl_boot.c +++ b/src/cpu/samsung/exynos5-common/spl_boot.c @@ -55,9 +55,6 @@ #include <arch/io.h> -/* FIXME(dhendrix): clean out u-boot global data stuff */ -//DECLARE_GLOBAL_DATA_PTR; - #define OM_STAT (0x1f << 1) /** @@ -344,15 +341,6 @@ void board_init_f(void) hlt(); } -/* Place Holders */ -void board_init_r(gd_t *id, ulong dest_addr) -{ - /* Function attribute is no-return */ - /* This Function never executes */ - while (1) - ; -} - //void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) {} #if 0

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coreboot January 2013