coreboot September 2012

coreboot@coreboot.org

29 participants
134 discussions

by Steve Goodrich

Can coreboot load ROMs that are over 64KB in size? By way of example, consider an iPXE ROM that's about 70 KB (uncompressed). Thanks, -- Steve G.

8 years, 5 months

Re: [coreboot] are the pci devices scanned two rounds?

by 王思源

thank you! Marc what is the scheme of of the pci scanning? when a new pci device is detected, all the pci device are re-scanned? for example,bridge 00:14.4 is scanned two times. there is a vga device connected to this bridge and the vga is allocted different bus number in the scanning. so I don't think it is resonable. Thank youi! On Thu, Sep 27, 2012 at 1:15 AM, Marc Jones <marcj303(a)gmail.com> wrote: > On Wed, Sep 26, 2012 at 4:14 AM, 王思源 <wangsiyuanbuaa(a)gmail.com> wrote: >> it seems that the pci devices are scanned two rounds in our mainboard. >> first round: bus 0 -> bridge 00:14.4 -> bus 1 (this is the vga device >> under the bridge 00:14.4) >> second round: bus 0 -> bridge 00:02.0 -> bridge 00:04.0 -> bridge >> 00:05.0. this bridges are all pcie bridges. >> >> I want to know whether the two rounds scanning style is right. if it >> is designed to scan two rounds, why? >> any reply is helpful to me. >> thank you! >> > Yes, there are multiple steps in device tress and pci resource > discovery and allocation. > >> WANG Siyuan >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot > > > > -- > http://se-eng.com -- 王思源

8 years, 5 months

patch for superiotool/freebsd

by Andriy Gapon

Guys, It's been quite a while since I worked with any coreboot tools. I see that a lot has changed... I am posting a trivial FreeBSD-related patch here, but I am ready to follow the proper way if you give me a kick towards it :-) Thank you! diff --git a/util/superiotool/Makefile b/util/superiotool/Makefile index 41625d3..2388f4e 100644 --- a/util/superiotool/Makefile +++ b/util/superiotool/Makefile @@ -41,7 +41,7 @@ LIBS = -framework IOKit -framework DirectHW -lpci -lz endif ifeq ($(OS_ARCH), FreeBSD) CFLAGS = -O2 -Wall -Werror -Wstrict-prototypes -Wundef -Wstrict-aliasing \ - -Werror-implicit-function-declaration -ansi $(SVNDEF) \ + -Werror-implicit-function-declaration -ansi $(VERSION) \ -I/usr/local/include LDFLAGS += -L/usr/local/lib LIBS = -lz -- Andriy Gapon

8 years, 5 months

Patch merged into coreboot/master: a8649ba libpayload: Extend CMOS access library

by gerrit＠coreboot.org

the following patch was just integrated into master: commit a8649ba43bcaef355b75ef9e11048342fa03ce71 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Mon Sep 24 20:06:27 2012 +0200 libpayload: Extend CMOS access library libpayload already contained a number of functions for convenient access to CMOS configuration. Add functions to support iteration over available enum fields. Change-Id: If95f45d7223d2e19c42f1d8680c12d23f6890a01 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Build-Tested: build bot (Jenkins) at Tue Sep 25 12:19:35 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Wed Sep 26 00:20:51 2012, giving +2 See http://review.coreboot.org/1538 for details. -gerrit

8 years, 5 months

New patch to review for coreboot: 83a039f libpayload: Set 8bits per char for serial port

by Anton Kochkov

Anton Kochkov (anton.kochkov(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1541 -gerrit commit 83a039fde2ec1516d0b38971b1e9db1605f38745 Author: Anton Kochkov <anton.kochkov(a)gmail.com> Date: Wed Sep 26 22:31:04 2012 +0400 libpayload: Set 8bits per char for serial port Previously we assume that hardware using 8 bits per char by default, but on Asrock A53 Pro this is not true (7 bit per char by default). Forcing use 8n1 now. Change-Id: Ib701725d2ec6dacd7862016b2045270956b27029 Signed-off-by: Anton Kochkov <anton.kochkov(a)gmail.com> --- payloads/libpayload/drivers/serial.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/payloads/libpayload/drivers/serial.c b/payloads/libpayload/drivers/serial.c index c6804d2..0f79b52 100644 --- a/payloads/libpayload/drivers/serial.c +++ b/payloads/libpayload/drivers/serial.c @@ -40,8 +40,6 @@ static void serial_io_hardware_init(int port, int speed, int word_bits, int pari { unsigned char reg; - /* We will assume 8n1 for now. Does anyone use anything else these days? */ - /* Disable interrupts. */ outb(0, port + 0x01); @@ -56,8 +54,9 @@ static void serial_io_hardware_init(int port, int speed, int word_bits, int pari outb(DIVISOR(speed) & 0xFF, port); outb(DIVISOR(speed) >> 8 & 0xFF, port + 1); - /* Restore the previous value of the divisor. */ - outb(reg & ~0x80, port + 0x03); + /* Restore the previous value of the divisor. + * And set 8 bits per character */ + outb((reg & ~0x80) | 3, port + 0x03); } static void serial_mem_hardware_init(int port, int speed, int word_bits, int parity, int stop_bits) @@ -80,8 +79,9 @@ static void serial_mem_hardware_init(int port, int speed, int word_bits, int par writeb(DIVISOR(speed) & 0xFF, MEMBASE); writeb(DIVISOR(speed) >> 8 & 0xFF, MEMBASE + 1); - /* Restore the previous value of the divisor. */ - writeb(reg & ~0x80, MEMBASE + 0x03); + /* Restore the previous value of the divisor. + * And set 8 bits per character */ + writeb((reg & ~0x80) | 3, MEMBASE + 0x03); } #endif

8 years, 5 months

New patch to review for coreboot: 18ae0cc Mainboard: Fix IO-HUB link number in Dinar mainboard

by Aladyshev Konstantin

Aladyshev Konstantin (kostr(a)list.ru) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1540 -gerrit commit 18ae0cc9515987ce5725185f6b7f99fd0d9a3a2b Author: Kostr <aladyshev(a)nicevt.ru> Date: Wed Sep 26 22:11:20 2012 +0400 Mainboard: Fix IO-HUB link number in Dinar mainboard According to file "northbridge.c" in family 15h code IO-HUB should be placed on link_lsit[0] in devicetree.cb. This hack in "northbridge.c" was made to satisfy both f10 and f15 cpu's. Change-Id: I4754235bd38239460347b0dc4a82cd4e58ae7cd0 Signed-off-by: Kostr <aladyshev(a)nicevt.ru> --- src/mainboard/amd/dinar/devicetree.cb | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/mainboard/amd/dinar/devicetree.cb b/src/mainboard/amd/dinar/devicetree.cb index 92fe521..3211a2f 100644 --- a/src/mainboard/amd/dinar/devicetree.cb +++ b/src/mainboard/amd/dinar/devicetree.cb @@ -26,8 +26,7 @@ chip northbridge/amd/agesa/family15/root_complex device pci_domain 0 on subsystemid 0x1022 0x1705 inherit chip northbridge/amd/agesa/family15 # CPU side of HT root complex - device pci 18.0 on end # Link 0 - device pci 18.0 on # Link 1, IO-HUB on socket0 link 2(internal Node0 Link 1) + device pci 18.0 on # Put IO-HUB at link_num 0, Instead of HT Link topology to satisfy both f10 and f15 CPUs chip northbridge/amd/cimx/rd890 # North Bridge PCI side of HT Root complex device pci 0.0 on end # HT Root Complex device pci 0.1 off end # CLKCONFIG

8 years, 5 months

Re: [coreboot] are the pci devices scanned two rounds?

by Marc Jones

On Wed, Sep 26, 2012 at 4:14 AM, 王思源 <wangsiyuanbuaa(a)gmail.com> wrote: > it seems that the pci devices are scanned two rounds in our mainboard. > first round: bus 0 -> bridge 00:14.4 -> bus 1 (this is the vga device > under the bridge 00:14.4) > second round: bus 0 -> bridge 00:02.0 -> bridge 00:04.0 -> bridge > 00:05.0. this bridges are all pcie bridges. > > I want to know whether the two rounds scanning style is right. if it > is designed to scan two rounds, why? > any reply is helpful to me. > thank you! > Yes, there are multiple steps in device tress and pci resource discovery and allocation. > WANG Siyuan > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot -- http://se-eng.com

8 years, 5 months

are the pci devices scanned two rounds?

by 王思源

it seems that the pci devices are scanned two rounds in our mainboard. first round: bus 0 -> bridge 00:14.4 -> bus 1 (this is the vga device under the bridge 00:14.4) second round: bus 0 -> bridge 00:02.0 -> bridge 00:04.0 -> bridge 00:05.0. this bridges are all pcie bridges. I want to know whether the two rounds scanning style is right. if it is designed to scan two rounds, why? any reply is helpful to me. thank you! the log is shown as fallow, the message unrelated to pci is cut. scan_static_bus for Root Device APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 scanning... PCI: 00:18.5 family15h, core_max=0x10, core_nums=0xf, siblings=0x7 lpaicid_start=0x10 node 0x0 core 0x0 apicid=0x10 CPU: APIC: 10 enabled lpaicid_start=0x10 node 0x0 core 0x1 apicid=0x11 CPU: APIC: 11 enabled lpaicid_start=0x10 node 0x0 core 0x2 apicid=0x12 CPU: APIC: 12 enabled lpaicid_start=0x10 node 0x0 core 0x3 apicid=0x13 CPU: APIC: 13 enabled lpaicid_start=0x10 node 0x0 core 0x4 apicid=0x14 CPU: APIC: 14 enabled lpaicid_start=0x10 node 0x0 core 0x5 apicid=0x15 CPU: APIC: 15 enabled lpaicid_start=0x10 node 0x0 core 0x6 apicid=0x16 CPU: APIC: 16 enabled lpaicid_start=0x10 node 0x0 core 0x7 apicid=0x17 CPU: APIC: 17 enabled PCI: 00:19.0 [1022/1600] bus ops PCI: 00:19.0 [1022/1600] enabled PCI: 00:19.1 [1022/1601] enabled PCI: 00:19.2 [1022/1602] enabled PCI: 00:19.3 [1022/1603] enabled PCI: 00:19.4 [1022/1604] enabled PCI: 00:19.5 [1022/1605] enabled PCI: 00:19.5 family15h, core_max=0x10, core_nums=0xf, siblings=0x7 lpaicid_start=0x10 node 0x1 core 0x0 apicid=0x18 CPU: APIC: 18 enabled lpaicid_start=0x10 node 0x1 core 0x1 apicid=0x19 CPU: APIC: 19 enabled lpaicid_start=0x10 node 0x1 core 0x2 apicid=0x1a CPU: APIC: 1a enabled lpaicid_start=0x10 node 0x1 core 0x3 apicid=0x1b CPU: APIC: 1b enabled lpaicid_start=0x10 node 0x1 core 0x4 apicid=0x1c CPU: APIC: 1c enabled lpaicid_start=0x10 node 0x1 core 0x5 apicid=0x1d CPU: APIC: 1d enabled lpaicid_start=0x10 node 0x1 core 0x6 apicid=0x1e CPU: APIC: 1e enabled lpaicid_start=0x10 node 0x1 core 0x7 apicid=0x1f CPU: APIC: 1f enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [1002/5a10] ops PCI: 00:00.0 [1002/5a10] enabled PCI: 00:11.0 [1002/4390] ops PCI: 00:11.0 [1002/4390] enabled PCI: 00:12.0 [1002/4397] ops PCI: 00:12.0 [1002/4397] enabled PCI: 00:12.1 [1002/4398] ops PCI: 00:12.1 [1002/4398] enabled PCI: 00:12.2 [1002/4396] ops PCI: 00:12.2 [1002/4396] enabled PCI: 00:13.0 [1002/4397] ops PCI: 00:13.0 [1002/4397] enabled PCI: 00:13.1 [1002/4398] ops PCI: 00:13.1 [1002/4398] enabled PCI: 00:13.2 [1002/4396] ops PCI: 00:13.2 [1002/4396] enabled PCI: 00:14.0 [1002/4385] enabled PCI: 00:14.1 [1002/439c] enabled PCI: 00:14.2 [1002/4383] ops PCI: 00:14.2 [1002/4383] enabled PCI: 00:14.3 [1002/439d] bus ops PCI: 00:14.3 [1002/439d] enabled PCI: 00:14.4 [1002/4384] bus ops PCI: 00:14.4 [1002/4384] enabled PCI: 00:14.5 [1002/4399] ops PCI: 00:14.5 [1002/4399] enabled PCI: 00:18.0 [1022/1600] bus ops PCI: 00:18.0 [1022/1600] enabled PCI: 00:18.1 [1022/1601] enabled PCI: 00:18.2 [1022/1602] enabled PCI: 00:18.3 [1022/1603] enabled PCI: 00:18.4 [1022/1604] enabled PCI: 00:18.5 [1022/1605] enabled PCI: 00:19.0 [1022/1600] enabled PCI: 00:19.1 [1022/1601] enabled PCI: 00:19.2 [1022/1602] enabled PCI: 00:19.3 [1022/1603] enabled PCI: 00:19.4 [1022/1604] enabled PCI: 00:19.5 [1022/1605] enabled scan_static_bus for PCI: 00:14.3 scan_static_bus for PCI: 00:14.3 done do_pci_scan_bridge for PCI: 00:14.4 PCI: pci_scan_bus for bus 01 PCI: Using configuration type 1 PCI: 01:00.0 [1a03/2000] enabled PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 PCI: pci_scan_bus for bus 00 rd890_enable Bus-0 Dev-0 Fun-0, enable=1 [NBPCIE] PortId 02 LinkState = 0x0 [NBPCIE] PortId 04 LinkState = 0x0 [NBPCIE] PortId 08 LinkState = 0x10 [NBPCIE] PortId 09 LinkState = 0x10 [NBPCIE] PortId 10 LinkState = 0x4 [NBPCIE] PortId 11 LinkState = 0x0 [NBPCIE] PortId 13 LinkState = 0x10 [NBPCIE] PortId 02 LinkState = 0x0 [NBPCIE] PortId 04 LinkState = 0x0 [NBPCIE] PortId 08 LinkState = 0x10 [NBPCIE] PortId 09 LinkState = 0x10 [NBPCIE] PortId 10 LinkState = 0x4 [NBPCIE] PortId 11 LinkState = 0x0 [NBPCIE] PortId 13 LinkState = 0x10 PCI: 00:00.0 [1002/5a10] ops PCI: 00:00.0 [1002/5a10] enabled rd890_enable Bus-0 Dev-0 Fun-1, enable=0 rd890_enable Bus-0 Dev-2 Fun-0, enable=1 PCI: 00:02.0 subordinate bus PCI Express PCI: 00:02.0 [1002/5a16] enabled rd890_enable Bus-0 Dev-3 Fun-0, enable=0 rd890_enable Bus-0 Dev-4 Fun-0, enable=1 PCI: 00:04.0 subordinate bus PCI Express PCI: 00:04.0 [1002/5a18] enabled rd890_enable Bus-0 Dev-5 Fun-0, enable=1 PCI: 00:05.0 subordinate bus PCI Express PCI: 00:05.0 [1002/5a19] enabled rd890_enable Bus-0 Dev-6 Fun-0, enable=1 PCI: 00:06.0 subordinate bus PCI Express PCI: 00:06.0 [1002/5a1a] enabled rd890_enable Bus-0 Dev-7 Fun-0, enable=1 PCI: 00:07.0 subordinate bus PCI Express PCI: 00:07.0 [1002/5a1b] enabled rd890_enable Bus-0 Dev-8 Fun-0, enable=0 rd890_enable Bus-0 Dev-9 Fun-0, enable=1 PCI: 00:09.0 subordinate bus PCI Express PCI: 00:09.0 [1002/5a1c] enabled rd890_enable Bus-0 Dev-A Fun-0, enable=1 PCI: 00:0a.0 subordinate bus PCI Express PCI: 00:0a.0 [1002/5a1d] enabled rd890_enable Bus-0 Dev-B Fun-0, enable=1 PCI: 00:0b.0 subordinate bus PCI Express PCI: 00:0b.0 [1002/5a1f] enabled rd890_enable Bus-0 Dev-C Fun-0, enable=0 rd890_enable Bus-0 Dev-D Fun-0, enable=1 PCI: 00:0d.0 subordinate bus PCI Express PCI: 00:0d.0 [1002/5a1e] enabled sb700_enable() SB700 - Cfg.c - sb700_cimx_config - Start. SB700 - Cfg.c - sb700_cimx_config - End. PCI: 00:11.0 [1002/4390] ops PCI: 00:11.0 [1002/4390] enabled sb700_enable() PCI: 00:12.0 [1002/4397] ops PCI: 00:12.0 [1002/4397] enabled sb700_enable() PCI: 00:12.1 [1002/4398] ops PCI: 00:12.1 [1002/4398] enabled sb700_enable() PCI: 00:12.2 [1002/4396] ops PCI: 00:12.2 [1002/4396] enabled sb700_enable() PCI: 00:13.0 [1002/4397] ops PCI: 00:13.0 [1002/4397] enabled sb700_enable() PCI: 00:13.1 [1002/4398] ops PCI: 00:13.1 [1002/4398] enabled sb700_enable() PCI: 00:13.2 [1002/4396] ops PCI: 00:13.2 [1002/4396] enabled sb700_enable() sm_init(). I PCI: 00:14.0 [1002/4385] enabled sb700_enable() PCI: 00:14.1 [1002/439c] disabled sb700_enable() hda disabled PCI: 00:14.2 [1002/4383] ops PCI: 00:14.2 [1002/4383] disabled sb700_enable() PCI: 00:14.3 [1002/439d] bus ops PCI: 00:14.3 [1002/439d] enabled sb700_enable() PCI: 00:14.4 [1002/4384] bus ops PCI: 00:14.4 [1002/4384] enabled sb700_enable() sb700 sb_Before_Pci_Init Start SB700 - Late.c - sb700_callout_entry - Start. SB700 - Late.c - sb700_callout_entry - End. SB700 - Late.c - sb700_callout_entry - Start. SB700 - Late.c - sb700_callout_entry - End. sb700 sb_Before_Pci_Init End PCI: 00:14.5 [1002/4399] ops PCI: 00:14.5 [1002/4399] enabled do_pci_scan_bridge for PCI: 00:02.0 PCI: pci_scan_bus for bus 01 PCI: 01:00.0 [1a03/2000] enabled PCI: pci_scan_bus returning with max=001 Capability: type 0x01 @ 0x40 do_pci_scan_bridge returns max 1 do_pci_scan_bridge for PCI: 00:04.0 PCI: pci_scan_bus for bus 02 PCI: pci_scan_bus returning with max=002 do_pci_scan_bridge returns max 2 do_pci_scan_bridge for PCI: 00:05.0 PCI: pci_scan_bus for bus 03 PCI: pci_scan_bus returning with max=003 do_pci_scan_bridge returns max 3 do_pci_scan_bridge for PCI: 00:06.0 PCI: pci_scan_bus for bus 04 PCI: pci_scan_bus returning with max=004 do_pci_scan_bridge returns max 4 do_pci_scan_bridge for PCI: 00:07.0 PCI: pci_scan_bus for bus 05 PCI: pci_scan_bus returning with max=005 do_pci_scan_bridge returns max 5 do_pci_scan_bridge for PCI: 00:09.0 PCI: pci_scan_bus for bus 06 PCI: 06:00.0 [8086/10d3] enabled PCI: pci_scan_bus returning with max=006 Capability: type 0x01 @ 0xc8 Capability: type 0x05 @ 0xd0 Capability: type 0x10 @ 0xe0 do_pci_scan_bridge returns max 6 do_pci_scan_bridge for PCI: 00:0a.0 PCI: pci_scan_bus for bus 07 PCI: pci_scan_bus returning with max=007 do_pci_scan_bridge returns max 7 do_pci_scan_bridge for PCI: 00:0b.0 PCI: pci_scan_bus for bus 08 PCI: pci_scan_bus returning with max=008 do_pci_scan_bridge returns max 8 do_pci_scan_bridge for PCI: 00:0d.0 PCI: pci_scan_bus for bus 09 PCI: 09:00.0 [8086/10c9] enabled PCI: 09:00.1 [8086/10c9] enabled PCI: pci_scan_bus returning with max=009 do_pci_scan_bridge returns max 9 scan_static_bus for PCI: 00:14.3 PNP: 002e.0 disabled PNP: 002e.1 disabled PNP: 002e.2 enabled PNP: 002e.3 enabled PNP: 002e.5 enabled PNP: 002e.6 disabled PNP: 002e.307 disabled PNP: 002e.8 disabled PNP: 002e.9 disabled PNP: 002e.109 disabled PNP: 002e.209 disabled PNP: 002e.309 disabled PNP: 002e.a disabled PNP: 002e.b disabled PNP: 002e.c disabled PNP: 005e.0 enabled scan_static_bus for PCI: 00:14.3 done do_pci_scan_bridge for PCI: 00:14.4 PCI: pci_scan_bus for bus 0a PCI: 0a:00.0 [1a03/2000] enabled PCI: pci_scan_bus returning with max=00a do_pci_scan_bridge returns max 10 PCI: pci_scan_bus returning with max=00a PCI: pci_scan_bus returning with max=00a scan_static_bus for Root Device done done -- WANG Siyuan

8 years, 5 months

Patch merged into coreboot/master: f787076 HAVE_HIGH_TABLES is gone

by gerrit＠coreboot.org

the following patch was just integrated into master: commit f7870767f5a5b82ec2eeb14afc0e7d7740bf4652 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Mon Sep 24 20:56:13 2012 +0200 HAVE_HIGH_TABLES is gone ... but no-one told intel/sch. Change-Id: I68eaae6910bd6fc579c35b5bc038b9597cd1b3e7 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Build-Tested: build bot (Jenkins) at Tue Sep 25 12:06:47 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Sep 25 16:09:19 2012, giving +2 See http://review.coreboot.org/1537 for details. -gerrit

8 years, 5 months

Patch merged into coreboot/master: 1fc1ca9 abuild: abort if payload.sh failed

by gerrit＠coreboot.org

the following patch was just integrated into master: commit 1fc1ca9986ad93f30eb82d23e8024a04398ea17f Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Mon Sep 24 20:52:42 2012 +0200 abuild: abort if payload.sh failed With this chance it becomes practical to have payload.sh build/update the payload, and abort abuild if something bad happened. Change-Id: Iee25de2e8b62153c477b8e5d32e097b59797523c Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Build-Tested: build bot (Jenkins) at Tue Sep 25 11:53:51 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Sep 25 16:08:53 2012, giving +2 See http://review.coreboot.org/1536 for details. -gerrit

8 years, 5 months

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coreboot September 2012