coreboot July 2012

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New patch to review for coreboot: 07e3a91 PCI Type2 config must die
by Ronald G. Minnich 02 Jul '12

02 Jul '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1159 -gerrit commit 07e3a917ccd6db641f7b3406abda3c9f46089749 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Mon Jul 2 09:41:10 2012 -0700 PCI Type2 config must die PCI Type 2 config was a strange and never-used config mechanism. It is unlikely that in the 13 years of coreboot's existence that type 2 was ever used; it just made life complicated for everyone. It lived long enough in coreboot to be replaced by mmioconf. Prior to making the device tree visible in romstage we want to get rid of type2. Delete two files we don't need any more (yay!). Replace two functions with one: pci_config_default, which returns a pointer to the default config method. At some future time this may change to mmio but for now it is old type1 style. Change-Id: Icc4ccf379a89bfca8be43f305b68ab45d88bf0ab Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/x86/include/arch/pci_ops.h | 7 +- src/arch/x86/lib/Makefile.inc | 1 - src/arch/x86/lib/pci_ops_auto.c | 107 ----------------------------------- src/arch/x86/lib/pci_ops_conf2.c | 80 -------------------------- src/devices/oprom/x86_interrupts.c | 2 - src/include/device/pci.h | 2 +- src/include/device/pci_ops.h | 3 - 7 files changed, 5 insertions(+), 197 deletions(-) diff --git a/src/arch/x86/include/arch/pci_ops.h b/src/arch/x86/include/arch/pci_ops.h index 955ccd3..84b1034 100644 --- a/src/arch/x86/include/arch/pci_ops.h +++ b/src/arch/x86/include/arch/pci_ops.h @@ -2,12 +2,13 @@ #define ARCH_I386_PCI_OPS_H extern const struct pci_bus_operations pci_cf8_conf1; -extern const struct pci_bus_operations pci_cf8_conf2; #if CONFIG_MMCONF_SUPPORT extern const struct pci_bus_operations pci_ops_mmconf; #endif -void pci_set_method(device_t dev); - +static inline const struct pci_bus_operations *pci_config_default(void) +{ + return &pci_cf8_conf1; +} #endif /* ARCH_I386_PCI_OPS_H */ diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index 4375952..2186072 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -3,7 +3,6 @@ ramstage-y += cpu.c ramstage-y += pci_ops_conf1.c ramstage-$(CONFIG_PCI_CONF2) += pci_ops_conf2.c ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c -ramstage-y += pci_ops_auto.c ramstage-y += exception.c ramstage-$(CONFIG_IOAPIC) += ioapic.c ramstage-y += memset.c diff --git a/src/arch/x86/lib/pci_ops_auto.c b/src/arch/x86/lib/pci_ops_auto.c deleted file mode 100644 index 58e098b..0000000 --- a/src/arch/x86/lib/pci_ops_auto.c +++ /dev/null @@ -1,107 +0,0 @@ -#include <stddef.h> -#include <console/console.h> -#include <arch/io.h> -#include <arch/pciconf.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> - -#if CONFIG_PCI_CONF2 -/* - * Before we decide to use direct hardware access mechanisms, we try to do some - * trivial checks to ensure it at least _seems_ to be working -- we just test - * whether bus 00 contains a host bridge (this is similar to checking - * techniques used in XFree86, but ours should be more reliable since we - * attempt to make use of direct access hints provided by the PCI BIOS). - * - * This should be close to trivial, but it isn't, because there are buggy - * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID. - */ -static int pci_sanity_check(const struct pci_bus_operations *o) -{ - uint16_t class, vendor; - unsigned bus; - int devfn; - struct bus pbus; /* Dummy device */ -#define PCI_CLASS_BRIDGE_HOST 0x0600 -#define PCI_CLASS_DISPLAY_VGA 0x0300 -#define PCI_VENDOR_ID_COMPAQ 0x0e11 -#define PCI_VENDOR_ID_INTEL 0x8086 -#define PCI_VENDOR_ID_MOTOROLA 0x1057 - - for (bus = 0, devfn = 0; devfn < 0x100; devfn++) { - class = o->read16(&pbus, bus, devfn, PCI_CLASS_DEVICE); - vendor = o->read16(&pbus, bus, devfn, PCI_VENDOR_ID); - if (((class == PCI_CLASS_BRIDGE_HOST) || (class == PCI_CLASS_DISPLAY_VGA)) || - ((vendor == PCI_VENDOR_ID_INTEL) || (vendor == PCI_VENDOR_ID_COMPAQ) || - (vendor == PCI_VENDOR_ID_MOTOROLA))) { - return 1; - } - } - printk(BIOS_ERR, "PCI: Sanity check failed\n"); - return 0; -} - -static struct pci_bus_operations *pci_bus_fallback_ops = NULL; - -static const struct pci_bus_operations *pci_check_direct(void) -{ - unsigned int tmp; - - /* - * Check if configuration type 1 works. - */ - { - outb(0x01, 0xCFB); - tmp = inl(0xCF8); - outl(0x80000000, 0xCF8); - if ((inl(0xCF8) == 0x80000000) && - pci_sanity_check(&pci_cf8_conf1)) - { - outl(tmp, 0xCF8); - printk(BIOS_DEBUG, "PCI: Using configuration type 1\n"); - return &pci_cf8_conf1; - } - outl(tmp, 0xCF8); - } - - /* - * Check if configuration type 2 works. - */ - { - outb(0x00, 0xCFB); - outb(0x00, 0xCF8); - outb(0x00, 0xCFA); - if ((inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00) && - pci_sanity_check(&pci_cf8_conf2)) - { - printk(BIOS_DEBUG, "PCI: Using configuration type 2\n"); - return &pci_cf8_conf2; - } - } - - die("pci_check_direct failed\n"); - return NULL; -} - -const struct pci_bus_operations *pci_remember_direct(void) -{ - if (!pci_bus_fallback_ops) - pci_bus_fallback_ops = (struct pci_bus_operations *)pci_check_direct(); - return pci_bus_fallback_ops; -} -#else -const struct pci_bus_operations *pci_remember_direct(void) -{ - return &pci_cf8_conf1; -} -#endif - -/** Set the method to be used for PCI, type I or type II - */ -void pci_set_method(device_t dev) -{ - printk(BIOS_INFO, "Finding PCI configuration type.\n"); - dev->ops->ops_pci_bus = pci_remember_direct(); - post_code(0x5f); -} diff --git a/src/arch/x86/lib/pci_ops_conf2.c b/src/arch/x86/lib/pci_ops_conf2.c deleted file mode 100644 index e89c933..0000000 --- a/src/arch/x86/lib/pci_ops_conf2.c +++ /dev/null @@ -1,80 +0,0 @@ -#include <console/console.h> -#include <arch/io.h> -#include <arch/pciconf.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -/* - * Functions for accessing PCI configuration space with type 2 accesses - */ - -#define IOADDR(devfn, where) ((0xC000 | ((devfn & 0x78) << 5)) + where) -#define FUNC(devfn) (((devfn & 7) << 1) | 0xf0) -#define SET(bus,devfn) outb(FUNC(devfn), 0xCF8); outb(bus, 0xCFA); - -static uint8_t pci_conf2_read_config8(struct bus *pbus, int bus, int devfn, - int where) -{ - uint8_t value; - SET(bus, devfn); - value = inb(IOADDR(devfn, where)); - outb(0, 0xCF8); - return value; -} - -static uint16_t pci_conf2_read_config16(struct bus *pbus, int bus, int devfn, - int where) -{ - uint16_t value; - SET(bus, devfn); - value = inw(IOADDR(devfn, where)); - outb(0, 0xCF8); - return value; -} - -static uint32_t pci_conf2_read_config32(struct bus *pbus, int bus, int devfn, - int where) -{ - uint32_t value; - SET(bus, devfn); - value = inl(IOADDR(devfn, where)); - outb(0, 0xCF8); - return value; -} - -static void pci_conf2_write_config8(struct bus *pbus, int bus, int devfn, - int where, uint8_t value) -{ - SET(bus, devfn); - outb(value, IOADDR(devfn, where)); - outb(0, 0xCF8); -} - -static void pci_conf2_write_config16(struct bus *pbus, int bus, int devfn, - int where, uint16_t value) -{ - SET(bus, devfn); - outw(value, IOADDR(devfn, where)); - outb(0, 0xCF8); -} - -static void pci_conf2_write_config32(struct bus *pbus, int bus, int devfn, - int where, uint32_t value) -{ - SET(bus, devfn); - outl(value, IOADDR(devfn, where)); - outb(0, 0xCF8); -} - -#undef SET -#undef IOADDR -#undef FUNC - -const struct pci_bus_operations pci_cf8_conf2 = { - .read8 = pci_conf2_read_config8, - .read16 = pci_conf2_read_config16, - .read32 = pci_conf2_read_config32, - .write8 = pci_conf2_write_config8, - .write16 = pci_conf2_write_config16, - .write32 = pci_conf2_write_config32, -}; diff --git a/src/devices/oprom/x86_interrupts.c b/src/devices/oprom/x86_interrupts.c index bada546..2ea05d4 100644 --- a/src/devices/oprom/x86_interrupts.c +++ b/src/devices/oprom/x86_interrupts.c @@ -114,9 +114,7 @@ int int16_handler(struct eregs *regs) } #define PCI_CONFIG_SPACE_TYPE1 (1 << 0) -#define PCI_CONFIG_SPACE_TYPE2 (1 << 1) #define PCI_SPECIAL_CYCLE_TYPE1 (1 << 4) -#define PCI_SPECIAL_CYCLE_TYPE2 (1 << 5) int int1a_handler(struct eregs *regs) { diff --git a/src/include/device/pci.h b/src/include/device/pci.h index e864d6d..51d5283 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -100,7 +100,7 @@ static inline const struct pci_bus_operations *ops_pci_bus(struct bus *bus) bops = bus->dev->ops->ops_pci_bus; } if (!bops) - bops = pci_remember_direct(); + bops = pci_config_default(); return bops; } diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index e5e54b6..2efbf9d 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -21,7 +21,4 @@ void pci_mmio_write_config16(device_t dev, unsigned int where, u16 val); void pci_mmio_write_config32(device_t dev, unsigned int where, u32 val); #endif -/* This function lives in pci_ops_auto.c */ -const struct pci_bus_operations *pci_remember_direct(void); - #endif /* PCI_OPS_H */

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Patch set updated for coreboot: e0964bb Use broadcast SIPI to startup siblings
by Sven Schnelle 02 Jul '12

02 Jul '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1139 -gerrit commit e0964bb5d09604ee29be453a353364e593899410 Author: Sven Schnelle <svens(a)stackframe.org> Date: Sun Jun 17 10:32:55 2012 +0200 Use broadcast SIPI to startup siblings The current code for initializing AP cpus has several shortcomings: - it assumes APIC IDs are sequential - it uses only the BSP for determining the AP count, which is bad if there's more than one physical CPU, and CPUs are of different type Note that the new code call cpu->ops->init() in parallel, and therefore some CPU code needs to be changed to address that. One example are old Intel HT enabled CPUs which can't do microcode update in parallel. Change-Id: Ic48a1ebab6a7c52aa76765f497268af09fa38c25 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/arch/x86/Kconfig | 4 - src/arch/x86/include/arch/cpu.h | 24 -- src/arch/x86/lib/cpu.c | 35 ++- src/cpu/intel/hyperthreading/Makefile.inc | 1 - src/cpu/intel/hyperthreading/intel_sibling.c | 73 ----- src/cpu/intel/model_1067x/model_1067x_init.c | 4 - src/cpu/intel/model_106cx/Kconfig | 1 - src/cpu/intel/model_106cx/model_106cx_init.c | 4 - src/cpu/intel/model_206ax/Kconfig | 1 - src/cpu/intel/model_206ax/acpi.c | 9 +- src/cpu/intel/model_206ax/model_206ax_init.c | 55 ---- src/cpu/intel/model_6ex/Kconfig | 1 - src/cpu/intel/model_6ex/model_6ex_init.c | 3 - src/cpu/intel/model_6fx/Kconfig | 1 - src/cpu/intel/model_6fx/model_6fx_init.c | 3 - src/cpu/intel/model_f2x/model_f2x_init.c | 4 - src/cpu/intel/model_f3x/model_f3x_init.c | 4 - src/cpu/intel/model_f4x/model_f4x_init.c | 4 - src/cpu/intel/socket_LGA771/Kconfig | 1 - src/cpu/x86/lapic/lapic_cpu_init.c | 369 +++++--------------------- src/cpu/x86/lapic/secondary.S | 20 +- src/cpu/x86/pae/pgtbl.c | 12 + src/drivers/i2c/w83795/w83795.c | 5 +- src/include/cpu/cpu.h | 6 +- src/include/cpu/x86/lapic.h | 15 +- src/include/device/path.h | 1 + 26 files changed, 136 insertions(+), 524 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 6d56ec6..4dfbe70 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -3,10 +3,6 @@ menu "Architecture (x86)" # This is an SMP option. It relates to starting up APs. # It is usually set in mainboard/*/Kconfig. # TODO: Improve description. -config AP_IN_SIPI_WAIT - bool - default n - depends on ARCH_X86 # Aligns 16bit entry code in bootblock so that hyper-threading CPUs # can boot AP CPUs to enable their shared caches. diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 0dc92fb..0fe5ea5 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -158,30 +158,6 @@ struct cpu_driver { struct device; struct cpu_driver *find_cpu_driver(struct device *cpu); -struct cpu_info { - device_t cpu; - unsigned long index; -}; - -static inline struct cpu_info *cpu_info(void) -{ - struct cpu_info *ci; - __asm__("andl %%esp,%0; " - "orl %2, %0 " - :"=r" (ci) - : "0" (~(CONFIG_STACK_SIZE - 1)), - "r" (CONFIG_STACK_SIZE - sizeof(struct cpu_info)) - ); - return ci; -} - -static inline unsigned long cpu_index(void) -{ - struct cpu_info *ci; - ci = cpu_info(); - return ci->index; -} - struct cpuinfo_x86 { uint8_t x86; /* CPU family */ uint8_t x86_vendor; /* CPU vendor */ diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c index 98ede06..2d64be9 100644 --- a/src/arch/x86/lib/cpu.c +++ b/src/arch/x86/lib/cpu.c @@ -9,6 +9,7 @@ #include <device/path.h> #include <device/device.h> #include <smp/spinlock.h> +#include <cpu/x86/lapic.h> /* Standard macro to see if a specific flag is changeable */ static inline int flag_is_changeable_p(uint32_t flag) @@ -234,7 +235,11 @@ static void set_cpu_ops(struct device *cpu) cpu->ops = driver ? driver->ops : NULL; } -void cpu_initialize(void) +#if CONFIG_SMP +static spinlock_t start_cpu_lock = SPIN_LOCK_UNLOCKED; +#endif + +void cpu_initialize(struct bus *cpu_bus, int index) { /* Because we busy wait at the printk spinlock. * It is important to keep the number of printed messages @@ -242,17 +247,22 @@ void cpu_initialize(void) * disabled. */ struct device *cpu; - struct cpu_info *info; struct cpuinfo_x86 c; - - info = cpu_info(); - - printk(BIOS_INFO, "Initializing CPU #%ld\n", info->index); - - cpu = info->cpu; - if (!cpu) { - die("CPU: missing cpu device structure"); - } + struct device_path cpu_path; + unsigned char id = lapicid(); + + cpu_path.type = DEVICE_PATH_APIC; + cpu_path.apic.apic_id = id; + cpu_path.apic.index = index; + +#if CONFIG_SMP + spin_lock(&start_cpu_lock); +#endif + cpu = alloc_find_dev(cpu_bus, &cpu_path); +#if CONFIG_SMP + spin_unlock(&start_cpu_lock); +#endif + printk(BIOS_DEBUG, "Initializing CPU #%d\n", id); /* Find what type of cpu we are dealing with */ identify_cpu(cpu); @@ -276,7 +286,6 @@ void cpu_initialize(void) printk(BIOS_DEBUG, "Using generic cpu ops (good)\n"); } - /* Initialize the cpu */ if (cpu->ops && cpu->ops->init) { cpu->enabled = 1; @@ -284,7 +293,7 @@ void cpu_initialize(void) cpu->ops->init(cpu); } - printk(BIOS_INFO, "CPU #%ld initialized\n", info->index); + printk(BIOS_INFO, "CPU #%d initialized\n", id); return; } diff --git a/src/cpu/intel/hyperthreading/Makefile.inc b/src/cpu/intel/hyperthreading/Makefile.inc deleted file mode 100644 index 8adbad9..0000000 --- a/src/cpu/intel/hyperthreading/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ramstage-y += intel_sibling.c diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c deleted file mode 100644 index 2d2e105..0000000 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ /dev/null @@ -1,73 +0,0 @@ -#include <console/console.h> -#include <cpu/cpu.h> -#include <cpu/x86/lapic.h> -#include <cpu/intel/hyperthreading.h> -#include <device/device.h> -#include <pc80/mc146818rtc.h> -#include <smp/spinlock.h> -#include <assert.h> - -#if !CONFIG_SERIAL_CPU_INIT -#error Intel hyper-threading requires serialized cpu init -#endif - -static int first_time = 1; -static int disable_siblings = !CONFIG_LOGICAL_CPUS; - -void intel_sibling_init(device_t cpu) -{ - unsigned i, siblings; - struct cpuid_result result; - - /* On the bootstrap processor see if I want sibling cpus enabled */ - if (first_time) { - first_time = 0; - get_option(&disable_siblings, "hyper_threading"); - } - result = cpuid(1); - /* Is hyperthreading supported */ - if (!(result.edx & (1 << 28))) { - return; - } - /* See how many sibling cpus we have */ - siblings = (result.ebx >> 16) & 0xff; - if (siblings < 1) { - siblings = 1; - } - - printk(BIOS_DEBUG, "CPU: %u %d siblings\n", - cpu->path.apic.apic_id, - siblings); - - /* See if I am a sibling cpu */ - if (cpu->path.apic.apic_id & (siblings -1)) { - if (disable_siblings) { - cpu->enabled = 0; - } - return; - } - - /* I am the primary cpu start up my siblings */ - for(i = 1; i < siblings; i++) { - struct device_path cpu_path; - device_t new; - /* Build the cpu device path */ - cpu_path.type = DEVICE_PATH_APIC; - cpu_path.apic.apic_id = cpu->path.apic.apic_id + i; - - - /* Allocate new cpu device structure iff sibling CPU - * was not in static device tree. - */ - new = alloc_find_dev(cpu->bus, &cpu_path); - - if (!new) { - continue; - } - - printk(BIOS_DEBUG, "CPU: %u has sibling %u\n", - cpu->path.apic.apic_id, - new->path.apic.apic_id); - } -} - diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index c6d716d9..ddd1381 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -29,7 +29,6 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> -#include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -221,9 +220,6 @@ static void model_1067x_init(device_t cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors(); - - /* Start up my cpu siblings */ - intel_sibling_init(cpu); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index 09449cb..fe44024 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -3,4 +3,3 @@ config CPU_INTEL_MODEL_106CX select SMP select SSE2 select UDELAY_LAPIC - select AP_IN_SIPI_WAIT diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 4bf2924..8d2ef3d 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -27,7 +27,6 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> -#include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> #include <usbdebug.h> @@ -178,9 +177,6 @@ static void model_106cx_init(device_t cpu) configure_misc(); /* TODO: PIC thermal sensor control */ - - /* Start up my cpu siblings */ - intel_sibling_init(cpu); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index d2d4c73..e3e4360 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -12,7 +12,6 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select UDELAY_LAPIC select SMM_TSEG - #select AP_IN_SIPI_WAIT config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index 6153174..dea23e7 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -26,6 +26,7 @@ #include <arch/acpigen.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> +#include <cpu/x86/lapic.h> #include <cpu/intel/acpi.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> @@ -88,8 +89,8 @@ static int generate_cstate_entries(acpi_cstate_t *cstates, static int generate_C_state_entries(void) { - struct cpu_info *info; struct cpu_driver *cpu; + struct device *cpu_dev; int len, lenif; device_t lapic; struct cpu_intel_model_206ax_config *conf = NULL; @@ -103,10 +104,10 @@ static int generate_C_state_entries(void) return 0; /* Find CPU map of supported C-states */ - info = cpu_info(); - if (!info) + cpu_dev = dev_find_lapic(lapicid()); + if (!cpu_dev) return 0; - cpu = find_cpu_driver(info->cpu); + cpu = find_cpu_driver(cpu_dev); if (!cpu || !cpu->cstates) return 0; diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 874ce4d..d60c237 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -414,58 +414,6 @@ static void configure_mca(void) static unsigned ehci_debug_addr; #endif -/* - * Initialize any extra cores/threads in this package. - */ -static void intel_cores_init(device_t cpu) -{ - struct cpuid_result result; - unsigned cores, threads, i; - - result = cpuid_ext(0xb, 0); /* Threads per core */ - threads = result.ebx & 0xff; - - result = cpuid_ext(0xb, 1); /* Cores per package */ - cores = result.ebx & 0xff; - - /* Only initialize extra cores from BSP */ - if (cpu->path.apic.apic_id) - return; - - printk(BIOS_DEBUG, "CPU: %u has %u cores %u threads\n", - cpu->path.apic.apic_id, cores, threads); - - for (i = 1; i < cores; ++i) { - struct device_path cpu_path; - device_t new; - - /* Build the cpu device path */ - cpu_path.type = DEVICE_PATH_APIC; - cpu_path.apic.apic_id = - cpu->path.apic.apic_id + i; - - /* Update APIC ID if no hyperthreading */ - if (threads == 1) - cpu_path.apic.apic_id <<= 1; - - /* Allocate the new cpu device structure */ - new = alloc_dev(cpu->bus, &cpu_path); - if (!new) - continue; - - printk(BIOS_DEBUG, "CPU: %u has core %u\n", - cpu->path.apic.apic_id, - new->path.apic.apic_id); - - /* Start the new cpu */ - if (!start_cpu(new)) { - /* Record the error in cpu? */ - printk(BIOS_ERR, "CPU %u would not start!\n", - new->path.apic.apic_id); - } - } -} - static void model_206ax_init(device_t cpu) { char processor_name[49]; @@ -528,9 +476,6 @@ static void model_206ax_init(device_t cpu) /* Enable Turbo */ enable_turbo(); - - /* Start up extra cores */ - intel_cores_init(cpu); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig index 31d24bd..c3faa39 100644 --- a/src/cpu/intel/model_6ex/Kconfig +++ b/src/cpu/intel/model_6ex/Kconfig @@ -3,4 +3,3 @@ config CPU_INTEL_MODEL_6EX select SMP select SSE2 select UDELAY_LAPIC - select AP_IN_SIPI_WAIT diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 1c8c72b..a0afd2e 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -205,9 +205,6 @@ static void model_6ex_init(device_t cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors(); - - /* Start up my cpu siblings */ - intel_sibling_init(cpu); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig index 851685c..065cdd9 100644 --- a/src/cpu/intel/model_6fx/Kconfig +++ b/src/cpu/intel/model_6fx/Kconfig @@ -3,4 +3,3 @@ config CPU_INTEL_MODEL_6FX select SMP select SSE2 select UDELAY_LAPIC - select AP_IN_SIPI_WAIT diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 106719e..c5d7a6b 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -243,9 +243,6 @@ static void model_6fx_init(device_t cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors(); - - /* Start up my cpu siblings */ - intel_sibling_init(cpu); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c index ec78672..51b72a3 100644 --- a/src/cpu/intel/model_f2x/model_f2x_init.c +++ b/src/cpu/intel/model_f2x/model_f2x_init.c @@ -7,7 +7,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> -#include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> /* 512KB cache */ @@ -56,9 +55,6 @@ static void model_f2x_init(device_t cpu) /* Enable the local cpu apics */ setup_lapic(); - - /* Start up my cpu siblings */ - intel_sibling_init(cpu); }; static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index 580c98b..ca346da 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -7,7 +7,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> -#include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> static uint32_t microcode_updates[] = { @@ -39,9 +38,6 @@ static void model_f3x_init(device_t cpu) /* Enable the local cpu apics */ setup_lapic(); - - /* Start up my cpu siblings */ - intel_sibling_init(cpu); }; static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c index 54edf2e..c857cef 100644 --- a/src/cpu/intel/model_f4x/model_f4x_init.c +++ b/src/cpu/intel/model_f4x/model_f4x_init.c @@ -7,7 +7,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> -#include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> static uint32_t microcode_updates[] = { @@ -47,9 +46,6 @@ static void model_f4x_init(device_t cpu) /* Enable the local cpu apics */ setup_lapic(); - - /* Start up my cpu siblings */ - intel_sibling_init(cpu); }; static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/socket_LGA771/Kconfig b/src/cpu/intel/socket_LGA771/Kconfig index 62bd17b..f549210 100644 --- a/src/cpu/intel/socket_LGA771/Kconfig +++ b/src/cpu/intel/socket_LGA771/Kconfig @@ -3,4 +3,3 @@ config CPU_INTEL_SOCKET_LGA771 select CPU_INTEL_MODEL_6FX select SSE2 select MMX - select AP_IN_SIPI_WAIT diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index e491d46..061d3d3 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -66,31 +66,28 @@ static void copy_secondary_start_to_1m_below(void) printk(BIOS_DEBUG, "start_eip=0x%08lx, offset=0x%08lx, code_size=0x%08lx\n", start_eip, ((unsigned long)_secondary_start - start_eip), code_size); } -static int lapic_start_cpu(unsigned long apicid) +static struct bus *current_cpu_bus; + +static int lapic_start_cpus(struct bus *cpu_bus) { int timeout; unsigned long send_status, accept_status, start_eip; - int j, num_starts, maxlvt; + int maxlvt; /* * Starting actual IPI sequence... */ - printk(BIOS_SPEW, "Asserting INIT.\n"); - - /* - * Turn INIT on target chip - */ - lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); + current_cpu_bus = cpu_bus; - /* - * Send IPI - */ + printk(BIOS_SPEW, "Asserting INIT.\n"); - lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT - | LAPIC_DM_INIT); + /* Send INIT SIPI to target chip */ + lapic_write_around(LAPIC_ICR2, 0); + lapic_write_around(LAPIC_ICR, LAPIC_INT_ASSERT + | LAPIC_DM_INIT | LAPIC_DEST_ALLBUT); - printk(BIOS_SPEW, "Waiting for send to finish...\n"); + printk(BIOS_DEBUG, "Waiting for send to finish...\n"); timeout = 0; do { printk(BIOS_SPEW, "+"); @@ -98,108 +95,67 @@ static int lapic_start_cpu(unsigned long apicid) send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; } while (send_status && (timeout++ < 1000)); if (timeout >= 1000) { - printk(BIOS_ERR, "CPU %ld: First apic write timed out. Disabling\n", - apicid); + printk(BIOS_DEBUG, "First apic write timed out. Disabling\n"); // too bad. - printk(BIOS_ERR, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); + printk(BIOS_DEBUG, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); if (lapic_read(LAPIC_ESR)) { - printk(BIOS_ERR, "Try to reset ESR\n"); + printk(BIOS_DEBUG, "Try to reset ESR\n"); lapic_write_around(LAPIC_ESR, 0); - printk(BIOS_ERR, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); + printk(BIOS_DEBUG, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); } return 0; } -#if !CONFIG_CPU_AMD_MODEL_10XXX && !CONFIG_CPU_INTEL_MODEL_206AX - mdelay(10); -#endif + start_eip = get_valid_start_eip((unsigned long)_secondary_start); + + maxlvt = 4; + + printk(BIOS_SPEW, "Sending STARTUP.\n"); + lapic_read_around(LAPIC_SPIV); + lapic_write(LAPIC_ESR, 0); + lapic_read(LAPIC_ESR); + printk(BIOS_SPEW, "After apic_write.\n"); - printk(BIOS_SPEW, "Deasserting INIT.\n"); + /* + * STARTUP IPI + */ /* Target chip */ - lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); + lapic_write_around(LAPIC_ICR2, 0); - /* Send IPI */ - lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT); + /* Boot on the stack */ + /* Kick the second */ + lapic_write_around(LAPIC_ICR, LAPIC_INT_ASSERT | LAPIC_DM_STARTUP | LAPIC_DEST_ALLBUT + | (start_eip >> 12)); - printk(BIOS_SPEW, "Waiting for send to finish...\n"); + /* + * Give the other CPU some time to accept the IPI. + */ + udelay(300); + + printk(BIOS_DEBUG, "Startup point 1.\n"); + + printk(BIOS_DEBUG, "Waiting for send to finish...\n"); timeout = 0; do { - printk(BIOS_SPEW, "+"); + printk(BIOS_DEBUG, "+"); udelay(100); send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; } while (send_status && (timeout++ < 1000)); - if (timeout >= 1000) { - printk(BIOS_ERR, "CPU %ld: Second apic write timed out. Disabling\n", - apicid); - // too bad. - return 0; - } - - start_eip = get_valid_start_eip((unsigned long)_secondary_start); - -#if !CONFIG_CPU_AMD_MODEL_10XXX - num_starts = 2; -#else - num_starts = 1; -#endif /* - * Run STARTUP IPI loop. + * Give the other CPU some time to accept the IPI. */ - printk(BIOS_SPEW, "#startup loops: %d.\n", num_starts); - - maxlvt = 4; - - for (j = 1; j <= num_starts; j++) { - printk(BIOS_SPEW, "Sending STARTUP #%d to %lu.\n", j, apicid); + udelay(200); + /* + * Due to the Pentium erratum 3AP. + */ + if (maxlvt > 3) { lapic_read_around(LAPIC_SPIV); lapic_write(LAPIC_ESR, 0); - lapic_read(LAPIC_ESR); - printk(BIOS_SPEW, "After apic_write.\n"); - - /* - * STARTUP IPI - */ - - /* Target chip */ - lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); - - /* Boot on the stack */ - /* Kick the second */ - lapic_write_around(LAPIC_ICR, LAPIC_DM_STARTUP - | (start_eip >> 12)); - - /* - * Give the other CPU some time to accept the IPI. - */ - udelay(300); - - printk(BIOS_SPEW, "Startup point 1.\n"); - - printk(BIOS_SPEW, "Waiting for send to finish...\n"); - timeout = 0; - do { - printk(BIOS_SPEW, "+"); - udelay(100); - send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; - } while (send_status && (timeout++ < 1000)); - - /* - * Give the other CPU some time to accept the IPI. - */ - udelay(200); - /* - * Due to the Pentium erratum 3AP. - */ - if (maxlvt > 3) { - lapic_read_around(LAPIC_SPIV); - lapic_write(LAPIC_ESR, 0); - } - accept_status = (lapic_read(LAPIC_ESR) & 0xEF); - if (send_status || accept_status) - break; } - printk(BIOS_SPEW, "After Startup.\n"); + accept_status = (lapic_read(LAPIC_ESR) & 0xEF); + + printk(BIOS_DEBUG, "After Startup.\n"); if (send_status) printk(BIOS_WARNING, "APIC never delivered???\n"); if (accept_status) @@ -209,156 +165,34 @@ static int lapic_start_cpu(unsigned long apicid) return 1; } + /* Number of cpus that are currently running in coreboot */ static atomic_t active_cpus = ATOMIC_INIT(1); -/* start_cpu_lock covers last_cpu_index and secondary_stack. - * Only starting one cpu at a time let's me remove the logic - * for select the stack from assembly language. - * - * In addition communicating by variables to the cpu I - * am starting allows me to veryify it has started before - * start_cpu returns. - */ - -static spinlock_t start_cpu_lock = SPIN_LOCK_UNLOCKED; -static unsigned last_cpu_index = 0; volatile unsigned long secondary_stack; +extern unsigned char _estack[]; -int start_cpu(device_t cpu) +static void stop_all_ap_cpus(void) { - extern unsigned char _estack[]; - struct cpu_info *info; - unsigned long stack_end; - unsigned long apicid; - unsigned long index; - unsigned long count; - int result; - - spin_lock(&start_cpu_lock); - - /* Get the cpu's apicid */ - apicid = cpu->path.apic.apic_id; - - /* Get an index for the new processor */ - index = ++last_cpu_index; - - /* Find end of the new processors stack */ - stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info); - - /* Record the index and which cpu structure we are using */ - info = (struct cpu_info *)stack_end; - info->index = index; - info->cpu = cpu; - - /* Advertise the new stack to start_cpu */ - secondary_stack = stack_end; - - /* Until the cpu starts up report the cpu is not enabled */ - cpu->enabled = 0; - cpu->initialized = 0; - - /* Start the cpu */ - result = lapic_start_cpu(apicid); - - if (result) { - result = 0; - /* Wait 1s or until the new cpu calls in */ - for(count = 0; count < 100000 ; count++) { - if (secondary_stack == 0) { - result = 1; - break; - } - udelay(10); - } - } - secondary_stack = 0; - spin_unlock(&start_cpu_lock); - return result; -} - -#if CONFIG_AP_IN_SIPI_WAIT - -/** - * Sending INIT IPI to self is equivalent of asserting #INIT with a bit of delay. - * An undefined number of instruction cycles will complete. All global locks - * must be released before INIT IPI and no printk is allowed after this. - * De-asserting INIT IPI is a no-op on later Intel CPUs. - * - * If you set DEBUG_HALT_SELF to 1, printk's after INIT IPI are enabled - * but running thread may halt without releasing the lock and effectively - * deadlock other CPUs. - */ -#define DEBUG_HALT_SELF 0 - -/** - * Normally this function is defined in lapic.h as an always inline function - * that just keeps the CPU in a hlt() loop. This does not work on all CPUs. - * I think all hyperthreading CPUs might need this version, but I could only - * verify this on the Intel Core Duo - */ -void stop_this_cpu(void) -{ - int timeout; unsigned long send_status; - unsigned long id; - - id = lapic_read(LAPIC_ID) >> 24; - - printk(BIOS_DEBUG, "CPU %ld going down...\n", id); - - /* send an LAPIC INIT to myself */ - lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id)); - lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT | LAPIC_DM_INIT); + int timeout; + /* send an LAPIC INIT to all but myself */ + lapic_write_around(LAPIC_ICR2, 0); + lapic_write_around(LAPIC_ICR, LAPIC_INT_ASSERT | LAPIC_DM_INIT | LAPIC_DEST_ALLBUT); /* wait for the ipi send to finish */ -#if DEBUG_HALT_SELF printk(BIOS_SPEW, "Waiting for send to finish...\n"); -#endif timeout = 0; do { -#if DEBUG_HALT_SELF printk(BIOS_SPEW, "+"); -#endif udelay(100); send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; } while (send_status && (timeout++ < 1000)); if (timeout >= 1000) { -#if DEBUG_HALT_SELF printk(BIOS_ERR, "timed out\n"); -#endif } mdelay(10); - -#if DEBUG_HALT_SELF - printk(BIOS_SPEW, "Deasserting INIT.\n"); -#endif - /* Deassert the LAPIC INIT */ - lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id)); - lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT); - -#if DEBUG_HALT_SELF - printk(BIOS_SPEW, "Waiting for send to finish...\n"); -#endif - timeout = 0; - do { -#if DEBUG_HALT_SELF - printk(BIOS_SPEW, "+"); -#endif - udelay(100); - send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; - } while (send_status && (timeout++ < 1000)); - if (timeout >= 1000) { -#if DEBUG_HALT_SELF - printk(BIOS_ERR, "timed out\n"); -#endif - } - - while(1) { - hlt(); - } } -#endif #ifdef __SSE3__ static __inline__ __attribute__((always_inline)) unsigned long readcr4(void) @@ -381,66 +215,21 @@ static __inline__ __attribute__((always_inline)) void writecr4(unsigned long Dat #endif /* C entry point of secondary cpus */ -void secondary_cpu_init(void) +void secondary_cpu_init(int index) { - atomic_inc(&active_cpus); -#if CONFIG_SERIAL_CPU_INIT - spin_lock(&start_cpu_lock); -#endif - #ifdef __SSE3__ - /* - * Seems that CR4 was cleared when AP start via lapic_start_cpu() - * Turn on CR4.OSFXSR and CR4.OSXMMEXCPT when SSE options enabled - */ - u32 cr4_val; - cr4_val = readcr4(); - cr4_val |= (1 << 9 | 1 << 10); - writecr4(cr4_val); -#endif - cpu_initialize(); -#if CONFIG_SERIAL_CPU_INIT - spin_unlock(&start_cpu_lock); + /* + * Seems that CR4 was cleared when AP start via lapic_start_cpu() + * Turn on CR4.OSFXSR and CR4.OSXMMEXCPT when SSE options enabled + */ + u32 cr4_val; + cr4_val = readcr4(); + cr4_val |= (1 << 9 | 1 << 10); + writecr4(cr4_val); #endif - + atomic_inc(&active_cpus); + cpu_initialize(current_cpu_bus, index); atomic_dec(&active_cpus); - - stop_this_cpu(); -} - -static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu) -{ - device_t cpu; - /* Loop through the cpus once getting them started */ - - for(cpu = cpu_bus->children; cpu ; cpu = cpu->sibling) { - if (cpu->path.type != DEVICE_PATH_APIC) { - continue; - } - #if !CONFIG_SERIAL_CPU_INIT - if(cpu==bsp_cpu) { - continue; - } - #endif - - if (!cpu->enabled) { - continue; - } - - if (cpu->initialized) { - continue; - } - - if (!start_cpu(cpu)) { - /* Record the error in cpu? */ - printk(BIOS_ERR, "CPU 0x%02x would not start!\n", - cpu->path.apic.apic_id); - } -#if CONFIG_SERIAL_CPU_INIT - udelay(10); -#endif - } - } static void wait_other_cpus_stop(struct bus *cpu_bus) @@ -473,6 +262,7 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) cpu->path.apic.apic_id); } } + stop_all_ap_cpus(); printk(BIOS_DEBUG, "All AP CPUs stopped (%ld loops)\n", loopcount); } @@ -481,10 +271,6 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) void initialize_cpus(struct bus *cpu_bus) { struct device_path cpu_path; - struct cpu_info *info; - - /* Find the info struct for this cpu */ - info = cpu_info(); #if NEED_LAPIC == 1 /* Ensure the local apic is enabled */ @@ -499,9 +285,6 @@ void initialize_cpus(struct bus *cpu_bus) cpu_path.cpu.id = 0; #endif - /* Find the device structure for the boot cpu */ - info->cpu = alloc_find_dev(cpu_bus, &cpu_path); - #if CONFIG_SMP copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init #endif @@ -512,21 +295,11 @@ void initialize_cpus(struct bus *cpu_bus) cpus_ready_for_init(); -#if CONFIG_SMP - #if !CONFIG_SERIAL_CPU_INIT - /* start all aps at first, so we can init ECC all together */ - start_other_cpus(cpu_bus, info->cpu); - #endif -#endif - /* Initialize the bootstrap processor */ - cpu_initialize(); + cpu_initialize(cpu_bus, 0); #if CONFIG_SMP - #if CONFIG_SERIAL_CPU_INIT - start_other_cpus(cpu_bus, info->cpu); - #endif - + lapic_start_cpus(cpu_bus); /* Now wait the rest of the cpus stop*/ wait_other_cpus_stop(cpu_bus); #endif diff --git a/src/cpu/x86/lapic/secondary.S b/src/cpu/x86/lapic/secondary.S index dc00b08..67e44c4 100644 --- a/src/cpu/x86/lapic/secondary.S +++ b/src/cpu/x86/lapic/secondary.S @@ -2,7 +2,7 @@ #include <cpu/x86/lapic_def.h> .text - .globl _secondary_start, _secondary_start_end + .globl _secondary_start, _secondary_start_end, cpucount .balign 4096 _secondary_start: .code16 @@ -38,15 +38,25 @@ _secondary_start: /* Load the Interrupt descriptor table */ lidt idtarg - /* Set the stack pointer, and flag that we are done */ - xorl %eax, %eax - movl secondary_stack, %esp - movl %eax, secondary_stack + /* increment our cpu index */ + movl $1, %eax + lock xadd %eax, cpucount + incl %eax + movl %eax, %ecx + + /* assign stack for this specific cpu */ + mov _stack, %esp + mov $CONFIG_STACK_SIZE, %ebx + mul %ebx + add %eax, %esp + pushl %ecx call secondary_cpu_init 1: hlt jmp 1b +cpucount: + .long 1 gdtaddr: .word gdt_limit /* the table limit */ .long gdt /* we know the offset */ diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index 814c5f1..7aa17c2 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -3,8 +3,10 @@ */ #include <console/console.h> +#include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/pae.h> +#include <cpu/x86/lapic.h> #include <string.h> static void paging_off(void) @@ -43,6 +45,14 @@ static void paging_on(void *pdp) ); } +static int cpu_index(void) +{ + device_t dev = dev_find_lapic(lapicid()); + if (!dev) + return -1; + return dev->path.apic.index; +} + void *map_2M_page(unsigned long page) { struct pde { @@ -60,7 +70,9 @@ void *map_2M_page(unsigned long page) unsigned long window; void *result; int i; + index = cpu_index(); + if ((index < 0) || (index >= CONFIG_MAX_CPUS)) { return MAPPING_ERROR; } diff --git a/src/drivers/i2c/w83795/w83795.c b/src/drivers/i2c/w83795/w83795.c index 392471a..12be4da 100644 --- a/src/drivers/i2c/w83795/w83795.c +++ b/src/drivers/i2c/w83795/w83795.c @@ -22,6 +22,7 @@ #include <console/console.h> #include <device/device.h> #include "southbridge/amd/cimx/sb700/smbus.h" /*SMBUS_IO_BASE*/ +#include <cpu/x86/lapic.h> #include "w83795.h" static u32 w83795_set_bank(u8 bank) @@ -224,10 +225,8 @@ static void w83795_init(w83795_fan_mode_t mode, u8 dts_src) static void w83795_hwm_init(device_t dev) { struct device *cpu; - struct cpu_info *info; - info = cpu_info(); - cpu = info->cpu; + cpu = dev_find_lapic(lapicid()); if (!cpu) die("CPU: missing cpu device structure"); diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index c2113c1..9765dfd 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -4,10 +4,12 @@ #include <arch/cpu.h> #if !defined(__ROMCC__) -void cpu_initialize(void); +void cpu_initialize(struct bus *cpu_bus, int index); struct bus; void initialize_cpus(struct bus *cpu_bus); -void secondary_cpu_init(void); +void secondary_cpu_init(int index); + +extern unsigned int cpucount; #if !CONFIG_WAIT_BEFORE_CPUS_INIT #define cpus_ready_for_init() do {} while(0) diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 078f2a7..5c48025 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -52,20 +52,13 @@ static inline __attribute__((always_inline)) unsigned long lapicid(void) } #ifndef __ROMCC__ -#if CONFIG_AP_IN_SIPI_WAIT != 1 -/* If we need to go back to sipi wait, we use the long non-inlined version of - * this function in lapic_cpu_init.c - */ static inline __attribute__((always_inline)) void stop_this_cpu(void) { - /* Called by an AP when it is ready to halt and wait for a new task */ - for(;;) { - hlt(); - } + /* Called by an AP when it is ready to halt and wait for a new task */ + for(;;) { + hlt(); + } } -#else -void stop_this_cpu(void); -#endif #if !defined(__PRE_RAM__) diff --git a/src/include/device/path.h b/src/include/device/path.h index 63e9538..018fb93 100644 --- a/src/include/device/path.h +++ b/src/include/device/path.h @@ -40,6 +40,7 @@ struct apic_path unsigned apic_id; unsigned node_id; unsigned core_id; + unsigned index; }; struct apic_cluster_path

2 1

ASRock E350M1: Linux dmesg: ACPI: Invalid PBLK length [0]
by Paul Menzel 02 Jul '12

02 Jul '12

Dear coreboot folks, the image Cristi gave me works fine. Looking through some log files I notice the following error message in the Linux kernel ring buffer (`dmesg`). ACPI: Invalid PBLK length [0] Please find the full output and the coreboot config attached. Does someone else have these problems? Thanks, Paul

1 0

Patch set updated for coreboot: 0c18ec8 Use broadcast SIPI to startup siblings
by Sven Schnelle 02 Jul '12

02 Jul '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1139 -gerrit commit 0c18ec83951db47d4bf84503c3553212d77d4b00 Author: Sven Schnelle <svens(a)stackframe.org> Date: Sun Jun 17 10:32:55 2012 +0200 Use broadcast SIPI to startup siblings The current code for initializing AP cpus has several shortcomings: - it assumes APIC IDs are sequential - it uses only the BSP for determining the AP count, which is bad if there's more than one physical CPU, and CPUs are of different type Note that the new code call cpu->ops->init() in parallel, and therefore some CPU code needs to be changed to address that. One example are old Intel HT enabled CPUs which can't do microcode update in parallel. Change-Id: Ic48a1ebab6a7c52aa76765f497268af09fa38c25 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/arch/x86/Kconfig | 4 - src/arch/x86/include/arch/cpu.h | 24 -- src/arch/x86/lib/cpu.c | 35 ++- src/cpu/intel/hyperthreading/intel_sibling.c | 65 ----- src/cpu/intel/model_1067x/model_1067x_init.c | 4 - src/cpu/intel/model_106cx/Kconfig | 1 - src/cpu/intel/model_106cx/model_106cx_init.c | 4 - src/cpu/intel/model_206ax/Kconfig | 1 - src/cpu/intel/model_206ax/acpi.c | 9 +- src/cpu/intel/model_206ax/model_206ax_init.c | 55 ---- src/cpu/intel/model_6ex/Kconfig | 1 - src/cpu/intel/model_6ex/model_6ex_init.c | 3 - src/cpu/intel/model_6fx/Kconfig | 1 - src/cpu/intel/model_6fx/model_6fx_init.c | 3 - src/cpu/intel/model_f2x/model_f2x_init.c | 3 - src/cpu/intel/model_f3x/model_f3x_init.c | 3 - src/cpu/intel/model_f4x/model_f4x_init.c | 3 - src/cpu/intel/socket_LGA771/Kconfig | 1 - src/cpu/x86/lapic/lapic_cpu_init.c | 369 +++++--------------------- src/cpu/x86/lapic/secondary.S | 20 +- src/cpu/x86/pae/pgtbl.c | 12 + src/drivers/i2c/w83795/w83795.c | 5 +- src/include/cpu/cpu.h | 6 +- src/include/cpu/x86/lapic.h | 15 +- src/include/device/path.h | 1 + 25 files changed, 136 insertions(+), 512 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 6d56ec6..4dfbe70 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -3,10 +3,6 @@ menu "Architecture (x86)" # This is an SMP option. It relates to starting up APs. # It is usually set in mainboard/*/Kconfig. # TODO: Improve description. -config AP_IN_SIPI_WAIT - bool - default n - depends on ARCH_X86 # Aligns 16bit entry code in bootblock so that hyper-threading CPUs # can boot AP CPUs to enable their shared caches. diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 0dc92fb..0fe5ea5 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -158,30 +158,6 @@ struct cpu_driver { struct device; struct cpu_driver *find_cpu_driver(struct device *cpu); -struct cpu_info { - device_t cpu; - unsigned long index; -}; - -static inline struct cpu_info *cpu_info(void) -{ - struct cpu_info *ci; - __asm__("andl %%esp,%0; " - "orl %2, %0 " - :"=r" (ci) - : "0" (~(CONFIG_STACK_SIZE - 1)), - "r" (CONFIG_STACK_SIZE - sizeof(struct cpu_info)) - ); - return ci; -} - -static inline unsigned long cpu_index(void) -{ - struct cpu_info *ci; - ci = cpu_info(); - return ci->index; -} - struct cpuinfo_x86 { uint8_t x86; /* CPU family */ uint8_t x86_vendor; /* CPU vendor */ diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c index 98ede06..2d64be9 100644 --- a/src/arch/x86/lib/cpu.c +++ b/src/arch/x86/lib/cpu.c @@ -9,6 +9,7 @@ #include <device/path.h> #include <device/device.h> #include <smp/spinlock.h> +#include <cpu/x86/lapic.h> /* Standard macro to see if a specific flag is changeable */ static inline int flag_is_changeable_p(uint32_t flag) @@ -234,7 +235,11 @@ static void set_cpu_ops(struct device *cpu) cpu->ops = driver ? driver->ops : NULL; } -void cpu_initialize(void) +#if CONFIG_SMP +static spinlock_t start_cpu_lock = SPIN_LOCK_UNLOCKED; +#endif + +void cpu_initialize(struct bus *cpu_bus, int index) { /* Because we busy wait at the printk spinlock. * It is important to keep the number of printed messages @@ -242,17 +247,22 @@ void cpu_initialize(void) * disabled. */ struct device *cpu; - struct cpu_info *info; struct cpuinfo_x86 c; - - info = cpu_info(); - - printk(BIOS_INFO, "Initializing CPU #%ld\n", info->index); - - cpu = info->cpu; - if (!cpu) { - die("CPU: missing cpu device structure"); - } + struct device_path cpu_path; + unsigned char id = lapicid(); + + cpu_path.type = DEVICE_PATH_APIC; + cpu_path.apic.apic_id = id; + cpu_path.apic.index = index; + +#if CONFIG_SMP + spin_lock(&start_cpu_lock); +#endif + cpu = alloc_find_dev(cpu_bus, &cpu_path); +#if CONFIG_SMP + spin_unlock(&start_cpu_lock); +#endif + printk(BIOS_DEBUG, "Initializing CPU #%d\n", id); /* Find what type of cpu we are dealing with */ identify_cpu(cpu); @@ -276,7 +286,6 @@ void cpu_initialize(void) printk(BIOS_DEBUG, "Using generic cpu ops (good)\n"); } - /* Initialize the cpu */ if (cpu->ops && cpu->ops->init) { cpu->enabled = 1; @@ -284,7 +293,7 @@ void cpu_initialize(void) cpu->ops->init(cpu); } - printk(BIOS_INFO, "CPU #%ld initialized\n", info->index); + printk(BIOS_INFO, "CPU #%d initialized\n", id); return; } diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index b9a9ae7..8377cd0 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -7,13 +7,6 @@ #include <smp/spinlock.h> #include <assert.h> -#if !CONFIG_SERIAL_CPU_INIT -#error Intel hyper-threading requires serialized cpu init -#endif - -static int first_time = 1; -static int disable_siblings = !CONFIG_LOGICAL_CPUS; - /* Return true if running thread does not have the smallest lapic ID * within a CPU core. */ @@ -34,61 +27,3 @@ int intel_ht_sibling(void) threads = (apic_ids / core_ids); return !!(lapicid() & (threads-1)); } - -void intel_sibling_init(device_t cpu) -{ - unsigned i, siblings; - struct cpuid_result result; - - /* On the bootstrap processor see if I want sibling cpus enabled */ - if (first_time) { - first_time = 0; - get_option(&disable_siblings, "hyper_threading"); - } - result = cpuid(1); - /* Is hyperthreading supported */ - if (!(result.edx & (1 << 28))) { - return; - } - /* See how many sibling cpus we have */ - siblings = (result.ebx >> 16) & 0xff; - if (siblings < 1) { - siblings = 1; - } - - printk(BIOS_DEBUG, "CPU: %u %d siblings\n", - cpu->path.apic.apic_id, - siblings); - - /* See if I am a sibling cpu */ - if (cpu->path.apic.apic_id & (siblings -1)) { - if (disable_siblings) { - cpu->enabled = 0; - } - return; - } - - /* I am the primary cpu start up my siblings */ - for(i = 1; i < siblings; i++) { - struct device_path cpu_path; - device_t new; - /* Build the cpu device path */ - cpu_path.type = DEVICE_PATH_APIC; - cpu_path.apic.apic_id = cpu->path.apic.apic_id + i; - - - /* Allocate new cpu device structure iff sibling CPU - * was not in static device tree. - */ - new = alloc_find_dev(cpu->bus, &cpu_path); - - if (!new) { - continue; - } - - printk(BIOS_DEBUG, "CPU: %u has sibling %u\n", - cpu->path.apic.apic_id, - new->path.apic.apic_id); - } -} - diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index c6d716d9..ddd1381 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -29,7 +29,6 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> -#include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -221,9 +220,6 @@ static void model_1067x_init(device_t cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors(); - - /* Start up my cpu siblings */ - intel_sibling_init(cpu); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index 09449cb..fe44024 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -3,4 +3,3 @@ config CPU_INTEL_MODEL_106CX select SMP select SSE2 select UDELAY_LAPIC - select AP_IN_SIPI_WAIT diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 4bf2924..8d2ef3d 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -27,7 +27,6 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> -#include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> #include <usbdebug.h> @@ -178,9 +177,6 @@ static void model_106cx_init(device_t cpu) configure_misc(); /* TODO: PIC thermal sensor control */ - - /* Start up my cpu siblings */ - intel_sibling_init(cpu); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index d2d4c73..e3e4360 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -12,7 +12,6 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select UDELAY_LAPIC select SMM_TSEG - #select AP_IN_SIPI_WAIT config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index 6153174..dea23e7 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -26,6 +26,7 @@ #include <arch/acpigen.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> +#include <cpu/x86/lapic.h> #include <cpu/intel/acpi.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> @@ -88,8 +89,8 @@ static int generate_cstate_entries(acpi_cstate_t *cstates, static int generate_C_state_entries(void) { - struct cpu_info *info; struct cpu_driver *cpu; + struct device *cpu_dev; int len, lenif; device_t lapic; struct cpu_intel_model_206ax_config *conf = NULL; @@ -103,10 +104,10 @@ static int generate_C_state_entries(void) return 0; /* Find CPU map of supported C-states */ - info = cpu_info(); - if (!info) + cpu_dev = dev_find_lapic(lapicid()); + if (!cpu_dev) return 0; - cpu = find_cpu_driver(info->cpu); + cpu = find_cpu_driver(cpu_dev); if (!cpu || !cpu->cstates) return 0; diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 874ce4d..d60c237 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -414,58 +414,6 @@ static void configure_mca(void) static unsigned ehci_debug_addr; #endif -/* - * Initialize any extra cores/threads in this package. - */ -static void intel_cores_init(device_t cpu) -{ - struct cpuid_result result; - unsigned cores, threads, i; - - result = cpuid_ext(0xb, 0); /* Threads per core */ - threads = result.ebx & 0xff; - - result = cpuid_ext(0xb, 1); /* Cores per package */ - cores = result.ebx & 0xff; - - /* Only initialize extra cores from BSP */ - if (cpu->path.apic.apic_id) - return; - - printk(BIOS_DEBUG, "CPU: %u has %u cores %u threads\n", - cpu->path.apic.apic_id, cores, threads); - - for (i = 1; i < cores; ++i) { - struct device_path cpu_path; - device_t new; - - /* Build the cpu device path */ - cpu_path.type = DEVICE_PATH_APIC; - cpu_path.apic.apic_id = - cpu->path.apic.apic_id + i; - - /* Update APIC ID if no hyperthreading */ - if (threads == 1) - cpu_path.apic.apic_id <<= 1; - - /* Allocate the new cpu device structure */ - new = alloc_dev(cpu->bus, &cpu_path); - if (!new) - continue; - - printk(BIOS_DEBUG, "CPU: %u has core %u\n", - cpu->path.apic.apic_id, - new->path.apic.apic_id); - - /* Start the new cpu */ - if (!start_cpu(new)) { - /* Record the error in cpu? */ - printk(BIOS_ERR, "CPU %u would not start!\n", - new->path.apic.apic_id); - } - } -} - static void model_206ax_init(device_t cpu) { char processor_name[49]; @@ -528,9 +476,6 @@ static void model_206ax_init(device_t cpu) /* Enable Turbo */ enable_turbo(); - - /* Start up extra cores */ - intel_cores_init(cpu); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig index 31d24bd..c3faa39 100644 --- a/src/cpu/intel/model_6ex/Kconfig +++ b/src/cpu/intel/model_6ex/Kconfig @@ -3,4 +3,3 @@ config CPU_INTEL_MODEL_6EX select SMP select SSE2 select UDELAY_LAPIC - select AP_IN_SIPI_WAIT diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 1c8c72b..a0afd2e 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -205,9 +205,6 @@ static void model_6ex_init(device_t cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors(); - - /* Start up my cpu siblings */ - intel_sibling_init(cpu); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig index 851685c..065cdd9 100644 --- a/src/cpu/intel/model_6fx/Kconfig +++ b/src/cpu/intel/model_6fx/Kconfig @@ -3,4 +3,3 @@ config CPU_INTEL_MODEL_6FX select SMP select SSE2 select UDELAY_LAPIC - select AP_IN_SIPI_WAIT diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 106719e..c5d7a6b 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -243,9 +243,6 @@ static void model_6fx_init(device_t cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors(); - - /* Start up my cpu siblings */ - intel_sibling_init(cpu); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c index 8fd8abc..fa9e05f 100644 --- a/src/cpu/intel/model_f2x/model_f2x_init.c +++ b/src/cpu/intel/model_f2x/model_f2x_init.c @@ -60,9 +60,6 @@ static void model_f2x_init(device_t cpu) /* Enable the local cpu apics */ setup_lapic(); - - /* Start up my cpu siblings */ - intel_sibling_init(cpu); }; static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index 2504ba9..dd2a45f 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -43,9 +43,6 @@ static void model_f3x_init(device_t cpu) /* Enable the local cpu apics */ setup_lapic(); - - /* Start up my cpu siblings */ - intel_sibling_init(cpu); }; static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c index f3f0b2a..af7d9d2 100644 --- a/src/cpu/intel/model_f4x/model_f4x_init.c +++ b/src/cpu/intel/model_f4x/model_f4x_init.c @@ -51,9 +51,6 @@ static void model_f4x_init(device_t cpu) /* Enable the local cpu apics */ setup_lapic(); - - /* Start up my cpu siblings */ - intel_sibling_init(cpu); }; static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/socket_LGA771/Kconfig b/src/cpu/intel/socket_LGA771/Kconfig index 62bd17b..f549210 100644 --- a/src/cpu/intel/socket_LGA771/Kconfig +++ b/src/cpu/intel/socket_LGA771/Kconfig @@ -3,4 +3,3 @@ config CPU_INTEL_SOCKET_LGA771 select CPU_INTEL_MODEL_6FX select SSE2 select MMX - select AP_IN_SIPI_WAIT diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index e491d46..061d3d3 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -66,31 +66,28 @@ static void copy_secondary_start_to_1m_below(void) printk(BIOS_DEBUG, "start_eip=0x%08lx, offset=0x%08lx, code_size=0x%08lx\n", start_eip, ((unsigned long)_secondary_start - start_eip), code_size); } -static int lapic_start_cpu(unsigned long apicid) +static struct bus *current_cpu_bus; + +static int lapic_start_cpus(struct bus *cpu_bus) { int timeout; unsigned long send_status, accept_status, start_eip; - int j, num_starts, maxlvt; + int maxlvt; /* * Starting actual IPI sequence... */ - printk(BIOS_SPEW, "Asserting INIT.\n"); - - /* - * Turn INIT on target chip - */ - lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); + current_cpu_bus = cpu_bus; - /* - * Send IPI - */ + printk(BIOS_SPEW, "Asserting INIT.\n"); - lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT - | LAPIC_DM_INIT); + /* Send INIT SIPI to target chip */ + lapic_write_around(LAPIC_ICR2, 0); + lapic_write_around(LAPIC_ICR, LAPIC_INT_ASSERT + | LAPIC_DM_INIT | LAPIC_DEST_ALLBUT); - printk(BIOS_SPEW, "Waiting for send to finish...\n"); + printk(BIOS_DEBUG, "Waiting for send to finish...\n"); timeout = 0; do { printk(BIOS_SPEW, "+"); @@ -98,108 +95,67 @@ static int lapic_start_cpu(unsigned long apicid) send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; } while (send_status && (timeout++ < 1000)); if (timeout >= 1000) { - printk(BIOS_ERR, "CPU %ld: First apic write timed out. Disabling\n", - apicid); + printk(BIOS_DEBUG, "First apic write timed out. Disabling\n"); // too bad. - printk(BIOS_ERR, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); + printk(BIOS_DEBUG, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); if (lapic_read(LAPIC_ESR)) { - printk(BIOS_ERR, "Try to reset ESR\n"); + printk(BIOS_DEBUG, "Try to reset ESR\n"); lapic_write_around(LAPIC_ESR, 0); - printk(BIOS_ERR, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); + printk(BIOS_DEBUG, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); } return 0; } -#if !CONFIG_CPU_AMD_MODEL_10XXX && !CONFIG_CPU_INTEL_MODEL_206AX - mdelay(10); -#endif + start_eip = get_valid_start_eip((unsigned long)_secondary_start); + + maxlvt = 4; + + printk(BIOS_SPEW, "Sending STARTUP.\n"); + lapic_read_around(LAPIC_SPIV); + lapic_write(LAPIC_ESR, 0); + lapic_read(LAPIC_ESR); + printk(BIOS_SPEW, "After apic_write.\n"); - printk(BIOS_SPEW, "Deasserting INIT.\n"); + /* + * STARTUP IPI + */ /* Target chip */ - lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); + lapic_write_around(LAPIC_ICR2, 0); - /* Send IPI */ - lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT); + /* Boot on the stack */ + /* Kick the second */ + lapic_write_around(LAPIC_ICR, LAPIC_INT_ASSERT | LAPIC_DM_STARTUP | LAPIC_DEST_ALLBUT + | (start_eip >> 12)); - printk(BIOS_SPEW, "Waiting for send to finish...\n"); + /* + * Give the other CPU some time to accept the IPI. + */ + udelay(300); + + printk(BIOS_DEBUG, "Startup point 1.\n"); + + printk(BIOS_DEBUG, "Waiting for send to finish...\n"); timeout = 0; do { - printk(BIOS_SPEW, "+"); + printk(BIOS_DEBUG, "+"); udelay(100); send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; } while (send_status && (timeout++ < 1000)); - if (timeout >= 1000) { - printk(BIOS_ERR, "CPU %ld: Second apic write timed out. Disabling\n", - apicid); - // too bad. - return 0; - } - - start_eip = get_valid_start_eip((unsigned long)_secondary_start); - -#if !CONFIG_CPU_AMD_MODEL_10XXX - num_starts = 2; -#else - num_starts = 1; -#endif /* - * Run STARTUP IPI loop. + * Give the other CPU some time to accept the IPI. */ - printk(BIOS_SPEW, "#startup loops: %d.\n", num_starts); - - maxlvt = 4; - - for (j = 1; j <= num_starts; j++) { - printk(BIOS_SPEW, "Sending STARTUP #%d to %lu.\n", j, apicid); + udelay(200); + /* + * Due to the Pentium erratum 3AP. + */ + if (maxlvt > 3) { lapic_read_around(LAPIC_SPIV); lapic_write(LAPIC_ESR, 0); - lapic_read(LAPIC_ESR); - printk(BIOS_SPEW, "After apic_write.\n"); - - /* - * STARTUP IPI - */ - - /* Target chip */ - lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); - - /* Boot on the stack */ - /* Kick the second */ - lapic_write_around(LAPIC_ICR, LAPIC_DM_STARTUP - | (start_eip >> 12)); - - /* - * Give the other CPU some time to accept the IPI. - */ - udelay(300); - - printk(BIOS_SPEW, "Startup point 1.\n"); - - printk(BIOS_SPEW, "Waiting for send to finish...\n"); - timeout = 0; - do { - printk(BIOS_SPEW, "+"); - udelay(100); - send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; - } while (send_status && (timeout++ < 1000)); - - /* - * Give the other CPU some time to accept the IPI. - */ - udelay(200); - /* - * Due to the Pentium erratum 3AP. - */ - if (maxlvt > 3) { - lapic_read_around(LAPIC_SPIV); - lapic_write(LAPIC_ESR, 0); - } - accept_status = (lapic_read(LAPIC_ESR) & 0xEF); - if (send_status || accept_status) - break; } - printk(BIOS_SPEW, "After Startup.\n"); + accept_status = (lapic_read(LAPIC_ESR) & 0xEF); + + printk(BIOS_DEBUG, "After Startup.\n"); if (send_status) printk(BIOS_WARNING, "APIC never delivered???\n"); if (accept_status) @@ -209,156 +165,34 @@ static int lapic_start_cpu(unsigned long apicid) return 1; } + /* Number of cpus that are currently running in coreboot */ static atomic_t active_cpus = ATOMIC_INIT(1); -/* start_cpu_lock covers last_cpu_index and secondary_stack. - * Only starting one cpu at a time let's me remove the logic - * for select the stack from assembly language. - * - * In addition communicating by variables to the cpu I - * am starting allows me to veryify it has started before - * start_cpu returns. - */ - -static spinlock_t start_cpu_lock = SPIN_LOCK_UNLOCKED; -static unsigned last_cpu_index = 0; volatile unsigned long secondary_stack; +extern unsigned char _estack[]; -int start_cpu(device_t cpu) +static void stop_all_ap_cpus(void) { - extern unsigned char _estack[]; - struct cpu_info *info; - unsigned long stack_end; - unsigned long apicid; - unsigned long index; - unsigned long count; - int result; - - spin_lock(&start_cpu_lock); - - /* Get the cpu's apicid */ - apicid = cpu->path.apic.apic_id; - - /* Get an index for the new processor */ - index = ++last_cpu_index; - - /* Find end of the new processors stack */ - stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info); - - /* Record the index and which cpu structure we are using */ - info = (struct cpu_info *)stack_end; - info->index = index; - info->cpu = cpu; - - /* Advertise the new stack to start_cpu */ - secondary_stack = stack_end; - - /* Until the cpu starts up report the cpu is not enabled */ - cpu->enabled = 0; - cpu->initialized = 0; - - /* Start the cpu */ - result = lapic_start_cpu(apicid); - - if (result) { - result = 0; - /* Wait 1s or until the new cpu calls in */ - for(count = 0; count < 100000 ; count++) { - if (secondary_stack == 0) { - result = 1; - break; - } - udelay(10); - } - } - secondary_stack = 0; - spin_unlock(&start_cpu_lock); - return result; -} - -#if CONFIG_AP_IN_SIPI_WAIT - -/** - * Sending INIT IPI to self is equivalent of asserting #INIT with a bit of delay. - * An undefined number of instruction cycles will complete. All global locks - * must be released before INIT IPI and no printk is allowed after this. - * De-asserting INIT IPI is a no-op on later Intel CPUs. - * - * If you set DEBUG_HALT_SELF to 1, printk's after INIT IPI are enabled - * but running thread may halt without releasing the lock and effectively - * deadlock other CPUs. - */ -#define DEBUG_HALT_SELF 0 - -/** - * Normally this function is defined in lapic.h as an always inline function - * that just keeps the CPU in a hlt() loop. This does not work on all CPUs. - * I think all hyperthreading CPUs might need this version, but I could only - * verify this on the Intel Core Duo - */ -void stop_this_cpu(void) -{ - int timeout; unsigned long send_status; - unsigned long id; - - id = lapic_read(LAPIC_ID) >> 24; - - printk(BIOS_DEBUG, "CPU %ld going down...\n", id); - - /* send an LAPIC INIT to myself */ - lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id)); - lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT | LAPIC_DM_INIT); + int timeout; + /* send an LAPIC INIT to all but myself */ + lapic_write_around(LAPIC_ICR2, 0); + lapic_write_around(LAPIC_ICR, LAPIC_INT_ASSERT | LAPIC_DM_INIT | LAPIC_DEST_ALLBUT); /* wait for the ipi send to finish */ -#if DEBUG_HALT_SELF printk(BIOS_SPEW, "Waiting for send to finish...\n"); -#endif timeout = 0; do { -#if DEBUG_HALT_SELF printk(BIOS_SPEW, "+"); -#endif udelay(100); send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; } while (send_status && (timeout++ < 1000)); if (timeout >= 1000) { -#if DEBUG_HALT_SELF printk(BIOS_ERR, "timed out\n"); -#endif } mdelay(10); - -#if DEBUG_HALT_SELF - printk(BIOS_SPEW, "Deasserting INIT.\n"); -#endif - /* Deassert the LAPIC INIT */ - lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id)); - lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT); - -#if DEBUG_HALT_SELF - printk(BIOS_SPEW, "Waiting for send to finish...\n"); -#endif - timeout = 0; - do { -#if DEBUG_HALT_SELF - printk(BIOS_SPEW, "+"); -#endif - udelay(100); - send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; - } while (send_status && (timeout++ < 1000)); - if (timeout >= 1000) { -#if DEBUG_HALT_SELF - printk(BIOS_ERR, "timed out\n"); -#endif - } - - while(1) { - hlt(); - } } -#endif #ifdef __SSE3__ static __inline__ __attribute__((always_inline)) unsigned long readcr4(void) @@ -381,66 +215,21 @@ static __inline__ __attribute__((always_inline)) void writecr4(unsigned long Dat #endif /* C entry point of secondary cpus */ -void secondary_cpu_init(void) +void secondary_cpu_init(int index) { - atomic_inc(&active_cpus); -#if CONFIG_SERIAL_CPU_INIT - spin_lock(&start_cpu_lock); -#endif - #ifdef __SSE3__ - /* - * Seems that CR4 was cleared when AP start via lapic_start_cpu() - * Turn on CR4.OSFXSR and CR4.OSXMMEXCPT when SSE options enabled - */ - u32 cr4_val; - cr4_val = readcr4(); - cr4_val |= (1 << 9 | 1 << 10); - writecr4(cr4_val); -#endif - cpu_initialize(); -#if CONFIG_SERIAL_CPU_INIT - spin_unlock(&start_cpu_lock); + /* + * Seems that CR4 was cleared when AP start via lapic_start_cpu() + * Turn on CR4.OSFXSR and CR4.OSXMMEXCPT when SSE options enabled + */ + u32 cr4_val; + cr4_val = readcr4(); + cr4_val |= (1 << 9 | 1 << 10); + writecr4(cr4_val); #endif - + atomic_inc(&active_cpus); + cpu_initialize(current_cpu_bus, index); atomic_dec(&active_cpus); - - stop_this_cpu(); -} - -static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu) -{ - device_t cpu; - /* Loop through the cpus once getting them started */ - - for(cpu = cpu_bus->children; cpu ; cpu = cpu->sibling) { - if (cpu->path.type != DEVICE_PATH_APIC) { - continue; - } - #if !CONFIG_SERIAL_CPU_INIT - if(cpu==bsp_cpu) { - continue; - } - #endif - - if (!cpu->enabled) { - continue; - } - - if (cpu->initialized) { - continue; - } - - if (!start_cpu(cpu)) { - /* Record the error in cpu? */ - printk(BIOS_ERR, "CPU 0x%02x would not start!\n", - cpu->path.apic.apic_id); - } -#if CONFIG_SERIAL_CPU_INIT - udelay(10); -#endif - } - } static void wait_other_cpus_stop(struct bus *cpu_bus) @@ -473,6 +262,7 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) cpu->path.apic.apic_id); } } + stop_all_ap_cpus(); printk(BIOS_DEBUG, "All AP CPUs stopped (%ld loops)\n", loopcount); } @@ -481,10 +271,6 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) void initialize_cpus(struct bus *cpu_bus) { struct device_path cpu_path; - struct cpu_info *info; - - /* Find the info struct for this cpu */ - info = cpu_info(); #if NEED_LAPIC == 1 /* Ensure the local apic is enabled */ @@ -499,9 +285,6 @@ void initialize_cpus(struct bus *cpu_bus) cpu_path.cpu.id = 0; #endif - /* Find the device structure for the boot cpu */ - info->cpu = alloc_find_dev(cpu_bus, &cpu_path); - #if CONFIG_SMP copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init #endif @@ -512,21 +295,11 @@ void initialize_cpus(struct bus *cpu_bus) cpus_ready_for_init(); -#if CONFIG_SMP - #if !CONFIG_SERIAL_CPU_INIT - /* start all aps at first, so we can init ECC all together */ - start_other_cpus(cpu_bus, info->cpu); - #endif -#endif - /* Initialize the bootstrap processor */ - cpu_initialize(); + cpu_initialize(cpu_bus, 0); #if CONFIG_SMP - #if CONFIG_SERIAL_CPU_INIT - start_other_cpus(cpu_bus, info->cpu); - #endif - + lapic_start_cpus(cpu_bus); /* Now wait the rest of the cpus stop*/ wait_other_cpus_stop(cpu_bus); #endif diff --git a/src/cpu/x86/lapic/secondary.S b/src/cpu/x86/lapic/secondary.S index dc00b08..67e44c4 100644 --- a/src/cpu/x86/lapic/secondary.S +++ b/src/cpu/x86/lapic/secondary.S @@ -2,7 +2,7 @@ #include <cpu/x86/lapic_def.h> .text - .globl _secondary_start, _secondary_start_end + .globl _secondary_start, _secondary_start_end, cpucount .balign 4096 _secondary_start: .code16 @@ -38,15 +38,25 @@ _secondary_start: /* Load the Interrupt descriptor table */ lidt idtarg - /* Set the stack pointer, and flag that we are done */ - xorl %eax, %eax - movl secondary_stack, %esp - movl %eax, secondary_stack + /* increment our cpu index */ + movl $1, %eax + lock xadd %eax, cpucount + incl %eax + movl %eax, %ecx + + /* assign stack for this specific cpu */ + mov _stack, %esp + mov $CONFIG_STACK_SIZE, %ebx + mul %ebx + add %eax, %esp + pushl %ecx call secondary_cpu_init 1: hlt jmp 1b +cpucount: + .long 1 gdtaddr: .word gdt_limit /* the table limit */ .long gdt /* we know the offset */ diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index 814c5f1..7aa17c2 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -3,8 +3,10 @@ */ #include <console/console.h> +#include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/pae.h> +#include <cpu/x86/lapic.h> #include <string.h> static void paging_off(void) @@ -43,6 +45,14 @@ static void paging_on(void *pdp) ); } +static int cpu_index(void) +{ + device_t dev = dev_find_lapic(lapicid()); + if (!dev) + return -1; + return dev->path.apic.index; +} + void *map_2M_page(unsigned long page) { struct pde { @@ -60,7 +70,9 @@ void *map_2M_page(unsigned long page) unsigned long window; void *result; int i; + index = cpu_index(); + if ((index < 0) || (index >= CONFIG_MAX_CPUS)) { return MAPPING_ERROR; } diff --git a/src/drivers/i2c/w83795/w83795.c b/src/drivers/i2c/w83795/w83795.c index 392471a..12be4da 100644 --- a/src/drivers/i2c/w83795/w83795.c +++ b/src/drivers/i2c/w83795/w83795.c @@ -22,6 +22,7 @@ #include <console/console.h> #include <device/device.h> #include "southbridge/amd/cimx/sb700/smbus.h" /*SMBUS_IO_BASE*/ +#include <cpu/x86/lapic.h> #include "w83795.h" static u32 w83795_set_bank(u8 bank) @@ -224,10 +225,8 @@ static void w83795_init(w83795_fan_mode_t mode, u8 dts_src) static void w83795_hwm_init(device_t dev) { struct device *cpu; - struct cpu_info *info; - info = cpu_info(); - cpu = info->cpu; + cpu = dev_find_lapic(lapicid()); if (!cpu) die("CPU: missing cpu device structure"); diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index c2113c1..9765dfd 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -4,10 +4,12 @@ #include <arch/cpu.h> #if !defined(__ROMCC__) -void cpu_initialize(void); +void cpu_initialize(struct bus *cpu_bus, int index); struct bus; void initialize_cpus(struct bus *cpu_bus); -void secondary_cpu_init(void); +void secondary_cpu_init(int index); + +extern unsigned int cpucount; #if !CONFIG_WAIT_BEFORE_CPUS_INIT #define cpus_ready_for_init() do {} while(0) diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 078f2a7..5c48025 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -52,20 +52,13 @@ static inline __attribute__((always_inline)) unsigned long lapicid(void) } #ifndef __ROMCC__ -#if CONFIG_AP_IN_SIPI_WAIT != 1 -/* If we need to go back to sipi wait, we use the long non-inlined version of - * this function in lapic_cpu_init.c - */ static inline __attribute__((always_inline)) void stop_this_cpu(void) { - /* Called by an AP when it is ready to halt and wait for a new task */ - for(;;) { - hlt(); - } + /* Called by an AP when it is ready to halt and wait for a new task */ + for(;;) { + hlt(); + } } -#else -void stop_this_cpu(void); -#endif #if !defined(__PRE_RAM__) diff --git a/src/include/device/path.h b/src/include/device/path.h index 63e9538..018fb93 100644 --- a/src/include/device/path.h +++ b/src/include/device/path.h @@ -40,6 +40,7 @@ struct apic_path unsigned apic_id; unsigned node_id; unsigned core_id; + unsigned index; }; struct apic_cluster_path

1 0

Trac reminder: list of new ticket(s)
by coreboot tracker 02 Jul '12

02 Jul '12

1 0

Patch merged into coreboot/master: 1816569 Intel CPUs: execute microcode update only once per core
by gerrit＠coreboot.org 02 Jul '12

02 Jul '12

the following patch was just integrated into master: commit 18165693d04195d9fb80c13e1e420cb9be8991b6 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Jun 27 16:14:49 2012 +0300 Intel CPUs: execute microcode update only once per core Early HT-enabled CPUs do not serialize microcode updates within a core. Solve this by running microcode updates on the thread with the smallest lapic ID of a core only. Also set MTRRs once per core only. Change-Id: I6a3cc9ecec2d8e0caed29605a9b19ec35a817620 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Jun 27 16:04:29 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Thu Jun 28 00:16:32 2012, giving +2 Reviewed-By: Sven Schnelle <svens(a)stackframe.org> at Wed Jun 27 16:57:37 2012, giving +2 See http://review.coreboot.org/1142 for details. -gerrit

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Re: [coreboot] [ltp] Re: [Thinkpad] Free T60
by Carl-Daniel Hailfinger 02 Jul '12

02 Jul '12

[CC coreboot(a)coreboot.org] Am 01.07.2012 16:45 schrieb Henrique de Moraes Holschuh: > On Mon, 25 Jun 2012, Carl-Daniel Hailfinger wrote: >> You do know that all Thinkpad T60/X60 can replace the BIOS with coreboot? > How would that work? About half the stuff the firmware does is an > interaction between the EC and the SMBIOS, did anyone reverse engineer > that? Actually, yes. You can achieve quite a lot if you have IDA Pro and a few high-end logic analyzers at hand. > Or are you guys just running the EC in whatever state it cold-starts at? > You can probably get away with it for a while on a T60/X60, but... > > Well, at least make sure to have thinkpad-acpi and use something to > monitor the kernel log, so that if the EC starts alarming that the > machine is going to catch fire, thinkpad-acpi will LOG_ALERT and > LOG_CRIT to the kernel log, and something will tell you to DO SOMETHING > ASAP. Gnome thinks it knows better, and *actively* refuses[1] to output > even the two "your box is about to do something REALLY bad" highest > priority log levels. KDE is not that irresponsible and will alert you. > > [1] as in: it was done on purpose, because "users don't know what to do > with those messages anyway". The information about assisted machine suicide on GNOME is actually quite interesting, I don't know how this is handled on a machine running coreboot. Regards, Carl-Daniel

3 2

Patch set updated for coreboot: 65529a4 Intel model_106cx: change CAR to model_6ex
by Kyösti Mälkki 02 Jul '12

02 Jul '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/642 -gerrit commit 65529a4d5647fafe0320fe4e3a5b497dc5dd6d1d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jun 28 21:50:43 2012 +0300 Intel model_106cx: change CAR to model_6ex Diff between model_106cx and model_6ex CAR codes suggests currently used model_106cx CAR is not optimal - destination RAM and source ROM of ramstage copy_and_run are only partly set cacheable. It appears variable MTRR setting for XIP cache is left enabled on model_106cx code, where it should have extended to cover all of Flash. Introduces untested functional change on boards: intel/d945gclf iwave/iWRainbowG6 Deletes file: model_106cx/cache_as_ram.inc Change-Id: I35229f8433927e83821e72e9d9a9fc8fb09c3f1d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/model_106cx/Makefile.inc | 2 +- src/cpu/intel/model_106cx/cache_as_ram.inc | 246 ---------------------------- 2 files changed, 1 insertions(+), 247 deletions(-) diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc index edcd01c..018febc 100644 --- a/src/cpu/intel/model_106cx/Makefile.inc +++ b/src/cpu/intel/model_106cx/Makefile.inc @@ -1,4 +1,4 @@ driver-y += model_106cx_init.c subdirs-y += ../../x86/name -cpu_incs += $(src)/cpu/intel/model_106cx/cache_as_ram.inc +cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc deleted file mode 100644 index c626cd8..0000000 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ /dev/null @@ -1,246 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <cpu/x86/stack.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/post_code.h> - -#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1) - -#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE -#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE - - /* Save the BIST result. */ - movl %eax, %ebp - -cache_as_ram: - post_code(0x20) - - /* Send INIT IPI to all excluding ourself. */ - movl $0x000C4500, %eax - movl $0xFEE00300, %esi - movl %eax, (%esi) - - /* Zero out all fixed range and variable range MTRRs. */ - movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) / 2), %edi - xorl %eax, %eax - xorl %edx, %edx -clear_mtrrs: - movw (%esi), %bx - movzx %bx, %ecx - wrmsr - add $2, %esi - dec %edi - jnz clear_mtrrs - - /* Configure the default memory type to uncacheable. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - andl $(~0x00000cff), %eax - wrmsr - - /* Set Cache-as-RAM base address. */ - movl $(MTRRphysBase_MSR(0)), %ecx - movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax - xorl %edx, %edx - wrmsr - - /* Set Cache-as-RAM mask. */ - movl $(MTRRphysMask_MSR(0)), %ecx - movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax - movl $CPU_PHYSMASK_HI, %edx - wrmsr - - /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $MTRRdefTypeEn, %eax - wrmsr - - /* Enable L2 cache. */ - movl $0x11e, %ecx - rdmsr - orl $(1 << 8), %eax - wrmsr - - /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax - andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax - invd - movl %eax, %cr0 - - /* Clear the cache memory reagion. */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx - // movl $0x23322332, %eax - xorl %eax, %eax - rep stosl - - /* Enable Cache-as-RAM mode by disabling cache. */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - -#if CONFIG_XIP_ROM_SIZE - /* Enable cache for our code in Flash because we do XIP here */ - movl $MTRRphysBase_MSR(1), %ecx - xorl %edx, %edx - /* - * IMPORTANT: The following calculation _must_ be done at runtime. See - * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html - */ - movl $copy_and_run, %eax - andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax - orl $MTRR_TYPE_WRBACK, %eax - wrmsr - - movl $MTRRphysMask_MSR(1), %ecx - movl $CPU_PHYSMASK_HI, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax - wrmsr -#endif /* CONFIG_XIP_ROM_SIZE */ - - /* Enable cache. */ - movl %cr0, %eax - andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax - movl %eax, %cr0 - - /* Set up the stack pointer. */ -#if CONFIG_USBDEBUG - /* Leave some space for the struct ehci_debug_info. */ - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax -#else - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax -#endif - movl %eax, %esp - - /* Restore the BIST result. */ - movl %ebp, %eax - movl %esp, %ebp - pushl %eax - - post_code(0x23) - - /* Call romstage.c main function. */ - call main - - post_code(0x2f) - - post_code(0x30) - - /* Disable cache. */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - - post_code(0x31) - - /* Disable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - andl $(~MTRRdefTypeEn), %eax - wrmsr - - post_code(0x31) - - invd - - post_code(0x33) - - /* Enable cache. */ - movl %cr0, %eax - andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax - movl %eax, %cr0 - - post_code(0x36) - - /* Disable cache. */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - - post_code(0x38) - - /* Enable Write Back and Speculative Reads for the first 1MB. */ - movl $MTRRphysBase_MSR(0), %ecx - movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax - xorl %edx, %edx - wrmsr - movl $MTRRphysMask_MSR(0), %ecx - movl $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax - movl $CPU_PHYSMASK_HI, %edx - wrmsr - - post_code(0x39) - - /* And enable cache again after setting MTRRs. */ - movl %cr0, %eax - andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax - movl %eax, %cr0 - - post_code(0x3a) - - /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $MTRRdefTypeEn, %eax - wrmsr - - post_code(0x3b) - - /* Invalidate the cache again. */ - invd - - post_code(0x3c) - - /* Clear boot_complete flag. */ - xorl %ebp, %ebp -__main: - post_code(POST_PREPARE_RAMSTAGE) - cld /* Clear direction flag. */ - - movl %ebp, %esi - - movl $ROMSTAGE_STACK, %esp - movl %esp, %ebp - pushl %esi - call copy_and_run - -.Lhlt: - post_code(POST_DEAD_CODE) - hlt - jmp .Lhlt - -mtrr_table: - /* Fixed MTRRs */ - .word 0x250, 0x258, 0x259 - .word 0x268, 0x269, 0x26A - .word 0x26B, 0x26C, 0x26D - .word 0x26E, 0x26F - /* Variable MTRRs */ - .word 0x200, 0x201, 0x202, 0x203 - .word 0x204, 0x205, 0x206, 0x207 - .word 0x208, 0x209, 0x20A, 0x20B - .word 0x20C, 0x20D, 0x20E, 0x20F -mtrr_table_end: -

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Patch set updated for coreboot: c4077f7 Intel cpus: Extend cache to cover complete Flash Device
by Kyösti Mälkki 02 Jul '12

02 Jul '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1146 -gerrit commit c4077f711d84cf6084c97af47adf0c2afecc352d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jun 30 11:41:08 2012 +0300 Intel cpus: Extend cache to cover complete Flash Device CACHE_ROM_SIZE default is ROM_SIZE, the Flash device size set in menuconfig. This fixes a case where 8 MB SPI flash MTRR setup would not cover the bottom 4 MB when ramstage is decompressed. Verify CACHE_ROM_SIZE is power of two. One may set CACHE_ROM_SIZE==0 to disable this cache. Change-Id: Ib2b4ea528a092b96ff954894e60406d64f250783 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/car/cache_as_ram_ht.inc | 5 ++--- src/cpu/intel/model_206ax/cache_as_ram.inc | 6 ++++-- src/cpu/intel/model_6ex/cache_as_ram.inc | 8 +++++--- src/include/cpu/x86/mtrr.h | 6 ++++++ 4 files changed, 17 insertions(+), 8 deletions(-) diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 4e0f391..65da516 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -30,9 +30,6 @@ #define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) #define START_IPI_VECTOR ((CONFIG_AP_SIPI_VECTOR >> 12) & 0xff) -/* Base address to cache all of Flash ROM, just below 4GB. */ -#define CACHE_ROM_BASE ((1<<22 - CONFIG_CACHE_ROM_SIZE>>10)<<10) - #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE @@ -380,6 +377,7 @@ no_msr_11e: movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax wrmsr +#if CONFIG_CACHE_ROM_SIZE /* Enable caching and Speculative Reads for Flash ROM device. */ movl $MTRRphysBase_MSR(1), %ecx movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax @@ -389,6 +387,7 @@ no_msr_11e: rdmsr movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr +#endif post_code(0x39) diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index 33246ff..9a2db37 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -259,17 +259,19 @@ before_romstage: movl $CPU_PHYSMASK_HI, %edx // 36bit address space wrmsr +#if CONFIG_CACHE_ROM_SIZE /* Enable Caching and speculative Reads for the * complete ROM now that we actually have RAM. */ movl $MTRRphysBase_MSR(1), %ecx - movl $(0xffc00000 | MTRR_TYPE_WRPROT), %eax + movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(1), %ecx - movl $(~(4*1024*1024 - 1) | MTRRphysMaskValid), %eax + movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr +#endif post_code(0x39) diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index bdefb21..82a568a 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -191,15 +191,17 @@ clear_mtrrs: movl $CPU_PHYSMASK_HI, %edx wrmsr - /* Enable caching and Speculative Reads for the last 4MB. */ +#if CONFIG_CACHE_ROM_SIZE + /* Enable caching and Speculative Reads for Flash ROM device. */ movl $MTRRphysBase_MSR(1), %ecx - movl $(0xffc00000 | MTRR_TYPE_WRPROT), %eax + movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(1), %ecx - movl $(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax + movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr +#endif post_code(0x39) diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 8b5cc28..58bee04 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -56,6 +56,12 @@ void x86_setup_fixed_mtrrs(void); # error "CONFIG_XIP_ROM_SIZE is not a power of 2" #endif +#if ((CONFIG_CACHE_ROM_SIZE & (CONFIG_CACHE_ROM_SIZE -1)) != 0) +# error "CONFIG_CACHE_ROM_SIZE is not a power of 2" +#endif + +#define CACHE_ROM_BASE (((1<<20) - (CONFIG_CACHE_ROM_SIZE>>12))<<12) + #if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0 # error "CONFIG_RAMTOP must be a power of 2" #endif

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Patch set updated for coreboot: cdee7db Enable ROM cache for payload decompression on all boards
by Kyösti Mälkki 02 Jul '12

02 Jul '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1147 -gerrit commit cdee7dbfc78a3d171feec85e0d57c70c569a455d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jun 30 11:42:08 2012 +0300 Enable ROM cache for payload decompression on all boards The static size of 8 MB ChromeOS defines for SPI flash would extend over write-protection control MMIO of older LPC/FWH flash, so use a configurable region size instead. Change-Id: Ife6d11a29794bdbf0463911e589e86102e9b897d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/x86/Kconfig | 4 ---- src/cpu/x86/mtrr/mtrr.c | 8 ++++---- src/mainboard/samsung/lumpy/Kconfig | 4 ++++ src/mainboard/samsung/stumpy/Kconfig | 4 ++++ src/vendorcode/google/chromeos/Kconfig | 1 - 5 files changed, 12 insertions(+), 9 deletions(-) diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 0eaee2e..9ac7365 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -40,10 +40,6 @@ config LOGICAL_CPUS bool default y -config CACHE_ROM - bool - default n - config SMM_TSEG bool default n diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index f8b2591..611ace9 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -36,7 +36,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> -#include <cpu/x86/lapic.h> #include <arch/cpu.h> #include <arch/acpi.h> @@ -496,12 +495,13 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits); } -#if CONFIG_CACHE_ROM +#if CONFIG_CACHE_ROM_SIZE /* Enable Caching and speculative Reads for the * complete ROM now that we actually have RAM. */ - if (boot_cpu() && (acpi_slp_type != 3)) { - set_var_mtrr(total_mtrrs - 1, (4096 - 8)*1024, 8 * 1024, + if (acpi_slp_type != 3) { + set_var_mtrr(total_mtrrs - 1, (unsigned) CACHE_ROM_BASE>>10, + CONFIG_CACHE_ROM_SIZE>>10, MTRR_TYPE_WRPROT, address_bits); } #endif diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index 0835012..dd1e8d3 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -40,6 +40,10 @@ config MAX_CPUS int default 8 +config CACHE_ROM_SIZE + hex + default 0x800000 + config VGA_BIOS_FILE string default "pci8086,0106.rom" diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index 18094cf..ff7aaa2 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -39,6 +39,10 @@ config MAX_CPUS int default 8 +config CACHE_ROM_SIZE + hex + default 0x800000 + config VGA_BIOS_FILE string default "pci8086,0106.rom" diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 179bbb1..f098912 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -20,7 +20,6 @@ config CHROMEOS bool default n select TPM - select CACHE_ROM help Enable ChromeOS specific features like the GPIO sub table in the coreboot table. NOTE: Enabling this option on an unsupported

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coreboot July 2012