Patch set updated for coreboot: cdee7db Enable ROM cache for payload decompression on all boards
Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1147
-gerrit
commit cdee7dbfc78a3d171feec85e0d57c70c569a455d Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Sat Jun 30 11:42:08 2012 +0300
Enable ROM cache for payload decompression on all boards
The static size of 8 MB ChromeOS defines for SPI flash would extend over write-protection control MMIO of older LPC/FWH flash, so use a configurable region size instead.
Change-Id: Ife6d11a29794bdbf0463911e589e86102e9b897d Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/cpu/x86/Kconfig | 4 ---- src/cpu/x86/mtrr/mtrr.c | 8 ++++---- src/mainboard/samsung/lumpy/Kconfig | 4 ++++ src/mainboard/samsung/stumpy/Kconfig | 4 ++++ src/vendorcode/google/chromeos/Kconfig | 1 - 5 files changed, 12 insertions(+), 9 deletions(-)
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 0eaee2e..9ac7365 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -40,10 +40,6 @@ config LOGICAL_CPUS bool default y
-config CACHE_ROM - bool - default n - config SMM_TSEG bool default n diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index f8b2591..611ace9 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -36,7 +36,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> -#include <cpu/x86/lapic.h> #include <arch/cpu.h> #include <arch/acpi.h>
@@ -496,12 +495,13 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits); }
-#if CONFIG_CACHE_ROM +#if CONFIG_CACHE_ROM_SIZE /* Enable Caching and speculative Reads for the * complete ROM now that we actually have RAM. */ - if (boot_cpu() && (acpi_slp_type != 3)) { - set_var_mtrr(total_mtrrs - 1, (4096 - 8)*1024, 8 * 1024, + if (acpi_slp_type != 3) { + set_var_mtrr(total_mtrrs - 1, (unsigned) CACHE_ROM_BASE>>10, + CONFIG_CACHE_ROM_SIZE>>10, MTRR_TYPE_WRPROT, address_bits); } #endif diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index 0835012..dd1e8d3 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -40,6 +40,10 @@ config MAX_CPUS int default 8
+config CACHE_ROM_SIZE + hex + default 0x800000 + config VGA_BIOS_FILE string default "pci8086,0106.rom" diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index 18094cf..ff7aaa2 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -39,6 +39,10 @@ config MAX_CPUS int default 8
+config CACHE_ROM_SIZE + hex + default 0x800000 + config VGA_BIOS_FILE string default "pci8086,0106.rom" diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 179bbb1..f098912 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -20,7 +20,6 @@ config CHROMEOS bool default n select TPM - select CACHE_ROM help Enable ChromeOS specific features like the GPIO sub table in the coreboot table. NOTE: Enabling this option on an unsupported
-
Kyösti Mälkki