coreboot June 2012

coreboot@coreboot.org

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241 discussions

GA-6BXE doesn't boot with Intel PRO/1000 GT
by Tomi Leppänen 26 Jun '12

26 Jun '12

Hi, I have a Gigabyte GA-6BXE (Rev 2.1) motherboard with coreboot (built last week, I think). My processor is Intel Pentium III 550 and I have 786 MiB of RAM (actually 1 GiB but the motherboard can't see a part of it). It works just fine when I connect graphics card (ATI Rage II3 or Nvidia GeForce 2 MX) and some other network card I have (I've got 3Com and some other 100 Mb/s NIC). I can even connect both of them and it boots just fine. When I connect Intel PRO/1000 GT Desktop Adapter it doesn't boot. Post card gives me code 0x9B. Nothing appears to my screen nor it reads CD (System Rescue Disk, that is just some random Linux). I get the same results if I use ATI Radeon 9200SE as the graphics card (last post code is also 0x9B and display is black). Original bios didn't like that graphics card but it at least got into console, just had some "overlapping memory BAR stuff" I don't know much about and thus I couldn't get X working. I haven't tried that Intel NIC with the motherboard's original bios (requires flashing it back). I'd like to get that Intel's card working because I was about to try making a router out of that old hardware. In addition I noticed that my CD drive didn't work correctly if I connected it to first IDE connector on motherboard. It had some trouble loading Linux and dmesg output following: ata1.00: qc_timeout (cmd 0xa0) ata1.00: TEST_UNIT_READY failed (err_mask=0x4) ata1.00: configured for UDMA/33 which was repeated twice and later it told me that ata1.00: disabled, it was soft resetting link (still ata1.00) and last message about that is "EH complete". After that I couldn't use the CD drive. I don't know if there is something wrong with my hardware, but the other IDE bus works just fine, which I okay, as I don't need more than two devices. I've had problems with that motherboard's IDE bus before still using original bios. If you are going to make some patches or anything, I'd just like you to know that I don't have any other 'special' equipment than the (cheap) post card, but I have another GA-6BXE (though Rev 1.9) motherboard that beeps continuosly when I boot it (still has the original bios). I might be able to switch the chips, although the chip with coreboot has one leg broken and I use a resistor's leg instead, so it's kind of annoing to fiddle with. I also tried the motherboard with IWill Sloket and VIA C3 (1 GHz, Nehemiah core), which works nicely with original bios (with 133 MHz×7,5=~1 GHz clock), but it didn't work and the last post code is 0x01. The motherboard has DIP switches for selecting FSB speed and I tried with 100 and 133 MHz settings, neither worked. But that's not the main issue right now, although it would be nice to have that setup working too. I could also try one Socket 370 Celeron if you want. :) Thanks. Ps. I hope I didn't make too many typos as it's my second (or third, whatever) language (Finns are odd people, you know ;)) and I wrote this at midnight. Feel free to ask if you don't understand something. I also know that my parts are from different ages and that might be the source of some compatibility issues.

2 1

Patch set updated for coreboot: c831bf6 Use broadcast SIPI to startup siblings
by Sven Schnelle 25 Jun '12

25 Jun '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1139 -gerrit commit c831bf6d7ab4974862b92c3eaefd08361c841353 Author: Sven Schnelle <svens(a)stackframe.org> Date: Sun Jun 17 10:32:55 2012 +0200 Use broadcast SIPI to startup siblings Change-Id: Ic48a1ebab6a7c52aa76765f497268af09fa38c25 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/arch/x86/include/arch/cpu.h | 24 -- src/arch/x86/lib/cpu.c | 30 ++- src/cpu/intel/hyperthreading/Makefile.inc | 1 - src/cpu/intel/hyperthreading/intel_sibling.c | 73 ------- src/cpu/intel/model_1067x/model_1067x_init.c | 4 - src/cpu/intel/model_106cx/model_106cx_init.c | 4 - src/cpu/intel/model_6ex/model_6ex_init.c | 3 - src/cpu/intel/model_6fx/model_6fx_init.c | 3 - src/cpu/intel/model_f2x/model_f2x_init.c | 4 - src/cpu/intel/model_f3x/model_f3x_init.c | 4 - src/cpu/intel/model_f4x/model_f4x_init.c | 4 - src/cpu/x86/lapic/lapic_cpu_init.c | 295 ++++++-------------------- src/cpu/x86/lapic/secondary.S | 17 ++- src/include/cpu/cpu.h | 3 +- 14 files changed, 98 insertions(+), 371 deletions(-) diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 0dc92fb..0fe5ea5 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -158,30 +158,6 @@ struct cpu_driver { struct device; struct cpu_driver *find_cpu_driver(struct device *cpu); -struct cpu_info { - device_t cpu; - unsigned long index; -}; - -static inline struct cpu_info *cpu_info(void) -{ - struct cpu_info *ci; - __asm__("andl %%esp,%0; " - "orl %2, %0 " - :"=r" (ci) - : "0" (~(CONFIG_STACK_SIZE - 1)), - "r" (CONFIG_STACK_SIZE - sizeof(struct cpu_info)) - ); - return ci; -} - -static inline unsigned long cpu_index(void) -{ - struct cpu_info *ci; - ci = cpu_info(); - return ci->index; -} - struct cpuinfo_x86 { uint8_t x86; /* CPU family */ uint8_t x86_vendor; /* CPU vendor */ diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c index 98ede06..f63a67b 100644 --- a/src/arch/x86/lib/cpu.c +++ b/src/arch/x86/lib/cpu.c @@ -9,6 +9,7 @@ #include <device/path.h> #include <device/device.h> #include <smp/spinlock.h> +#include <cpu/x86/lapic.h> /* Standard macro to see if a specific flag is changeable */ static inline int flag_is_changeable_p(uint32_t flag) @@ -234,7 +235,11 @@ static void set_cpu_ops(struct device *cpu) cpu->ops = driver ? driver->ops : NULL; } -void cpu_initialize(void) +#if CONFIG_SMP +static spinlock_t start_cpu_lock = SPIN_LOCK_UNLOCKED; +#endif + +void cpu_initialize(struct bus *cpu_bus) { /* Because we busy wait at the printk spinlock. * It is important to keep the number of printed messages @@ -242,17 +247,21 @@ void cpu_initialize(void) * disabled. */ struct device *cpu; - struct cpu_info *info; struct cpuinfo_x86 c; + struct device_path cpu_path; + unsigned char id = lapicid(); - info = cpu_info(); + cpu_path.type = DEVICE_PATH_APIC; + cpu_path.apic.apic_id = id; - printk(BIOS_INFO, "Initializing CPU #%ld\n", info->index); - - cpu = info->cpu; - if (!cpu) { - die("CPU: missing cpu device structure"); - } +#if CONFIG_SMP + spin_lock(&start_cpu_lock); +#endif + cpu = alloc_find_dev(cpu_bus, &cpu_path); +#if CONFIG_SMP + spin_unlock(&start_cpu_lock); +#endif + printk(BIOS_DEBUG, "Initializing CPU #%d\n", id); /* Find what type of cpu we are dealing with */ identify_cpu(cpu); @@ -276,7 +285,6 @@ void cpu_initialize(void) printk(BIOS_DEBUG, "Using generic cpu ops (good)\n"); } - /* Initialize the cpu */ if (cpu->ops && cpu->ops->init) { cpu->enabled = 1; @@ -284,7 +292,7 @@ void cpu_initialize(void) cpu->ops->init(cpu); } - printk(BIOS_INFO, "CPU #%ld initialized\n", info->index); + printk(BIOS_INFO, "CPU #%d initialized\n", id); return; } diff --git a/src/cpu/intel/hyperthreading/Makefile.inc b/src/cpu/intel/hyperthreading/Makefile.inc deleted file mode 100644 index 8adbad9..0000000 --- a/src/cpu/intel/hyperthreading/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ramstage-y += intel_sibling.c diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c deleted file mode 100644 index 2d2e105..0000000 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ /dev/null @@ -1,73 +0,0 @@ -#include <console/console.h> -#include <cpu/cpu.h> -#include <cpu/x86/lapic.h> -#include <cpu/intel/hyperthreading.h> -#include <device/device.h> -#include <pc80/mc146818rtc.h> -#include <smp/spinlock.h> -#include <assert.h> - -#if !CONFIG_SERIAL_CPU_INIT -#error Intel hyper-threading requires serialized cpu init -#endif - -static int first_time = 1; -static int disable_siblings = !CONFIG_LOGICAL_CPUS; - -void intel_sibling_init(device_t cpu) -{ - unsigned i, siblings; - struct cpuid_result result; - - /* On the bootstrap processor see if I want sibling cpus enabled */ - if (first_time) { - first_time = 0; - get_option(&disable_siblings, "hyper_threading"); - } - result = cpuid(1); - /* Is hyperthreading supported */ - if (!(result.edx & (1 << 28))) { - return; - } - /* See how many sibling cpus we have */ - siblings = (result.ebx >> 16) & 0xff; - if (siblings < 1) { - siblings = 1; - } - - printk(BIOS_DEBUG, "CPU: %u %d siblings\n", - cpu->path.apic.apic_id, - siblings); - - /* See if I am a sibling cpu */ - if (cpu->path.apic.apic_id & (siblings -1)) { - if (disable_siblings) { - cpu->enabled = 0; - } - return; - } - - /* I am the primary cpu start up my siblings */ - for(i = 1; i < siblings; i++) { - struct device_path cpu_path; - device_t new; - /* Build the cpu device path */ - cpu_path.type = DEVICE_PATH_APIC; - cpu_path.apic.apic_id = cpu->path.apic.apic_id + i; - - - /* Allocate new cpu device structure iff sibling CPU - * was not in static device tree. - */ - new = alloc_find_dev(cpu->bus, &cpu_path); - - if (!new) { - continue; - } - - printk(BIOS_DEBUG, "CPU: %u has sibling %u\n", - cpu->path.apic.apic_id, - new->path.apic.apic_id); - } -} - diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index c6d716d9..ddd1381 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -29,7 +29,6 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> -#include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -221,9 +220,6 @@ static void model_1067x_init(device_t cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors(); - - /* Start up my cpu siblings */ - intel_sibling_init(cpu); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 4bf2924..8d2ef3d 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -27,7 +27,6 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> -#include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> #include <usbdebug.h> @@ -178,9 +177,6 @@ static void model_106cx_init(device_t cpu) configure_misc(); /* TODO: PIC thermal sensor control */ - - /* Start up my cpu siblings */ - intel_sibling_init(cpu); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 1c8c72b..a0afd2e 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -205,9 +205,6 @@ static void model_6ex_init(device_t cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors(); - - /* Start up my cpu siblings */ - intel_sibling_init(cpu); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 106719e..c5d7a6b 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -243,9 +243,6 @@ static void model_6fx_init(device_t cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors(); - - /* Start up my cpu siblings */ - intel_sibling_init(cpu); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c index ec78672..51b72a3 100644 --- a/src/cpu/intel/model_f2x/model_f2x_init.c +++ b/src/cpu/intel/model_f2x/model_f2x_init.c @@ -7,7 +7,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> -#include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> /* 512KB cache */ @@ -56,9 +55,6 @@ static void model_f2x_init(device_t cpu) /* Enable the local cpu apics */ setup_lapic(); - - /* Start up my cpu siblings */ - intel_sibling_init(cpu); }; static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index 580c98b..ca346da 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -7,7 +7,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> -#include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> static uint32_t microcode_updates[] = { @@ -39,9 +38,6 @@ static void model_f3x_init(device_t cpu) /* Enable the local cpu apics */ setup_lapic(); - - /* Start up my cpu siblings */ - intel_sibling_init(cpu); }; static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c index 54edf2e..c857cef 100644 --- a/src/cpu/intel/model_f4x/model_f4x_init.c +++ b/src/cpu/intel/model_f4x/model_f4x_init.c @@ -7,7 +7,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> -#include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> static uint32_t microcode_updates[] = { @@ -47,9 +46,6 @@ static void model_f4x_init(device_t cpu) /* Enable the local cpu apics */ setup_lapic(); - - /* Start up my cpu siblings */ - intel_sibling_init(cpu); }; static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index e491d46..3c0f5a2 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -66,31 +66,28 @@ static void copy_secondary_start_to_1m_below(void) printk(BIOS_DEBUG, "start_eip=0x%08lx, offset=0x%08lx, code_size=0x%08lx\n", start_eip, ((unsigned long)_secondary_start - start_eip), code_size); } -static int lapic_start_cpu(unsigned long apicid) +static struct bus *current_cpu_bus; + +static int lapic_start_cpus(struct bus *cpu_bus) { int timeout; unsigned long send_status, accept_status, start_eip; - int j, num_starts, maxlvt; + int maxlvt; /* * Starting actual IPI sequence... */ - printk(BIOS_SPEW, "Asserting INIT.\n"); - - /* - * Turn INIT on target chip - */ - lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); + current_cpu_bus = cpu_bus; - /* - * Send IPI - */ + printk(BIOS_SPEW, "Asserting INIT.\n"); - lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT - | LAPIC_DM_INIT); + /* Send INIT SIPI to target chip */ + lapic_write_around(LAPIC_ICR2, 0); + lapic_write_around(LAPIC_ICR, LAPIC_INT_ASSERT + | LAPIC_DM_INIT | LAPIC_DEST_ALLBUT); - printk(BIOS_SPEW, "Waiting for send to finish...\n"); + printk(BIOS_DEBUG, "Waiting for send to finish...\n"); timeout = 0; do { printk(BIOS_SPEW, "+"); @@ -98,108 +95,67 @@ static int lapic_start_cpu(unsigned long apicid) send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; } while (send_status && (timeout++ < 1000)); if (timeout >= 1000) { - printk(BIOS_ERR, "CPU %ld: First apic write timed out. Disabling\n", - apicid); + printk(BIOS_DEBUG, "First apic write timed out. Disabling\n"); // too bad. - printk(BIOS_ERR, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); + printk(BIOS_DEBUG, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); if (lapic_read(LAPIC_ESR)) { - printk(BIOS_ERR, "Try to reset ESR\n"); + printk(BIOS_DEBUG, "Try to reset ESR\n"); lapic_write_around(LAPIC_ESR, 0); - printk(BIOS_ERR, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); + printk(BIOS_DEBUG, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); } return 0; } -#if !CONFIG_CPU_AMD_MODEL_10XXX && !CONFIG_CPU_INTEL_MODEL_206AX - mdelay(10); -#endif + start_eip = get_valid_start_eip((unsigned long)_secondary_start); - printk(BIOS_SPEW, "Deasserting INIT.\n"); + maxlvt = 4; + + printk(BIOS_SPEW, "Sending STARTUP.\n"); + lapic_read_around(LAPIC_SPIV); + lapic_write(LAPIC_ESR, 0); + lapic_read(LAPIC_ESR); + printk(BIOS_SPEW, "After apic_write.\n"); + + /* + * STARTUP IPI + */ /* Target chip */ - lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); + lapic_write_around(LAPIC_ICR2, 0); - /* Send IPI */ - lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT); + /* Boot on the stack */ + /* Kick the second */ + lapic_write_around(LAPIC_ICR, LAPIC_INT_ASSERT | LAPIC_DM_STARTUP | LAPIC_DEST_ALLBUT + | (start_eip >> 12)); - printk(BIOS_SPEW, "Waiting for send to finish...\n"); + /* + * Give the other CPU some time to accept the IPI. + */ + udelay(300); + + printk(BIOS_DEBUG, "Startup point 1.\n"); + + printk(BIOS_DEBUG, "Waiting for send to finish...\n"); timeout = 0; do { - printk(BIOS_SPEW, "+"); + printk(BIOS_DEBUG, "+"); udelay(100); send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; } while (send_status && (timeout++ < 1000)); - if (timeout >= 1000) { - printk(BIOS_ERR, "CPU %ld: Second apic write timed out. Disabling\n", - apicid); - // too bad. - return 0; - } - - start_eip = get_valid_start_eip((unsigned long)_secondary_start); - -#if !CONFIG_CPU_AMD_MODEL_10XXX - num_starts = 2; -#else - num_starts = 1; -#endif /* - * Run STARTUP IPI loop. + * Give the other CPU some time to accept the IPI. */ - printk(BIOS_SPEW, "#startup loops: %d.\n", num_starts); - - maxlvt = 4; - - for (j = 1; j <= num_starts; j++) { - printk(BIOS_SPEW, "Sending STARTUP #%d to %lu.\n", j, apicid); + udelay(200); + /* + * Due to the Pentium erratum 3AP. + */ + if (maxlvt > 3) { lapic_read_around(LAPIC_SPIV); lapic_write(LAPIC_ESR, 0); - lapic_read(LAPIC_ESR); - printk(BIOS_SPEW, "After apic_write.\n"); - - /* - * STARTUP IPI - */ - - /* Target chip */ - lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); - - /* Boot on the stack */ - /* Kick the second */ - lapic_write_around(LAPIC_ICR, LAPIC_DM_STARTUP - | (start_eip >> 12)); - - /* - * Give the other CPU some time to accept the IPI. - */ - udelay(300); - - printk(BIOS_SPEW, "Startup point 1.\n"); - - printk(BIOS_SPEW, "Waiting for send to finish...\n"); - timeout = 0; - do { - printk(BIOS_SPEW, "+"); - udelay(100); - send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; - } while (send_status && (timeout++ < 1000)); - - /* - * Give the other CPU some time to accept the IPI. - */ - udelay(200); - /* - * Due to the Pentium erratum 3AP. - */ - if (maxlvt > 3) { - lapic_read_around(LAPIC_SPIV); - lapic_write(LAPIC_ESR, 0); - } - accept_status = (lapic_read(LAPIC_ESR) & 0xEF); - if (send_status || accept_status) - break; } - printk(BIOS_SPEW, "After Startup.\n"); + accept_status = (lapic_read(LAPIC_ESR) & 0xEF); + + printk(BIOS_DEBUG, "After Startup.\n"); if (send_status) printk(BIOS_WARNING, "APIC never delivered???\n"); if (accept_status) @@ -209,73 +165,12 @@ static int lapic_start_cpu(unsigned long apicid) return 1; } + /* Number of cpus that are currently running in coreboot */ static atomic_t active_cpus = ATOMIC_INIT(1); -/* start_cpu_lock covers last_cpu_index and secondary_stack. - * Only starting one cpu at a time let's me remove the logic - * for select the stack from assembly language. - * - * In addition communicating by variables to the cpu I - * am starting allows me to veryify it has started before - * start_cpu returns. - */ - -static spinlock_t start_cpu_lock = SPIN_LOCK_UNLOCKED; -static unsigned last_cpu_index = 0; volatile unsigned long secondary_stack; - -int start_cpu(device_t cpu) -{ - extern unsigned char _estack[]; - struct cpu_info *info; - unsigned long stack_end; - unsigned long apicid; - unsigned long index; - unsigned long count; - int result; - - spin_lock(&start_cpu_lock); - - /* Get the cpu's apicid */ - apicid = cpu->path.apic.apic_id; - - /* Get an index for the new processor */ - index = ++last_cpu_index; - - /* Find end of the new processors stack */ - stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info); - - /* Record the index and which cpu structure we are using */ - info = (struct cpu_info *)stack_end; - info->index = index; - info->cpu = cpu; - - /* Advertise the new stack to start_cpu */ - secondary_stack = stack_end; - - /* Until the cpu starts up report the cpu is not enabled */ - cpu->enabled = 0; - cpu->initialized = 0; - - /* Start the cpu */ - result = lapic_start_cpu(apicid); - - if (result) { - result = 0; - /* Wait 1s or until the new cpu calls in */ - for(count = 0; count < 100000 ; count++) { - if (secondary_stack == 0) { - result = 1; - break; - } - udelay(10); - } - } - secondary_stack = 0; - spin_unlock(&start_cpu_lock); - return result; -} +extern unsigned char _estack[]; #if CONFIG_AP_IN_SIPI_WAIT @@ -383,64 +278,19 @@ static __inline__ __attribute__((always_inline)) void writecr4(unsigned long Dat /* C entry point of secondary cpus */ void secondary_cpu_init(void) { - atomic_inc(&active_cpus); -#if CONFIG_SERIAL_CPU_INIT - spin_lock(&start_cpu_lock); -#endif - #ifdef __SSE3__ - /* - * Seems that CR4 was cleared when AP start via lapic_start_cpu() - * Turn on CR4.OSFXSR and CR4.OSXMMEXCPT when SSE options enabled - */ - u32 cr4_val; - cr4_val = readcr4(); - cr4_val |= (1 << 9 | 1 << 10); - writecr4(cr4_val); + /* + * Seems that CR4 was cleared when AP start via lapic_start_cpu() + * Turn on CR4.OSFXSR and CR4.OSXMMEXCPT when SSE options enabled + */ + u32 cr4_val; + cr4_val = readcr4(); + cr4_val |= (1 << 9 | 1 << 10); + writecr4(cr4_val); #endif - cpu_initialize(); -#if CONFIG_SERIAL_CPU_INIT - spin_unlock(&start_cpu_lock); -#endif - + atomic_inc(&active_cpus); + cpu_initialize(current_cpu_bus); atomic_dec(&active_cpus); - - stop_this_cpu(); -} - -static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu) -{ - device_t cpu; - /* Loop through the cpus once getting them started */ - - for(cpu = cpu_bus->children; cpu ; cpu = cpu->sibling) { - if (cpu->path.type != DEVICE_PATH_APIC) { - continue; - } - #if !CONFIG_SERIAL_CPU_INIT - if(cpu==bsp_cpu) { - continue; - } - #endif - - if (!cpu->enabled) { - continue; - } - - if (cpu->initialized) { - continue; - } - - if (!start_cpu(cpu)) { - /* Record the error in cpu? */ - printk(BIOS_ERR, "CPU 0x%02x would not start!\n", - cpu->path.apic.apic_id); - } -#if CONFIG_SERIAL_CPU_INIT - udelay(10); -#endif - } - } static void wait_other_cpus_stop(struct bus *cpu_bus) @@ -481,10 +331,6 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) void initialize_cpus(struct bus *cpu_bus) { struct device_path cpu_path; - struct cpu_info *info; - - /* Find the info struct for this cpu */ - info = cpu_info(); #if NEED_LAPIC == 1 /* Ensure the local apic is enabled */ @@ -499,9 +345,6 @@ void initialize_cpus(struct bus *cpu_bus) cpu_path.cpu.id = 0; #endif - /* Find the device structure for the boot cpu */ - info->cpu = alloc_find_dev(cpu_bus, &cpu_path); - #if CONFIG_SMP copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init #endif @@ -512,21 +355,11 @@ void initialize_cpus(struct bus *cpu_bus) cpus_ready_for_init(); -#if CONFIG_SMP - #if !CONFIG_SERIAL_CPU_INIT - /* start all aps at first, so we can init ECC all together */ - start_other_cpus(cpu_bus, info->cpu); - #endif -#endif - /* Initialize the bootstrap processor */ - cpu_initialize(); + cpu_initialize(cpu_bus); #if CONFIG_SMP - #if CONFIG_SERIAL_CPU_INIT - start_other_cpus(cpu_bus, info->cpu); - #endif - + lapic_start_cpus(cpu_bus); /* Now wait the rest of the cpus stop*/ wait_other_cpus_stop(cpu_bus); #endif diff --git a/src/cpu/x86/lapic/secondary.S b/src/cpu/x86/lapic/secondary.S index dc00b08..afffbd3 100644 --- a/src/cpu/x86/lapic/secondary.S +++ b/src/cpu/x86/lapic/secondary.S @@ -38,10 +38,19 @@ _secondary_start: /* Load the Interrupt descriptor table */ lidt idtarg - /* Set the stack pointer, and flag that we are done */ - xorl %eax, %eax - movl secondary_stack, %esp - movl %eax, secondary_stack +cpu: + .long 0 + + /* increment our cpu index */ + movl $1, %eax + lock xadd %eax, cpu + incl %eax + + /* assign stack for this specific cpu */ + mov _stack, %esp + mov $CONFIG_STACK_SIZE, %ebx + mul %ebx + add %eax, %esp call secondary_cpu_init 1: hlt diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index c2113c1..b631d4e 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -3,8 +3,9 @@ #include <arch/cpu.h> +struct bus; #if !defined(__ROMCC__) -void cpu_initialize(void); +void cpu_initialize(struct bus *cpu_bus); struct bus; void initialize_cpus(struct bus *cpu_bus); void secondary_cpu_init(void);

1 0

RFC: automatic mptable creation
by Sven Schnelle 25 Jun '12

25 Jun '12

Hi coreboot folks, i've just pushed the following changes for discussion: http://review.coreboot.org/#/c/1137/ http://review.coreboot.org/#/c/1138/ Those changes add support for creating the MPTABLE during runtime, which resolves one of the most painful tasks in the past during porting a new board. Basically the first patch adds a generic IOAPIC driver, which can be added to the devicetree, and holds the generic configuration data, and does all the IOAPIC initialization. An example entry looks like this (two entries, as mny X7DB8 has two IOAPICs): chip drivers/generic/ioapic register "irq_on_fsb" = "1" register "base" = "0xfec00000" register "have_isa_interrupts" = "1" register "enable_virtual_wire" = "1" device ioapic 8 on end end chip drivers/generic/ioapic register "irq_on_fsb" = "1" register "base" = "0xfec80000" device ioapic 9 on end end I think the entries are pretty self-explaining - the 'have_isa_interrupts' tells the mptable code for which IOAPIC to generate the ISA interrupts. The second patch adds support for the 'ioapic_irq' keyword, and the main mptable stuff. The ioapic_irq has the following syntax: ioapic_irq APICID PCI-INT-PIN IOAPIC-IRQ-PIN PCI-INT-PIN is currently an integer, where 0 stands for INTA, 1 for INTB and so on. Patrick Georgi suggested to change that to A/B/C/D, which i might do later. For non onboard device the mptable code currently searches for ioapic entries of the parents, and writes the appropriate IRQ entries. With that patch, a devicetree could look like this: device pci 02.0 on # PCI Express x8 Port 2-3 ioapic_irq 8 0 0x10 ioapic_irq 8 1 0x11 ioapic_irq 8 2 0x12 ioapic_irq 8 3 0x13 device pci 00.0 on # PCI Express Upstream Port device pci 00.0 on # PCI Express Downstream Port E1 device pci 00.0 on # 6700PXH PCI Express-to-PCI Bridge A ioapic_irq 8 0 0x11 ioapic_irq 8 1 0x10 ioapic_irq 8 2 0x11 ioapic_irq 8 3 0x10 # PCI slot device pci 02.0 on # Adaptec U320 #1 ioapic_irq 8 0 0x10 end device pci 02.1 on # Adaptec U320 #2 ioapic_irq 8 1 0x11 end end device pci 00.2 on # 6700PXH PCI Express-to-PCI Bridge B # PCI slot end end device pci 02.0 on # PCI Express Port E3 device pci 00.0 on end # e1000 #1 device pci 00.1 on end # e1000 #2 end end device pci 00.3 on # PCI Express to PCI-X Bridge ioapic_irq 9 0 3 ioapic_irq 9 1 0 ioapic_irq 9 2 1 ioapic_irq 9 3 2 # PCI-X Slot end end I would be really happy to see people checking the patch, and especially checking that my logic is correct. I'm also happy to hear about improvements, bug fixes, and other ideas. Thanks for listening, Sven

2 1

Trac reminder: list of new ticket(s)
by coreboot tracker 25 Jun '12

25 Jun '12

1 0

New patch to review for coreboot: 915a711 Use broadcast SIPI to startup siblings
by Sven Schnelle 25 Jun '12

25 Jun '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1139 -gerrit commit 915a71191ae585a89f703dc83aec65c004ef53b0 Author: Sven Schnelle <svens(a)stackframe.org> Date: Sun Jun 17 10:32:55 2012 +0200 Use broadcast SIPI to startup siblings The current code for initializing AP cpus has several shortcomings: - it assumes APIC IDs are sequential - it uses only the BSP for determining the AP count, which is bad if there's more than one physical CPU package Change-Id: Ic48a1ebab6a7c52aa76765f497268af09fa38c25 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/arch/x86/include/arch/cpu.h | 24 -- src/arch/x86/lib/cpu.c | 25 ++- src/cpu/intel/hyperthreading/Makefile.inc | 1 - src/cpu/intel/hyperthreading/intel_sibling.c | 73 ------- src/cpu/intel/model_1067x/model_1067x_init.c | 4 - src/cpu/intel/model_106cx/model_106cx_init.c | 4 - src/cpu/intel/model_6ex/model_6ex_init.c | 4 - src/cpu/intel/model_6fx/model_6fx_init.c | 4 - src/cpu/intel/model_f2x/model_f2x_init.c | 4 - src/cpu/intel/model_f3x/model_f3x_init.c | 4 - src/cpu/intel/model_f4x/model_f4x_init.c | 4 - src/cpu/x86/lapic/lapic_cpu_init.c | 295 ++++++-------------------- src/cpu/x86/lapic/secondary.S | 31 +++- src/include/cpu/cpu.h | 3 +- src/include/cpu/intel/hyperthreading.h | 7 - 15 files changed, 106 insertions(+), 381 deletions(-) diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 0dc92fb..0fe5ea5 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -158,30 +158,6 @@ struct cpu_driver { struct device; struct cpu_driver *find_cpu_driver(struct device *cpu); -struct cpu_info { - device_t cpu; - unsigned long index; -}; - -static inline struct cpu_info *cpu_info(void) -{ - struct cpu_info *ci; - __asm__("andl %%esp,%0; " - "orl %2, %0 " - :"=r" (ci) - : "0" (~(CONFIG_STACK_SIZE - 1)), - "r" (CONFIG_STACK_SIZE - sizeof(struct cpu_info)) - ); - return ci; -} - -static inline unsigned long cpu_index(void) -{ - struct cpu_info *ci; - ci = cpu_info(); - return ci->index; -} - struct cpuinfo_x86 { uint8_t x86; /* CPU family */ uint8_t x86_vendor; /* CPU vendor */ diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c index 98ede06..53d3fb2 100644 --- a/src/arch/x86/lib/cpu.c +++ b/src/arch/x86/lib/cpu.c @@ -9,7 +9,7 @@ #include <device/path.h> #include <device/device.h> #include <smp/spinlock.h> - +#include <cpu/x86/lapic.h> /* Standard macro to see if a specific flag is changeable */ static inline int flag_is_changeable_p(uint32_t flag) { @@ -234,7 +234,9 @@ static void set_cpu_ops(struct device *cpu) cpu->ops = driver ? driver->ops : NULL; } -void cpu_initialize(void) +static spinlock_t start_cpu_lock = SPIN_LOCK_UNLOCKED; + +void cpu_initialize(struct bus *cpu_bus) { /* Because we busy wait at the printk spinlock. * It is important to keep the number of printed messages @@ -242,17 +244,17 @@ void cpu_initialize(void) * disabled. */ struct device *cpu; - struct cpu_info *info; struct cpuinfo_x86 c; + struct device_path cpu_path; + unsigned char id = lapicid(); - info = cpu_info(); + cpu_path.type = DEVICE_PATH_APIC; + cpu_path.apic.apic_id = id; - printk(BIOS_INFO, "Initializing CPU #%ld\n", info->index); - - cpu = info->cpu; - if (!cpu) { - die("CPU: missing cpu device structure"); - } + spin_lock(&start_cpu_lock); + cpu = alloc_find_dev(cpu_bus, &cpu_path); + spin_unlock(&start_cpu_lock); + printk(BIOS_DEBUG, "Initializing CPU #%d\n", id); /* Find what type of cpu we are dealing with */ identify_cpu(cpu); @@ -276,7 +278,6 @@ void cpu_initialize(void) printk(BIOS_DEBUG, "Using generic cpu ops (good)\n"); } - /* Initialize the cpu */ if (cpu->ops && cpu->ops->init) { cpu->enabled = 1; @@ -284,7 +285,7 @@ void cpu_initialize(void) cpu->ops->init(cpu); } - printk(BIOS_INFO, "CPU #%ld initialized\n", info->index); + printk(BIOS_INFO, "CPU #%d initialized\n", id); return; } diff --git a/src/cpu/intel/hyperthreading/Makefile.inc b/src/cpu/intel/hyperthreading/Makefile.inc deleted file mode 100644 index 8adbad9..0000000 --- a/src/cpu/intel/hyperthreading/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ramstage-y += intel_sibling.c diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c deleted file mode 100644 index 2d2e105..0000000 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ /dev/null @@ -1,73 +0,0 @@ -#include <console/console.h> -#include <cpu/cpu.h> -#include <cpu/x86/lapic.h> -#include <cpu/intel/hyperthreading.h> -#include <device/device.h> -#include <pc80/mc146818rtc.h> -#include <smp/spinlock.h> -#include <assert.h> - -#if !CONFIG_SERIAL_CPU_INIT -#error Intel hyper-threading requires serialized cpu init -#endif - -static int first_time = 1; -static int disable_siblings = !CONFIG_LOGICAL_CPUS; - -void intel_sibling_init(device_t cpu) -{ - unsigned i, siblings; - struct cpuid_result result; - - /* On the bootstrap processor see if I want sibling cpus enabled */ - if (first_time) { - first_time = 0; - get_option(&disable_siblings, "hyper_threading"); - } - result = cpuid(1); - /* Is hyperthreading supported */ - if (!(result.edx & (1 << 28))) { - return; - } - /* See how many sibling cpus we have */ - siblings = (result.ebx >> 16) & 0xff; - if (siblings < 1) { - siblings = 1; - } - - printk(BIOS_DEBUG, "CPU: %u %d siblings\n", - cpu->path.apic.apic_id, - siblings); - - /* See if I am a sibling cpu */ - if (cpu->path.apic.apic_id & (siblings -1)) { - if (disable_siblings) { - cpu->enabled = 0; - } - return; - } - - /* I am the primary cpu start up my siblings */ - for(i = 1; i < siblings; i++) { - struct device_path cpu_path; - device_t new; - /* Build the cpu device path */ - cpu_path.type = DEVICE_PATH_APIC; - cpu_path.apic.apic_id = cpu->path.apic.apic_id + i; - - - /* Allocate new cpu device structure iff sibling CPU - * was not in static device tree. - */ - new = alloc_find_dev(cpu->bus, &cpu_path); - - if (!new) { - continue; - } - - printk(BIOS_DEBUG, "CPU: %u has sibling %u\n", - cpu->path.apic.apic_id, - new->path.apic.apic_id); - } -} - diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index c6d716d9..ddd1381 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -29,7 +29,6 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> -#include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -221,9 +220,6 @@ static void model_1067x_init(device_t cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors(); - - /* Start up my cpu siblings */ - intel_sibling_init(cpu); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 4bf2924..8d2ef3d 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -27,7 +27,6 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> -#include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> #include <usbdebug.h> @@ -178,9 +177,6 @@ static void model_106cx_init(device_t cpu) configure_misc(); /* TODO: PIC thermal sensor control */ - - /* Start up my cpu siblings */ - intel_sibling_init(cpu); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 1c8c72b..46f01ee 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -28,7 +28,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> -#include <cpu/intel/hyperthreading.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/acpi.h> #include <cpu/x86/cache.h> @@ -205,9 +204,6 @@ static void model_6ex_init(device_t cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors(); - - /* Start up my cpu siblings */ - intel_sibling_init(cpu); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 106719e..aec41dc 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -30,7 +30,6 @@ #include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/acpi.h> -#include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> #include <usbdebug.h> @@ -243,9 +242,6 @@ static void model_6fx_init(device_t cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors(); - - /* Start up my cpu siblings */ - intel_sibling_init(cpu); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c index ec78672..51b72a3 100644 --- a/src/cpu/intel/model_f2x/model_f2x_init.c +++ b/src/cpu/intel/model_f2x/model_f2x_init.c @@ -7,7 +7,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> -#include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> /* 512KB cache */ @@ -56,9 +55,6 @@ static void model_f2x_init(device_t cpu) /* Enable the local cpu apics */ setup_lapic(); - - /* Start up my cpu siblings */ - intel_sibling_init(cpu); }; static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index 580c98b..ca346da 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -7,7 +7,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> -#include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> static uint32_t microcode_updates[] = { @@ -39,9 +38,6 @@ static void model_f3x_init(device_t cpu) /* Enable the local cpu apics */ setup_lapic(); - - /* Start up my cpu siblings */ - intel_sibling_init(cpu); }; static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c index 54edf2e..c857cef 100644 --- a/src/cpu/intel/model_f4x/model_f4x_init.c +++ b/src/cpu/intel/model_f4x/model_f4x_init.c @@ -7,7 +7,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> -#include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> static uint32_t microcode_updates[] = { @@ -47,9 +46,6 @@ static void model_f4x_init(device_t cpu) /* Enable the local cpu apics */ setup_lapic(); - - /* Start up my cpu siblings */ - intel_sibling_init(cpu); }; static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index e491d46..3c0f5a2 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -66,31 +66,28 @@ static void copy_secondary_start_to_1m_below(void) printk(BIOS_DEBUG, "start_eip=0x%08lx, offset=0x%08lx, code_size=0x%08lx\n", start_eip, ((unsigned long)_secondary_start - start_eip), code_size); } -static int lapic_start_cpu(unsigned long apicid) +static struct bus *current_cpu_bus; + +static int lapic_start_cpus(struct bus *cpu_bus) { int timeout; unsigned long send_status, accept_status, start_eip; - int j, num_starts, maxlvt; + int maxlvt; /* * Starting actual IPI sequence... */ - printk(BIOS_SPEW, "Asserting INIT.\n"); - - /* - * Turn INIT on target chip - */ - lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); + current_cpu_bus = cpu_bus; - /* - * Send IPI - */ + printk(BIOS_SPEW, "Asserting INIT.\n"); - lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT - | LAPIC_DM_INIT); + /* Send INIT SIPI to target chip */ + lapic_write_around(LAPIC_ICR2, 0); + lapic_write_around(LAPIC_ICR, LAPIC_INT_ASSERT + | LAPIC_DM_INIT | LAPIC_DEST_ALLBUT); - printk(BIOS_SPEW, "Waiting for send to finish...\n"); + printk(BIOS_DEBUG, "Waiting for send to finish...\n"); timeout = 0; do { printk(BIOS_SPEW, "+"); @@ -98,108 +95,67 @@ static int lapic_start_cpu(unsigned long apicid) send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; } while (send_status && (timeout++ < 1000)); if (timeout >= 1000) { - printk(BIOS_ERR, "CPU %ld: First apic write timed out. Disabling\n", - apicid); + printk(BIOS_DEBUG, "First apic write timed out. Disabling\n"); // too bad. - printk(BIOS_ERR, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); + printk(BIOS_DEBUG, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); if (lapic_read(LAPIC_ESR)) { - printk(BIOS_ERR, "Try to reset ESR\n"); + printk(BIOS_DEBUG, "Try to reset ESR\n"); lapic_write_around(LAPIC_ESR, 0); - printk(BIOS_ERR, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); + printk(BIOS_DEBUG, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); } return 0; } -#if !CONFIG_CPU_AMD_MODEL_10XXX && !CONFIG_CPU_INTEL_MODEL_206AX - mdelay(10); -#endif + start_eip = get_valid_start_eip((unsigned long)_secondary_start); - printk(BIOS_SPEW, "Deasserting INIT.\n"); + maxlvt = 4; + + printk(BIOS_SPEW, "Sending STARTUP.\n"); + lapic_read_around(LAPIC_SPIV); + lapic_write(LAPIC_ESR, 0); + lapic_read(LAPIC_ESR); + printk(BIOS_SPEW, "After apic_write.\n"); + + /* + * STARTUP IPI + */ /* Target chip */ - lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); + lapic_write_around(LAPIC_ICR2, 0); - /* Send IPI */ - lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT); + /* Boot on the stack */ + /* Kick the second */ + lapic_write_around(LAPIC_ICR, LAPIC_INT_ASSERT | LAPIC_DM_STARTUP | LAPIC_DEST_ALLBUT + | (start_eip >> 12)); - printk(BIOS_SPEW, "Waiting for send to finish...\n"); + /* + * Give the other CPU some time to accept the IPI. + */ + udelay(300); + + printk(BIOS_DEBUG, "Startup point 1.\n"); + + printk(BIOS_DEBUG, "Waiting for send to finish...\n"); timeout = 0; do { - printk(BIOS_SPEW, "+"); + printk(BIOS_DEBUG, "+"); udelay(100); send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; } while (send_status && (timeout++ < 1000)); - if (timeout >= 1000) { - printk(BIOS_ERR, "CPU %ld: Second apic write timed out. Disabling\n", - apicid); - // too bad. - return 0; - } - - start_eip = get_valid_start_eip((unsigned long)_secondary_start); - -#if !CONFIG_CPU_AMD_MODEL_10XXX - num_starts = 2; -#else - num_starts = 1; -#endif /* - * Run STARTUP IPI loop. + * Give the other CPU some time to accept the IPI. */ - printk(BIOS_SPEW, "#startup loops: %d.\n", num_starts); - - maxlvt = 4; - - for (j = 1; j <= num_starts; j++) { - printk(BIOS_SPEW, "Sending STARTUP #%d to %lu.\n", j, apicid); + udelay(200); + /* + * Due to the Pentium erratum 3AP. + */ + if (maxlvt > 3) { lapic_read_around(LAPIC_SPIV); lapic_write(LAPIC_ESR, 0); - lapic_read(LAPIC_ESR); - printk(BIOS_SPEW, "After apic_write.\n"); - - /* - * STARTUP IPI - */ - - /* Target chip */ - lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); - - /* Boot on the stack */ - /* Kick the second */ - lapic_write_around(LAPIC_ICR, LAPIC_DM_STARTUP - | (start_eip >> 12)); - - /* - * Give the other CPU some time to accept the IPI. - */ - udelay(300); - - printk(BIOS_SPEW, "Startup point 1.\n"); - - printk(BIOS_SPEW, "Waiting for send to finish...\n"); - timeout = 0; - do { - printk(BIOS_SPEW, "+"); - udelay(100); - send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; - } while (send_status && (timeout++ < 1000)); - - /* - * Give the other CPU some time to accept the IPI. - */ - udelay(200); - /* - * Due to the Pentium erratum 3AP. - */ - if (maxlvt > 3) { - lapic_read_around(LAPIC_SPIV); - lapic_write(LAPIC_ESR, 0); - } - accept_status = (lapic_read(LAPIC_ESR) & 0xEF); - if (send_status || accept_status) - break; } - printk(BIOS_SPEW, "After Startup.\n"); + accept_status = (lapic_read(LAPIC_ESR) & 0xEF); + + printk(BIOS_DEBUG, "After Startup.\n"); if (send_status) printk(BIOS_WARNING, "APIC never delivered???\n"); if (accept_status) @@ -209,73 +165,12 @@ static int lapic_start_cpu(unsigned long apicid) return 1; } + /* Number of cpus that are currently running in coreboot */ static atomic_t active_cpus = ATOMIC_INIT(1); -/* start_cpu_lock covers last_cpu_index and secondary_stack. - * Only starting one cpu at a time let's me remove the logic - * for select the stack from assembly language. - * - * In addition communicating by variables to the cpu I - * am starting allows me to veryify it has started before - * start_cpu returns. - */ - -static spinlock_t start_cpu_lock = SPIN_LOCK_UNLOCKED; -static unsigned last_cpu_index = 0; volatile unsigned long secondary_stack; - -int start_cpu(device_t cpu) -{ - extern unsigned char _estack[]; - struct cpu_info *info; - unsigned long stack_end; - unsigned long apicid; - unsigned long index; - unsigned long count; - int result; - - spin_lock(&start_cpu_lock); - - /* Get the cpu's apicid */ - apicid = cpu->path.apic.apic_id; - - /* Get an index for the new processor */ - index = ++last_cpu_index; - - /* Find end of the new processors stack */ - stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info); - - /* Record the index and which cpu structure we are using */ - info = (struct cpu_info *)stack_end; - info->index = index; - info->cpu = cpu; - - /* Advertise the new stack to start_cpu */ - secondary_stack = stack_end; - - /* Until the cpu starts up report the cpu is not enabled */ - cpu->enabled = 0; - cpu->initialized = 0; - - /* Start the cpu */ - result = lapic_start_cpu(apicid); - - if (result) { - result = 0; - /* Wait 1s or until the new cpu calls in */ - for(count = 0; count < 100000 ; count++) { - if (secondary_stack == 0) { - result = 1; - break; - } - udelay(10); - } - } - secondary_stack = 0; - spin_unlock(&start_cpu_lock); - return result; -} +extern unsigned char _estack[]; #if CONFIG_AP_IN_SIPI_WAIT @@ -383,64 +278,19 @@ static __inline__ __attribute__((always_inline)) void writecr4(unsigned long Dat /* C entry point of secondary cpus */ void secondary_cpu_init(void) { - atomic_inc(&active_cpus); -#if CONFIG_SERIAL_CPU_INIT - spin_lock(&start_cpu_lock); -#endif - #ifdef __SSE3__ - /* - * Seems that CR4 was cleared when AP start via lapic_start_cpu() - * Turn on CR4.OSFXSR and CR4.OSXMMEXCPT when SSE options enabled - */ - u32 cr4_val; - cr4_val = readcr4(); - cr4_val |= (1 << 9 | 1 << 10); - writecr4(cr4_val); + /* + * Seems that CR4 was cleared when AP start via lapic_start_cpu() + * Turn on CR4.OSFXSR and CR4.OSXMMEXCPT when SSE options enabled + */ + u32 cr4_val; + cr4_val = readcr4(); + cr4_val |= (1 << 9 | 1 << 10); + writecr4(cr4_val); #endif - cpu_initialize(); -#if CONFIG_SERIAL_CPU_INIT - spin_unlock(&start_cpu_lock); -#endif - + atomic_inc(&active_cpus); + cpu_initialize(current_cpu_bus); atomic_dec(&active_cpus); - - stop_this_cpu(); -} - -static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu) -{ - device_t cpu; - /* Loop through the cpus once getting them started */ - - for(cpu = cpu_bus->children; cpu ; cpu = cpu->sibling) { - if (cpu->path.type != DEVICE_PATH_APIC) { - continue; - } - #if !CONFIG_SERIAL_CPU_INIT - if(cpu==bsp_cpu) { - continue; - } - #endif - - if (!cpu->enabled) { - continue; - } - - if (cpu->initialized) { - continue; - } - - if (!start_cpu(cpu)) { - /* Record the error in cpu? */ - printk(BIOS_ERR, "CPU 0x%02x would not start!\n", - cpu->path.apic.apic_id); - } -#if CONFIG_SERIAL_CPU_INIT - udelay(10); -#endif - } - } static void wait_other_cpus_stop(struct bus *cpu_bus) @@ -481,10 +331,6 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) void initialize_cpus(struct bus *cpu_bus) { struct device_path cpu_path; - struct cpu_info *info; - - /* Find the info struct for this cpu */ - info = cpu_info(); #if NEED_LAPIC == 1 /* Ensure the local apic is enabled */ @@ -499,9 +345,6 @@ void initialize_cpus(struct bus *cpu_bus) cpu_path.cpu.id = 0; #endif - /* Find the device structure for the boot cpu */ - info->cpu = alloc_find_dev(cpu_bus, &cpu_path); - #if CONFIG_SMP copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init #endif @@ -512,21 +355,11 @@ void initialize_cpus(struct bus *cpu_bus) cpus_ready_for_init(); -#if CONFIG_SMP - #if !CONFIG_SERIAL_CPU_INIT - /* start all aps at first, so we can init ECC all together */ - start_other_cpus(cpu_bus, info->cpu); - #endif -#endif - /* Initialize the bootstrap processor */ - cpu_initialize(); + cpu_initialize(cpu_bus); #if CONFIG_SMP - #if CONFIG_SERIAL_CPU_INIT - start_other_cpus(cpu_bus, info->cpu); - #endif - + lapic_start_cpus(cpu_bus); /* Now wait the rest of the cpus stop*/ wait_other_cpus_stop(cpu_bus); #endif diff --git a/src/cpu/x86/lapic/secondary.S b/src/cpu/x86/lapic/secondary.S index dc00b08..b0fec8f 100644 --- a/src/cpu/x86/lapic/secondary.S +++ b/src/cpu/x86/lapic/secondary.S @@ -38,10 +38,33 @@ _secondary_start: /* Load the Interrupt descriptor table */ lidt idtarg - /* Set the stack pointer, and flag that we are done */ - xorl %eax, %eax - movl secondary_stack, %esp - movl %eax, secondary_stack +lock: + .long 0 + +cpu: + .long 0 + +locked: + /* grab lock */ + mov $1, %eax + xchg lock, %eax + test %eax, %eax + jnz locked + + /* increment our cpu index */ + incl cpu + + /* assign stack for this specific cpu */ + mov _stack, %esp + mov cpu, %eax + incl %eax + mov $CONFIG_STACK_SIZE, %ebx + mul %ebx + add %eax, %esp + + /* release lock */ + xor %eax, %eax + xchg lock, %eax call secondary_cpu_init 1: hlt diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index c2113c1..b631d4e 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -3,8 +3,9 @@ #include <arch/cpu.h> +struct bus; #if !defined(__ROMCC__) -void cpu_initialize(void); +void cpu_initialize(struct bus *cpu_bus); struct bus; void initialize_cpus(struct bus *cpu_bus); void secondary_cpu_init(void); diff --git a/src/include/cpu/intel/hyperthreading.h b/src/include/cpu/intel/hyperthreading.h deleted file mode 100644 index 0a1461c..0000000 --- a/src/include/cpu/intel/hyperthreading.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef CPU_INTEL_HYPERTHREADING_H -#define CPU_INTEL_HYPERTHREADING_H - -struct device; -void intel_sibling_init(struct device *cpu); - -#endif /* CPU_INTEL_HYPERTHREADING_H */

1 0

New patch to review for coreboot: 8d6a210 MPTAPLE autogen wip
by Sven Schnelle 25 Jun '12

25 Jun '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1138 -gerrit commit 8d6a210aa50a4dacf589fb30ea8c39170e0efd70 Author: Sven Schnelle <svens(a)stackframe.org> Date: Thu Jun 21 22:19:48 2012 +0200 MPTAPLE autogen wip Change-Id: I4df5b198e8430f939d477c14c798414e398a2027 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/arch/x86/Makefile.inc | 6 +- src/arch/x86/boot/mpspec.c | 112 +++++ src/devices/device_util.c | 4 + src/drivers/generic/Kconfig | 2 +- src/drivers/generic/Makefile.inc | 1 + src/include/device/device.h | 9 +- src/include/device/path.h | 7 + src/mainboard/supermicro/x7db8/devicetree.cb | 112 ++++-- src/mainboard/supermicro/x7db8/mptable.c | 90 ---- util/sconfig/lex.yy.c_shipped | 207 +++++----- util/sconfig/main.c | 61 +++- util/sconfig/sconfig.h | 6 + util/sconfig/sconfig.l | 2 + util/sconfig/sconfig.tab.c_shipped | 575 ++++++++++++++------------ util/sconfig/sconfig.tab.h_shipped | 12 +- util/sconfig/sconfig.y | 7 +- 16 files changed, 714 insertions(+), 499 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index f498831..d9a61f9 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -228,9 +228,9 @@ endif # Things that appear in every board romstage-srcs += $(objgenerated)/crt0.s ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c -ifeq ($(CONFIG_GENERATE_MP_TABLE),y) -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mptable.c -endif +#ifeq ($(CONFIG_GENERATE_MP_TABLE),y) +#ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mptable.c +#endif ifeq ($(CONFIG_GENERATE_PIRQ_TABLE),y) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/irq_tables.c endif diff --git a/src/arch/x86/boot/mpspec.c b/src/arch/x86/boot/mpspec.c index e7d767b..3cc2b85 100644 --- a/src/arch/x86/boot/mpspec.c +++ b/src/arch/x86/boot/mpspec.c @@ -6,6 +6,7 @@ #include <string.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> +#include <drivers/generic/ioapic/chip.h> /* Initialize the specified "mc" struct with initial values. */ void mptable_init(struct mp_config_table *mc, u32 lapic_addr) @@ -189,6 +190,8 @@ void smp_write_ioapic(struct mp_config_table *mc, unsigned char id, unsigned char ver, unsigned long apicaddr) { + + printk(BIOS_DEBUG, "writing IOAPIC: ID %d, ver %02x, addr %lx\n", id, ver, apicaddr); struct mpc_config_ioapic *mpc; mpc = smp_next_mpc_entry(mc); memset(mpc, '\0', sizeof(*mpc)); @@ -205,6 +208,8 @@ void smp_write_intsrc(struct mp_config_table *mc, unsigned char srcbus, unsigned char srcbusirq, unsigned char dstapic, unsigned char dstirq) { + printk(BIOS_DEBUG, "smp_write_intsrc irqtype %x, irqflag %x, srcbus %d, srcbusirq %d, dstapic %x, dstirq %x\n", + irqtype, irqflag, srcbus, srcbusirq, dstapic, dstirq); struct mpc_config_intsrc *mpc; mpc = smp_next_mpc_entry(mc); memset(mpc, '\0', sizeof(*mpc)); @@ -410,3 +415,110 @@ void *mptable_finalize(struct mp_config_table *mc) printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); } + +static void *smp_write_config_table(void *v) +{ + struct drivers_generic_ioapic_config *ioapic_config; + struct mp_config_table *mc; + int isa_bus, pin, parentpin; + device_t dev, parent, oldparent; + void *tmp; + int isaioapic = -1; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + + smp_write_processors(mc); + + mptable_write_buses(mc, NULL, &isa_bus); + + for(dev = all_devices; dev; dev = dev->next) { + if (dev->path.type != DEVICE_PATH_IOAPIC) + continue; + + if (!(ioapic_config = dev->chip_info)) { + printk(BIOS_ERR, "%s has no config, ignoring\n", dev_path(dev)); + continue; + } + smp_write_ioapic(mc, dev->path.ioapic.ioapic_id, + ioapic_config->version, + ioapic_config->base); + + if (ioapic_config->have_isa_interrupts) { + if (isaioapic > 1) + printk(BIOS_ERR, "More than one IOAPIC with ISA interrupts?\n"); + else + isaioapic = dev->path.ioapic.ioapic_id;; + } + } + + if (isaioapic >= 0) { + /* Legacy Interrupts */ + printk(BIOS_DEBUG, "writing ISA IRQs\n"); + mptable_add_isa_interrupts(mc, isa_bus, isaioapic, 0); + } + + for(dev = all_devices; dev; dev = dev->next) { + + if (dev->path.type != DEVICE_PATH_PCI) + continue; + + pin = (dev->path.pci.devfn & 7) % 4; + + if (dev->pci_irq_info[pin].ioapic_dst_id) { + printk(BIOS_INFO, "fixed IRQ entry for: %s: INT%c# -> IOAPIC %d PIN %d\n", dev_path(dev), + pin + 'A', + dev->pci_irq_info[pin].ioapic_dst_id, + dev->pci_irq_info[pin].ioapic_irq_pin); + smp_write_intsrc(mc, mp_INT, + dev->pci_irq_info[pin].ioapic_flags, + dev->bus->secondary, + ((dev->path.pci.devfn & 0xf8) >> 1) | pin, + dev->pci_irq_info[pin].ioapic_dst_id, + dev->pci_irq_info[pin].ioapic_irq_pin); + } else { + oldparent = parent = dev; + while((parent = parent->bus->dev)) { + if (parent->path.type == DEVICE_PATH_PCI_DOMAIN) { + printk(BIOS_ERR, "no IRQ found for %s\n", dev_path(dev)); + break; + } + + parentpin = (oldparent->path.pci.devfn >> 3) + (oldparent->path.pci.devfn & 7); + parentpin += dev->path.pci.devfn & 7; + parentpin += dev->path.pci.devfn >> 3; + parentpin %= 4; + printk(BIOS_INFO, "%s: INT%c#\n", dev_path(parent), parentpin + 'A'); + + if (parent->pci_irq_info[parentpin].ioapic_dst_id) { + printk(BIOS_INFO, "automatic IRQ entry for %s: INT%c# -> IOAPIC %d PIN %d\n", + dev_path(dev), pin + 'A', + parent->pci_irq_info[parentpin].ioapic_dst_id, + parent->pci_irq_info[parentpin].ioapic_irq_pin); + smp_write_intsrc(mc, mp_INT, + parent->pci_irq_info[parentpin].ioapic_flags, + dev->bus->secondary, + ((dev->path.pci.devfn & 0xf8) >> 1) | pin, + parent->pci_irq_info[parentpin].ioapic_dst_id, + parent->pci_irq_info[parentpin].ioapic_irq_pin); + + break; + } + oldparent = parent; + } + } + } + + mptable_lintsrc(mc, isa_bus); + tmp = mptable_finalize(mc); + printk(BIOS_INFO, "MPTABLE len: %d\n", (unsigned int)tmp - (unsigned int)v); + return tmp; +} + +unsigned long __attribute__((weak)) write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/devices/device_util.c b/src/devices/device_util.c index 5225938..864f349 100644 --- a/src/devices/device_util.c +++ b/src/devices/device_util.c @@ -217,6 +217,10 @@ const char *dev_path(device_t dev) sprintf(buffer, "APIC: %02x", dev->path.apic.apic_id); break; + case DEVICE_PATH_IOAPIC: + sprintf(buffer, "IOAPIC: %02x", + dev->path.ioapic.ioapic_id); + break; case DEVICE_PATH_PCI_DOMAIN: sprintf(buffer, "PCI_DOMAIN: %04x", dev->path.pci_domain.domain); diff --git a/src/drivers/generic/Kconfig b/src/drivers/generic/Kconfig index fbbfeb1..597a186 100644 --- a/src/drivers/generic/Kconfig +++ b/src/drivers/generic/Kconfig @@ -1,3 +1,3 @@ source src/drivers/generic/debug/Kconfig source src/drivers/generic/generic/Kconfig - +source src/drivers/generic/ioapic/Kconfig diff --git a/src/drivers/generic/Makefile.inc b/src/drivers/generic/Makefile.inc index 08e6cc5..7618150 100644 --- a/src/drivers/generic/Makefile.inc +++ b/src/drivers/generic/Makefile.inc @@ -1,2 +1,3 @@ subdirs-y += debug subdirs-y += generic +subdirs-y += ioapic \ No newline at end of file diff --git a/src/include/device/device.h b/src/include/device/device.h index 0aea1d6..f36710a 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -61,6 +61,13 @@ struct bus { * combination: */ +struct pci_irq_info { + unsigned int ioapic_irq_pin; + unsigned int ioapic_src_pin; + unsigned int ioapic_dst_id; + unsigned int ioapic_flags; +}; + struct device { struct bus * bus; /* bus this device is on, for bridge * devices, it is the up stream bus */ @@ -77,7 +84,7 @@ struct device { unsigned int enabled : 1; /* set if we should enable the device */ unsigned int initialized : 1; /* set if we have initialized the device */ unsigned int on_mainboard : 1; - + struct pci_irq_info pci_irq_info[4]; u8 command; /* Base registers for this device. I/O, MEM and Expansion ROM */ diff --git a/src/include/device/path.h b/src/include/device/path.h index 63e9538..5af761e 100644 --- a/src/include/device/path.h +++ b/src/include/device/path.h @@ -12,6 +12,7 @@ enum device_path_type { DEVICE_PATH_APIC_CLUSTER, DEVICE_PATH_CPU, DEVICE_PATH_CPU_BUS, + DEVICE_PATH_IOAPIC, }; struct pci_domain_path @@ -42,6 +43,11 @@ struct apic_path unsigned core_id; }; +struct ioapic_path +{ + unsigned ioapic_id; +}; + struct apic_cluster_path { unsigned cluster; @@ -65,6 +71,7 @@ struct device_path { struct pnp_path pnp; struct i2c_path i2c; struct apic_path apic; + struct ioapic_path ioapic; struct pci_domain_path pci_domain; struct apic_cluster_path apic_cluster; struct cpu_path cpu; diff --git a/src/mainboard/supermicro/x7db8/devicetree.cb b/src/mainboard/supermicro/x7db8/devicetree.cb index 7c90ba2..c54196b 100644 --- a/src/mainboard/supermicro/x7db8/devicetree.cb +++ b/src/mainboard/supermicro/x7db8/devicetree.cb @@ -27,37 +27,64 @@ chip northbridge/intel/i5000 device lapic 0 on end end end - device pci_domain 0 on device pci 00.0 on # Host bridge subsystemid 0x15d9 0x2017 end - device pci 02.0 on # PCIe bridge - device pci 00.0 on - device pci 00.0 on - device pci 00.0 on end - device pci 02.0 on end - end - device pci 02.0 on - device pci 00.0 on - device pci 02.0 on - device pci 00.0 on end # e1000 #1 - device pci 00.1 on end # e1000 #2 + device pci 02.0 on # PCI Express x8 Port 2-3 + ioapic_irq 8 0 0x10 + ioapic_irq 8 1 0x11 + ioapic_irq 8 2 0x12 + ioapic_irq 8 3 0x13 + device pci 00.0 on # PCI Express Upstream Port + device pci 00.0 on # PCI Express Downstream Port E1 + device pci 00.0 on # 6700PXH PCI Express-to-PCI Bridge A + ioapic_irq 8 0 0x11 + ioapic_irq 8 1 0x10 + ioapic_irq 8 2 0x11 + ioapic_irq 8 3 0x10 + # PCI slot + device pci 02.0 on # Adaptec U320 #1 + ioapic_irq 8 0 0x10 end + device pci 02.1 on # Adaptec U320 #2 + ioapic_irq 8 1 0x11 + end + end + device pci 00.2 on # 6700PXH PCI Express-to-PCI Bridge B + # PCI slot end - device pci 00.1 on end end + device pci 02.0 on # PCI Express Downstream Port E3 + device pci 00.0 on end # e1000 #1 + device pci 00.1 on end # e1000 #2 + end + end + device pci 00.3 on # PCI Express to PCI-X Bridge + ioapic_irq 9 0 3 + ioapic_irq 9 1 0 + ioapic_irq 9 2 1 + ioapic_irq 9 3 2 + # PCI-X Slot end - device pci 00.1 on end - device pci 00.3 on end end - device pci 03.0 on end - device pci 04.0 on end - device pci 05.0 on end - device pci 06.0 on end - device pci 07.0 on end + device pci 03.0 on + ioapic_irq 8 0 0x10 + end + device pci 04.0 on + ioapic_irq 8 0 0x10 + end + device pci 05.0 on + ioapic_irq 8 0 0x10 + end + device pci 06.0 on + ioapic_irq 8 0 0x10 + end + device pci 07.0 on + ioapic_irq 8 0 0x10 + end device pci 10.0 on end # FBD device pci 10.1 on end # FBD device pci 10.2 on end # FBD @@ -66,23 +93,49 @@ chip northbridge/intel/i5000 device pci 15.0 on end # FBD device pci 16.0 on end # FBD + chip drivers/generic/ioapic + register "irq_on_fsb" = "1" + register "base" = "0xfec00000" + register "have_isa_interrupts" = "1" + register "enable_virtual_wire" = "1" + device ioapic 8 on end + end + chip drivers/generic/ioapic + register "irq_on_fsb" = "1" + register "base" = "0xfec80000" + device ioapic 9 on end + end + chip southbridge/intel/i3100 register "pirq_a_d" = "0x0b0b0b0b" register "pirq_e_h" = "0x80808080" register "sata_ports_implemented" = "0x3f" - device pci 1c.0 on end # PCIe bridge - device pci 1d.0 on end # USB UHCI - device pci 1d.1 on end # USB UHCI - device pci 1d.2 on end # USB UHCI - device pci 1d.3 on end # USB UHCI + device pci 1c.0 on + ioapic_irq 8 0 0x14 + ioapic_irq 8 1 0x15 + ioapic_irq 8 2 0x16 + ioapic_irq 8 3 0x17 + end # PCIe bridge + device pci 1d.0 on + ioapic_irq 8 0 0x10 + end # USB UHCI + device pci 1d.1 on + ioapic_irq 8 1 0x11 + end # USB UHCI + device pci 1d.2 on + ioapic_irq 8 2 0x12 + end # USB UHCI + device pci 1d.3 on + ioapic_irq 8 3 0x13 + end # USB UHCI device pci 1d.7 on end # USB2 EHCI device pci 1e.0 on - device pci 01.0 on - end + device pci 01.0 on end end device pci 1f.0 on # PCI-LPC bridge + ioapic_irq 8 0 0x11 subsystemid 0x15d9 0x2009 chip superio/winbond/w83627hf device pnp 2e.0 off end # FDC @@ -111,10 +164,11 @@ chip northbridge/intel/i5000 device pnp 2e.a on end # ACPI device pnp 2e.b off end # HWMON end + end - device pci 1f.1 off end # IDE + device pci 1f.1 on end # IDE device pci 1f.2 on end # SATA - device pci 1f.3 off end # SMBUS + device pci 1f.3 on end # SMBUS end end diff --git a/src/mainboard/supermicro/x7db8/mptable.c b/src/mainboard/supermicro/x7db8/mptable.c deleted file mode 100644 index d0ddada..0000000 --- a/src/mainboard/supermicro/x7db8/mptable.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <device/device.h> -#include <device/pci.h> -#include <console/console.h> -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <string.h> -#include <stdint.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int isa_bus; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &isa_bus); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, 8, 0x20, IO_APIC_ADDR); - smp_write_ioapic(mc, 9, 0x20, IO_APIC_ADDR + 0x80000); - - /* Legacy Interrupts */ - mptable_add_isa_interrupts(mc, isa_bus, 0x8, 0); - - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x00 << 2), 0x08, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x02 << 2), 0x08, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x03 << 2), 0x08, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x04 << 2), 0x08, 0x10); - - - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x02, (0x02 << 2), 0x08, 0x10); - - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1b << 2), 0x08, 0x11); /* HD Audio 0:1b.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2), 0x08, 0x14); /* PCIe 0:1c.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x01, 0x08, 0x15); /* PCIe 0:1c.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x02, 0x08, 0x16); /* PCIe 0:1c.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x03, 0x08, 0x17); /* PCIe 0:1c.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) , 0x08, 0x10); /* USB 0:1d.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x01, 0x08, 0x11); /* USB 0:1d.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x02, 0x08, 0x12); /* USB 0:1d.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x03, 0x08, 0x13); /* USB 0:1d.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2), 0x08, 0x11); /* SATA 0:1f.2 */ - - /* e1000 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x07, (0x00 << 2) | 0x00, 0x08, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x07, (0x00 << 2) | 0x01, 0x08, 0x13); - - /* SCSI on board */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x04, (0x02 << 2) | 0x00, 0x08, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x04, (0x02 << 2) | 0x01, 0x08, 0x11); - /* SCSI add on */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x08, (0x01 << 2) | 0x00, 0x09, 0x00); - - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_HIGH, isa_bus, 0x00, MP_APIC_ALL, 0x00); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x00, MP_APIC_ALL, 0x01); - - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/util/sconfig/lex.yy.c_shipped b/util/sconfig/lex.yy.c_shipped index 5b02db8..a955e2e 100644 --- a/util/sconfig/lex.yy.c_shipped +++ b/util/sconfig/lex.yy.c_shipped @@ -1,5 +1,5 @@ -#line 3 "/home/svens/coreboot/coreboot-svn/util/sconfig/lex.yy.c_shipped" +#line 3 "/home/svens/coreboot/coreboot-i5000-latest/util/sconfig/lex.yy.c_shipped" #define YY_INT_ALIGNED short int @@ -368,8 +368,8 @@ static void yy_fatal_error (yyconst char msg[] ); *yy_cp = '\0'; \ (yy_c_buf_p) = yy_cp; -#define YY_NUM_RULES 27 -#define YY_END_OF_BUFFER 28 +#define YY_NUM_RULES 29 +#define YY_END_OF_BUFFER 30 /* This struct is not used in this scanner, but its presence is necessary. */ struct yy_trans_info @@ -377,20 +377,21 @@ struct yy_trans_info flex_int32_t yy_verify; flex_int32_t yy_nxt; }; -static yyconst flex_int16_t yy_accept[104] = +static yyconst flex_int16_t yy_accept[112] = { 0, - 0, 0, 28, 26, 1, 3, 26, 26, 26, 23, - 23, 21, 24, 24, 24, 24, 26, 26, 26, 26, - 26, 26, 26, 1, 3, 26, 0, 26, 0, 2, - 23, 24, 26, 26, 24, 26, 26, 26, 26, 17, - 26, 26, 26, 7, 26, 26, 26, 26, 25, 25, - 22, 26, 26, 16, 20, 11, 26, 15, 26, 8, - 9, 10, 26, 26, 4, 26, 26, 26, 26, 26, - 26, 26, 26, 12, 26, 26, 26, 5, 26, 26, - 26, 26, 26, 18, 26, 26, 26, 26, 26, 26, - 6, 26, 26, 26, 26, 26, 14, 26, 26, 19, - - 26, 13, 0 + 0, 0, 30, 28, 1, 3, 28, 28, 28, 25, + 25, 23, 26, 26, 26, 26, 28, 28, 28, 28, + 28, 28, 28, 1, 3, 28, 0, 28, 0, 2, + 25, 26, 28, 28, 26, 28, 28, 28, 28, 18, + 28, 28, 28, 7, 28, 28, 28, 28, 27, 27, + 24, 28, 28, 17, 22, 12, 28, 28, 16, 28, + 8, 9, 11, 28, 28, 4, 28, 28, 28, 28, + 28, 28, 28, 28, 28, 28, 13, 28, 28, 28, + 5, 28, 10, 28, 28, 28, 28, 20, 28, 28, + 28, 28, 28, 28, 28, 28, 6, 28, 28, 28, + + 28, 28, 19, 28, 15, 28, 28, 21, 28, 14, + 0 } ; static yyconst flex_int32_t yy_ec[256] = @@ -433,39 +434,41 @@ static yyconst flex_int32_t yy_meta[35] = 1, 1, 1, 1 } ; -static yyconst flex_int16_t yy_base[109] = +static yyconst flex_int16_t yy_base[117] = { 0, - 0, 0, 164, 0, 161, 165, 159, 33, 37, 34, - 128, 0, 46, 49, 53, 56, 50, 147, 48, 22, - 142, 127, 0, 155, 165, 74, 151, 65, 152, 165, - 0, 75, 78, 133, 90, 126, 136, 136, 130, 0, - 122, 122, 129, 0, 125, 119, 125, 129, 0, 165, - 0, 116, 120, 0, 0, 0, 123, 0, 118, 0, - 126, 0, 116, 107, 0, 120, 106, 118, 116, 102, - 87, 103, 98, 106, 92, 86, 86, 0, 84, 98, - 89, 94, 80, 0, 87, 95, 79, 89, 74, 83, - 0, 80, 73, 77, 79, 60, 0, 72, 56, 0, - - 43, 0, 165, 43, 122, 124, 126, 128 + 0, 0, 172, 0, 169, 173, 167, 33, 37, 34, + 136, 0, 46, 49, 53, 56, 50, 155, 48, 22, + 150, 135, 0, 163, 173, 74, 159, 65, 160, 173, + 0, 75, 78, 141, 90, 134, 144, 144, 138, 144, + 129, 129, 136, 0, 132, 126, 132, 136, 0, 173, + 0, 123, 127, 0, 0, 0, 130, 120, 0, 124, + 0, 132, 0, 122, 113, 0, 126, 112, 118, 123, + 121, 107, 101, 117, 112, 117, 119, 96, 90, 90, + 0, 88, 105, 101, 92, 97, 83, 0, 91, 89, + 97, 81, 91, 79, 75, 84, 0, 81, 76, 73, + + 77, 79, 0, 60, 0, 72, 56, 0, 43, 0, + 173, 43, 122, 124, 126, 128 } ; -static yyconst flex_int16_t yy_def[109] = +static yyconst flex_int16_t yy_def[117] = { 0, - 103, 1, 103, 104, 103, 103, 104, 105, 106, 104, - 10, 104, 10, 10, 10, 10, 104, 104, 104, 104, - 104, 104, 104, 103, 103, 105, 107, 106, 108, 103, - 10, 10, 10, 104, 10, 104, 104, 104, 104, 104, - 104, 104, 104, 104, 104, 104, 104, 104, 104, 103, - 33, 104, 104, 104, 104, 104, 104, 104, 104, 104, - 104, 104, 104, 104, 104, 104, 104, 104, 104, 104, - 104, 104, 104, 104, 104, 104, 104, 104, 104, 104, - 104, 104, 104, 104, 104, 104, 104, 104, 104, 104, - 104, 104, 104, 104, 104, 104, 104, 104, 104, 104, - - 104, 104, 0, 103, 103, 103, 103, 103 + 111, 1, 111, 112, 111, 111, 112, 113, 114, 112, + 10, 112, 10, 10, 10, 10, 112, 112, 112, 112, + 112, 112, 112, 111, 111, 113, 115, 114, 116, 111, + 10, 10, 10, 112, 10, 112, 112, 112, 112, 112, + 112, 112, 112, 112, 112, 112, 112, 112, 112, 111, + 33, 112, 112, 112, 112, 112, 112, 112, 112, 112, + 112, 112, 112, 112, 112, 112, 112, 112, 112, 112, + 112, 112, 112, 112, 112, 112, 112, 112, 112, 112, + 112, 112, 112, 112, 112, 112, 112, 112, 112, 112, + 112, 112, 112, 112, 112, 112, 112, 112, 112, 112, + + 112, 112, 112, 112, 112, 112, 112, 112, 112, 112, + 0, 111, 111, 111, 111, 111 } ; -static yyconst flex_int16_t yy_nxt[200] = +static yyconst flex_int16_t yy_nxt[208] = { 0, 4, 5, 6, 7, 8, 9, 10, 11, 10, 12, 13, 4, 13, 13, 14, 15, 16, 13, 4, 4, @@ -474,47 +477,49 @@ static yyconst flex_int16_t yy_nxt[200] = 31, 31, 31, 23, 32, 46, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 38, 32, 32, 32, 32, 32, 32, 43, 29, 30, 34, 35, - 102, 44, 101, 39, 40, 27, 27, 41, 49, 37, - 36, 32, 32, 32, 51, 51, 51, 100, 51, 99, - 51, 51, 51, 51, 51, 51, 32, 32, 32, 98, - - 97, 96, 95, 94, 93, 92, 91, 90, 89, 88, - 87, 86, 85, 84, 83, 82, 81, 80, 79, 78, - 77, 53, 26, 26, 28, 28, 27, 27, 29, 29, - 76, 75, 74, 73, 72, 71, 70, 69, 68, 67, - 66, 65, 64, 63, 62, 61, 60, 59, 58, 57, - 56, 55, 54, 52, 30, 50, 24, 48, 47, 42, - 33, 25, 24, 103, 3, 103, 103, 103, 103, 103, - 103, 103, 103, 103, 103, 103, 103, 103, 103, 103, - 103, 103, 103, 103, 103, 103, 103, 103, 103, 103, - 103, 103, 103, 103, 103, 103, 103, 103, 103 - + 110, 44, 109, 39, 40, 27, 27, 41, 49, 37, + 36, 32, 32, 32, 51, 51, 51, 108, 51, 107, + 51, 51, 51, 51, 51, 51, 32, 32, 32, 106, + + 105, 104, 103, 102, 101, 100, 99, 98, 97, 96, + 95, 94, 93, 92, 91, 90, 89, 88, 87, 86, + 85, 53, 26, 26, 28, 28, 27, 27, 29, 29, + 84, 83, 82, 81, 80, 79, 78, 77, 76, 75, + 74, 73, 72, 71, 70, 69, 68, 67, 66, 65, + 64, 63, 62, 61, 60, 59, 58, 57, 56, 55, + 54, 52, 30, 50, 24, 48, 47, 42, 33, 25, + 24, 111, 3, 111, 111, 111, 111, 111, 111, 111, + 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, + 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, + + 111, 111, 111, 111, 111, 111, 111 } ; -static yyconst flex_int16_t yy_chk[200] = +static yyconst flex_int16_t yy_chk[208] = { 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 8, 8, 20, 8, 9, 9, - 10, 10, 10, 104, 10, 20, 10, 10, 10, 10, + 10, 10, 10, 112, 10, 20, 10, 10, 10, 10, 10, 10, 13, 13, 13, 14, 14, 14, 17, 15, 15, 15, 16, 16, 16, 19, 28, 28, 14, 15, - 101, 19, 99, 17, 17, 26, 26, 17, 26, 16, - 15, 32, 32, 32, 33, 33, 33, 98, 33, 96, - 33, 33, 33, 33, 33, 33, 35, 35, 35, 95, - - 94, 93, 92, 90, 89, 88, 87, 86, 85, 83, - 82, 81, 80, 79, 77, 76, 75, 74, 73, 72, - 71, 35, 105, 105, 106, 106, 107, 107, 108, 108, - 70, 69, 68, 67, 66, 64, 63, 61, 59, 57, - 53, 52, 48, 47, 46, 45, 43, 42, 41, 39, - 38, 37, 36, 34, 29, 27, 24, 22, 21, 18, - 11, 7, 5, 3, 103, 103, 103, 103, 103, 103, - 103, 103, 103, 103, 103, 103, 103, 103, 103, 103, - 103, 103, 103, 103, 103, 103, 103, 103, 103, 103, - 103, 103, 103, 103, 103, 103, 103, 103, 103 - + 109, 19, 107, 17, 17, 26, 26, 17, 26, 16, + 15, 32, 32, 32, 33, 33, 33, 106, 33, 104, + 33, 33, 33, 33, 33, 33, 35, 35, 35, 102, + + 101, 100, 99, 98, 96, 95, 94, 93, 92, 91, + 90, 89, 87, 86, 85, 84, 83, 82, 80, 79, + 78, 35, 113, 113, 114, 114, 115, 115, 116, 116, + 77, 76, 75, 74, 73, 72, 71, 70, 69, 68, + 67, 65, 64, 62, 60, 58, 57, 53, 52, 48, + 47, 46, 45, 43, 42, 41, 40, 39, 38, 37, + 36, 34, 29, 27, 24, 22, 21, 18, 11, 7, + 5, 3, 111, 111, 111, 111, 111, 111, 111, 111, + 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, + 111, 111, 111, 111, 111, 111, 111, 111, 111, 111, + + 111, 111, 111, 111, 111, 111, 111 } ; static yy_state_type yy_last_accepting_state; @@ -791,13 +796,13 @@ yy_match: while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 104 ) + if ( yy_current_state >= 112 ) yy_c = yy_meta[(unsigned int) yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c]; ++yy_cp; } - while ( yy_base[yy_current_state] != 165 ); + while ( yy_base[yy_current_state] != 173 ); yy_find_action: yy_act = yy_accept[yy_current_state]; @@ -861,74 +866,82 @@ YY_RULE_SETUP YY_BREAK case 10: YY_RULE_SETUP -{yylval.number=PNP; return(BUS);} +{yylval.number=IOAPIC; return(BUS);} YY_BREAK case 11: YY_RULE_SETUP -{yylval.number=I2C; return(BUS);} +{yylval.number=PNP; return(BUS);} YY_BREAK case 12: YY_RULE_SETUP -{yylval.number=APIC; return(BUS);} +{yylval.number=I2C; return(BUS);} YY_BREAK case 13: YY_RULE_SETUP -{yylval.number=APIC_CLUSTER; return(BUS);} +{yylval.number=APIC; return(BUS);} YY_BREAK case 14: YY_RULE_SETUP -{yylval.number=PCI_DOMAIN; return(BUS);} +{yylval.number=APIC_CLUSTER; return(BUS);} YY_BREAK case 15: YY_RULE_SETUP -{yylval.number=IRQ; return(RESOURCE);} +{yylval.number=PCI_DOMAIN; return(BUS);} YY_BREAK case 16: YY_RULE_SETUP -{yylval.number=DRQ; return(RESOURCE);} +{yylval.number=IRQ; return(RESOURCE);} YY_BREAK case 17: YY_RULE_SETUP -{yylval.number=IO; return(RESOURCE);} +{yylval.number=DRQ; return(RESOURCE);} YY_BREAK case 18: YY_RULE_SETUP -{return(INHERIT);} +{yylval.number=IO; return(RESOURCE);} YY_BREAK case 19: YY_RULE_SETUP -{return(SUBSYSTEMID);} +{return(IOAPIC_IRQ);} YY_BREAK case 20: YY_RULE_SETUP -{return(END);} +{return(INHERIT);} YY_BREAK case 21: YY_RULE_SETUP -{return(EQUALS);} +{return(SUBSYSTEMID);} YY_BREAK case 22: YY_RULE_SETUP -{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} +{return(END);} YY_BREAK case 23: YY_RULE_SETUP -{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} +{return(EQUALS);} YY_BREAK case 24: YY_RULE_SETUP {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} YY_BREAK case 25: -/* rule 25 can match eol */ YY_RULE_SETUP -{yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} +{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} YY_BREAK case 26: YY_RULE_SETUP -{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(STRING);} +{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} YY_BREAK case 27: +/* rule 27 can match eol */ +YY_RULE_SETUP +{yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} + YY_BREAK +case 28: +YY_RULE_SETUP +{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(STRING);} + YY_BREAK +case 29: YY_RULE_SETUP ECHO; YY_BREAK @@ -1223,7 +1236,7 @@ static int yy_get_next_buffer (void) while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 104 ) + if ( yy_current_state >= 112 ) yy_c = yy_meta[(unsigned int) yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c]; @@ -1251,11 +1264,11 @@ static int yy_get_next_buffer (void) while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 104 ) + if ( yy_current_state >= 112 ) yy_c = yy_meta[(unsigned int) yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c]; - yy_is_jam = (yy_current_state == 103); + yy_is_jam = (yy_current_state == 111); return yy_is_jam ? 0 : yy_current_state; } diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 5d97274..00fd0e5 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -226,23 +226,35 @@ struct device *new_device(struct device *parent, struct device *busdev, const in lastdev->nextdev = new_d; lastdev = new_d; - if (bus == PCI) { + + switch(bus) { + case PCI: new_d->path = ".type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x%x,%d)}}"; - } - if (bus == PNP) { + break; + + case PNP: new_d->path = ".type=DEVICE_PATH_PNP,{.pnp={ .port = 0x%x, .device = 0x%x }}"; - } - if (bus == I2C) { + break; + + case I2C: new_d->path = ".type=DEVICE_PATH_I2C,{.i2c={ .device = 0x%x }}"; - } - if (bus == APIC) { + break; + + case APIC: new_d->path = ".type=DEVICE_PATH_APIC,{.apic={ .apic_id = 0x%x }}"; - } - if (bus == APIC_CLUSTER) { + break; + + case APIC_CLUSTER: new_d->path = ".type=DEVICE_PATH_APIC_CLUSTER,{.apic_cluster={ .cluster = 0x%x }}"; - } - if (bus == PCI_DOMAIN) { + break; + + case PCI_DOMAIN: new_d->path = ".type=DEVICE_PATH_PCI_DOMAIN,{.pci_domain={ .domain = 0x%x }}"; + break; + + case IOAPIC: + new_d->path = ".type=DEVICE_PATH_IOAPIC,{.ioapic={ .ioapic_id = 0x%x }}"; + break; } return new_d; } @@ -322,6 +334,21 @@ void add_pci_subsystem_ids(struct device *dev, int vendor, int device, int inher dev->inherit_subsystem = inherit; } +void add_ioapic_info(struct device *dev, int apicid, int srcpin, int irqpin) +{ + if (dev->bustype != PCI) { + printf("ERROR: 'apic config only allowed for PCI devices\n"); + exit(1); + } + + if (srcpin > 3) { + printf("ERROR: srcpin '%d' invalid\n"); + exit(1); + } + dev->pci_irq_info[srcpin].ioapic_irq_pin = irqpin; + dev->pci_irq_info[srcpin].ioapic_dst_id = apicid; +} + static void pass0(FILE *fil, struct device *ptr) { if (ptr->type == device && ptr->id == 0) fprintf(fil, "struct bus %s_links[];\n", ptr->name); @@ -334,7 +361,9 @@ static void pass0(FILE *fil, struct device *ptr) { } } -static void pass1(FILE *fil, struct device *ptr) { +static void pass1(FILE *fil, struct device *ptr) +{ + int pin; if (!ptr->used && (ptr->type == device)) { if (ptr->id != 0) fprintf(fil, "static "); @@ -349,6 +378,14 @@ static void pass1(FILE *fil, struct device *ptr) { if (ptr->subsystem_vendor > 0) fprintf(fil, "\t.subsystem_vendor = 0x%04x,\n", ptr->subsystem_vendor); + for(pin = 0; pin < 4; pin++) { + if (ptr->pci_irq_info[pin].ioapic_irq_pin > 0) + fprintf(fil, "\t.pci_irq_info[%d].ioapic_irq_pin = %d,\n", pin, ptr->pci_irq_info[pin].ioapic_irq_pin); + + if (ptr->pci_irq_info[pin].ioapic_dst_id > 0) + fprintf(fil, "\t.pci_irq_info[%d].ioapic_dst_id = %d,\n", pin, ptr->pci_irq_info[pin].ioapic_dst_id); + } + if (ptr->subsystem_device > 0) fprintf(fil, "\t.subsystem_device = 0x%04x,\n", ptr->subsystem_device); diff --git a/util/sconfig/sconfig.h b/util/sconfig/sconfig.h index d893c05..d69289b 100644 --- a/util/sconfig/sconfig.h +++ b/util/sconfig/sconfig.h @@ -43,6 +43,11 @@ struct reg { struct reg *next; }; +struct pci_irq_info { + int ioapic_irq_pin; +// int ioapic_src_pin; + int ioapic_dst_id; +}; struct device; struct device { int id; @@ -62,6 +67,7 @@ struct device { int path_a; int path_b; int bustype; + struct pci_irq_info pci_irq_info[4]; enum devtype type; struct device *parent; struct device *bus; diff --git a/util/sconfig/sconfig.l b/util/sconfig/sconfig.l index 50c315b..0f346db 100755 --- a/util/sconfig/sconfig.l +++ b/util/sconfig/sconfig.l @@ -34,6 +34,7 @@ register {return(REGISTER);} on {yylval.number=1; return(BOOL);} off {yylval.number=0; return(BOOL);} pci {yylval.number=PCI; return(BUS);} +ioapic {yylval.number=IOAPIC; return(BUS);} pnp {yylval.number=PNP; return(BUS);} i2c {yylval.number=I2C; return(BUS);} lapic {yylval.number=APIC; return(BUS);} @@ -42,6 +43,7 @@ pci_domain {yylval.number=PCI_DOMAIN; return(BUS);} irq {yylval.number=IRQ; return(RESOURCE);} drq {yylval.number=DRQ; return(RESOURCE);} io {yylval.number=IO; return(RESOURCE);} +ioapic_irq {return(IOAPIC_IRQ);} inherit {return(INHERIT);} subsystemid {return(SUBSYSTEMID);} end {return(END);} diff --git a/util/sconfig/sconfig.tab.c_shipped b/util/sconfig/sconfig.tab.c_shipped index dbefe06..2004f30 100644 --- a/util/sconfig/sconfig.tab.c_shipped +++ b/util/sconfig/sconfig.tab.c_shipped @@ -1,10 +1,8 @@ +/* A Bison parser, made by GNU Bison 2.5. */ -/* A Bison parser, made by GNU Bison 2.4.1. */ - -/* Skeleton implementation for Bison's Yacc-like parsers in C +/* Bison implementation for Yacc-like parsers in C - Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005, 2006 - Free Software Foundation, Inc. + Copyright (C) 1984, 1989-1990, 2000-2011 Free Software Foundation, Inc. This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -46,7 +44,7 @@ #define YYBISON 1 /* Bison version. */ -#define YYBISON_VERSION "2.4.1" +#define YYBISON_VERSION "2.5" /* Skeleton name. */ #define YYSKELETON_NAME "yacc.c" @@ -141,7 +139,9 @@ static struct device *cur_parent, *cur_bus; IO = 276, NUMBER = 277, SUBSYSTEMID = 278, - INHERIT = 279 + INHERIT = 279, + IOAPIC_IRQ = 280, + IOAPIC = 281 }; #endif @@ -217,7 +217,7 @@ typedef short int yytype_int16; #define YYSIZE_MAXIMUM ((YYSIZE_T) -1) #ifndef YY_ -# if YYENABLE_NLS +# if defined YYENABLE_NLS && YYENABLE_NLS # if ENABLE_NLS # include <libintl.h> /* INFRINGES ON USER NAME SPACE */ # define YY_(msgid) dgettext ("bison-runtime", msgid) @@ -270,11 +270,11 @@ YYID (yyi) # define alloca _alloca # else # define YYSTACK_ALLOC alloca -# if ! defined _ALLOCA_H && ! defined _STDLIB_H && (defined __STDC__ || defined __C99__FUNC__ \ +# if ! defined _ALLOCA_H && ! defined EXIT_SUCCESS && (defined __STDC__ || defined __C99__FUNC__ \ || defined __cplusplus || defined _MSC_VER) # include <stdlib.h> /* INFRINGES ON USER NAME SPACE */ -# ifndef _STDLIB_H -# define _STDLIB_H 1 +# ifndef EXIT_SUCCESS +# define EXIT_SUCCESS 0 # endif # endif # endif @@ -297,24 +297,24 @@ YYID (yyi) # ifndef YYSTACK_ALLOC_MAXIMUM # define YYSTACK_ALLOC_MAXIMUM YYSIZE_MAXIMUM # endif -# if (defined __cplusplus && ! defined _STDLIB_H \ +# if (defined __cplusplus && ! defined EXIT_SUCCESS \ && ! ((defined YYMALLOC || defined malloc) \ && (defined YYFREE || defined free))) # include <stdlib.h> /* INFRINGES ON USER NAME SPACE */ -# ifndef _STDLIB_H -# define _STDLIB_H 1 +# ifndef EXIT_SUCCESS +# define EXIT_SUCCESS 0 # endif # endif # ifndef YYMALLOC # define YYMALLOC malloc -# if ! defined malloc && ! defined _STDLIB_H && (defined __STDC__ || defined __C99__FUNC__ \ +# if ! defined malloc && ! defined EXIT_SUCCESS && (defined __STDC__ || defined __C99__FUNC__ \ || defined __cplusplus || defined _MSC_VER) void *malloc (YYSIZE_T); /* INFRINGES ON USER NAME SPACE */ # endif # endif # ifndef YYFREE # define YYFREE free -# if ! defined free && ! defined _STDLIB_H && (defined __STDC__ || defined __C99__FUNC__ \ +# if ! defined free && ! defined EXIT_SUCCESS && (defined __STDC__ || defined __C99__FUNC__ \ || defined __cplusplus || defined _MSC_VER) void free (void *); /* INFRINGES ON USER NAME SPACE */ # endif @@ -343,23 +343,7 @@ union yyalloc ((N) * (sizeof (yytype_int16) + sizeof (YYSTYPE)) \ + YYSTACK_GAP_MAXIMUM) -/* Copy COUNT objects from FROM to TO. The source and destination do - not overlap. */ -# ifndef YYCOPY -# if defined __GNUC__ && 1 < __GNUC__ -# define YYCOPY(To, From, Count) \ - __builtin_memcpy (To, From, (Count) * sizeof (*(From))) -# else -# define YYCOPY(To, From, Count) \ - do \ - { \ - YYSIZE_T yyi; \ - for (yyi = 0; yyi < (Count); yyi++) \ - (To)[yyi] = (From)[yyi]; \ - } \ - while (YYID (0)) -# endif -# endif +# define YYCOPY_NEEDED 1 /* Relocate STACK from its old location to the new one. The local variables YYSIZE and YYSTACKSIZE give the old and new number of @@ -379,23 +363,43 @@ union yyalloc #endif +#if defined YYCOPY_NEEDED && YYCOPY_NEEDED +/* Copy COUNT objects from FROM to TO. The source and destination do + not overlap. */ +# ifndef YYCOPY +# if defined __GNUC__ && 1 < __GNUC__ +# define YYCOPY(To, From, Count) \ + __builtin_memcpy (To, From, (Count) * sizeof (*(From))) +# else +# define YYCOPY(To, From, Count) \ + do \ + { \ + YYSIZE_T yyi; \ + for (yyi = 0; yyi < (Count); yyi++) \ + (To)[yyi] = (From)[yyi]; \ + } \ + while (YYID (0)) +# endif +# endif +#endif /* !YYCOPY_NEEDED */ + /* YYFINAL -- State number of the termination state. */ #define YYFINAL 3 /* YYLAST -- Last index in YYTABLE. */ -#define YYLAST 34 +#define YYLAST 38 /* YYNTOKENS -- Number of terminals. */ -#define YYNTOKENS 25 +#define YYNTOKENS 27 /* YYNNTS -- Number of nonterminals. */ -#define YYNNTS 12 +#define YYNNTS 13 /* YYNRULES -- Number of rules. */ -#define YYNRULES 20 +#define YYNRULES 22 /* YYNRULES -- Number of states. */ -#define YYNSTATES 36 +#define YYNSTATES 41 /* YYTRANSLATE(YYLEX) -- Bison symbol number corresponding to YYLEX. */ #define YYUNDEFTOK 2 -#define YYMAXUTOK 279 +#define YYMAXUTOK 281 #define YYTRANSLATE(YYX) \ ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK) @@ -430,7 +434,8 @@ static const yytype_uint8 yytranslate[] = 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, - 15, 16, 17, 18, 19, 20, 21, 22, 23, 24 + 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, + 25, 26 }; #if YYDEBUG @@ -439,28 +444,29 @@ static const yytype_uint8 yytranslate[] = static const yytype_uint8 yyprhs[] = { 0, 0, 3, 4, 7, 10, 13, 16, 17, 20, - 23, 26, 29, 30, 31, 37, 38, 46, 51, 56, - 60 + 23, 26, 29, 32, 33, 34, 40, 41, 49, 54, + 59, 63, 68 }; /* YYRHS -- A `-1'-separated list of the rules' RHS. */ static const yytype_int8 yyrhs[] = { - 26, 0, -1, -1, 27, 30, -1, 28, 32, -1, - 28, 30, -1, 28, 35, -1, -1, 29, 32, -1, - 29, 30, -1, 29, 34, -1, 29, 36, -1, -1, - -1, 3, 12, 31, 28, 9, -1, -1, 4, 7, - 22, 6, 33, 29, 9, -1, 8, 22, 10, 22, - -1, 5, 12, 10, 12, -1, 23, 22, 22, -1, - 23, 22, 22, 24, -1 + 28, 0, -1, -1, 29, 32, -1, 30, 34, -1, + 30, 32, -1, 30, 37, -1, -1, 31, 34, -1, + 31, 32, -1, 31, 36, -1, 31, 38, -1, 31, + 39, -1, -1, -1, 3, 12, 33, 30, 9, -1, + -1, 4, 7, 22, 6, 35, 31, 9, -1, 8, + 22, 10, 22, -1, 5, 12, 10, 12, -1, 23, + 22, 22, -1, 23, 22, 22, 24, -1, 25, 22, + 22, 22, -1 }; /* YYRLINE[YYN] -- source line where rule number YYN was defined. */ static const yytype_uint8 yyrline[] = { 0, 35, 35, 35, 37, 37, 37, 37, 39, 39, - 39, 39, 39, 41, 41, 51, 51, 63, 66, 69, - 72 + 39, 39, 39, 39, 41, 41, 51, 51, 63, 66, + 69, 72, 75 }; #endif @@ -472,9 +478,9 @@ static const char *const yytname[] = "$end", "error", "$undefined", "CHIP", "DEVICE", "REGISTER", "BOOL", "BUS", "RESOURCE", "END", "EQUALS", "HEX", "STRING", "PCI", "PNP", "I2C", "APIC", "APIC_CLUSTER", "PCI_DOMAIN", "IRQ", "DRQ", "IO", "NUMBER", - "SUBSYSTEMID", "INHERIT", "$accept", "devtree", "$@1", "chipchildren", - "devicechildren", "chip", "@2", "device", "@3", "resource", "registers", - "subsystemid", 0 + "SUBSYSTEMID", "INHERIT", "IOAPIC_IRQ", "IOAPIC", "$accept", "devtree", + "$@1", "chipchildren", "devicechildren", "chip", "@2", "device", "@3", + "resource", "registers", "subsystemid", "ioapic_irq", 0 }; #endif @@ -485,42 +491,43 @@ static const yytype_uint16 yytoknum[] = { 0, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, - 275, 276, 277, 278, 279 + 275, 276, 277, 278, 279, 280, 281 }; # endif /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */ static const yytype_uint8 yyr1[] = { - 0, 25, 27, 26, 28, 28, 28, 28, 29, 29, - 29, 29, 29, 31, 30, 33, 32, 34, 35, 36, - 36 + 0, 27, 29, 28, 30, 30, 30, 30, 31, 31, + 31, 31, 31, 31, 33, 32, 35, 34, 36, 37, + 38, 38, 39 }; /* YYR2[YYN] -- Number of symbols composing right hand side of rule YYN. */ static const yytype_uint8 yyr2[] = { 0, 2, 0, 2, 2, 2, 2, 0, 2, 2, - 2, 2, 0, 0, 5, 0, 7, 4, 4, 3, - 4 + 2, 2, 2, 0, 0, 5, 0, 7, 4, 4, + 3, 4, 4 }; -/* YYDEFACT[STATE-NAME] -- Default rule to reduce with in state - STATE-NUM when YYTABLE doesn't specify something else to do. Zero +/* YYDEFACT[STATE-NAME] -- Default reduction number in state STATE-NUM. + Performed when YYTABLE doesn't specify something else to do. Zero means the default is an error. */ static const yytype_uint8 yydefact[] = { - 2, 0, 0, 1, 0, 3, 13, 7, 0, 0, - 0, 14, 5, 4, 6, 0, 0, 0, 0, 15, - 18, 12, 0, 0, 16, 0, 9, 8, 10, 11, - 0, 0, 0, 19, 17, 20 + 2, 0, 0, 1, 0, 3, 14, 7, 0, 0, + 0, 15, 5, 4, 6, 0, 0, 0, 0, 16, + 19, 13, 0, 0, 17, 0, 0, 9, 8, 10, + 11, 12, 0, 0, 0, 0, 20, 0, 18, 21, + 22 }; /* YYDEFGOTO[NTERM-NUM]. */ static const yytype_int8 yydefgoto[] = { - -1, 1, 2, 8, 22, 5, 7, 13, 21, 28, - 14, 29 + -1, 1, 2, 8, 22, 5, 7, 13, 21, 29, + 14, 30, 31 }; /* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing @@ -530,46 +537,53 @@ static const yytype_int8 yypact[] = { -9, 3, 1, -9, -2, -9, -9, -9, 4, 5, -1, -9, -9, -9, -9, -8, 7, 9, 6, -9, - -9, -9, -3, 0, -9, 2, -9, -9, -9, -9, - 11, 8, 10, -5, -9, -9 + -9, -9, -3, 2, -9, 8, 10, -9, -9, -9, + -9, -9, 11, 12, 13, 14, -5, 15, -9, -9, + -9 }; /* YYPGOTO[NTERM-NUM]. */ static const yytype_int8 yypgoto[] = { - -9, -9, -9, -9, -9, -6, -9, 12, -9, -9, - -9, -9 + -9, -9, -9, -9, -9, -6, -9, 16, -9, -9, + -9, -9, -9 }; /* YYTABLE[YYPACT[STATE-NUM]]. What to do in state STATE-NUM. If positive, shift that token. If negative, reduce the rule which - number is the opposite. If zero, do what YYDEFACT says. - If YYTABLE_NINF, syntax error. */ + number is the opposite. If YYTABLE_NINF, syntax error. */ #define YYTABLE_NINF -1 static const yytype_uint8 yytable[] = { 4, 9, 12, 3, 4, 23, 24, 4, 9, 10, - 6, 16, 15, 11, 17, 19, 26, 18, 20, 35, - 25, 32, 30, 0, 31, 0, 0, 0, 0, 0, - 33, 0, 34, 0, 27 + 6, 16, 15, 11, 17, 19, 27, 18, 20, 39, + 25, 35, 26, 0, 32, 0, 0, 0, 0, 0, + 33, 0, 34, 0, 36, 37, 38, 40, 28 }; +#define yypact_value_is_default(yystate) \ + ((yystate) == (-9)) + +#define yytable_value_is_error(yytable_value) \ + YYID (0) + static const yytype_int8 yycheck[] = { 3, 4, 8, 0, 3, 8, 9, 3, 4, 5, 12, 12, 7, 9, 22, 6, 22, 10, 12, 24, - 23, 10, 22, -1, 22, -1, -1, -1, -1, -1, - 22, -1, 22, -1, 22 + 23, 10, 25, -1, 22, -1, -1, -1, -1, -1, + 22, -1, 22, -1, 22, 22, 22, 22, 22 }; /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing symbol of state STATE-NUM. */ static const yytype_uint8 yystos[] = { - 0, 26, 27, 0, 3, 30, 12, 31, 28, 4, - 5, 9, 30, 32, 35, 7, 12, 22, 10, 6, - 12, 33, 29, 8, 9, 23, 30, 32, 34, 36, - 22, 22, 10, 22, 22, 24 + 0, 28, 29, 0, 3, 32, 12, 33, 30, 4, + 5, 9, 32, 34, 37, 7, 12, 22, 10, 6, + 12, 35, 31, 8, 9, 23, 25, 32, 34, 36, + 38, 39, 22, 22, 22, 10, 22, 22, 22, 24, + 22 }; #define yyerrok (yyerrstatus = 0) @@ -584,9 +598,18 @@ static const yytype_uint8 yystos[] = /* Like YYERROR except do call yyerror. This remains here temporarily to ease the transition to the new meaning of YYERROR, for GCC. - Once GCC version 2 has supplanted version 1, this can go. */ + Once GCC version 2 has supplanted version 1, this can go. However, + YYFAIL appears to be in use. Nevertheless, it is formally deprecated + in Bison 2.4.2's NEWS entry, where a plan to phase it out is + discussed. */ #define YYFAIL goto yyerrlab +#if defined YYFAIL + /* This is here to suppress warnings from the GCC cpp's + -Wunused-macros. Normally we don't worry about that warning, but + some users do, and we want to make it easy for users to remove + YYFAIL uses, which will produce warnings from Bison 2.5. */ +#endif #define YYRECOVERING() (!!yyerrstatus) @@ -596,7 +619,6 @@ do \ { \ yychar = (Token); \ yylval = (Value); \ - yytoken = YYTRANSLATE (yychar); \ YYPOPSTACK (1); \ goto yybackup; \ } \ @@ -638,19 +660,10 @@ while (YYID (0)) #endif -/* YY_LOCATION_PRINT -- Print the location on the stream. - This macro was not mandated originally: define only if we know - we won't break user code: when these are the locations we know. */ +/* This macro is provided for backward compatibility. */ #ifndef YY_LOCATION_PRINT -# if YYLTYPE_IS_TRIVIAL -# define YY_LOCATION_PRINT(File, Loc) \ - fprintf (File, "%d.%d-%d.%d", \ - (Loc).first_line, (Loc).first_column, \ - (Loc).last_line, (Loc).last_column) -# else -# define YY_LOCATION_PRINT(File, Loc) ((void) 0) -# endif +# define YY_LOCATION_PRINT(File, Loc) ((void) 0) #endif @@ -842,7 +855,6 @@ int yydebug; # define YYMAXDEPTH 10000 #endif - #if YYERROR_VERBOSE @@ -945,115 +957,142 @@ yytnamerr (char *yyres, const char *yystr) } # endif -/* Copy into YYRESULT an error message about the unexpected token - YYCHAR while in state YYSTATE. Return the number of bytes copied, - including the terminating null byte. If YYRESULT is null, do not - copy anything; just return the number of bytes that would be - copied. As a special case, return 0 if an ordinary "syntax error" - message will do. Return YYSIZE_MAXIMUM if overflow occurs during - size calculation. */ -static YYSIZE_T -yysyntax_error (char *yyresult, int yystate, int yychar) -{ - int yyn = yypact[yystate]; +/* Copy into *YYMSG, which is of size *YYMSG_ALLOC, an error message + about the unexpected token YYTOKEN for the state stack whose top is + YYSSP. - if (! (YYPACT_NINF < yyn && yyn <= YYLAST)) - return 0; - else + Return 0 if *YYMSG was successfully written. Return 1 if *YYMSG is + not large enough to hold the message. In that case, also set + *YYMSG_ALLOC to the required number of bytes. Return 2 if the + required number of bytes is too large to store. */ +static int +yysyntax_error (YYSIZE_T *yymsg_alloc, char **yymsg, + yytype_int16 *yyssp, int yytoken) +{ + YYSIZE_T yysize0 = yytnamerr (0, yytname[yytoken]); + YYSIZE_T yysize = yysize0; + YYSIZE_T yysize1; + enum { YYERROR_VERBOSE_ARGS_MAXIMUM = 5 }; + /* Internationalized format string. */ + const char *yyformat = 0; + /* Arguments of yyformat. */ + char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM]; + /* Number of reported tokens (one for the "unexpected", one per + "expected"). */ + int yycount = 0; + + /* There are many possibilities here to consider: + - Assume YYFAIL is not used. It's too flawed to consider. See + <http://lists.gnu.org/archive/html/bison-patches/2009-12/msg00024.html> + for details. YYERROR is fine as it does not invoke this + function. + - If this state is a consistent state with a default action, then + the only way this function was invoked is if the default action + is an error action. In that case, don't check for expected + tokens because there are none. + - The only way there can be no lookahead present (in yychar) is if + this state is a consistent state with a default action. Thus, + detecting the absence of a lookahead is sufficient to determine + that there is no unexpected or expected token to report. In that + case, just report a simple "syntax error". + - Don't assume there isn't a lookahead just because this state is a + consistent state with a default action. There might have been a + previous inconsistent state, consistent state with a non-default + action, or user semantic action that manipulated yychar. + - Of course, the expected token list depends on states to have + correct lookahead information, and it depends on the parser not + to perform extra reductions after fetching a lookahead from the + scanner and before detecting a syntax error. Thus, state merging + (from LALR or IELR) and default reductions corrupt the expected + token list. However, the list is correct for canonical LR with + one exception: it will still contain any token that will not be + accepted due to an error action in a later state. + */ + if (yytoken != YYEMPTY) { - int yytype = YYTRANSLATE (yychar); - YYSIZE_T yysize0 = yytnamerr (0, yytname[yytype]); - YYSIZE_T yysize = yysize0; - YYSIZE_T yysize1; - int yysize_overflow = 0; - enum { YYERROR_VERBOSE_ARGS_MAXIMUM = 5 }; - char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM]; - int yyx; - -# if 0 - /* This is so xgettext sees the translatable formats that are - constructed on the fly. */ - YY_("syntax error, unexpected %s"); - YY_("syntax error, unexpected %s, expecting %s"); - YY_("syntax error, unexpected %s, expecting %s or %s"); - YY_("syntax error, unexpected %s, expecting %s or %s or %s"); - YY_("syntax error, unexpected %s, expecting %s or %s or %s or %s"); -# endif - char *yyfmt; - char const *yyf; - static char const yyunexpected[] = "syntax error, unexpected %s"; - static char const yyexpecting[] = ", expecting %s"; - static char const yyor[] = " or %s"; - char yyformat[sizeof yyunexpected - + sizeof yyexpecting - 1 - + ((YYERROR_VERBOSE_ARGS_MAXIMUM - 2) - * (sizeof yyor - 1))]; - char const *yyprefix = yyexpecting; - - /* Start YYX at -YYN if negative to avoid negative indexes in - YYCHECK. */ - int yyxbegin = yyn < 0 ? -yyn : 0; - - /* Stay within bounds of both yycheck and yytname. */ - int yychecklim = YYLAST - yyn + 1; - int yyxend = yychecklim < YYNTOKENS ? yychecklim : YYNTOKENS; - int yycount = 1; - - yyarg[0] = yytname[yytype]; - yyfmt = yystpcpy (yyformat, yyunexpected); - - for (yyx = yyxbegin; yyx < yyxend; ++yyx) - if (yycheck[yyx + yyn] == yyx && yyx != YYTERROR) - { - if (yycount == YYERROR_VERBOSE_ARGS_MAXIMUM) - { - yycount = 1; - yysize = yysize0; - yyformat[sizeof yyunexpected - 1] = '\0'; - break; - } - yyarg[yycount++] = yytname[yyx]; - yysize1 = yysize + yytnamerr (0, yytname[yyx]); - yysize_overflow |= (yysize1 < yysize); - yysize = yysize1; - yyfmt = yystpcpy (yyfmt, yyprefix); - yyprefix = yyor; - } + int yyn = yypact[*yyssp]; + yyarg[yycount++] = yytname[yytoken]; + if (!yypact_value_is_default (yyn)) + { + /* Start YYX at -YYN if negative to avoid negative indexes in + YYCHECK. In other words, skip the first -YYN actions for + this state because they are default actions. */ + int yyxbegin = yyn < 0 ? -yyn : 0; + /* Stay within bounds of both yycheck and yytname. */ + int yychecklim = YYLAST - yyn + 1; + int yyxend = yychecklim < YYNTOKENS ? yychecklim : YYNTOKENS; + int yyx; + + for (yyx = yyxbegin; yyx < yyxend; ++yyx) + if (yycheck[yyx + yyn] == yyx && yyx != YYTERROR + && !yytable_value_is_error (yytable[yyx + yyn])) + { + if (yycount == YYERROR_VERBOSE_ARGS_MAXIMUM) + { + yycount = 1; + yysize = yysize0; + break; + } + yyarg[yycount++] = yytname[yyx]; + yysize1 = yysize + yytnamerr (0, yytname[yyx]); + if (! (yysize <= yysize1 + && yysize1 <= YYSTACK_ALLOC_MAXIMUM)) + return 2; + yysize = yysize1; + } + } + } - yyf = YY_(yyformat); - yysize1 = yysize + yystrlen (yyf); - yysize_overflow |= (yysize1 < yysize); - yysize = yysize1; + switch (yycount) + { +# define YYCASE_(N, S) \ + case N: \ + yyformat = S; \ + break + YYCASE_(0, YY_("syntax error")); + YYCASE_(1, YY_("syntax error, unexpected %s")); + YYCASE_(2, YY_("syntax error, unexpected %s, expecting %s")); + YYCASE_(3, YY_("syntax error, unexpected %s, expecting %s or %s")); + YYCASE_(4, YY_("syntax error, unexpected %s, expecting %s or %s or %s")); + YYCASE_(5, YY_("syntax error, unexpected %s, expecting %s or %s or %s or %s")); +# undef YYCASE_ + } - if (yysize_overflow) - return YYSIZE_MAXIMUM; + yysize1 = yysize + yystrlen (yyformat); + if (! (yysize <= yysize1 && yysize1 <= YYSTACK_ALLOC_MAXIMUM)) + return 2; + yysize = yysize1; - if (yyresult) - { - /* Avoid sprintf, as that infringes on the user's name space. - Don't have undefined behavior even if the translation - produced a string with the wrong number of "%s"s. */ - char *yyp = yyresult; - int yyi = 0; - while ((*yyp = *yyf) != '\0') - { - if (*yyp == '%' && yyf[1] == 's' && yyi < yycount) - { - yyp += yytnamerr (yyp, yyarg[yyi++]); - yyf += 2; - } - else - { - yyp++; - yyf++; - } - } - } - return yysize; + if (*yymsg_alloc < yysize) + { + *yymsg_alloc = 2 * yysize; + if (! (yysize <= *yymsg_alloc + && *yymsg_alloc <= YYSTACK_ALLOC_MAXIMUM)) + *yymsg_alloc = YYSTACK_ALLOC_MAXIMUM; + return 1; } + + /* Avoid sprintf, as that infringes on the user's name space. + Don't have undefined behavior even if the translation + produced a string with the wrong number of "%s"s. */ + { + char *yyp = *yymsg; + int yyi = 0; + while ((*yyp = *yyformat) != '\0') + if (*yyp == '%' && yyformat[1] == 's' && yyi < yycount) + { + yyp += yytnamerr (yyp, yyarg[yyi++]); + yyformat += 2; + } + else + { + yyp++; + yyformat++; + } + } + return 0; } #endif /* YYERROR_VERBOSE */ - /*-----------------------------------------------. | Release the memory associated to this symbol. | @@ -1086,6 +1125,7 @@ yydestruct (yymsg, yytype, yyvaluep) } } + /* Prevent warnings from -Wmissing-prototypes. */ #ifdef YYPARSE_PARAM #if defined __STDC__ || defined __cplusplus @@ -1112,10 +1152,9 @@ YYSTYPE yylval; int yynerrs; - -/*-------------------------. -| yyparse or yypush_parse. | -`-------------------------*/ +/*----------. +| yyparse. | +`----------*/ #ifdef YYPARSE_PARAM #if (defined __STDC__ || defined __C99__FUNC__ \ @@ -1139,8 +1178,6 @@ yyparse () #endif #endif { - - int yystate; /* Number of tokens to shift before error messages enabled. */ int yyerrstatus; @@ -1295,7 +1332,7 @@ yybackup: /* First try to decide what to do without reference to lookahead token. */ yyn = yypact[yystate]; - if (yyn == YYPACT_NINF) + if (yypact_value_is_default (yyn)) goto yydefault; /* Not known => get a lookahead token if don't already have one. */ @@ -1326,8 +1363,8 @@ yybackup: yyn = yytable[yyn]; if (yyn <= 0) { - if (yyn == 0 || yyn == YYTABLE_NINF) - goto yyerrlab; + if (yytable_value_is_error (yyn)) + goto yyerrlab; yyn = -yyn; goto yyreduce; } @@ -1382,74 +1419,90 @@ yyreduce: { case 2: - { cur_parent = cur_bus = head; ;} + { cur_parent = cur_bus = head; } break; case 3: - { postprocess_devtree(); ;} + { postprocess_devtree(); } break; - case 13: + case 14: { (yyval.device) = new_chip(cur_parent, cur_bus, (yyvsp[(2) - (2)].string)); cur_parent = (yyval.device); -;} +} break; - case 14: + case 15: { cur_parent = (yyvsp[(3) - (5)].device)->parent; fold_in((yyvsp[(3) - (5)].device)); add_header((yyvsp[(3) - (5)].device)); -;} +} break; - case 15: + case 16: { (yyval.device) = new_device(cur_parent, cur_bus, (yyvsp[(2) - (4)].number), (yyvsp[(3) - (4)].string), (yyvsp[(4) - (4)].number)); cur_parent = (yyval.device); cur_bus = (yyval.device); -;} +} break; - case 16: + case 17: { cur_parent = (yyvsp[(5) - (7)].device)->parent; cur_bus = (yyvsp[(5) - (7)].device)->bus; fold_in((yyvsp[(5) - (7)].device)); alias_siblings((yyvsp[(5) - (7)].device)->children); -;} - break; - - case 17: - - { add_resource(cur_parent, (yyvsp[(1) - (4)].number), strtol((yyvsp[(2) - (4)].string), NULL, 0), strtol((yyvsp[(4) - (4)].string), NULL, 0)); ;} +} break; case 18: - { add_register(cur_parent, (yyvsp[(2) - (4)].string), (yyvsp[(4) - (4)].string)); ;} + { add_resource(cur_parent, (yyvsp[(1) - (4)].number), strtol((yyvsp[(2) - (4)].string), NULL, 0), strtol((yyvsp[(4) - (4)].string), NULL, 0)); } break; case 19: - { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[(2) - (3)].string), NULL, 16), strtol((yyvsp[(3) - (3)].string), NULL, 16), 0); ;} + { add_register(cur_parent, (yyvsp[(2) - (4)].string), (yyvsp[(4) - (4)].string)); } break; case 20: - { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[(2) - (4)].string), NULL, 16), strtol((yyvsp[(3) - (4)].string), NULL, 16), 1); ;} + { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[(2) - (3)].string), NULL, 16), strtol((yyvsp[(3) - (3)].string), NULL, 16), 0); } + break; + + case 21: + + { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[(2) - (4)].string), NULL, 16), strtol((yyvsp[(3) - (4)].string), NULL, 16), 1); } + break; + + case 22: + + { add_ioapic_info(cur_parent, strtol((yyvsp[(2) - (4)].string), NULL, 16), strtol((yyvsp[(3) - (4)].string), NULL, 16), strtol((yyvsp[(4) - (4)].string), NULL, 16)); } break; default: break; } + /* User semantic actions sometimes alter yychar, and that requires + that yytoken be updated with the new translation. We take the + approach of translating immediately before every use of yytoken. + One alternative is translating here after every semantic action, + but that translation would be missed if the semantic action invokes + YYABORT, YYACCEPT, or YYERROR immediately after altering yychar or + if it invokes YYBACKUP. In the case of YYABORT or YYACCEPT, an + incorrect destructor might then be invoked immediately. In the + case of YYERROR or YYBACKUP, subsequent parser actions might lead + to an incorrect destructor call or verbose syntax error message + before the lookahead is translated. */ YY_SYMBOL_PRINT ("-> $$ =", yyr1[yyn], &yyval, &yyloc); YYPOPSTACK (yylen); @@ -1477,6 +1530,10 @@ yyreduce: | yyerrlab -- here on detecting error | `------------------------------------*/ yyerrlab: + /* Make sure we have latest lookahead translation. See comments at + user semantic actions for why this is necessary. */ + yytoken = yychar == YYEMPTY ? YYEMPTY : YYTRANSLATE (yychar); + /* If not already recovering from an error, report this error. */ if (!yyerrstatus) { @@ -1484,37 +1541,36 @@ yyerrlab: #if ! YYERROR_VERBOSE yyerror (YY_("syntax error")); #else +# define YYSYNTAX_ERROR yysyntax_error (&yymsg_alloc, &yymsg, \ + yyssp, yytoken) { - YYSIZE_T yysize = yysyntax_error (0, yystate, yychar); - if (yymsg_alloc < yysize && yymsg_alloc < YYSTACK_ALLOC_MAXIMUM) - { - YYSIZE_T yyalloc = 2 * yysize; - if (! (yysize <= yyalloc && yyalloc <= YYSTACK_ALLOC_MAXIMUM)) - yyalloc = YYSTACK_ALLOC_MAXIMUM; - if (yymsg != yymsgbuf) - YYSTACK_FREE (yymsg); - yymsg = (char *) YYSTACK_ALLOC (yyalloc); - if (yymsg) - yymsg_alloc = yyalloc; - else - { - yymsg = yymsgbuf; - yymsg_alloc = sizeof yymsgbuf; - } - } - - if (0 < yysize && yysize <= yymsg_alloc) - { - (void) yysyntax_error (yymsg, yystate, yychar); - yyerror (yymsg); - } - else - { - yyerror (YY_("syntax error")); - if (yysize != 0) - goto yyexhaustedlab; - } + char const *yymsgp = YY_("syntax error"); + int yysyntax_error_status; + yysyntax_error_status = YYSYNTAX_ERROR; + if (yysyntax_error_status == 0) + yymsgp = yymsg; + else if (yysyntax_error_status == 1) + { + if (yymsg != yymsgbuf) + YYSTACK_FREE (yymsg); + yymsg = (char *) YYSTACK_ALLOC (yymsg_alloc); + if (!yymsg) + { + yymsg = yymsgbuf; + yymsg_alloc = sizeof yymsgbuf; + yysyntax_error_status = 2; + } + else + { + yysyntax_error_status = YYSYNTAX_ERROR; + yymsgp = yymsg; + } + } + yyerror (yymsgp); + if (yysyntax_error_status == 2) + goto yyexhaustedlab; } +# undef YYSYNTAX_ERROR #endif } @@ -1573,7 +1629,7 @@ yyerrlab1: for (;;) { yyn = yypact[yystate]; - if (yyn != YYPACT_NINF) + if (!yypact_value_is_default (yyn)) { yyn += YYTERROR; if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR) @@ -1632,8 +1688,13 @@ yyexhaustedlab: yyreturn: if (yychar != YYEMPTY) - yydestruct ("Cleanup: discarding lookahead", - yytoken, &yylval); + { + /* Make sure we have latest lookahead translation. See comments at + user semantic actions for why this is necessary. */ + yytoken = YYTRANSLATE (yychar); + yydestruct ("Cleanup: discarding lookahead", + yytoken, &yylval); + } /* Do not reclaim the symbols of the rule which action triggered this YYABORT or YYACCEPT. */ YYPOPSTACK (yylen); diff --git a/util/sconfig/sconfig.tab.h_shipped b/util/sconfig/sconfig.tab.h_shipped index fc101c2..ceb7ef3 100644 --- a/util/sconfig/sconfig.tab.h_shipped +++ b/util/sconfig/sconfig.tab.h_shipped @@ -1,10 +1,8 @@ +/* A Bison parser, made by GNU Bison 2.5. */ -/* A Bison parser, made by GNU Bison 2.4.1. */ - -/* Skeleton interface for Bison's Yacc-like parsers in C +/* Bison interface for Yacc-like parsers in C - Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005, 2006 - Free Software Foundation, Inc. + Copyright (C) 1984, 1989-1990, 2000-2011 Free Software Foundation, Inc. This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -60,7 +58,9 @@ IO = 276, NUMBER = 277, SUBSYSTEMID = 278, - INHERIT = 279 + INHERIT = 279, + IOAPIC_IRQ = 280, + IOAPIC = 281 }; #endif diff --git a/util/sconfig/sconfig.y b/util/sconfig/sconfig.y index f97850f..3d013aa 100755 --- a/util/sconfig/sconfig.y +++ b/util/sconfig/sconfig.y @@ -30,13 +30,13 @@ static struct device *cur_parent, *cur_bus; int number; } -%token CHIP DEVICE REGISTER BOOL BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC APIC_CLUSTER PCI_DOMAIN IRQ DRQ IO NUMBER SUBSYSTEMID INHERIT +%token CHIP DEVICE REGISTER BOOL BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC APIC_CLUSTER PCI_DOMAIN IRQ DRQ IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC %% devtree: { cur_parent = cur_bus = head; } chip { postprocess_devtree(); } ; chipchildren: chipchildren device | chipchildren chip | chipchildren registers | /* empty */ ; -devicechildren: devicechildren device | devicechildren chip | devicechildren resource | devicechildren subsystemid | /* empty */ ; +devicechildren: devicechildren device | devicechildren chip | devicechildren resource | devicechildren subsystemid | devicechildren ioapic_irq | /* empty */ ; chip: CHIP STRING /* == path */ { $<device>$ = new_chip(cur_parent, cur_bus, $<string>2); @@ -72,5 +72,6 @@ subsystemid: SUBSYSTEMID NUMBER NUMBER subsystemid: SUBSYSTEMID NUMBER NUMBER INHERIT { add_pci_subsystem_ids(cur_parent, strtol($<string>2, NULL, 16), strtol($<string>3, NULL, 16), 1); }; - +ioapic_irq: IOAPIC_IRQ NUMBER NUMBER NUMBER + { add_ioapic_info(cur_parent, strtol($<string>2, NULL, 16), strtol($<string>3, NULL, 16), strtol($<string>4, NULL, 16)); }; %%

1 0

New patch to review for coreboot: 10075b5 Add generic IOAPIC driver
by Sven Schnelle 25 Jun '12

25 Jun '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1137 -gerrit commit 10075b5b1cfec64a25c526e4a4a22017035db2a9 Author: Sven Schnelle <svens(a)stackframe.org> Date: Fri Jun 22 11:04:22 2012 +0200 Add generic IOAPIC driver Used for automatic generation of IOAPIC interrupt entries. Change-Id: Ia746f01906c840800956ce551306f864e440b6ec Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/drivers/generic/ioapic/Kconfig | 2 + src/drivers/generic/ioapic/Makefile.inc | 1 + src/drivers/generic/ioapic/chip.h | 32 +++++++ src/drivers/generic/ioapic/ioapic.c | 135 +++++++++++++++++++++++++++++++ 4 files changed, 170 insertions(+), 0 deletions(-) diff --git a/src/drivers/generic/ioapic/Kconfig b/src/drivers/generic/ioapic/Kconfig new file mode 100644 index 0000000..f8b46cb --- /dev/null +++ b/src/drivers/generic/ioapic/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_GENERIC_IOAPIC + bool diff --git a/src/drivers/generic/ioapic/Makefile.inc b/src/drivers/generic/ioapic/Makefile.inc new file mode 100644 index 0000000..35d0934 --- /dev/null +++ b/src/drivers/generic/ioapic/Makefile.inc @@ -0,0 +1 @@ +driver-$(CONFIG_DRIVERS_GENERIC_IOAPIC) += ioapic.c diff --git a/src/drivers/generic/ioapic/chip.h b/src/drivers/generic/ioapic/chip.h new file mode 100644 index 0000000..f6b298f --- /dev/null +++ b/src/drivers/generic/ioapic/chip.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef DRIVERS_GENERIC_IOAPIC_CHIP_H +#define DRIVERS_GENERIC_IOAPIC_CHIP_H + +extern struct chip_operations drivers_generic_ioapic_ops; +struct drivers_generic_ioapic_config { + u32 version; + u8 apicid; + u8 irq_on_fsb; + u8 enable_virtual_wire; + u8 have_isa_interrupts; + u32 base; +}; +#endif diff --git a/src/drivers/generic/ioapic/ioapic.c b/src/drivers/generic/ioapic/ioapic.c new file mode 100644 index 0000000..9a93c78 --- /dev/null +++ b/src/drivers/generic/ioapic/ioapic.c @@ -0,0 +1,135 @@ +#include <console/console.h> +#include <device/device.h> +#include <device/smbus.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <cpu/x86/msr.h> +#include <reset.h> +#include <delay.h> +#include "chip.h" +#include <arch/ioapic.h> +#include <arch/io.h> +#include <cpu/x86/lapic.h> + +static u32 io_apic_read(u32 ioapic_base, u32 reg) +{ + write32(ioapic_base, reg); + return read32(ioapic_base + 0x10); +} + +static void io_apic_write(u32 ioapic_base, u32 reg, u32 value) +{ + write32(ioapic_base, reg); + write32(ioapic_base + 0x10, value); +} + +static void ioapic_init(device_t dev) +{ + struct drivers_generic_ioapic_config *config = dev->chip_info; + u32 bsp_lapicid = lapicid(); + u32 low, high; + u32 i, ioapic_interrupts; + u32 ioapic_base; + u8 ioapic_id; + if (!dev->enabled || !config) + return; + + ioapic_base = config->base; + ioapic_id = config->apicid; + + printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n", + ioapic_base); + printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = 0x%02x\n", + bsp_lapicid); + + if (ioapic_id) { + printk(BIOS_DEBUG, "IOAPIC: ID = 0x%02x\n", ioapic_id); + /* Set IOAPIC ID if it has been specified. */ + io_apic_write(ioapic_base, 0x00, + (io_apic_read(ioapic_base, 0x00) & 0xf0ffffff) | + (ioapic_id << 24)); + } + + /* Read the available number of interrupts. */ + ioapic_interrupts = (io_apic_read(ioapic_base, 0x01) >> 16) & 0xff; + if (!ioapic_interrupts || ioapic_interrupts == 0xff) + ioapic_interrupts = 24; + printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts); + + if (config->irq_on_fsb) { + /* + * For the Pentium 4 and above APICs deliver their interrupts + * on the front side bus, enable that. + */ + printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n"); + io_apic_write(ioapic_base, 0x03, + io_apic_read(ioapic_base, 0x03) | (1 << 0)); + } else { + printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n"); + io_apic_write(ioapic_base, 0x03, 0); + } + + if (config->enable_virtual_wire) { + /* Enable Virtual Wire Mode. */ + low = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT; + high = bsp_lapicid << (56 - 32); + + io_apic_write(ioapic_base, 0x10, low); + io_apic_write(ioapic_base, 0x11, high); + + if (io_apic_read(ioapic_base, 0x10) == 0xffffffff) { + printk(BIOS_WARNING, "IOAPIC not responding.\n"); + return; + } + + printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", 0, + high, low); + } + low = DISABLED; + high = NONE; + + for (i = 1; i < ioapic_interrupts; i++) { + io_apic_write(ioapic_base, i * 2 + 0x10, low); + io_apic_write(ioapic_base, i * 2 + 0x11, high); + + printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", + i, high, low); + } +} + +static void ioapic_enable_resources(device_t dev) +{ +} + +static void ioapic_nop(device_t dummy) +{ +} + +static void ioapic_read_resources(device_t dev) +{ + struct drivers_generic_ioapic_config *config = (struct drivers_generic_ioapic_config *)dev->chip_info; + struct resource *res; + + res = new_resource(dev, 0); + res->base = config->base; + res->size = 0x1000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static struct device_operations ioapic_operations = { + .read_resources = ioapic_read_resources, + .set_resources = ioapic_nop, + .enable_resources = ioapic_enable_resources, + .init = ioapic_init, +}; + +static void enable_dev(struct device *dev) +{ + dev->ops = &ioapic_operations; +} + +struct chip_operations drivers_generic_ioapic_ops = { + CHIP_NAME("IOAPIC") + .enable_dev = enable_dev, +};

1 0

Patch merged into coreboot/master: eec1a96 X60/T60: fix mptable LINT entries
by gerrit＠coreboot.org 24 Jun '12

24 Jun '12

the following patch was just integrated into master: commit eec1a963cf70845ff9b837ad347811cd7be2f974 Author: Sven Schnelle <svens(a)stackframe.org> Date: Sun Jun 24 10:02:22 2012 +0200 X60/T60: fix mptable LINT entries They used MP_IRQ_TRIGGER_LEVEL, but it should be MP_IRQ_TRIGGER_EDGE. While at it, uses mptable_lintsrc() instead. Change-Id: Ie71311b8bf865889cf0d8808467df98af4b0132d Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Sun Jun 24 13:03:52 2012, giving +2 See http://review.coreboot.org/1136 for details. -gerrit

1 0

New patch to review for coreboot: eec1a96 X60/T60: fix mptable LINT entries
by Sven Schnelle 24 Jun '12

24 Jun '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1136 -gerrit commit eec1a963cf70845ff9b837ad347811cd7be2f974 Author: Sven Schnelle <svens(a)stackframe.org> Date: Sun Jun 24 10:02:22 2012 +0200 X60/T60: fix mptable LINT entries They used MP_IRQ_TRIGGER_LEVEL, but it should be MP_IRQ_TRIGGER_EDGE. While at it, uses mptable_lintsrc() instead. Change-Id: Ie71311b8bf865889cf0d8808467df98af4b0132d Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/mainboard/lenovo/t60/mptable.c | 4 +--- src/mainboard/lenovo/x60/mptable.c | 4 +--- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/src/mainboard/lenovo/t60/mptable.c b/src/mainboard/lenovo/t60/mptable.c index 312e30d..744ef30 100644 --- a/src/mainboard/lenovo/t60/mptable.c +++ b/src/mainboard/lenovo/t60/mptable.c @@ -64,9 +64,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x02, 0x02, 0x10); /* SATA 0:1f.2 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x06, (0x00 << 2) | 0x00, 0x02, 0x10); /* Cardbus 6:00.0 */ - smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_HIGH, isa_bus, 0, MP_APIC_ALL, 0); - smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_HIGH, isa_bus, 0, MP_APIC_ALL, 1); - + mptable_lintsrc(mc, isa_bus); return mptable_finalize(mc); } diff --git a/src/mainboard/lenovo/x60/mptable.c b/src/mainboard/lenovo/x60/mptable.c index f21e76f..8ade71b 100644 --- a/src/mainboard/lenovo/x60/mptable.c +++ b/src/mainboard/lenovo/x60/mptable.c @@ -66,9 +66,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x01, 0x02, 0x11); /* Firewire 5:00.1 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x02, 0x02, 0x12); /* SDHC 5:00.2 */ - smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_HIGH, isa_bus, 0, MP_APIC_ALL, 0); - smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_HIGH, isa_bus, 0, MP_APIC_ALL, 1); - + mptable_lintsrc(mc, isa_bus); return mptable_finalize(mc); }

1 0

Re: [coreboot] Future Supported Chipsets
by ron minnich 24 Jun '12

24 Jun '12

how much memory per node do you need? what kind of graphics if any? Local disk? How much? USB? GigE or 10 GigE? ron

1 0

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coreboot June 2012