coreboot June 2012

coreboot@coreboot.org

41 participants
241 discussions

Future Supported Chipsets
by x414e54 23 Jun '12

23 Jun '12

Hi, I am needing to upgrade my computers, they are used for 3d modelling, so require some fairly high end specs. However I am wanting to make sure that they are possibly future proof for coreboot. I am looking at the AMD 990FX chipset for example Sapphire PURE Black. Do you know if there will be any support from AMD with regards to these, or if there will be any effort put into a specific motherboard of this generation? If it is 3/5 years time from now then this is fine. Any advice would be great. Thanks

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Patch merged into coreboot/master: 647e866 Add Supermicro X7DB8 motherboard
by gerrit＠coreboot.org 23 Jun '12

23 Jun '12

the following patch was just integrated into master: commit 647e8664ea84d8205934263d0864977b1c4408eb Author: Sven Schnelle <svens(a)stackframe.org> Date: Wed Jun 20 14:56:46 2012 +0200 Add Supermicro X7DB8 motherboard This adds basic supported for the Supermicro X7DB8. Basic means that almost all onboard peripherals are working. Known problems are: - mptable needs to be written dynamically. If you plan to use Add on cards, modify mptable.c according to your needs. A patch to add generic mptable autogeneration based on devicetree is coming up. Change-Id: I5eaac32a8bafa69a05929cf08d869127b9464661 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Build-Tested: build bot (Jenkins) at Sat Jun 23 10:06:56 2012, giving +1 Reviewed-By: Sven Schnelle <svens(a)stackframe.org> at Sat Jun 23 17:45:04 2012, giving +2 See http://review.coreboot.org/493 for details. -gerrit

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Patch merged into coreboot/master: 3505f09 i3100: add smbus_write_byte()
by gerrit＠coreboot.org 23 Jun '12

23 Jun '12

the following patch was just integrated into master: commit 3505f09e9c25332a430c77fdfcb41ed45e9039cc Author: Sven Schnelle <svens(a)stackframe.org> Date: Wed Jun 20 14:54:08 2012 +0200 i3100: add smbus_write_byte() Required for Supermicro X7DB8, which needs the FBDIMM clock generator setup during romstage. Change-Id: I30ca8354087e851487aee0614595782131d4d9bc Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Build-Tested: build bot (Jenkins) at Fri Jun 22 10:26:10 2012, giving +1 Reviewed-By: Sven Schnelle <svens(a)stackframe.org> at Sat Jun 23 10:04:53 2012, giving +2 See http://review.coreboot.org/1116 for details. -gerrit

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Patch set updated for coreboot: 647e866 Add Supermicro X7DB8 motherboard
by Sven Schnelle 23 Jun '12

23 Jun '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/493 -gerrit commit 647e8664ea84d8205934263d0864977b1c4408eb Author: Sven Schnelle <svens(a)stackframe.org> Date: Wed Jun 20 14:56:46 2012 +0200 Add Supermicro X7DB8 motherboard This adds basic supported for the Supermicro X7DB8. Basic means that almost all onboard peripherals are working. Known problems are: - mptable needs to be written dynamically. If you plan to use Add on cards, modify mptable.c according to your needs. A patch to add generic mptable autogeneration based on devicetree is coming up. Change-Id: I5eaac32a8bafa69a05929cf08d869127b9464661 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/mainboard/supermicro/Kconfig | 3 + src/mainboard/supermicro/x7db8/Kconfig | 43 +++++++ src/mainboard/supermicro/x7db8/chip.h | 21 ++++ src/mainboard/supermicro/x7db8/cmos.layout | 142 ++++++++++++++++++++++++ src/mainboard/supermicro/x7db8/devicetree.cb | 121 ++++++++++++++++++++ src/mainboard/supermicro/x7db8/irq_tables.c | 57 ++++++++++ src/mainboard/supermicro/x7db8/mainboard.c | 41 +++++++ src/mainboard/supermicro/x7db8/mptable.c | 90 +++++++++++++++ src/mainboard/supermicro/x7db8/romstage.c | 152 ++++++++++++++++++++++++++ 9 files changed, 670 insertions(+), 0 deletions(-) diff --git a/src/mainboard/supermicro/Kconfig b/src/mainboard/supermicro/Kconfig index 80ffd6a..1fe9b1b 100644 --- a/src/mainboard/supermicro/Kconfig +++ b/src/mainboard/supermicro/Kconfig @@ -25,6 +25,8 @@ config BOARD_SUPERMICRO_X6DHR_IG2 bool "X6DHR-iG2" config BOARD_SUPERMICRO_X6DHR_IG bool "X6DHR-iG" +config BOARD_SUPERMICRO_X7DB8 + bool "X7DB8 / X7DB8+" endchoice @@ -39,6 +41,7 @@ source "src/mainboard/supermicro/x6dhe_g2/Kconfig" source "src/mainboard/supermicro/x6dhe_g/Kconfig" source "src/mainboard/supermicro/x6dhr_ig2/Kconfig" source "src/mainboard/supermicro/x6dhr_ig/Kconfig" +source "src/mainboard/supermicro/x7db8/Kconfig" config MAINBOARD_VENDOR string diff --git a/src/mainboard/supermicro/x7db8/Kconfig b/src/mainboard/supermicro/x7db8/Kconfig new file mode 100644 index 0000000..48859f1 --- /dev/null +++ b/src/mainboard/supermicro/x7db8/Kconfig @@ -0,0 +1,43 @@ +if BOARD_SUPERMICRO_X7DB8 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA771 + select SOUTHBRIDGE_INTEL_I3100 + select NORTHBRIDGE_INTEL_I5000 + select SUPERIO_WINBOND_W83627HF + select MMCONF_SUPPORT + select BOARD_ROMSIZE_KB_512 + select HAVE_MP_TABLE + select HAVE_PIRQ_TABLE + +config MAINBOARD_DIR + string + default supermicro/x7db8 + +config DCACHE_RAM_BASE + hex + default 0xffdf8000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + +config MAINBOARD_PART_NUMBER + string + default "X7DB8 / X7DB8+" + +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + +config IRQ_SLOT_COUNT + int + default 48 + +config MAX_CPUS + int + default 8 + +endif diff --git a/src/mainboard/supermicro/x7db8/chip.h b/src/mainboard/supermicro/x7db8/chip.h new file mode 100644 index 0000000..70f9bb4 --- /dev/null +++ b/src/mainboard/supermicro/x7db8/chip.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/supermicro/x7db8/cmos.layout b/src/mainboard/supermicro/x7db8/cmos.layout new file mode 100644 index 0000000..29e78ad --- /dev/null +++ b/src/mainboard/supermicro/x7db8/cmos.layout @@ -0,0 +1,142 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2008 coresystems GmbH +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; version 2 of +# the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +#409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +416 512 s 0 boot_devices +928 8 h 0 boot_default +936 1 e 8 cmos_defaults_loaded +937 1 e 1 lpt +#938 46 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 No +8 1 Yes +9 0 Secondary +9 1 Primary +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/supermicro/x7db8/devicetree.cb b/src/mainboard/supermicro/x7db8/devicetree.cb new file mode 100644 index 0000000..7c90ba2 --- /dev/null +++ b/src/mainboard/supermicro/x7db8/devicetree.cb @@ -0,0 +1,121 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +chip northbridge/intel/i5000 + + device lapic_cluster 0 on + chip cpu/intel/socket_LGA771 + device lapic 0 on end + end + end + + device pci_domain 0 on + device pci 00.0 on # Host bridge + subsystemid 0x15d9 0x2017 + end + + device pci 02.0 on # PCIe bridge + device pci 00.0 on + device pci 00.0 on + device pci 00.0 on end + device pci 02.0 on end + end + device pci 02.0 on + device pci 00.0 on + device pci 02.0 on + device pci 00.0 on end # e1000 #1 + device pci 00.1 on end # e1000 #2 + end + end + device pci 00.1 on end + end + end + device pci 00.1 on end + device pci 00.3 on end + end + + device pci 03.0 on end + device pci 04.0 on end + device pci 05.0 on end + device pci 06.0 on end + device pci 07.0 on end + device pci 10.0 on end # FBD + device pci 10.1 on end # FBD + device pci 10.2 on end # FBD + device pci 11.0 on end # FBD reserved + device pci 13.0 on end # FBD reserved + device pci 15.0 on end # FBD + device pci 16.0 on end # FBD + + chip southbridge/intel/i3100 + register "pirq_a_d" = "0x0b0b0b0b" + register "pirq_e_h" = "0x80808080" + register "sata_ports_implemented" = "0x3f" + + device pci 1c.0 on end # PCIe bridge + device pci 1d.0 on end # USB UHCI + device pci 1d.1 on end # USB UHCI + device pci 1d.2 on end # USB UHCI + device pci 1d.3 on end # USB UHCI + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on + device pci 01.0 on + end + end + + device pci 1f.0 on # PCI-LPC bridge + subsystemid 0x15d9 0x2009 + chip superio/winbond/w83627hf + device pnp 2e.0 off end # FDC + device pnp 2e.1 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Serial Port 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + + device pnp 2e.3 off end + device pnp 2e.5 on # KBC + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + + end + + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # Game port / MIDI + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 on end # GPIO3 + device pnp 2e.a on end # ACPI + device pnp 2e.b off end # HWMON + end + end + device pci 1f.1 off end # IDE + device pci 1f.2 on end # SATA + device pci 1f.3 off end # SMBUS + + end + end +end diff --git a/src/mainboard/supermicro/x7db8/irq_tables.c b/src/mainboard/supermicro/x7db8/irq_tables.c new file mode 100644 index 0000000..84f456a --- /dev/null +++ b/src/mainboard/supermicro/x7db8/irq_tables.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x1f << 3) | 0x0, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x2670, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x1c << 3) | 0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1c << 3) | 0x1, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1c << 3) | 0x2, {{0x00, 0x0000}, {0x00, 0x0000}, {0x62, 0x1ef8}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1c << 3) | 0x3, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x63, 0x1ef8}}, 0, 0}, + {0x00, (0x1d << 3) | 0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1d << 3) | 0x1, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1d << 3) | 0x2, {{0x00, 0x0000}, {0x00, 0x0000}, {0x62, 0x1ef8}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1d << 3) | 0x3, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x63, 0x1ef8}}, 0, 0}, + {0x00, (0x1d << 3) | 0x7, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1f << 3) | 0x1, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1f << 3) | 0x2, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} diff --git a/src/mainboard/supermicro/x7db8/mainboard.c b/src/mainboard/supermicro/x7db8/mainboard.c new file mode 100644 index 0000000..27a26f9 --- /dev/null +++ b/src/mainboard/supermicro/x7db8/mainboard.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/io.h> +#include <boot/tables.h> +#include <delay.h> +#include <arch/coreboot_tables.h> +#include "chip.h" +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <arch/io.h> + +static void mainboard_enable(device_t dev) +{ +} + +struct chip_operations mainboard_ops = { + CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER) + .enable_dev = mainboard_enable, +}; + diff --git a/src/mainboard/supermicro/x7db8/mptable.c b/src/mainboard/supermicro/x7db8/mptable.c new file mode 100644 index 0000000..d0ddada --- /dev/null +++ b/src/mainboard/supermicro/x7db8/mptable.c @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/pci.h> +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <arch/ioapic.h> +#include <string.h> +#include <stdint.h> + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int isa_bus; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + + smp_write_processors(mc); + + mptable_write_buses(mc, NULL, &isa_bus); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, 8, 0x20, IO_APIC_ADDR); + smp_write_ioapic(mc, 9, 0x20, IO_APIC_ADDR + 0x80000); + + /* Legacy Interrupts */ + mptable_add_isa_interrupts(mc, isa_bus, 0x8, 0); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x00 << 2), 0x08, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x02 << 2), 0x08, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x03 << 2), 0x08, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x04 << 2), 0x08, 0x10); + + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x02, (0x02 << 2), 0x08, 0x10); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1b << 2), 0x08, 0x11); /* HD Audio 0:1b.0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2), 0x08, 0x14); /* PCIe 0:1c.0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x01, 0x08, 0x15); /* PCIe 0:1c.1 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x02, 0x08, 0x16); /* PCIe 0:1c.2 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x03, 0x08, 0x17); /* PCIe 0:1c.3 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) , 0x08, 0x10); /* USB 0:1d.0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x01, 0x08, 0x11); /* USB 0:1d.1 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x02, 0x08, 0x12); /* USB 0:1d.2 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x03, 0x08, 0x13); /* USB 0:1d.3 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2), 0x08, 0x11); /* SATA 0:1f.2 */ + + /* e1000 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x07, (0x00 << 2) | 0x00, 0x08, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x07, (0x00 << 2) | 0x01, 0x08, 0x13); + + /* SCSI on board */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x04, (0x02 << 2) | 0x00, 0x08, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x04, (0x02 << 2) | 0x01, 0x08, 0x11); + /* SCSI add on */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x08, (0x01 << 2) | 0x00, 0x09, 0x00); + + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_HIGH, isa_bus, 0x00, MP_APIC_ALL, 0x00); + smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x00, MP_APIC_ALL, 0x01); + + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/supermicro/x7db8/romstage.c b/src/mainboard/supermicro/x7db8/romstage.c new file mode 100644 index 0000000..43ba238 --- /dev/null +++ b/src/mainboard/supermicro/x7db8/romstage.c @@ -0,0 +1,152 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <lib.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include <superio/winbond/w83627hf/early_serial.c> +#include <northbridge/intel/i5000/raminit.h> +#include "northbridge/intel/i3100/i3100.h" +#include "southbridge/intel/i3100/i3100.h" +#include <southbridge/intel/i3100/early_smbus.c> + +#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0) +#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) + +#define RCBA_RPC 0x0224 /* 32 bit */ +#define RCBA_HPTC 0x3404 /* 32 bit */ +#define RCBA_GCS 0x3410 /* 32 bit */ +#define RCBA_FD 0x3418 /* 32 bit */ + +static void early_config(void) +{ + u32 gcs, rpc, fd; + + /* Enable RCBA */ + pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, DEFAULT_RCBA | 1); + + /* Disable watchdog */ + gcs = read32(DEFAULT_RCBA + RCBA_GCS); + gcs |= (1 << 5); /* No reset */ + write32(DEFAULT_RCBA + RCBA_GCS, gcs); + + /* Configure PCIe port B as 4x */ + rpc = read32(DEFAULT_RCBA + RCBA_RPC); + rpc |= (3 << 0); + write32(DEFAULT_RCBA + RCBA_RPC, rpc); + + /* Disable Modem, Audio, PCIe ports 2/3/4 */ + fd = read32(DEFAULT_RCBA + RCBA_FD); + fd |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 6) | (1 << 5); + write32(DEFAULT_RCBA + RCBA_FD, fd); + + /* Enable HPET */ + write32(DEFAULT_RCBA + RCBA_HPTC, (1 << 7)); + + /* Setup sata mode */ + pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, 0x40); +} + +#define DEFAULT_GPIOBASE 0x1180 +static void setup_gpio(void) +{ + pci_write_config32(PCI_DEV(0, 31, 0), 0x48, DEFAULT_GPIOBASE | 1); + pci_write_config8(PCI_DEV(0, 31, 0), 0x4c, (1 << 4)); + + outl(0xff0c79cf, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xe700ffff, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0x65b70000, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + outl(0x0000718a, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x00000106, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ + outl(0x00000301, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ + outl(0x00030301, DEFAULT_GPIOBASE + 0x38); /* GPIO_LVL2 */ +} + +static void i5000_lpc_config(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); +} + +int mainboard_set_fbd_clock(int speed) +{ + switch(speed) { + case 533: + smbus_write_byte(0x6f, 0x80, 0x21); + return 0; + case 667: + smbus_write_byte(0x6f, 0x80, 0x23); + return 0; + default: + printk(BIOS_ERR, "Invalid clock: %dMHz\n", speed); + die(""); + return -1; + } +} + +void main(unsigned long bist) +{ + if (bist == 0) + enable_lapic(); + + i5000_lpc_config(); + + w83627hf_enable_serial(PNP_DEV(0x2e, 2), 0x3f8); + + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + early_config(); + + setup_gpio(); + + enable_smbus(); + + /* setup PCIe MMCONF base address */ + pci_write_config32(PCI_DEV(0, 16, 0), 0x64, + CONFIG_MMCONF_BASE_ADDRESS >> 16); + + outb(0x07, 0x11b8); + + /* These are smbus write captured with serialice. They + seem to setup the clock generator */ + + smbus_write_byte(0x6f, 0x88, 0x1f); + smbus_write_byte(0x6f, 0x81, 0xff); + smbus_write_byte(0x6f, 0x82, 0xff); + smbus_write_byte(0x6f, 0x80, 0x23); + + outb(0x03, 0x11b8); + outb(0x01, 0x11b8); + + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, DEFAULT_RCBA | 1); + i5000_fbdimm_init(); + smbus_write_byte(0x69, 0x01, 0x01); +}

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Patch merged into coreboot/master: e251653 Add an option for Waiting for gdb connection if the gdb stub configuration is chosen.
by gerrit＠coreboot.org 23 Jun '12

23 Jun '12

the following patch was just integrated into master: commit e251653bf5f5d807218f1822ba950161648e0e34 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Fri Jun 22 15:56:37 2012 +0200 Add an option for Waiting for gdb connection if the gdb stub configuration is chosen. Here's a quick demonstration on how to use it(tested on M4A785T-M). (gdb) file ./build/cbfs/fallback/coreboot_ram.debug Reading symbols from [...]/build/cbfs/fallback/coreboot_ram.debug...done. (gdb) set remotebaud 115200 (gdb) target remote /dev/ttyUSB0 Remote debugging using /dev/ttyUSB0 _text () at src/arch/x86/lib/c_start.S:85 85 call hardwaremain Change-Id: Ia49cbecc41deb061433bc39f5b81715da49edc98 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Build-Tested: build bot (Jenkins) at Sat Jun 23 02:44:45 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Sat Jun 23 07:50:07 2012, giving +2 See http://review.coreboot.org/1134 for details. -gerrit

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Patch set updated for coreboot: e251653 Add an option for Waiting for gdb connection if the gdb stub configuration is chosen.
by Denis Carikli 23 Jun '12

23 Jun '12

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1134 -gerrit commit e251653bf5f5d807218f1822ba950161648e0e34 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Fri Jun 22 15:56:37 2012 +0200 Add an option for Waiting for gdb connection if the gdb stub configuration is chosen. Here's a quick demonstration on how to use it(tested on M4A785T-M). (gdb) file ./build/cbfs/fallback/coreboot_ram.debug Reading symbols from [...]/build/cbfs/fallback/coreboot_ram.debug...done. (gdb) set remotebaud 115200 (gdb) target remote /dev/ttyUSB0 Remote debugging using /dev/ttyUSB0 _text () at src/arch/x86/lib/c_start.S:85 85 call hardwaremain Change-Id: Ia49cbecc41deb061433bc39f5b81715da49edc98 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/Kconfig | 7 +++++++ src/arch/x86/lib/c_start.S | 5 ++++- 2 files changed, 11 insertions(+), 1 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 717146d..3453614 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -779,6 +779,13 @@ config GDB_STUB If enabled, you will be able to set breakpoints for gdb debugging. See src/arch/x86/lib/c_start.S for details. +config GDB_WAIT + bool "Wait for a GDB connection" + default n + depends on GDB_STUB + help + If enabled, coreboot will wait for a GDB connection. + config DEBUG_CBFS bool "Output verbose CBFS debug messages" default n diff --git a/src/arch/x86/lib/c_start.S b/src/arch/x86/lib/c_start.S index 005ac33..fd9dce7 100644 --- a/src/arch/x86/lib/c_start.S +++ b/src/arch/x86/lib/c_start.S @@ -78,6 +78,9 @@ _start: /* Restore the stack location */ movl %ebp, %esp +#if CONFIG_GDB_WAIT == 1 + call gdb_stub_breakpoint +#endif /* The boot_complete flag has already been pushed */ call hardwaremain /* NOTREACHED */ @@ -228,7 +231,7 @@ int_hand: iret -#if CONFIG_GDB_STUB == 1 +#if CONFIG_GDB_WAIT == 1 .globl gdb_stub_breakpoint gdb_stub_breakpoint:

1 0

Patch merged into coreboot/master: 84d1809 romcc: fix up attribute((unused)) detection
by gerrit＠coreboot.org 22 Jun '12

22 Jun '12

the following patch was just integrated into master: commit 84d18095b8e10b15d5e95c026fc96148b3603580 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Jun 22 11:07:25 2012 -0700 romcc: fix up attribute((unused)) detection The length was not accounted for correctly. Change-Id: If34f288ba9dee1cd19d60da1b9f3647b9593ac1f Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Fri Jun 22 20:37:18 2012, giving +1 See http://review.coreboot.org/1135 for details. -gerrit

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New patch to review for coreboot: 84d1809 romcc: fix up attribute((unused)) detection
by Stefan Reinauer 22 Jun '12

22 Jun '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1135 -gerrit commit 84d18095b8e10b15d5e95c026fc96148b3603580 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Jun 22 11:07:25 2012 -0700 romcc: fix up attribute((unused)) detection The length was not accounted for correctly. Change-Id: If34f288ba9dee1cd19d60da1b9f3647b9593ac1f Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- util/romcc/romcc.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c index b0f6198..15e950c 100644 --- a/util/romcc/romcc.c +++ b/util/romcc/romcc.c @@ -24992,7 +24992,7 @@ static void compile(const char *filename, state.i_noinline = lookup(&state, "noinline", 8); state.i_always_inline = lookup(&state, "always_inline", 13); state.i_noreturn = lookup(&state, "noreturn", 8); - state.i_unused = lookup(&state, "unused", 8); + state.i_unused = lookup(&state, "unused", 6); /* Process the command line macros */ process_cmdline_macros(&state);

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Patch merged into coreboot/master: 8f0e148 libpayload: Adjust timeouts and delays in OHCI driver
by gerrit＠coreboot.org 22 Jun '12

22 Jun '12

the following patch was just integrated into master: commit 8f0e148abe2490e677ed5f3ac588aea860c29c44 Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue Jun 19 10:27:00 2012 +0200 libpayload: Adjust timeouts and delays in OHCI driver This sets the timeout for control and bulk transfers to 2s per transfer descriptor (like we set it in the EHCI driver). It also adds delays around the disabling of control and bulk list access to overcome some race conditions. Change-Id: Ia2d1db890fca51c7d9477de163d55030e0c5a04a Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Build-Tested: build bot (Jenkins) at Wed Jun 20 22:37:43 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Thu Jun 21 22:58:37 2012, giving +2 See http://review.coreboot.org/1127 for details. -gerrit

1 0

Patch set updated for coreboot: 23f0956 Add Supermicro X7DB8 motherboard
by Sven Schnelle 22 Jun '12

22 Jun '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/493 -gerrit commit 23f09565998fe811057c4d243947c6957bd9135e Author: Sven Schnelle <svens(a)stackframe.org> Date: Wed Jun 20 14:56:46 2012 +0200 Add Supermicro X7DB8 motherboard This adds basic supported for the Supermicro X7DB8. Basic means that almost all onboard peripherals are working. Known problems are: - mptable needs to be written dynamically. If you plan to use Add on cards, modify mptable.c according to your needs. A patch to add generic mptable autogeneration based on devicetree is coming up. Change-Id: I5eaac32a8bafa69a05929cf08d869127b9464661 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/mainboard/supermicro/Kconfig | 3 + src/mainboard/supermicro/x7db8/Kconfig | 43 +++++++ src/mainboard/supermicro/x7db8/chip.h | 21 ++++ src/mainboard/supermicro/x7db8/cmos.layout | 142 +++++++++++++++++++++++ src/mainboard/supermicro/x7db8/devicetree.cb | 121 ++++++++++++++++++++ src/mainboard/supermicro/x7db8/irq_tables.c | 57 ++++++++++ src/mainboard/supermicro/x7db8/mainboard.c | 41 +++++++ src/mainboard/supermicro/x7db8/mptable.c | 90 +++++++++++++++ src/mainboard/supermicro/x7db8/romstage.c | 155 ++++++++++++++++++++++++++ 9 files changed, 673 insertions(+), 0 deletions(-) diff --git a/src/mainboard/supermicro/Kconfig b/src/mainboard/supermicro/Kconfig index 80ffd6a..1fe9b1b 100644 --- a/src/mainboard/supermicro/Kconfig +++ b/src/mainboard/supermicro/Kconfig @@ -25,6 +25,8 @@ config BOARD_SUPERMICRO_X6DHR_IG2 bool "X6DHR-iG2" config BOARD_SUPERMICRO_X6DHR_IG bool "X6DHR-iG" +config BOARD_SUPERMICRO_X7DB8 + bool "X7DB8 / X7DB8+" endchoice @@ -39,6 +41,7 @@ source "src/mainboard/supermicro/x6dhe_g2/Kconfig" source "src/mainboard/supermicro/x6dhe_g/Kconfig" source "src/mainboard/supermicro/x6dhr_ig2/Kconfig" source "src/mainboard/supermicro/x6dhr_ig/Kconfig" +source "src/mainboard/supermicro/x7db8/Kconfig" config MAINBOARD_VENDOR string diff --git a/src/mainboard/supermicro/x7db8/Kconfig b/src/mainboard/supermicro/x7db8/Kconfig new file mode 100644 index 0000000..48859f1 --- /dev/null +++ b/src/mainboard/supermicro/x7db8/Kconfig @@ -0,0 +1,43 @@ +if BOARD_SUPERMICRO_X7DB8 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA771 + select SOUTHBRIDGE_INTEL_I3100 + select NORTHBRIDGE_INTEL_I5000 + select SUPERIO_WINBOND_W83627HF + select MMCONF_SUPPORT + select BOARD_ROMSIZE_KB_512 + select HAVE_MP_TABLE + select HAVE_PIRQ_TABLE + +config MAINBOARD_DIR + string + default supermicro/x7db8 + +config DCACHE_RAM_BASE + hex + default 0xffdf8000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + +config MAINBOARD_PART_NUMBER + string + default "X7DB8 / X7DB8+" + +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + +config IRQ_SLOT_COUNT + int + default 48 + +config MAX_CPUS + int + default 8 + +endif diff --git a/src/mainboard/supermicro/x7db8/chip.h b/src/mainboard/supermicro/x7db8/chip.h new file mode 100644 index 0000000..70f9bb4 --- /dev/null +++ b/src/mainboard/supermicro/x7db8/chip.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/supermicro/x7db8/cmos.layout b/src/mainboard/supermicro/x7db8/cmos.layout new file mode 100644 index 0000000..29e78ad --- /dev/null +++ b/src/mainboard/supermicro/x7db8/cmos.layout @@ -0,0 +1,142 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2008 coresystems GmbH +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; version 2 of +# the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +#409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +416 512 s 0 boot_devices +928 8 h 0 boot_default +936 1 e 8 cmos_defaults_loaded +937 1 e 1 lpt +#938 46 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 No +8 1 Yes +9 0 Secondary +9 1 Primary +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/supermicro/x7db8/devicetree.cb b/src/mainboard/supermicro/x7db8/devicetree.cb new file mode 100644 index 0000000..7c90ba2 --- /dev/null +++ b/src/mainboard/supermicro/x7db8/devicetree.cb @@ -0,0 +1,121 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +chip northbridge/intel/i5000 + + device lapic_cluster 0 on + chip cpu/intel/socket_LGA771 + device lapic 0 on end + end + end + + device pci_domain 0 on + device pci 00.0 on # Host bridge + subsystemid 0x15d9 0x2017 + end + + device pci 02.0 on # PCIe bridge + device pci 00.0 on + device pci 00.0 on + device pci 00.0 on end + device pci 02.0 on end + end + device pci 02.0 on + device pci 00.0 on + device pci 02.0 on + device pci 00.0 on end # e1000 #1 + device pci 00.1 on end # e1000 #2 + end + end + device pci 00.1 on end + end + end + device pci 00.1 on end + device pci 00.3 on end + end + + device pci 03.0 on end + device pci 04.0 on end + device pci 05.0 on end + device pci 06.0 on end + device pci 07.0 on end + device pci 10.0 on end # FBD + device pci 10.1 on end # FBD + device pci 10.2 on end # FBD + device pci 11.0 on end # FBD reserved + device pci 13.0 on end # FBD reserved + device pci 15.0 on end # FBD + device pci 16.0 on end # FBD + + chip southbridge/intel/i3100 + register "pirq_a_d" = "0x0b0b0b0b" + register "pirq_e_h" = "0x80808080" + register "sata_ports_implemented" = "0x3f" + + device pci 1c.0 on end # PCIe bridge + device pci 1d.0 on end # USB UHCI + device pci 1d.1 on end # USB UHCI + device pci 1d.2 on end # USB UHCI + device pci 1d.3 on end # USB UHCI + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on + device pci 01.0 on + end + end + + device pci 1f.0 on # PCI-LPC bridge + subsystemid 0x15d9 0x2009 + chip superio/winbond/w83627hf + device pnp 2e.0 off end # FDC + device pnp 2e.1 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Serial Port 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + + device pnp 2e.3 off end + device pnp 2e.5 on # KBC + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + + end + + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # Game port / MIDI + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 on end # GPIO3 + device pnp 2e.a on end # ACPI + device pnp 2e.b off end # HWMON + end + end + device pci 1f.1 off end # IDE + device pci 1f.2 on end # SATA + device pci 1f.3 off end # SMBUS + + end + end +end diff --git a/src/mainboard/supermicro/x7db8/irq_tables.c b/src/mainboard/supermicro/x7db8/irq_tables.c new file mode 100644 index 0000000..84f456a --- /dev/null +++ b/src/mainboard/supermicro/x7db8/irq_tables.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x1f << 3) | 0x0, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x2670, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x1c << 3) | 0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1c << 3) | 0x1, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1c << 3) | 0x2, {{0x00, 0x0000}, {0x00, 0x0000}, {0x62, 0x1ef8}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1c << 3) | 0x3, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x63, 0x1ef8}}, 0, 0}, + {0x00, (0x1d << 3) | 0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1d << 3) | 0x1, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1d << 3) | 0x2, {{0x00, 0x0000}, {0x00, 0x0000}, {0x62, 0x1ef8}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1d << 3) | 0x3, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x63, 0x1ef8}}, 0, 0}, + {0x00, (0x1d << 3) | 0x7, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1f << 3) | 0x1, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1f << 3) | 0x2, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} diff --git a/src/mainboard/supermicro/x7db8/mainboard.c b/src/mainboard/supermicro/x7db8/mainboard.c new file mode 100644 index 0000000..27a26f9 --- /dev/null +++ b/src/mainboard/supermicro/x7db8/mainboard.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/io.h> +#include <boot/tables.h> +#include <delay.h> +#include <arch/coreboot_tables.h> +#include "chip.h" +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <arch/io.h> + +static void mainboard_enable(device_t dev) +{ +} + +struct chip_operations mainboard_ops = { + CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER) + .enable_dev = mainboard_enable, +}; + diff --git a/src/mainboard/supermicro/x7db8/mptable.c b/src/mainboard/supermicro/x7db8/mptable.c new file mode 100644 index 0000000..d0ddada --- /dev/null +++ b/src/mainboard/supermicro/x7db8/mptable.c @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/pci.h> +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <arch/ioapic.h> +#include <string.h> +#include <stdint.h> + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int isa_bus; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + + smp_write_processors(mc); + + mptable_write_buses(mc, NULL, &isa_bus); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, 8, 0x20, IO_APIC_ADDR); + smp_write_ioapic(mc, 9, 0x20, IO_APIC_ADDR + 0x80000); + + /* Legacy Interrupts */ + mptable_add_isa_interrupts(mc, isa_bus, 0x8, 0); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x00 << 2), 0x08, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x02 << 2), 0x08, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x03 << 2), 0x08, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x04 << 2), 0x08, 0x10); + + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x02, (0x02 << 2), 0x08, 0x10); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1b << 2), 0x08, 0x11); /* HD Audio 0:1b.0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2), 0x08, 0x14); /* PCIe 0:1c.0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x01, 0x08, 0x15); /* PCIe 0:1c.1 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x02, 0x08, 0x16); /* PCIe 0:1c.2 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x03, 0x08, 0x17); /* PCIe 0:1c.3 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) , 0x08, 0x10); /* USB 0:1d.0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x01, 0x08, 0x11); /* USB 0:1d.1 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x02, 0x08, 0x12); /* USB 0:1d.2 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x03, 0x08, 0x13); /* USB 0:1d.3 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2), 0x08, 0x11); /* SATA 0:1f.2 */ + + /* e1000 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x07, (0x00 << 2) | 0x00, 0x08, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x07, (0x00 << 2) | 0x01, 0x08, 0x13); + + /* SCSI on board */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x04, (0x02 << 2) | 0x00, 0x08, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x04, (0x02 << 2) | 0x01, 0x08, 0x11); + /* SCSI add on */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x08, (0x01 << 2) | 0x00, 0x09, 0x00); + + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_HIGH, isa_bus, 0x00, MP_APIC_ALL, 0x00); + smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x00, MP_APIC_ALL, 0x01); + + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/supermicro/x7db8/romstage.c b/src/mainboard/supermicro/x7db8/romstage.c new file mode 100644 index 0000000..26390ad --- /dev/null +++ b/src/mainboard/supermicro/x7db8/romstage.c @@ -0,0 +1,155 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <lib.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include <superio/winbond/w83627hf/early_serial.c> +#include <northbridge/intel/i5000/raminit.h> +#include "northbridge/intel/i3100/i3100.h" +#include "southbridge/intel/i3100/i3100.h" +#include <southbridge/intel/i3100/early_smbus.c> + +#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0) +#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) + +#define RCBA_RPC 0x0224 /* 32 bit */ +#define RCBA_HPTC 0x3404 /* 32 bit */ +#define RCBA_GCS 0x3410 /* 32 bit */ +#define RCBA_FD 0x3418 /* 32 bit */ + +static void early_config(void) +{ + u32 gcs, rpc, fd; + + /* Enable RCBA */ + pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, DEFAULT_RCBA | 1); + + /* Disable watchdog */ + gcs = read32(DEFAULT_RCBA + RCBA_GCS); + gcs |= (1 << 5); /* No reset */ + write32(DEFAULT_RCBA + RCBA_GCS, gcs); + + /* Configure PCIe port B as 4x */ + rpc = read32(DEFAULT_RCBA + RCBA_RPC); + rpc |= (3 << 0); + write32(DEFAULT_RCBA + RCBA_RPC, rpc); + + /* Disable Modem, Audio, PCIe ports 2/3/4 */ + fd = read32(DEFAULT_RCBA + RCBA_FD); + fd |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 6) | (1 << 5); + write32(DEFAULT_RCBA + RCBA_FD, fd); + + /* Enable HPET */ + write32(DEFAULT_RCBA + RCBA_HPTC, (1 << 7)); + + /* Setup sata mode */ + pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, 0x40); +} + +#define DEFAULT_GPIOBASE 0x1180 +static void setup_gpio(void) +{ + pci_write_config32(PCI_DEV(0, 31, 0), 0x48, DEFAULT_GPIOBASE | 1); + pci_write_config8(PCI_DEV(0, 31, 0), 0x4c, (1 << 4)); + + outl(0xff0c79cf, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xe700ffff, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0x65b70000, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + outl(0x0000718a, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x00000106, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ + outl(0x00000301, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ + outl(0x00030301, DEFAULT_GPIOBASE + 0x38); /* GPIO_LVL2 */ +} + +static void i5000_lpc_config(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); +} + +int mainboard_set_fbd_clock(int speed) +{ + switch(speed) { + case 533: + smbus_write_byte(0x6f, 0x80, 0x21); + return 0; + case 667: + smbus_write_byte(0x6f, 0x80, 0x23); + return 0; + default: + printk(BIOS_ERR, "Invalid clock: %dMHz\n", speed); + die(""); + return -1; + } +} + +void main(unsigned long bist) +{ + if (bist == 0) + enable_lapic(); + + i5000_lpc_config(); + + w83627hf_enable_serial(PNP_DEV(0x2e, 2), 0x3f8); + + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + early_config(); + + /* Prevent the TCO timer from rebooting us */ + i3100_halt_tco_timer(); + + setup_gpio(); + + enable_smbus(); + + /* setup PCIe MMCONF base address */ + pci_write_config32(PCI_DEV(0, 16, 0), 0x64, + CONFIG_MMCONF_BASE_ADDRESS >> 16); + + outb(0x07, 0x11b8); + + /* These are smbus write captured with serialice. They + seem to setup the clock generator */ + + smbus_write_byte(0x6f, 0x88, 0x1f); + smbus_write_byte(0x6f, 0x81, 0xff); + smbus_write_byte(0x6f, 0x82, 0xff); + smbus_write_byte(0x6f, 0x80, 0x23); + + outb(0x03, 0x11b8); + outb(0x01, 0x11b8); + + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, DEFAULT_RCBA | 1); + i5000_fbdimm_init(); + smbus_write_byte(0x69, 0x01, 0x01); +}

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coreboot June 2012