coreboot June 2012

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Patch set updated for coreboot: 5ca8014 superiotool: Add support for git-based version number
by Guenter Roeck 29 Jun '12

29 Jun '12

Guenter Roeck (linux(a)roeck-us.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1151 -gerrit commit 5ca8014b8aa506b31dca23c5c3291d4b20bb0bd9 Author: Guenter Roeck <linux(a)roeck-us.net> Date: Fri Jun 29 12:25:46 2012 -0700 superiotool: Add support for git-based version number The superiotool Makefile extracts a version number from SVN. This does not work well with a git repository, and results in an empty version number. Expand it to use the git version number (using git describe) if the repository is not a svn repository. Change-Id: Idf92c02753b28ef5bcdd3b6df4a08d79ae974434 Signed-off-by: Guenter Roeck <linux(a)roeck-us.net> --- util/superiotool/Makefile | 7 ++++++- 1 files changed, 6 insertions(+), 1 deletions(-) diff --git a/util/superiotool/Makefile b/util/superiotool/Makefile index e7d2f63..e141638 100644 --- a/util/superiotool/Makefile +++ b/util/superiotool/Makefile @@ -26,8 +26,13 @@ PREFIX = /usr/local # Set the superiotool version string from the highest revision number # of the checked out superiotool files. + +ifneq ($(shell svnversion -cn .), exported) SVNDEF := -D'SUPERIOTOOL_VERSION="$(shell svnversion -cn . \ - | sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/")"' + | sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/")"' +else +SVNDEF := -D'SUPERIOTOOL_VERSION="$(shell git describe 2>/dev/null)"' +endif CFLAGS += -O2 -Wall -Wstrict-prototypes -Wundef -Wstrict-aliasing \ -Werror-implicit-function-declaration -ansi -pedantic $(SVNDEF)

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Patch merged into coreboot/master: ba08fd1 libpayload: OHCI driver correct PCI BAR reading
by gerrit＠coreboot.org 29 Jun '12

29 Jun '12

the following patch was just integrated into master: commit ba08fd1e1d823ad64c37d7e3d50a796ffbf81b9d Author: Anton Kochkov <anton.kochkov(a)gmail.com> Date: Wed Jun 27 07:16:03 2012 +0400 libpayload: OHCI driver correct PCI BAR reading Correct registers base (PCI BAR) reading to be more specification friendly. Registers base only in [31-12] bits, all other proposed to be 0 but that not true for some motherboards. So adding mask to use only valid bits. Change-Id: I2e9a4997e016dab812ccfe654e966bc91d42a625 Signed-off-by: Anton Kochkov <anton.kochkov(a)gmail.com> See http://review.coreboot.org/1143 for details. -gerrit

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Patch merged into coreboot/master: 0a2af45 libpayload: use correct types in UHCI driver
by gerrit＠coreboot.org 29 Jun '12

29 Jun '12

the following patch was just integrated into master: commit 0a2af45778eb373d2e819b0c3c46e284265813ac Author: Anton Kochkov <anton.kochkov(a)gmail.com> Date: Thu Jun 28 08:19:41 2012 +0400 libpayload: use correct types in UHCI driver As we using 16-bit reading and writing in UHCI drive, so all variables related to that must be 16-bit too. Change-Id: Ib1abb03d054c167512e21f24f3c3da688c7fd01f Signed-off-by: Anton Kochkov <anton.kochkov(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Jun 29 22:12:02 2012, giving +2 See http://review.coreboot.org/1144 for details. -gerrit

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New patch to review for coreboot: 8f09719 superiotool: Add support for git-based version number
by Guenter Roeck 29 Jun '12

29 Jun '12

Guenter Roeck (linux(a)roeck-us.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1151 -gerrit commit 8f09719f1a868c59b09e877ba40684a80836949b Author: Guenter Roeck <linux(a)roeck-us.net> Date: Fri Jun 29 12:25:46 2012 -0700 superiotool: Add support for git-based version number The superiotool Makefile extracts a version number from SVN. This does not work well with a git repository, and results in an empty version number. Expand it to use the git version number (using git describe) if the repository is not a svn repository. Change-Id: Idf92c02753b28ef5bcdd3b6df4a08d79ae974434 Signed-off-by: Guenter Roeck <linux(a)roeck-us.net> --- util/superiotool/Makefile | 7 ++++++- 1 files changed, 6 insertions(+), 1 deletions(-) diff --git a/util/superiotool/Makefile b/util/superiotool/Makefile index e7d2f63..e141638 100644 --- a/util/superiotool/Makefile +++ b/util/superiotool/Makefile @@ -26,8 +26,13 @@ PREFIX = /usr/local # Set the superiotool version string from the highest revision number # of the checked out superiotool files. + +ifneq ($(shell svnversion -cn .), exported) SVNDEF := -D'SUPERIOTOOL_VERSION="$(shell svnversion -cn . \ - | sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/")"' + | sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/")"' +else +SVNDEF := -D'SUPERIOTOOL_VERSION="$(shell git describe 2>/dev/null)"' +endif CFLAGS += -O2 -Wall -Wstrict-prototypes -Wundef -Wstrict-aliasing \ -Werror-implicit-function-declaration -ansi -pedantic $(SVNDEF)

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New patch to review for coreboot: 2963933 superiotool: Dump data registers for Nuvoton chips
by Guenter Roeck 29 Jun '12

29 Jun '12

Guenter Roeck (linux(a)roeck-us.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1150 -gerrit commit 29639337304a58d02080535301d13e8149b93e76 Author: Guenter Roeck <linux(a)roeck-us.net> Date: Fri Jun 29 12:24:57 2012 -0700 superiotool: Dump data registers for Nuvoton chips Add support to dump all data registers for Nuvoton chips (NCT6775F, NCT6776F, and NCT6779D). Register contents will be dumped if the -e option is provided on the command line. Change-Id: I2b425b48c1f28a10ff3c1ca1d7f21c501eff74ad Signed-off-by: Guenter Roeck <linux(a)roeck-us.net> --- util/superiotool/nuvoton.c | 27 ++++++++++++++++++++++++++- 1 files changed, 26 insertions(+), 1 deletions(-) diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c index 46b8c2a..2adb90a 100644 --- a/util/superiotool/nuvoton.c +++ b/util/superiotool/nuvoton.c @@ -476,12 +476,16 @@ void probe_idregs_nuvoton(uint16_t port) uint8_t sid, srid; uint16_t chip_id = 0; uint8_t chip_rev = 0; + uint16_t iobase = 0; + int i; /* Probe for the 16bit IDs first to avoid collisions */ probing_for("Nuvoton", "", port); enter_conf_mode_winbond_fintek_ite_8787(port); chip_id = (regval(port, DEVICE_ID_REG) << 8) | regval(port, DEVICE_ID_REG + 1); + regwrite(port, LDN_SEL, 0x0b); + iobase = (regval(port, 0x60) << 8) | (regval(port, 0x61) & ~7); exit_conf_mode_winbond_fintek_ite_8787(port); @@ -492,7 +496,7 @@ void probe_idregs_nuvoton(uint16_t port) enter_conf_mode_winbond_fintek_ite_8787(port); dump_superio("Nuvoton", reg_table, port, chip_id, LDN_SEL); exit_conf_mode_winbond_fintek_ite_8787(port); - return; + goto extra; } if (verbose) @@ -524,6 +528,27 @@ void probe_idregs_nuvoton(uint16_t port) get_superio_name(reg_table, sid), chip_id, chip_rev, port); chip_found = 1; dump_superio("Nuvoton", reg_table, port, sid, LDN_SEL); + +extra: + if (extra_dump && iobase) { + switch (chip_id & 0xfff0) { + case 0xb470: /* NCT6775F */ + for (i = 0; i < 7; i++) + dump_data(iobase + 5, i); + dump_data(iobase + 5, 0xa); + dump_data(iobase + 5, 0xc); + dump_data(iobase + 5, 0xd); + break; + case 0xc330: /* NCT6776F */ + for (i = 0; i < 8; i++) + dump_data(iobase + 5, i); + break; + case 0xc560: /* NCT6779D */ + for (i = 0; i < 10; i++) + dump_data(iobase + 5, i); + break; + } + } } void print_nuvoton_chips(void)

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New patch to review for coreboot: 32eba63 superiotool: Add support for function to dump superio chip data registers
by Guenter Roeck 29 Jun '12

29 Jun '12

Guenter Roeck (linux(a)roeck-us.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1149 -gerrit commit 32eba63c34a2777b1b5f6147e8d1323b75e4adf6 Author: Guenter Roeck <linux(a)roeck-us.net> Date: Fri Jun 29 12:23:50 2012 -0700 superiotool: Add support for function to dump superio chip data registers Add new function dump_data() to dump a bank of superio data registers. Change-Id: I13a58d87c14d319cfcdea1ec1d54c2b110d90f9f Signed-off-by: Guenter Roeck <linux(a)roeck-us.net> --- util/superiotool/superiotool.c | 29 +++++++++++++++++++++++++++++ util/superiotool/superiotool.h | 1 + 2 files changed, 30 insertions(+), 0 deletions(-) diff --git a/util/superiotool/superiotool.c b/util/superiotool/superiotool.c index 293aaa6..538aa09 100644 --- a/util/superiotool/superiotool.c +++ b/util/superiotool/superiotool.c @@ -34,6 +34,18 @@ int dump = 0, verbose = 0, extra_dump = 0; /* Global flag which indicates whether a chip was detected at all. */ int chip_found = 0; +static void set_bank(uint16_t port, uint8_t bank) +{ + OUTB(0x4E, port); + OUTB(bank, port + 1); +} + +static uint8_t datareg(uint16_t port, uint8_t reg) +{ + OUTB(reg, port); + return INB(port + 1); +} + uint8_t regval(uint16_t port, uint8_t reg) { OUTB(reg, port); @@ -186,6 +198,23 @@ void dump_io(uint16_t iobase, uint16_t length) printf("\n"); } +void dump_data(uint16_t iobase, int bank) +{ + uint16_t i; + + printf("Bank %d:\n", bank); + printf(" "); + for (i = 0; i < 16; i++) + printf("%02x ", i); + set_bank(iobase, bank); + for (i = 0; i < 256; i++) { + if (i % 16 == 0) + printf("\n%02x: ", i / 16); + printf("%02x ", datareg(iobase, i)); + } + printf("\n"); +} + void probing_for(const char *vendor, const char *info, uint16_t port) { if (!verbose) diff --git a/util/superiotool/superiotool.h b/util/superiotool/superiotool.h index 94918b8..7a0b7f6 100644 --- a/util/superiotool/superiotool.h +++ b/util/superiotool/superiotool.h @@ -174,6 +174,7 @@ const char *get_superio_name(const struct superio_registers reg_table[], void dump_superio(const char *name, const struct superio_registers reg_table[], uint16_t port, uint16_t id, uint8_t ldn_sel); void dump_io(uint16_t iobase, uint16_t length); +void dump_data(uint16_t iobase, int bank); void probing_for(const char *vendor, const char *info, uint16_t port); void print_vendor_chips(const char *vendor, const struct superio_registers reg_table[]);

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Patch set updated for coreboot: 7fe1ebb Intel model_106cx: change CAR to model_6ex
by Kyösti Mälkki 28 Jun '12

28 Jun '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/642 -gerrit commit 7fe1ebb9b7fb93b8f46b9838c6555fb416f6991e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jun 28 21:50:43 2012 +0300 Intel model_106cx: change CAR to model_6ex Diff between model_106cx and model_6ex CAR codes suggests currently used model_106cx CAR is not optimal - destination RAM and source ROM of ramstage copy_and_run are only partly set cacheable. It appears variable MTRR setting for XIP cache is left enabled on model_106cx code, where it should have extended to cover all of Flash. Introduces untested functional change on boards: intel/d945gclf iwave/iWRainbowG6 Deletes file: model_106cx/cache_as_ram.inc Change-Id: I35229f8433927e83821e72e9d9a9fc8fb09c3f1d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/model_106cx/Makefile.inc | 2 +- src/cpu/intel/model_106cx/cache_as_ram.inc | 246 ---------------------------- 2 files changed, 1 insertions(+), 247 deletions(-) diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc index edcd01c..018febc 100644 --- a/src/cpu/intel/model_106cx/Makefile.inc +++ b/src/cpu/intel/model_106cx/Makefile.inc @@ -1,4 +1,4 @@ driver-y += model_106cx_init.c subdirs-y += ../../x86/name -cpu_incs += $(src)/cpu/intel/model_106cx/cache_as_ram.inc +cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc deleted file mode 100644 index c626cd8..0000000 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ /dev/null @@ -1,246 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <cpu/x86/stack.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/post_code.h> - -#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1) - -#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE -#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE - - /* Save the BIST result. */ - movl %eax, %ebp - -cache_as_ram: - post_code(0x20) - - /* Send INIT IPI to all excluding ourself. */ - movl $0x000C4500, %eax - movl $0xFEE00300, %esi - movl %eax, (%esi) - - /* Zero out all fixed range and variable range MTRRs. */ - movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) / 2), %edi - xorl %eax, %eax - xorl %edx, %edx -clear_mtrrs: - movw (%esi), %bx - movzx %bx, %ecx - wrmsr - add $2, %esi - dec %edi - jnz clear_mtrrs - - /* Configure the default memory type to uncacheable. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - andl $(~0x00000cff), %eax - wrmsr - - /* Set Cache-as-RAM base address. */ - movl $(MTRRphysBase_MSR(0)), %ecx - movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax - xorl %edx, %edx - wrmsr - - /* Set Cache-as-RAM mask. */ - movl $(MTRRphysMask_MSR(0)), %ecx - movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax - movl $CPU_PHYSMASK_HI, %edx - wrmsr - - /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $MTRRdefTypeEn, %eax - wrmsr - - /* Enable L2 cache. */ - movl $0x11e, %ecx - rdmsr - orl $(1 << 8), %eax - wrmsr - - /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax - andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax - invd - movl %eax, %cr0 - - /* Clear the cache memory reagion. */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx - // movl $0x23322332, %eax - xorl %eax, %eax - rep stosl - - /* Enable Cache-as-RAM mode by disabling cache. */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - -#if CONFIG_XIP_ROM_SIZE - /* Enable cache for our code in Flash because we do XIP here */ - movl $MTRRphysBase_MSR(1), %ecx - xorl %edx, %edx - /* - * IMPORTANT: The following calculation _must_ be done at runtime. See - * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html - */ - movl $copy_and_run, %eax - andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax - orl $MTRR_TYPE_WRBACK, %eax - wrmsr - - movl $MTRRphysMask_MSR(1), %ecx - movl $CPU_PHYSMASK_HI, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax - wrmsr -#endif /* CONFIG_XIP_ROM_SIZE */ - - /* Enable cache. */ - movl %cr0, %eax - andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax - movl %eax, %cr0 - - /* Set up the stack pointer. */ -#if CONFIG_USBDEBUG - /* Leave some space for the struct ehci_debug_info. */ - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax -#else - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax -#endif - movl %eax, %esp - - /* Restore the BIST result. */ - movl %ebp, %eax - movl %esp, %ebp - pushl %eax - - post_code(0x23) - - /* Call romstage.c main function. */ - call main - - post_code(0x2f) - - post_code(0x30) - - /* Disable cache. */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - - post_code(0x31) - - /* Disable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - andl $(~MTRRdefTypeEn), %eax - wrmsr - - post_code(0x31) - - invd - - post_code(0x33) - - /* Enable cache. */ - movl %cr0, %eax - andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax - movl %eax, %cr0 - - post_code(0x36) - - /* Disable cache. */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - - post_code(0x38) - - /* Enable Write Back and Speculative Reads for the first 1MB. */ - movl $MTRRphysBase_MSR(0), %ecx - movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax - xorl %edx, %edx - wrmsr - movl $MTRRphysMask_MSR(0), %ecx - movl $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax - movl $CPU_PHYSMASK_HI, %edx - wrmsr - - post_code(0x39) - - /* And enable cache again after setting MTRRs. */ - movl %cr0, %eax - andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax - movl %eax, %cr0 - - post_code(0x3a) - - /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $MTRRdefTypeEn, %eax - wrmsr - - post_code(0x3b) - - /* Invalidate the cache again. */ - invd - - post_code(0x3c) - - /* Clear boot_complete flag. */ - xorl %ebp, %ebp -__main: - post_code(POST_PREPARE_RAMSTAGE) - cld /* Clear direction flag. */ - - movl %ebp, %esi - - movl $ROMSTAGE_STACK, %esp - movl %esp, %ebp - pushl %esi - call copy_and_run - -.Lhlt: - post_code(POST_DEAD_CODE) - hlt - jmp .Lhlt - -mtrr_table: - /* Fixed MTRRs */ - .word 0x250, 0x258, 0x259 - .word 0x268, 0x269, 0x26A - .word 0x26B, 0x26C, 0x26D - .word 0x26E, 0x26F - /* Variable MTRRs */ - .word 0x200, 0x201, 0x202, 0x203 - .word 0x204, 0x205, 0x206, 0x207 - .word 0x208, 0x209, 0x20A, 0x20B - .word 0x20C, 0x20D, 0x20E, 0x20F -mtrr_table_end: -

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Patch set updated for coreboot: f0d584a Intel cpus: delete dead CAR code and whitespace fixes
by Kyösti Mälkki 28 Jun '12

28 Jun '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/640 -gerrit commit f0d584a489fa69bd8c49154132ec4742d7a74415 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jun 28 12:16:12 2012 +0300 Intel cpus: delete dead CAR code and whitespace fixes A diff from model_6fx to model_106cx suggests there is little CORE2 specific code that was once considered useful to have. In its current status however, sockets supporting model_6fx use model_6ex CAR init, so that specific code is actually never used. Deletes file: model_6fx/cache_as_ram.inc Change-Id: I6c0204446fa98207e31f91895e1cf30fde42382c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/model_106cx/cache_as_ram.inc | 14 +-- src/cpu/intel/model_6ex/cache_as_ram.inc | 16 +-- src/cpu/intel/model_6fx/cache_as_ram.inc | 272 ---------------------------- 3 files changed, 3 insertions(+), 299 deletions(-) diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc index 74d0a99..c626cd8 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ b/src/cpu/intel/model_106cx/cache_as_ram.inc @@ -83,7 +83,7 @@ clear_mtrrs: wrmsr /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax + movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0 @@ -164,18 +164,6 @@ clear_mtrrs: post_code(0x31) invd -#if 0 - xorl %eax, %eax - xorl %edx, %edx - movl $MTRRphysBase_MSR(0), %ecx - wrmsr - movl $MTRRphysMask_MSR(0), %ecx - wrmsr - movl $MTRRphysBase_MSR(1), %ecx - wrmsr - movl $MTRRphysMask_MSR(1), %ecx - wrmsr -#endif post_code(0x33) diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 6f13cd9..bdefb21 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -83,7 +83,7 @@ clear_mtrrs: wrmsr /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax + movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0 @@ -164,18 +164,6 @@ clear_mtrrs: post_code(0x31) invd -#if 0 - xorl %eax, %eax - xorl %edx, %edx - movl $MTRRphysBase_MSR(0), %ecx - wrmsr - movl $MTRRphysMask_MSR(0), %ecx - wrmsr - movl $MTRRphysBase_MSR(1), %ecx - wrmsr - movl $MTRRphysMask_MSR(1), %ecx - wrmsr -#endif post_code(0x33) @@ -193,7 +181,7 @@ clear_mtrrs: post_code(0x38) - /* Enable Write Back and Speculative Reads for the first 1MB. */ + /* Enable Write Back and Speculative Reads for low RAM. */ movl $MTRRphysBase_MSR(0), %ecx movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax xorl %edx, %edx diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc deleted file mode 100644 index d8d25a0..0000000 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ /dev/null @@ -1,272 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <cpu/x86/stack.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/post_code.h> - -#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1) - -#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE -#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE - - /* Save the BIST result. */ - movl %eax, %ebp - -cache_as_ram: - post_code(0x20) - - /* Send INIT IPI to all excluding ourself. */ - movl $0x000C4500, %eax - movl $0xFEE00300, %esi - movl %eax, (%esi) - - /* Disable prefetchers */ - movl $0x01a0, %ecx - rdmsr - orl $((1 << 9) | (1 << 19)), %eax - orl $((1 << 5) | (1 << 7)), %edx - wrmsr - - /* Zero out all fixed range and variable range MTRRs. */ - movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) / 2), %edi - xorl %eax, %eax - xorl %edx, %edx -clear_mtrrs: - movw (%esi), %bx - movzx %bx, %ecx - wrmsr - add $2, %esi - dec %edi - jnz clear_mtrrs - - /* Configure the default memory type to uncacheable. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - andl $(~0x00000cff), %eax - wrmsr - - /* Set Cache-as-RAM base address. */ - movl $(MTRRphysBase_MSR(0)), %ecx - movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax - xorl %edx, %edx - wrmsr - - /* Set Cache-as-RAM mask. */ - movl $(MTRRphysMask_MSR(0)), %ecx - movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax - movl $CPU_PHYSMASK_HI, %edx - wrmsr - - /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $MTRRdefTypeEn, %eax - wrmsr - - /* Enable L2 cache. */ - movl $0x11e, %ecx - rdmsr - orl $(1 << 8), %eax - wrmsr - - /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax - andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax - invd - movl %eax, %cr0 - - /* Clear the cache memory reagion. */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx - // movl $0x23322332, %eax - xorl %eax, %eax - rep stosl - - /* Enable Cache-as-RAM mode by disabling cache. */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - -#if CONFIG_XIP_ROM_SIZE - /* Enable cache for our code in Flash because we do XIP here */ - movl $MTRRphysBase_MSR(1), %ecx - xorl %edx, %edx - /* - * IMPORTANT: The following calculation _must_ be done at runtime. See - * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html - */ - movl $copy_and_run, %eax - andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax - orl $MTRR_TYPE_WRBACK, %eax - wrmsr - - movl $MTRRphysMask_MSR(1), %ecx - movl $CPU_PHYSMASK_HI, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax - wrmsr -#endif /* CONFIG_XIP_ROM_SIZE */ - - /* Enable cache. */ - movl %cr0, %eax - andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax - movl %eax, %cr0 - - /* Set up the stack pointer. */ -#if CONFIG_USBDEBUG - /* Leave some space for the struct ehci_debug_info. */ - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax -#else - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax -#endif - movl %eax, %esp - - /* Restore the BIST result. */ - movl %ebp, %eax - movl %esp, %ebp - pushl %eax - - post_code(0x23) - - /* Call romstage.c main function. */ - call main - - post_code(0x2f) - - post_code(0x30) - - /* Disable cache. */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - - post_code(0x31) - - /* Disable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - andl $(~MTRRdefTypeEn), %eax - wrmsr - - post_code(0x31) - - invd -#if 0 - xorl %eax, %eax - xorl %edx, %edx - movl $MTRRphysBase_MSR(0), %ecx - wrmsr - movl $MTRRphysMask_MSR(0), %ecx - wrmsr - movl $MTRRphysBase_MSR(1), %ecx - wrmsr - movl $MTRRphysMask_MSR(1), %ecx - wrmsr -#endif - - post_code(0x33) - - /* Enable cache. */ - movl %cr0, %eax - andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax - movl %eax, %cr0 - - post_code(0x36) - - /* Disable cache. */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - - post_code(0x38) - - /* Enable Write Back and Speculative Reads for the first 1MB. */ - movl $MTRRphysBase_MSR(0), %ecx - movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax - xorl %edx, %edx - wrmsr - movl $MTRRphysMask_MSR(0), %ecx - movl $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax - movl $CPU_PHYSMASK_HI, %edx - wrmsr - - post_code(0x39) - - /* And enable cache again after setting MTRRs. */ - movl %cr0, %eax - andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax - movl %eax, %cr0 - - post_code(0x3a) - - /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $MTRRdefTypeEn, %eax - wrmsr - - post_code(0x3b) - - /* Enable prefetchers */ - movl $0x01a0, %ecx - rdmsr - andl $~((1 << 9) | (1 << 19)), %eax - andl $~((1 << 5) | (1 << 7)), %edx - wrmsr - - /* Invalidate the cache again. */ - invd - - post_code(0x3c) - - /* Clear boot_complete flag. */ - xorl %ebp, %ebp -__main: - post_code(POST_PREPARE_RAMSTAGE) - cld /* Clear direction flag. */ - - movl %ebp, %esi - - movl $ROMSTAGE_STACK, %esp - movl %esp, %ebp - pushl %esi - call copy_and_run - -.Lhlt: - post_code(POST_DEAD_CODE) - hlt - jmp .Lhlt - -mtrr_table: - /* Fixed MTRRs */ - .word 0x250, 0x258, 0x259 - .word 0x268, 0x269, 0x26A - .word 0x26B, 0x26C, 0x26D - .word 0x26E, 0x26F - /* Variable MTRRs */ - .word 0x200, 0x201, 0x202, 0x203 - .word 0x204, 0x205, 0x206, 0x207 - .word 0x208, 0x209, 0x20A, 0x20B - .word 0x20C, 0x20D, 0x20E, 0x20F -mtrr_table_end: -

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Patch set updated for coreboot: 0ca1542 Intel cpus: use CPU_ADDR_BITS from Kconfig during CAR
by Kyösti Mälkki 28 Jun '12

28 Jun '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/639 -gerrit commit 0ca15429f24f01791c6e9b3a0c419e01b36e3a3e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jun 28 21:26:41 2012 +0300 Intel cpus: use CPU_ADDR_BITS from Kconfig during CAR Default CPU_ADDR_BITS is 36. For Atom (model_106cx) use 32. This model is known to fail execution-in-place (XIP) with the default 36. Pentium M should use 32, but doesn't even with this patch. Some Xeon and CORE(2) models should use 38 or 40. Change-Id: If604badcdc578c4f4bc7d30da2f61397ec0d754c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/model_106cx/Kconfig | 8 ++++++++ src/cpu/intel/model_106cx/cache_as_ram.inc | 3 +-- src/cpu/intel/model_206ax/cache_as_ram.inc | 3 +-- src/cpu/intel/model_6ex/cache_as_ram.inc | 3 +-- src/cpu/intel/model_6fx/cache_as_ram.inc | 3 +-- 5 files changed, 12 insertions(+), 8 deletions(-) diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index 09449cb..a08f85a 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -4,3 +4,11 @@ config CPU_INTEL_MODEL_106CX select SSE2 select UDELAY_LAPIC select AP_IN_SIPI_WAIT + +if CPU_INTEL_MODEL_106CX + +config CPU_ADDR_BITS + int + default 32 + +endif diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc index e74e24c..74d0a99 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ b/src/cpu/intel/model_106cx/cache_as_ram.inc @@ -23,8 +23,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> -#define CPU_MAXPHYADDR 32 -#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) +#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1) #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index 7d402e4..33246ff 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -32,8 +32,7 @@ #define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES) #define CACHE_MRC_MASK (~CACHE_MRC_BYTES) -#define CPU_MAXPHYSADDR 36 -#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYSADDR - 32) - 1) +#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1) #define NoEvictMod_MSR 0x2e0 diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 92337c8..6f13cd9 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -23,8 +23,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> -#define CPU_MAXPHYADDR 36 -#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) +#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1) #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc index 61feb1d..d8d25a0 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ b/src/cpu/intel/model_6fx/cache_as_ram.inc @@ -23,8 +23,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> -#define CPU_MAXPHYADDR 36 -#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) +#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1) #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE

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New patch to review for coreboot: 688f18b Enable ROM cache for payload decompression on all boards
by Kyösti Mälkki 28 Jun '12

28 Jun '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1147 -gerrit commit 688f18b304a53e97b83076602a67476e10e1add4 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jun 28 21:41:05 2012 +0300 Enable ROM cache for payload decompression on all boards The static size of 8 MB ChromeOS defines for SPI flash would extend over write-protection control MMIO of older LPC/FWH flash, so use a configurable region size instead. Change-Id: Ife6d11a29794bdbf0463911e589e86102e9b897d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/x86/Kconfig | 4 ---- src/cpu/x86/mtrr/mtrr.c | 6 ++++-- src/mainboard/samsung/lumpy/Kconfig | 4 ++++ src/mainboard/samsung/stumpy/Kconfig | 4 ++++ src/vendorcode/google/chromeos/Kconfig | 1 - 5 files changed, 12 insertions(+), 7 deletions(-) diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 0eaee2e..9ac7365 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -40,10 +40,6 @@ config LOGICAL_CPUS bool default y -config CACHE_ROM - bool - default n - config SMM_TSEG bool default n diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index f8b2591..198edb4 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -496,12 +496,14 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits); } -#if CONFIG_CACHE_ROM +#if CONFIG_CACHE_ROM_SIZE +#define CACHE_ROM_BASEK ((1<<22) - (CONFIG_CACHE_ROM_SIZE>>10)) /* Enable Caching and speculative Reads for the * complete ROM now that we actually have RAM. */ if (boot_cpu() && (acpi_slp_type != 3)) { - set_var_mtrr(total_mtrrs - 1, (4096 - 8)*1024, 8 * 1024, + set_var_mtrr(total_mtrrs - 1, CACHE_ROM_BASEK, + CONFIG_CACHE_ROM_SIZE>>10, MTRR_TYPE_WRPROT, address_bits); } #endif diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index 0835012..dd1e8d3 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -40,6 +40,10 @@ config MAX_CPUS int default 8 +config CACHE_ROM_SIZE + hex + default 0x800000 + config VGA_BIOS_FILE string default "pci8086,0106.rom" diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index 18094cf..ff7aaa2 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -39,6 +39,10 @@ config MAX_CPUS int default 8 +config CACHE_ROM_SIZE + hex + default 0x800000 + config VGA_BIOS_FILE string default "pci8086,0106.rom" diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 179bbb1..f098912 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -20,7 +20,6 @@ config CHROMEOS bool default n select TPM - select CACHE_ROM help Enable ChromeOS specific features like the GPIO sub table in the coreboot table. NOTE: Enabling this option on an unsupported

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coreboot June 2012