coreboot December 2012

coreboot@coreboot.org

30 participants
341 discussions

Patch merged into coreboot/master: b01097e USBDEBUG: Enable the EHCI in AMD Southbridge
by gerrit＠coreboot.org 28 Dec '12

28 Dec '12

the following patch was just integrated into master: commit b01097e0fe03b7dc81eadd898ff380b57f291852 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Fri Dec 14 15:58:15 2012 +0800 USBDEBUG: Enable the EHCI in AMD Southbridge Since SB800, USB2.0 debug port is dev 0x12, func 2. Change-Id: Ie0e33cb2f0833b0baeef81323e1a0634242fbe55 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> Reviewed-on: http://review.coreboot.org/1880 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Anton Kochkov <anton.kochkov(a)gmail.com> Reviewed-by: Marc Jones <marcj303(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Dec 14 07:31:47 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Dec 14 22:11:11 2012, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Fri Dec 28 21:16:42 2012, giving +2 See http://review.coreboot.org/1880 for details. -gerrit

1 0

Patch set updated for coreboot: dcee624 move iRAM config variable to exynos5250 Kconfig
by David Hendricks 28 Dec '12

28 Dec '12

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2077 -gerrit commit dcee624f226eebaa6e2f2d4391755ad6ce2d1bc5 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Dec 27 13:50:32 2012 -0800 move iRAM config variable to exynos5250 Kconfig Since these don't seem very generic and depend on the BL1, let's move them to the CPU-specific Kconfig. Change-Id: I33059b7db30d35a1853918a580f312e50a3499fa Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/Kconfig | 26 -------------------------- src/cpu/samsung/exynos5250/Kconfig | 20 ++++++++++++++++++++ 2 files changed, 20 insertions(+), 26 deletions(-) diff --git a/src/cpu/samsung/Kconfig b/src/cpu/samsung/Kconfig index 3a14ab8..4a09ca3 100644 --- a/src/cpu/samsung/Kconfig +++ b/src/cpu/samsung/Kconfig @@ -15,32 +15,6 @@ config SKIP_LOWLEVEL_INIT Certain functions (ie PLL init) and processor features may already be handled by masked ROM code. -config IRAM_BOTTOM - hex - default 0x02020000 - -# FIXME(dhendrix): 0x02050000 was in the u-boot sources, but the docs say the -# iRAM range is 0x0202_0000 - 0x0207_7fff (352KB). -#config IRAM_TOP -# hex -# default 0x02050000 -config IRAM_TOP - hex - default 0x02077fff - -config SYS_INIT_SP_ADDR - hex - default 0x0204F800 - -config IRAM_STACK - hex - default SYS_INIT_SP_ADDR - -# FIXME(dhendrix): what should this really be? -config XIP_ROM_SIZE - hex - default 0x20000 - if CPU_SAMSUNG_EXYNOS5 source src/cpu/samsung/exynos5250/Kconfig endif diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index 8d4ba2d..c2d9b9f 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -26,3 +26,23 @@ config RAMBASE config RAMTOP hex default 0x40100000 + +config IRAM_BOTTOM + hex + default 0x02020000 + +config IRAM_TOP + hex + default 0x02077fff + +config SYS_INIT_SP_ADDR + hex + default 0x0204F800 + +config IRAM_STACK + hex + default SYS_INIT_SP_ADDR + +config XIP_ROM_SIZE + hex "ROM stage (BL2) size" + default 0x20000

1 0

Meeting during 29C3 in Hamburg on 28/12 at 19:30 in CCH lobby
by Peter Stuge 27 Dec '12

27 Dec '12

Hi everyone! Several coreboot project participants and followers will be in Hamburg during this year's Chaos Communication Congress, also known as 29C3, so let's go for dinner and a nice chat again, on the evening of December 28th. Let's meet near the CCH entrance as a starting point. There are not really many restaurants just outside the CCH, but downtown Hamburg is only a few hundred meters away from the venue, so I'm sure that we will find something. To repeat a tradition for coreboot in Hamburg we could visit Vapiano, there is one near Axel-Springer-Platz on the other side of Gänsemarkt seen from the CCH, about 1km on foot, but there are also plenty of other choices along the way. If I don't already know that you will be coming along and if you want to make sure that we don't leave the CCH without you by mistake then you can of course drop me an email. Just to be clear there is no reservation, we'll just go ad-hoc to some restaurant. Feel free to come along without sending me anything. Feel free to join us if you are so far only curious about coreboot but have never even used it. I'm looking forward to meeting you in Hamburg - see you there! //Peter

1 1

Patch set updated for coreboot: e3055bb import i2c header from u-boot
by David Hendricks 27 Dec '12

27 Dec '12

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2079 -gerrit commit e3055bb7231e202596f1d2f074d31d6b7c2a202e Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Dec 27 14:15:51 2012 -0800 import i2c header from u-boot This just imports a header. We may wish to modify the i2c interface and/or unify it with the smbus interface we currently have. Change-Id: I314f3aef62be936456c6c3e164a3db2c473b8792 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/include/device/i2c.h | 279 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 279 insertions(+) diff --git a/src/include/device/i2c.h b/src/include/device/i2c.h new file mode 100644 index 0000000..f1275e3 --- /dev/null +++ b/src/include/device/i2c.h @@ -0,0 +1,279 @@ +/* + * (C) Copyright 2001 + * Gerald Van Baren, Custom IDEAS, vanbaren(a)cideas.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * The original I2C interface was + * (C) 2000 by Paolo Scaffardi (arsenio(a)tin.it) + * AIRVENT SAM s.p.a - RIMINI(ITALY) + * but has been changed substantially. + */ + +#ifndef _I2C_H_ +#define _I2C_H_ + +/* + * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING + * + * The implementation MUST NOT use static or global variables if the + * I2C routines are used to read SDRAM configuration information + * because this is done before the memories are initialized. Limited + * use of stack-based variables are OK (the initial stack size is + * limited). + * + * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING + */ + +/* + * Configuration items. + */ +#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */ + +#ifdef CONFIG_I2C_MULTI_BUS +#define MAX_I2C_BUS 2 +#define I2C_MULTI_BUS 1 +#else +#define MAX_I2C_BUS 1 +#define I2C_MULTI_BUS 0 +#endif + +#if !defined(CONFIG_SYS_MAX_I2C_BUS) +#define CONFIG_SYS_MAX_I2C_BUS MAX_I2C_BUS +#endif + +/* define the I2C bus number for RTC and DTT if not already done */ +#if !defined(CONFIG_SYS_RTC_BUS_NUM) +#define CONFIG_SYS_RTC_BUS_NUM 0 +#endif +#if !defined(CONFIG_SYS_DTT_BUS_NUM) +#define CONFIG_SYS_DTT_BUS_NUM 0 +#endif +#if !defined(CONFIG_SYS_SPD_BUS_NUM) +#define CONFIG_SYS_SPD_BUS_NUM 0 +#endif + +#ifndef I2C_SOFT_DECLARATIONS +# if defined(CONFIG_MPC8260) +# define I2C_SOFT_DECLARATIONS volatile ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT); +# elif defined(CONFIG_8xx) +# define I2C_SOFT_DECLARATIONS volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + +# elif (defined(CONFIG_AT91RM9200) || \ + defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \ + defined(CONFIG_AT91SAM9263)) && !defined(CONFIG_AT91_LEGACY) +# define I2C_SOFT_DECLARATIONS at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; +# else +# define I2C_SOFT_DECLARATIONS +# endif +#endif + +#ifdef CONFIG_8xx +/* Set default value for the I2C bus speed on 8xx. In the + * future, we'll define these in all 8xx board config files. + */ +#ifndef CONFIG_SYS_I2C_SPEED +#define CONFIG_SYS_I2C_SPEED 50000 +#endif +#endif + +/* + * Many boards/controllers/drivers don't support an I2C slave interface so + * provide a default slave address for them for use in common code. A real + * value for CONFIG_SYS_I2C_SLAVE should be defined for any board which does + * support a slave interface. + */ +#ifndef CONFIG_SYS_I2C_SLAVE +#define CONFIG_SYS_I2C_SLAVE 0xfe +#endif + +/* + * Initialization, must be called once on start up, may be called + * repeatedly to change the speed and slave addresses. + */ +void i2c_init(int speed, int slaveaddr); +void i2c_init_board(void); +#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT +void i2c_board_late_init(void); +#endif + +#if defined(CONFIG_I2C_MUX) + +typedef struct _mux { + uchar chip; + uchar channel; + char *name; + struct _mux *next; +} I2C_MUX; + +typedef struct _mux_device { + int busid; + I2C_MUX *mux; /* List of muxes, to reach the device */ + struct _mux_device *next; +} I2C_MUX_DEVICE; + +I2C_MUX_DEVICE *i2c_mux_search_device(int id); +I2C_MUX_DEVICE *i2c_mux_ident_muxstring (uchar *buf); +int i2x_mux_select_mux(int bus); +int i2c_mux_ident_muxstring_f (uchar *buf); +#endif + +/* + * Probe the given I2C chip address. Returns 0 if a chip responded, + * not 0 on failure. + */ +int i2c_probe(uchar chip); + +/* + * Read/Write interface: + * chip: I2C chip address, range 0..127 + * addr: Memory (register) address within the chip + * alen: Number of bytes to use for addr (typically 1, 2 for larger + * memories, 0 for register type devices with only one + * register) + * buffer: Where to read/write the data + * len: How many bytes to read/write + * + * Returns: 0 on success, not 0 on failure + */ +int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len); +int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len); + +/* + * Utility routines to read/write registers. + */ +static inline u8 i2c_reg_read(u8 addr, u8 reg) +{ + u8 buf; + +#ifdef CONFIG_8xx + /* MPC8xx needs this. Maybe one day we can get rid of it. */ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif + +#ifdef DEBUG + printf("%s: addr=0x%02x, reg=0x%02x\n", __func__, addr, reg); +#endif + + i2c_read(addr, reg, 1, &buf, 1); + + return buf; +} + +static inline void i2c_reg_write(u8 addr, u8 reg, u8 val) +{ +#ifdef CONFIG_8xx + /* MPC8xx needs this. Maybe one day we can get rid of it. */ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif + +#ifdef DEBUG + printf("%s: addr=0x%02x, reg=0x%02x, val=0x%02x\n", + __func__, addr, reg, val); +#endif + + i2c_write(addr, reg, 1, &val, 1); +} + +/* + * Functions for setting the current I2C bus and its speed + */ + +/* + * i2c_set_bus_num: + * + * Change the active I2C bus. Subsequent read/write calls will + * go to this one. + * + * bus - bus index, zero based + * + * Returns: 0 on success, not 0 on failure + * + */ +int i2c_set_bus_num(unsigned int bus); + +/* + * i2c_get_bus_num: + * + * Returns index of currently active I2C bus. Zero-based. + */ + +unsigned int i2c_get_bus_num(void); + +/* + * i2c_set_bus_speed: + * + * Change the speed of the active I2C bus + * + * speed - bus speed in Hz + * + * Returns: 0 on success, not 0 on failure + * + */ +int i2c_set_bus_speed(unsigned int); + +/* + * i2c_get_bus_speed: + * + * Returns speed of currently active I2C bus in Hz + */ + +unsigned int i2c_get_bus_speed(void); + +/* NOTE: These two functions MUST be always_inline to avoid code growth! */ +static inline unsigned int I2C_GET_BUS(void) __attribute__((always_inline)); +static inline unsigned int I2C_GET_BUS(void) +{ + return I2C_MULTI_BUS ? i2c_get_bus_num() : 0; +} + +static inline void I2C_SET_BUS(unsigned int bus) __attribute__((always_inline)); +static inline void I2C_SET_BUS(unsigned int bus) +{ + if (I2C_MULTI_BUS) + i2c_set_bus_num(bus); +} + +/* + * Set an early register base for a given i2c peripheral. + * This is used to access a single i2c bus early on in the boot sequence. + * + * @param base: The base address of the i2c peripheral's register map + */ +void i2c_set_early_reg(unsigned int base); + +/** + * Find the I2C bus number by given a FDT I2C node. + * + * @param blob Device tree blbo + * @param node FDT I2C node to find + * @return the number of I2C bus (zero based), or -1 on error + */ +int i2c_get_bus_num_fdt(const void *blob, int node); + +/** + * Reset the I2C bus represented by the given a FDT I2C node. + * + * @param blob Device tree blbo + * @param node FDT I2C node to find + * @return 0 if port was reset, -1 if not found + */ +int i2c_reset_port_fdt(const void *blob, int node); + +#endif /* _I2C_H_ */

1 0

Patch set updated for coreboot: eb45ccb Simplify romstage.ld for armv7
by David Hendricks 27 Dec '12

27 Dec '12

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2041 -gerrit commit eb45ccbeba711e7be5146f080ffa304f12d5012f Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Dec 17 20:41:32 2012 -0800 Simplify romstage.ld for armv7 This is still a work-in-progress, but it seems to work better than before and is less complicated... Change-Id: I6f730d017391f9ec4401cdfd34931c869df10a9e Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/romstage.ld | 62 +++++++++------------------------------------- 1 file changed, 12 insertions(+), 50 deletions(-) diff --git a/src/arch/armv7/romstage.ld b/src/arch/armv7/romstage.ld index 0a2f7f2..d2b69d7 100644 --- a/src/arch/armv7/romstage.ld +++ b/src/arch/armv7/romstage.ld @@ -29,7 +29,7 @@ * FIXME 2: Somehow linker didn't like CONFIG_SPL_MAX_SIZE and CONFIG_SPL_TEXT_BASE... */ /* MEMORY { .sram : ORIGIN = 0x02023400, LENGTH = 0x3800 } */ -MEMORY { .sram : ORIGIN = 0x02023400, LENGTH = 0x10000 } +/*MEMORY { .sram : ORIGIN = 0x02023400, LENGTH = 0x10000 }*/ /* We use ELF as output format. So that we can debug the code in some form. */ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") @@ -39,58 +39,20 @@ ENTRY(_start) SECTIONS { - . = ROMSTAGE_BASE; + /* FIXME: replace this with CPU-specific Kconfig variable */ + . = 0x02023400; /* Exynos5 */ - /* - .rom . : { + .romtext . : { _rom = .; - *(.rom.text); - *(.rom.data); + *(.text); + } + + .romdata . : { *(.rodata); - *(.rodata.*); - *(.rom.data.*); - . = ALIGN(16); + *(.machine_param); + . = ALIGN(8); _erom = .; } - */ - - /* First we place the code and read only data (typically const declared). - * This could theoretically be placed in rom. - */ - .text : { - _text = .; - *(.text); - *(.text.*); - . = ALIGN(4); - _etext = .; - } >.sram - - .rodata : { - _rodata = .; - . = ALIGN(4); - cpu_drivers = . ; - *(.rodata.cpu_driver) - ecpu_drivers = . ; - *(.rodata) - *(.rodata.*) - /* kevinh/Ispiri - Added an align, because the objcopy tool - * incorrectly converts sections that are not long word aligned. - */ - . = ALIGN(4); - - _erodata = .; - } >.sram - /* After the code we place initialized data (typically initialized - * global variables). This gets copied into ram by startup code. - * __data_start and __data_end shows where in ram this should be placed, - * whereas __data_loadstart and __data_loadend shows where in rom to - * copy from. - */ - .data : { - _data = .; - *(.data) - _edata = .; - } >.sram __image_copy_end = .; @@ -99,12 +61,12 @@ SECTIONS * crt0.S fills between _bss and _ebss with zeroes. */ .bss . : { - . = ALIGN(4); + . = ALIGN(8); _bss = .; *(.bss) *(.sbss) *(COMMON) - } >.sram + } _ebss = .; _end = .;

1 0

Patch set updated for coreboot: 4f9b473 import SPL files for board_i2c_{claim, release}_bus()
by David Hendricks 27 Dec '12

27 Dec '12

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2081 -gerrit commit 4f9b473b5f6aa11670dc1355713df62cde32850d Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Dec 27 15:11:27 2012 -0800 import SPL files for board_i2c_{claim,release}_bus() This imports SPL (second phase loader) files from U-Boot. Most of the content of these files will eventually go away since they're fairly U-Boot specific. For now they are here to make Jenkins happy. Change-Id: Ib3a365ecb9dc304b20f7c1c06665aad2c0c53e69 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5-common/spl.h | 4 ++++ src/mainboard/google/snow/smdk5250_spl.c | 35 ++++++++++++++++++++++++++++++-- 2 files changed, 37 insertions(+), 2 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/spl.h b/src/cpu/samsung/exynos5-common/spl.h index afa9a8e..439e1b0 100644 --- a/src/cpu/samsung/exynos5-common/spl.h +++ b/src/cpu/samsung/exynos5-common/spl.h @@ -91,4 +91,8 @@ struct spl_machine_param *spl_get_machine_params(void); */ void spl_early_init(void); +/* FIXME(dhendrix): for early i2c init */ +void board_i2c_release_bus(int node); +int board_i2c_claim_bus(int node); + #endif /* __ASM_ARCH_EXYNOS_SPL_H__ */ diff --git a/src/mainboard/google/snow/smdk5250_spl.c b/src/mainboard/google/snow/smdk5250_spl.c index 204e411..19d8610 100644 --- a/src/mainboard/google/snow/smdk5250_spl.c +++ b/src/mainboard/google/snow/smdk5250_spl.c @@ -24,8 +24,12 @@ #define SIGNATURE 0xdeadbeef /* Parameters of early board initialization in SPL */ -static struct spl_machine_param machine_param - __attribute__((section(".machine_param"))) = { +/* FIXME(dhendrix): does this really need to be in a particular section? + * I suspect in U-boot's case the section attribute was needed for global + * data. */ +//static struct spl_machine_param machine_param +// __attribute__((section(".machine_param"))) = { +static struct spl_machine_param machine_param = { .signature = SIGNATURE, .version = 1, .params = "vmubfasirMw", @@ -65,6 +69,18 @@ struct spl_machine_param *spl_get_machine_params(void) return &machine_param; } +#if 0 +int board_get_revision(void) +{ + struct spl_machine_param *params = spl_get_machine_params(); + unsigned gpio[CONFIG_BOARD_REV_GPIO_COUNT]; + + gpio[0] = params->board_rev_gpios & 0xffff; + gpio[1] = params->board_rev_gpios >> 16; + return gpio_decode_number(gpio, CONFIG_BOARD_REV_GPIO_COUNT); +} +#endif + int board_wakeup_permitted(void) { struct spl_machine_param *param = spl_get_machine_params(); @@ -76,3 +92,18 @@ int board_wakeup_permitted(void) return !is_bad_wake; } + +/* + * TODO(sjg(a)chromium.org): + * Declared there here for SPL, since there is no core i2c subsystem and + * cmd_i2c.c is not included. + */ +void board_i2c_release_bus(int node) +{ +} + +int board_i2c_claim_bus(int node) +{ + /* EC is not allowed to touch the bus until we enter U-Boot */ + return 0; +}

1 0

Patch set updated for coreboot: fbaa9bb armv7: begin splitting old start.S apart
by David Hendricks 27 Dec '12

27 Dec '12

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2083 -gerrit commit fbaa9bb36397cb146cb6172a1a86ff454630e106 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Dec 27 15:23:57 2012 -0800 armv7: begin splitting old start.S apart The old start.S file did a lot of work and had a few ugly #ifndef's. This init.S file will eventually contain only bare minimum, generic ARM code. Processor-specific stuff and things that take place later in the boot process should go elsewhere. Change-Id: I7db0a77ee4bbad1ddecb193ea125d8941a50532b Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/Makefile.inc | 4 +- src/arch/armv7/init/init.S | 561 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 562 insertions(+), 3 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index b413d3e..1a1271f 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -142,9 +142,7 @@ endif CFLAGS += -D__KERNEL__ CFLAGS += -D__LINUX_ARM_ARCH__=7 -# FIXME(dhendrix): trying to split start.S apart... -crt0s = $(src)/arch/armv7/start.S -#crt0s = $(src)/arch/armv7/romstage.S +crt0s = $(src)/arch/armv7/init/init.S ldscripts = ldscripts += $(src)/arch/armv7/romstage.ld diff --git a/src/arch/armv7/init/init.S b/src/arch/armv7/init/init.S new file mode 100644 index 0000000..72adfdc --- /dev/null +++ b/src/arch/armv7/init/init.S @@ -0,0 +1,561 @@ +/* + * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core + * + * Copyright (c) 2004 Texas Instruments <r-woodruff2(a)ti.com> + * + * Copyright (c) 2001 Marius Gröger <mag(a)sysgo.de> + * Copyright (c) 2002 Alex Züpke <azu(a)sysgo.de> + * Copyright (c) 2002 Gary Jennejohn <garyj(a)denx.de> + * Copyright (c) 2003 Richard Woodruff <r-woodruff2(a)ti.com> + * Copyright (c) 2003 Kshitij <kshitij(a)ti.com> + * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim(a)ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define __ASSEMBLY__ +#include <system.h> + +.globl _start +_start: b reset + ldr pc, _undefined_instruction + ldr pc, _software_interrupt + ldr pc, _prefetch_abort + ldr pc, _data_abort + ldr pc, _not_used + ldr pc, _irq + ldr pc, _fiq +_undefined_instruction: .word _undefined_instruction +_software_interrupt: .word _software_interrupt +_prefetch_abort: .word _prefetch_abort +_data_abort: .word _data_abort +_not_used: .word _not_used +_irq: .word _irq +_fiq: .word _fiq +_pad: .word 0x12345678 /* now 16*4=64 */ + +.global _end_vect +_end_vect: + + .balignl 16,0xdeadbeef +/************************************************************************* + * + * Startup Code (reset vector) + * + * do important init only if we don't start from memory! + * setup Memory and board specific bits prior to relocation. + * relocate armboot to ram + * setup stack + * + *************************************************************************/ + +.globl _TEXT_BASE +_TEXT_BASE: + .word CONFIG_SYS_TEXT_BASE + +/* + * These are defined in the board-specific linker script. + */ +.globl _bss_start_ofs +_bss_start_ofs: + .word _bss - _start + +.global _image_copy_end_ofs +_image_copy_end_ofs: + .word __image_copy_end - _start + +.globl _bss_end_ofs +_bss_end_ofs: + .word _ebss - _start +# .word __bss_end__ - _start + +.globl _end_ofs +_end_ofs: + .word _end - _start + +#ifdef CONFIG_USE_IRQ +/* IRQ stack memory (calculated at run-time) */ +.globl IRQ_STACK_START +IRQ_STACK_START: + .word 0x0badc0de + +/* IRQ stack memory (calculated at run-time) */ +.globl FIQ_STACK_START +FIQ_STACK_START: + .word 0x0badc0de +#endif + +/* IRQ stack memory (calculated at run-time) + 8 bytes */ +.globl IRQ_STACK_START_IN +IRQ_STACK_START_IN: + .word 0x0badc0de + +/* + * the actual reset code + */ + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0, cpsr + bic r0, r0, #0x1f + orr r0, r0, #0xd3 + msr cpsr,r0 + + /* + * From Cortex-A Series Programmer's Guide: + * Only CPU 0 performs initialization. Other CPUs go into WFI + * to do this, first work out which CPU this is + * this code typically is run before any other initialization step + */ + mrc p15, 0, r1, c0, c0, 5 @ Read Multiprocessor Affinity Register + and r1, r1, #0x3 @ Extract CPU ID bits + cmp r1, #0 + /* FIXME(dhendrix): this should be WFI or something */ + bne infinite_loop @ Loop if not core0 + + /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */ + mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register + bic r0, #CR_V @ V = 0 + mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register + + /* Set vector address in CP15 VBAR register */ + ldr r0, =_start + mcr p15, 0, r0, c12, c0, 0 @Set VBAR + + /* the mask ROM code should have PLL and others stable */ + /* + * FIXME(dhendrix): Do we need to explicitly disable icache/dcache + * first? See example 15-3 in Cortex-A programmers guide... + */ +#if 0 + bl cpu_init_cp15 + /* FIXME(dhendrix): this function essentially sets the stack + * pointer again, so let's skip it and only set SP in + * call_board_init_f below. + */ + bl cpu_init_crit +#endif + +/* Set stackpointer in internal RAM to call board_init_f */ +call_board_init_f: + /* + * FIXME(dhendrix): The ldr instruction below made some really weird + * looking assembly... Ron and I replaced it with the mov{w,t} to + * setup the stack pointer and things look better. + * + * (hungte) I think "movw/movt/mov" makes it even weird, and may put + * extra assumption to system architecture? My vote for ldr :) + */ +/* ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) */ + movw r0, #0xF800 + movt r0, 0x0204 + mov sp, r0 + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ + ldr r0,=0x00000000 + bl board_init_f + +set_ps_hold: + movw r3, #13068 + movt r3, 4100 + movw r2, #13068 + movt r2, 4100 + ldr r2, [r2, #0] + orr r2, r2, #256 + str r2, [r3, #0] + mov pc, lr @ back to my caller + +infinite_loop: + b infinite_loop + + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + */ + .globl relocate_code +relocate_code: + mov r4, r0 /* save addr_sp */ + mov r5, r1 /* save addr of gd */ + mov r6, r2 /* save addr of destination */ + + /* Set up the stack */ +stack_setup: + mov sp, r4 + + adr r0, _start + subs r9, r6, r0 /* r9 <- relocation offset */ + beq clear_bss /* skip relocation */ + mov r1, r6 /* r1 <- scratch for copy_loop */ + ldr r3, _image_copy_end_ofs + add r2, r0, r3 /* r2 <- source end address */ + +copy_loop: + ldmia r0!, {r9-r10} /* copy from source address [r0] */ + stmia r1!, {r9-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end address [r2] */ + blo copy_loop + +#ifndef CONFIG_SPL_BUILD + /* + * fix .rel.dyn relocations + */ + ldr r0, _TEXT_BASE /* r0 <- Text base */ + sub r9, r6, r0 /* r9 <- relocation offset */ + ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ + add r10, r10, r0 /* r10 <- sym table in FLASH */ + ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ + add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ + ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ + add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ +fixloop: + ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ + add r0, r0, r9 /* r0 <- location to fix up in RAM */ + ldr r1, [r2, #4] + and r7, r1, #0xff + cmp r7, #23 /* relative fixup? */ + beq fixrel + cmp r7, #2 /* absolute fixup? */ + beq fixabs + /* ignore unknown type of fixup */ + b fixnext +fixabs: + /* absolute fix: set location to (offset) symbol value */ + mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ + add r1, r10, r1 /* r1 <- address of symbol in table */ + ldr r1, [r1, #4] /* r1 <- symbol value */ + add r1, r1, r9 /* r1 <- relocated sym addr */ + b fixnext +fixrel: + /* relative fix: increase location by offset */ + ldr r1, [r0] + add r1, r1, r9 +fixnext: + str r1, [r0] + add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ + cmp r2, r3 + blo fixloop + b clear_bss +_rel_dyn_start_ofs: + .word __rel_dyn_start - _start +_rel_dyn_end_ofs: + .word __rel_dyn_end - _start +_dynsym_start_ofs: + .word __dynsym_start - _start + +#endif /* #ifndef CONFIG_SPL_BUILD */ + +clear_bss: +#ifdef CONFIG_SPL_BUILD + /* No relocation for SPL */ + ldr r0, =_bss + ldr r1, =_ebss +#else + ldr r0, _bss_start_ofs + ldr r1, _bss_end_ofs + mov r4, r6 /* reloc addr */ + add r0, r0, r4 + add r1, r1, r4 +#endif + mov r2, #0x00000000 /* clear */ + +clbss_l:str r2, [r0] /* clear loop... */ + add r0, r0, #4 + cmp r0, r1 + bne clbss_l + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ +jump_2_ram: +/* + * If I-cache is enabled invalidate it + */ +#ifndef CONFIG_SYS_ICACHE_OFF + mcr p15, 0, r0, c7, c5, 0 @ invalidate icache + mcr p15, 0, r0, c7, c10, 4 @ DSB + mcr p15, 0, r0, c7, c5, 4 @ ISB +#endif + ldr r0, _board_init_r_ofs + adr r1, _start + add lr, r0, r1 + add lr, lr, r9 + /* setup parameters for board_init_r */ + mov r0, r5 /* gd_t */ + mov r1, r6 /* dest_addr */ + /* jump to it ... */ + mov pc, lr + +_board_init_r_ofs: + .word board_init_r - _start + +/************************************************************************* + * + * cpu_init_cp15 + * + * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless + * CONFIG_SYS_ICACHE_OFF is defined. + * + *************************************************************************/ +.globl cpu_init_cp15 +cpu_init_cp15: + /* + * Invalidate L1 I/D + */ + mov r0, #0 @ set up for MCR + mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs + mcr p15, 0, r0, c7, c5, 0 @ invalidate icache + mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array + mcr p15, 0, r0, c7, c10, 4 @ DSB + mcr p15, 0, r0, c7, c5, 4 @ ISB + + /* + * disable MMU stuff and caches + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00002000 @ clear bits 13 (--V-) + bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) + orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align + orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB +#ifdef CONFIG_SYS_ICACHE_OFF + bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache +#else + orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache +#endif + mcr p15, 0, r0, c1, c0, 0 + mov pc, lr @ back to my caller + + +/************************************************************************* + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + *************************************************************************/ +cpu_init_crit: + /* + * Jump to board specific initialization... + * The Mask ROM will have already initialized + * basic memory. Go here to bump up clock rate and handle + * wake up conditions. + */ + mov ip, lr @ persevere link reg across call + bl lowlevel_init @ go setup pll,mux,memory + mov lr, ip @ restore link + mov pc, lr @ back to my caller + +#ifndef CONFIG_SPL_BUILD +/* + ************************************************************************* + * + * Interrupt handling + * + ************************************************************************* + */ +@ +@ IRQ stack frame. +@ +#define S_FRAME_SIZE 72 + +#define S_OLD_R0 68 +#define S_PSR 64 +#define S_PC 60 +#define S_LR 56 +#define S_SP 52 + +#define S_IP 48 +#define S_FP 44 +#define S_R10 40 +#define S_R9 36 +#define S_R8 32 +#define S_R7 28 +#define S_R6 24 +#define S_R5 20 +#define S_R4 16 +#define S_R3 12 +#define S_R2 8 +#define S_R1 4 +#define S_R0 0 + +#define MODE_SVC 0x13 +#define I_BIT 0x80 + +/* + * use bad_save_user_regs for abort/prefetch/undef/swi ... + * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling + */ + + .macro bad_save_user_regs + sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current + @ user stack + stmia sp, {r0 - r12} @ Save user registers (now in + @ svc mode) r0-r12 + ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort + @ stack + ldmia r2, {r2 - r3} @ get values for "aborted" pc + @ and cpsr (into parm regs) + add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack + + add r5, sp, #S_SP + mov r1, lr + stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr + mov r0, sp @ save current stack into r0 + @ (param register) + .endm + + .macro irq_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Calling r0-r12 + add r8, sp, #S_PC @ !! R8 NEEDS to be saved !! + @ a reserved stack spot would + @ be good. + stmdb r8, {sp, lr}^ @ Calling SP, LR + str lr, [r8, #0] @ Save calling PC + mrs r6, spsr + str r6, [r8, #4] @ Save CPSR + str r0, [r8, #8] @ Save OLD_R0 + mov r0, sp + .endm + + .macro irq_restore_user_regs + ldmia sp, {r0 - lr}^ @ Calling r0 - lr + mov r0, r0 + ldr lr, [sp, #S_PC] @ Get PC + add sp, sp, #S_FRAME_SIZE + subs pc, lr, #4 @ return & move spsr_svc into + @ cpsr + .endm + + .macro get_bad_stack + ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter + @ in banked mode) + + str lr, [r13] @ save caller lr in position 0 + @ of saved stack + mrs lr, spsr @ get the spsr + str lr, [r13, #4] @ save spsr in position 1 of + @ saved stack + + mov r13, #MODE_SVC @ prepare SVC-Mode + @ msr spsr_c, r13 + msr spsr, r13 @ switch modes, make sure + @ moves will execute + mov lr, pc @ capture return pc + movs pc, lr @ jump to next instruction & + @ switch modes. + .endm + + .macro get_bad_stack_swi + sub r13, r13, #4 @ space on current stack for + @ scratch reg. + str r0, [r13] @ save R0's value. + ldr r0, IRQ_STACK_START_IN @ get data regions start + @ spots for abort stack + str lr, [r0] @ save caller lr in position 0 + @ of saved stack + mrs r0, spsr @ get the spsr + str lr, [r0, #4] @ save spsr in position 1 of + @ saved stack + ldr r0, [r13] @ restore r0 + add r13, r13, #4 @ pop stack entry + .endm + + .macro get_irq_stack @ setup IRQ stack + ldr sp, IRQ_STACK_START + .endm + + .macro get_fiq_stack @ setup FIQ stack + ldr sp, FIQ_STACK_START + .endm + +/* + * exception handlers + */ + .align 5 +undefined_instruction: + get_bad_stack + bad_save_user_regs + bl do_undefined_instruction + + .align 5 +software_interrupt: + get_bad_stack_swi + bad_save_user_regs + bl do_software_interrupt + + .align 5 +prefetch_abort: + get_bad_stack + bad_save_user_regs + bl do_prefetch_abort + + .align 5 +data_abort: + get_bad_stack + bad_save_user_regs + bl do_data_abort + + .align 5 +not_used: + get_bad_stack + bad_save_user_regs + bl do_not_used + +#ifdef CONFIG_USE_IRQ + + .align 5 +irq: + get_irq_stack + irq_save_user_regs + bl do_irq + irq_restore_user_regs + + .align 5 +fiq: + get_fiq_stack + /* someone ought to write a more effective fiq_save_user_regs */ + irq_save_user_regs + bl do_fiq + irq_restore_user_regs + +#else + + .align 5 +irq: + get_bad_stack + bad_save_user_regs + bl do_irq + + .align 5 +fiq: + get_bad_stack + bad_save_user_regs + bl do_fiq + +#endif /* CONFIG_USE_IRQ */ +#endif /* CONFIG_SPL_BUILD */

1 0

Patch set updated for coreboot: f11b572 remove obsolete include paths from INCLUDES
by David Hendricks 27 Dec '12

27 Dec '12

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2082 -gerrit commit f11b572534b4945e3774e3cf9e876629512175b0 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Dec 27 15:22:27 2012 -0800 remove obsolete include paths from INCLUDES Change-Id: I621fd49b1f1b96ef388c61ff1abc2130ad2163a5 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/Makefile.inc | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 65e1f5b..b413d3e 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -141,8 +141,6 @@ endif # For various headers imported from Linux CFLAGS += -D__KERNEL__ CFLAGS += -D__LINUX_ARM_ARCH__=7 -INCLUDES += -Isrc/include/linux -INCLUDES += -Isrc/include/linux/uapi # FIXME(dhendrix): trying to split start.S apart... crt0s = $(src)/arch/armv7/start.S

1 0

Patch set updated for coreboot: a287e0f armv7: begin splitting old start.S apart
by David Hendricks 27 Dec '12

27 Dec '12

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2083 -gerrit commit a287e0fc53028c4826c086e1148ed7e09c3d1d82 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Dec 27 15:23:57 2012 -0800 armv7: begin splitting old start.S apart The old start.S file did a lot of work and had a few ugly #ifndef's. This init.S file will eventually contain only bare minimum, generic ARM code. Processor-specific stuff and things that take place later in the boot process should go elsewhere. Change-Id: I7db0a77ee4bbad1ddecb193ea125d8941a50532b Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/Makefile.inc | 4 +- src/arch/armv7/init/init.S | 561 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 562 insertions(+), 3 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index b413d3e..1a1271f 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -142,9 +142,7 @@ endif CFLAGS += -D__KERNEL__ CFLAGS += -D__LINUX_ARM_ARCH__=7 -# FIXME(dhendrix): trying to split start.S apart... -crt0s = $(src)/arch/armv7/start.S -#crt0s = $(src)/arch/armv7/romstage.S +crt0s = $(src)/arch/armv7/init/init.S ldscripts = ldscripts += $(src)/arch/armv7/romstage.ld diff --git a/src/arch/armv7/init/init.S b/src/arch/armv7/init/init.S new file mode 100644 index 0000000..72adfdc --- /dev/null +++ b/src/arch/armv7/init/init.S @@ -0,0 +1,561 @@ +/* + * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core + * + * Copyright (c) 2004 Texas Instruments <r-woodruff2(a)ti.com> + * + * Copyright (c) 2001 Marius Gröger <mag(a)sysgo.de> + * Copyright (c) 2002 Alex Züpke <azu(a)sysgo.de> + * Copyright (c) 2002 Gary Jennejohn <garyj(a)denx.de> + * Copyright (c) 2003 Richard Woodruff <r-woodruff2(a)ti.com> + * Copyright (c) 2003 Kshitij <kshitij(a)ti.com> + * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim(a)ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define __ASSEMBLY__ +#include <system.h> + +.globl _start +_start: b reset + ldr pc, _undefined_instruction + ldr pc, _software_interrupt + ldr pc, _prefetch_abort + ldr pc, _data_abort + ldr pc, _not_used + ldr pc, _irq + ldr pc, _fiq +_undefined_instruction: .word _undefined_instruction +_software_interrupt: .word _software_interrupt +_prefetch_abort: .word _prefetch_abort +_data_abort: .word _data_abort +_not_used: .word _not_used +_irq: .word _irq +_fiq: .word _fiq +_pad: .word 0x12345678 /* now 16*4=64 */ + +.global _end_vect +_end_vect: + + .balignl 16,0xdeadbeef +/************************************************************************* + * + * Startup Code (reset vector) + * + * do important init only if we don't start from memory! + * setup Memory and board specific bits prior to relocation. + * relocate armboot to ram + * setup stack + * + *************************************************************************/ + +.globl _TEXT_BASE +_TEXT_BASE: + .word CONFIG_SYS_TEXT_BASE + +/* + * These are defined in the board-specific linker script. + */ +.globl _bss_start_ofs +_bss_start_ofs: + .word _bss - _start + +.global _image_copy_end_ofs +_image_copy_end_ofs: + .word __image_copy_end - _start + +.globl _bss_end_ofs +_bss_end_ofs: + .word _ebss - _start +# .word __bss_end__ - _start + +.globl _end_ofs +_end_ofs: + .word _end - _start + +#ifdef CONFIG_USE_IRQ +/* IRQ stack memory (calculated at run-time) */ +.globl IRQ_STACK_START +IRQ_STACK_START: + .word 0x0badc0de + +/* IRQ stack memory (calculated at run-time) */ +.globl FIQ_STACK_START +FIQ_STACK_START: + .word 0x0badc0de +#endif + +/* IRQ stack memory (calculated at run-time) + 8 bytes */ +.globl IRQ_STACK_START_IN +IRQ_STACK_START_IN: + .word 0x0badc0de + +/* + * the actual reset code + */ + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0, cpsr + bic r0, r0, #0x1f + orr r0, r0, #0xd3 + msr cpsr,r0 + + /* + * From Cortex-A Series Programmer's Guide: + * Only CPU 0 performs initialization. Other CPUs go into WFI + * to do this, first work out which CPU this is + * this code typically is run before any other initialization step + */ + mrc p15, 0, r1, c0, c0, 5 @ Read Multiprocessor Affinity Register + and r1, r1, #0x3 @ Extract CPU ID bits + cmp r1, #0 + /* FIXME(dhendrix): this should be WFI or something */ + bne infinite_loop @ Loop if not core0 + + /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */ + mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register + bic r0, #CR_V @ V = 0 + mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register + + /* Set vector address in CP15 VBAR register */ + ldr r0, =_start + mcr p15, 0, r0, c12, c0, 0 @Set VBAR + + /* the mask ROM code should have PLL and others stable */ + /* + * FIXME(dhendrix): Do we need to explicitly disable icache/dcache + * first? See example 15-3 in Cortex-A programmers guide... + */ +#if 0 + bl cpu_init_cp15 + /* FIXME(dhendrix): this function essentially sets the stack + * pointer again, so let's skip it and only set SP in + * call_board_init_f below. + */ + bl cpu_init_crit +#endif + +/* Set stackpointer in internal RAM to call board_init_f */ +call_board_init_f: + /* + * FIXME(dhendrix): The ldr instruction below made some really weird + * looking assembly... Ron and I replaced it with the mov{w,t} to + * setup the stack pointer and things look better. + * + * (hungte) I think "movw/movt/mov" makes it even weird, and may put + * extra assumption to system architecture? My vote for ldr :) + */ +/* ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) */ + movw r0, #0xF800 + movt r0, 0x0204 + mov sp, r0 + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ + ldr r0,=0x00000000 + bl board_init_f + +set_ps_hold: + movw r3, #13068 + movt r3, 4100 + movw r2, #13068 + movt r2, 4100 + ldr r2, [r2, #0] + orr r2, r2, #256 + str r2, [r3, #0] + mov pc, lr @ back to my caller + +infinite_loop: + b infinite_loop + + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + */ + .globl relocate_code +relocate_code: + mov r4, r0 /* save addr_sp */ + mov r5, r1 /* save addr of gd */ + mov r6, r2 /* save addr of destination */ + + /* Set up the stack */ +stack_setup: + mov sp, r4 + + adr r0, _start + subs r9, r6, r0 /* r9 <- relocation offset */ + beq clear_bss /* skip relocation */ + mov r1, r6 /* r1 <- scratch for copy_loop */ + ldr r3, _image_copy_end_ofs + add r2, r0, r3 /* r2 <- source end address */ + +copy_loop: + ldmia r0!, {r9-r10} /* copy from source address [r0] */ + stmia r1!, {r9-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end address [r2] */ + blo copy_loop + +#ifndef CONFIG_SPL_BUILD + /* + * fix .rel.dyn relocations + */ + ldr r0, _TEXT_BASE /* r0 <- Text base */ + sub r9, r6, r0 /* r9 <- relocation offset */ + ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ + add r10, r10, r0 /* r10 <- sym table in FLASH */ + ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ + add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ + ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ + add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ +fixloop: + ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ + add r0, r0, r9 /* r0 <- location to fix up in RAM */ + ldr r1, [r2, #4] + and r7, r1, #0xff + cmp r7, #23 /* relative fixup? */ + beq fixrel + cmp r7, #2 /* absolute fixup? */ + beq fixabs + /* ignore unknown type of fixup */ + b fixnext +fixabs: + /* absolute fix: set location to (offset) symbol value */ + mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ + add r1, r10, r1 /* r1 <- address of symbol in table */ + ldr r1, [r1, #4] /* r1 <- symbol value */ + add r1, r1, r9 /* r1 <- relocated sym addr */ + b fixnext +fixrel: + /* relative fix: increase location by offset */ + ldr r1, [r0] + add r1, r1, r9 +fixnext: + str r1, [r0] + add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ + cmp r2, r3 + blo fixloop + b clear_bss +_rel_dyn_start_ofs: + .word __rel_dyn_start - _start +_rel_dyn_end_ofs: + .word __rel_dyn_end - _start +_dynsym_start_ofs: + .word __dynsym_start - _start + +#endif /* #ifndef CONFIG_SPL_BUILD */ + +clear_bss: +#ifdef CONFIG_SPL_BUILD + /* No relocation for SPL */ + ldr r0, =_bss + ldr r1, =_ebss +#else + ldr r0, _bss_start_ofs + ldr r1, _bss_end_ofs + mov r4, r6 /* reloc addr */ + add r0, r0, r4 + add r1, r1, r4 +#endif + mov r2, #0x00000000 /* clear */ + +clbss_l:str r2, [r0] /* clear loop... */ + add r0, r0, #4 + cmp r0, r1 + bne clbss_l + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ +jump_2_ram: +/* + * If I-cache is enabled invalidate it + */ +#ifndef CONFIG_SYS_ICACHE_OFF + mcr p15, 0, r0, c7, c5, 0 @ invalidate icache + mcr p15, 0, r0, c7, c10, 4 @ DSB + mcr p15, 0, r0, c7, c5, 4 @ ISB +#endif + ldr r0, _board_init_r_ofs + adr r1, _start + add lr, r0, r1 + add lr, lr, r9 + /* setup parameters for board_init_r */ + mov r0, r5 /* gd_t */ + mov r1, r6 /* dest_addr */ + /* jump to it ... */ + mov pc, lr + +_board_init_r_ofs: + .word board_init_r - _start + +/************************************************************************* + * + * cpu_init_cp15 + * + * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless + * CONFIG_SYS_ICACHE_OFF is defined. + * + *************************************************************************/ +.globl cpu_init_cp15 +cpu_init_cp15: + /* + * Invalidate L1 I/D + */ + mov r0, #0 @ set up for MCR + mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs + mcr p15, 0, r0, c7, c5, 0 @ invalidate icache + mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array + mcr p15, 0, r0, c7, c10, 4 @ DSB + mcr p15, 0, r0, c7, c5, 4 @ ISB + + /* + * disable MMU stuff and caches + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00002000 @ clear bits 13 (--V-) + bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) + orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align + orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB +#ifdef CONFIG_SYS_ICACHE_OFF + bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache +#else + orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache +#endif + mcr p15, 0, r0, c1, c0, 0 + mov pc, lr @ back to my caller + + +/************************************************************************* + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + *************************************************************************/ +cpu_init_crit: + /* + * Jump to board specific initialization... + * The Mask ROM will have already initialized + * basic memory. Go here to bump up clock rate and handle + * wake up conditions. + */ + mov ip, lr @ persevere link reg across call + bl lowlevel_init @ go setup pll,mux,memory + mov lr, ip @ restore link + mov pc, lr @ back to my caller + +#ifndef CONFIG_SPL_BUILD +/* + ************************************************************************* + * + * Interrupt handling + * + ************************************************************************* + */ +@ +@ IRQ stack frame. +@ +#define S_FRAME_SIZE 72 + +#define S_OLD_R0 68 +#define S_PSR 64 +#define S_PC 60 +#define S_LR 56 +#define S_SP 52 + +#define S_IP 48 +#define S_FP 44 +#define S_R10 40 +#define S_R9 36 +#define S_R8 32 +#define S_R7 28 +#define S_R6 24 +#define S_R5 20 +#define S_R4 16 +#define S_R3 12 +#define S_R2 8 +#define S_R1 4 +#define S_R0 0 + +#define MODE_SVC 0x13 +#define I_BIT 0x80 + +/* + * use bad_save_user_regs for abort/prefetch/undef/swi ... + * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling + */ + + .macro bad_save_user_regs + sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current + @ user stack + stmia sp, {r0 - r12} @ Save user registers (now in + @ svc mode) r0-r12 + ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort + @ stack + ldmia r2, {r2 - r3} @ get values for "aborted" pc + @ and cpsr (into parm regs) + add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack + + add r5, sp, #S_SP + mov r1, lr + stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr + mov r0, sp @ save current stack into r0 + @ (param register) + .endm + + .macro irq_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Calling r0-r12 + add r8, sp, #S_PC @ !! R8 NEEDS to be saved !! + @ a reserved stack spot would + @ be good. + stmdb r8, {sp, lr}^ @ Calling SP, LR + str lr, [r8, #0] @ Save calling PC + mrs r6, spsr + str r6, [r8, #4] @ Save CPSR + str r0, [r8, #8] @ Save OLD_R0 + mov r0, sp + .endm + + .macro irq_restore_user_regs + ldmia sp, {r0 - lr}^ @ Calling r0 - lr + mov r0, r0 + ldr lr, [sp, #S_PC] @ Get PC + add sp, sp, #S_FRAME_SIZE + subs pc, lr, #4 @ return & move spsr_svc into + @ cpsr + .endm + + .macro get_bad_stack + ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter + @ in banked mode) + + str lr, [r13] @ save caller lr in position 0 + @ of saved stack + mrs lr, spsr @ get the spsr + str lr, [r13, #4] @ save spsr in position 1 of + @ saved stack + + mov r13, #MODE_SVC @ prepare SVC-Mode + @ msr spsr_c, r13 + msr spsr, r13 @ switch modes, make sure + @ moves will execute + mov lr, pc @ capture return pc + movs pc, lr @ jump to next instruction & + @ switch modes. + .endm + + .macro get_bad_stack_swi + sub r13, r13, #4 @ space on current stack for + @ scratch reg. + str r0, [r13] @ save R0's value. + ldr r0, IRQ_STACK_START_IN @ get data regions start + @ spots for abort stack + str lr, [r0] @ save caller lr in position 0 + @ of saved stack + mrs r0, spsr @ get the spsr + str lr, [r0, #4] @ save spsr in position 1 of + @ saved stack + ldr r0, [r13] @ restore r0 + add r13, r13, #4 @ pop stack entry + .endm + + .macro get_irq_stack @ setup IRQ stack + ldr sp, IRQ_STACK_START + .endm + + .macro get_fiq_stack @ setup FIQ stack + ldr sp, FIQ_STACK_START + .endm + +/* + * exception handlers + */ + .align 5 +undefined_instruction: + get_bad_stack + bad_save_user_regs + bl do_undefined_instruction + + .align 5 +software_interrupt: + get_bad_stack_swi + bad_save_user_regs + bl do_software_interrupt + + .align 5 +prefetch_abort: + get_bad_stack + bad_save_user_regs + bl do_prefetch_abort + + .align 5 +data_abort: + get_bad_stack + bad_save_user_regs + bl do_data_abort + + .align 5 +not_used: + get_bad_stack + bad_save_user_regs + bl do_not_used + +#ifdef CONFIG_USE_IRQ + + .align 5 +irq: + get_irq_stack + irq_save_user_regs + bl do_irq + irq_restore_user_regs + + .align 5 +fiq: + get_fiq_stack + /* someone ought to write a more effective fiq_save_user_regs */ + irq_save_user_regs + bl do_fiq + irq_restore_user_regs + +#else + + .align 5 +irq: + get_bad_stack + bad_save_user_regs + bl do_irq + + .align 5 +fiq: + get_bad_stack + bad_save_user_regs + bl do_fiq + +#endif /* CONFIG_USE_IRQ */ +#endif /* CONFIG_SPL_BUILD */

1 0

Patch set updated for coreboot: 8343b26 remove obsolete include paths from INCLUDES
by David Hendricks 27 Dec '12

27 Dec '12

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2082 -gerrit commit 8343b260d5f915497893946954d3d1885507bce9 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Dec 27 15:22:27 2012 -0800 remove obsolete include paths from INCLUDES Change-Id: I621fd49b1f1b96ef388c61ff1abc2130ad2163a5 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/Makefile.inc | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 65e1f5b..b413d3e 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -141,8 +141,6 @@ endif # For various headers imported from Linux CFLAGS += -D__KERNEL__ CFLAGS += -D__LINUX_ARM_ARCH__=7 -INCLUDES += -Isrc/include/linux -INCLUDES += -Isrc/include/linux/uapi # FIXME(dhendrix): trying to split start.S apart... crt0s = $(src)/arch/armv7/start.S

1 0

← Newer
1
2
3
4
5
6
7
8
...
35
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot December 2012