coreboot December 2012

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Patch set updated for coreboot: 77a1a53 rs780: Implement `rs780_internal_gfx_disable` and add .disable pcie_ops
by Paul Menzel 30 Dec '12

30 Dec '12

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2065 -gerrit commit 77a1a53955af7f2e55889b0060cd6d82c5791596 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu Dec 20 18:42:00 2012 +0100 rs780: Implement `rs780_internal_gfx_disable` and add .disable pcie_ops That code will be used to disable the internal GFX card and enable the external PCIe card. The following lines from function `rs780_internal_gfx_enable()` are taken and reversed. /* Disable external GFX and enable internal GFX. */ l_dword = pci_read_config32(nb_dev, 0x8c); l_dword &= ~(1<<0); l_dword |= 1<<1; pci_write_config32(nb_dev, 0x8c, l_dword); It has been tested on the M4A785T-M with the following card inside the PCIe 16x slot: 02:00.0 VGA compatible controller: nVidia Corporation GT218 [GeForce 210] (rev a2) Change-Id: I7bd412b987fde98c97464175e2c7a384a8f0fb84 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/amd/rs780/gfx.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c index f70cd9b..f4a5120 100644 --- a/src/southbridge/amd/rs780/gfx.c +++ b/src/southbridge/amd/rs780/gfx.c @@ -760,6 +760,24 @@ static void internal_gfx_pci_dev_init(struct device *dev) clkind_write(dev, 0x5C, 0x0); } +/* + * Set registers in RS780 and CPU to disable the internal GFX. + * Please refer to `rs780_internal_gfx_enable()`. + * +*/ +static void rs780_internal_gfx_disable(device_t dev) +{ + u32 l_dword; + device_t nb_dev = dev_find_slot(0, 0); + + /* Disable internal GFX and enable external GFX. */ + l_dword = pci_read_config32(nb_dev, 0x8c); + l_dword |= 1<<0; + l_dword &= ~(1<<1); + pci_write_config32(nb_dev, 0x8c, l_dword); + + dev->enabled = 0; +} /* * Set registers in RS780 and CPU to enable the internal GFX. @@ -999,6 +1017,7 @@ static struct device_operations pcie_ops = { .init = internal_gfx_pci_dev_init, /* The option ROM initializes the device. rs780_gfx_init, */ .scan_bus = 0, .enable = rs780_internal_gfx_enable, + .disable = rs780_internal_gfx_disable, .ops_pci = &lops_pci, };

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Patch set updated for coreboot: f5d7954 rs780: Implement `rs780_internal_gfx_disable` and add .disable pcie_ops
by Paul Menzel 30 Dec '12

30 Dec '12

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2065 -gerrit commit f5d7954799070621aabf9c18ec249fae5fcab68d Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu Dec 20 18:42:00 2012 +0100 rs780: Implement `rs780_internal_gfx_disable` and add .disable pcie_ops That code will be used to disable the internal GFX card and enable the external PCIe card. The bits from function `rs780_internal_gfx_enable()` are taken and reversed. /* Disable external GFX and enable internal GFX. */ l_dword = pci_read_config32(nb_dev, 0x8c); l_dword &= ~(1<<0); l_dword |= 1<<1; pci_write_config32(nb_dev, 0x8c, l_dword); It has been tested on the M4A785T-M with the following card inside the PCIe 16x slot: 02:00.0 VGA compatible controller: nVidia Corporation GT218 [GeForce 210] (rev a2) Change-Id: I7bd412b987fde98c97464175e2c7a384a8f0fb84 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/amd/rs780/gfx.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c index f70cd9b..f4a5120 100644 --- a/src/southbridge/amd/rs780/gfx.c +++ b/src/southbridge/amd/rs780/gfx.c @@ -760,6 +760,24 @@ static void internal_gfx_pci_dev_init(struct device *dev) clkind_write(dev, 0x5C, 0x0); } +/* + * Set registers in RS780 and CPU to disable the internal GFX. + * Please refer to `rs780_internal_gfx_enable()`. + * +*/ +static void rs780_internal_gfx_disable(device_t dev) +{ + u32 l_dword; + device_t nb_dev = dev_find_slot(0, 0); + + /* Disable internal GFX and enable external GFX. */ + l_dword = pci_read_config32(nb_dev, 0x8c); + l_dword |= 1<<0; + l_dword &= ~(1<<1); + pci_write_config32(nb_dev, 0x8c, l_dword); + + dev->enabled = 0; +} /* * Set registers in RS780 and CPU to enable the internal GFX. @@ -999,6 +1017,7 @@ static struct device_operations pcie_ops = { .init = internal_gfx_pci_dev_init, /* The option ROM initializes the device. rs780_gfx_init, */ .scan_bus = 0, .enable = rs780_internal_gfx_enable, + .disable = rs780_internal_gfx_disable, .ops_pci = &lops_pci, };

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Re: [coreboot] new to list
by David Hubbard 30 Dec '12

30 Dec '12

Hi Stuart, On Sat, Dec 29, 2012 at 6:21 AM, Stuart Stevenson <stustev(a)gmail.com> wrote: > Gentlemen, > I am new to this list. > I am looking for a fast boot setup for Linux. > My search leads me to think/hope coreboot has the flexibility to support a > very fast boot time eg 1 to 3 seconds. > > I would like more information than what my searches give me. I you would > be able to point me to further information I would greatly appreciate it. > > thank you > Stuart > Welcome to coreboot! What are your searches? I don't know fully what you need. Do you own a desktop PC or laptop? The type of machine can make a big difference. Coreboot can give you that very fast boot time. But it can also be frustrating if the device isn't supported, so please take a look at for example http://www.coreboot.org/Supported_Motherboards Regards, David

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Feedback On Coreboot: the Solution to the Secure Boot Fiasco
by Rex Djere 30 Dec '12

30 Dec '12

Hello everyone! My name is Rex Djere and I write on GNU/Linux, free sotware, open source, and related topics.Thank you for the wonderful product. I sincerely hope that the pressure being applied by the Free Software Foundation will help Coreboot to be more widely implemented and deployed. I recently wrote an article called Coreboot: the Solution to the Secure Boot Fiasco. You can read it here: http://goo.gl/7fxOx I did a lot of research for the article, and I feel that I got a pretty good picture regarding what happened with AMD, coreboot, and UEFI/secure boot. I am looking for 2 things please: -feedback on whether I got anything egregiously wrong. -help if you agree with my current assessments or after I make any requisite fixes. The help would come in the form of signing the petitions that I cite in the article. Thank you and Happy New Year. Sincerely, Rex Djere

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To be FAM_F or not to be ?
by lautriv 30 Dec '12

30 Dec '12

Hello there, i won't annoy people with my questions here in but some of them in the IRC repeadedly told me to ask the ML. So here we go : On the way of a new/changed port for a Tyan B4882 Mobo which is/was somewhat in the supported list but with a lot of issues ( at lest for me ) i started over and did it from scratch, using parts from serengeti cheetah which is basically the same hardware with another CPU-Socket. The Board in Question will be equipped with 4 dual-cores from type OST880FAA6CC this specific model is a HP-OEM CPU functionally identical to it's OSA sibling but drawing just 68 instead of 95W. it reports as Family 0x0F, Model 0x21, Stepping 0x02 so i did some minor changes ( change Socket, and FAM_F, fake a CPU_SOCKET_TYPE with 0x0a which would be a logical predecessor of 0x10 for Socket_F ) and got an error-free build. However this code can't and won't work because S940 has no DDR2 but DDR and so i get "no RAM" as assumed. Right now i did nothing else enabling all DRAM clocks due to the lack of Documentation for this particular model, the Kernel and Bios Developer Guide for FAM_F does not even mention Socket 940, in particular shown in the functional description from Function2, Offset 0x88 [31:24]. The same Board/CPU boots with a slightly modified s4882 setup from the past which is pre_f, pointing out either this model lacks on some register-changes or it runs in a somewhat compatible mode. on the other hand, the CPU in question and a Socket_F CPU from a different board reporting both the very same " DRAM Controller [1022:1102] ". so my final "real Question" is : can anyone tell/provide more details/links/specs/whitepapers/whatever to shed some light in this dark place ? P.S: from certain readings, this may also affect single-cores from 852 and above because a bunch of Boards did not even boot them without a bios-change, if i did not mix something up, we are talking about a 90nm Italy/Egypt core with Rev. E6+. PPS: I wish all a happy new year in a few days ;)

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Patch merged into coreboot/master: 9a0e3e2 M4A785T-M: Add support for external GFX.
by gerrit＠coreboot.org 30 Dec '12

30 Dec '12

the following patch was just integrated into master: commit 9a0e3e2fc205381746875bee5296777b608bea54 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu Dec 20 18:45:53 2012 +0100 M4A785T-M: Add support for external GFX. This commit enables the external graphics card. In order to work, the internal graphic card has to be disabled, that is done in src/device/device.c through: vga_onboard->ops->disable(vga_onboard); which calls the RS780 disable operation introduced in the following commit: "rs780: add .disable pcie_ops" This commit was tested with and without the following card: 02:00.0 VGA compatible controller: nVidia Corporation GT218 [GeForce 210] (rev a2) Thanks Aladyshev for the pointer(in the #coreboot IRC channel on Freenode servers): Dec 20 19:43:32 <Aladyshev> If you list your internal card in devicetree.cb, coreboot will distinguish external and internal VGA and choose external one Change-Id: I92e59dffd158db096a6e99d1ef6e2e248fef933c Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Reviewed-on: http://review.coreboot.org/2067 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Sat Dec 29 20:46:34 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Sun Dec 30 03:25:33 2012, giving +2 See http://review.coreboot.org/2067 for details. -gerrit

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Re: [coreboot] Asus F2A85-M progress
by Rudolf Marek 30 Dec '12

30 Dec '12

> I checked the bootlog.txt and I see cmd gets 3 and 2 for the on-board VGA, Bus > Mastering is never enabled by coreboot. Is 7 the right value? Why does the > bootlog say this: > > PCI: 01:00.0 cmd <- 03 > PCI: 01:00.1 cmd <- 02 Yes but in reality the IO decode is not set for some reason. OK, so it works for you without the patch? > The linux messages are odd, since coreboot does assign the resources to the > devices correctly. Maybe something is changing the PCI-PCI bridge windows after > coreboot is done? Like, maybe, seabios? Just a guess :) No seabios is not reconfiguring PCI if set to coreboot. > I don't know about the HD Audio problem. OK, please tell what works for you! For a reference here is current list: http://www.coreboot.org/ASUS_F2A85-M Thanks Rudolf

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Patch set updated for coreboot: da1b9dd rs780: add .disable pcie_ops
by Denis Carikli 29 Dec '12

29 Dec '12

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2065 -gerrit commit da1b9ddec39b0dc1dfda76dabc0568d47e942183 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu Dec 20 18:42:00 2012 +0100 rs780: add .disable pcie_ops That code will be used to disable the internal GFX card and enable the external PCIe CARD. It has been tested on the M4A785T-M with the following card inside the PCIe 16x slot: 02:00.0 VGA compatible controller: nVidia Corporation GT218 [GeForce 210] (rev a2) Change-Id: I7bd412b987fde98c97464175e2c7a384a8f0fb84 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/southbridge/amd/rs780/gfx.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c index f70cd9b..eb85d01 100644 --- a/src/southbridge/amd/rs780/gfx.c +++ b/src/southbridge/amd/rs780/gfx.c @@ -760,6 +760,20 @@ static void internal_gfx_pci_dev_init(struct device *dev) clkind_write(dev, 0x5C, 0x0); } +/* Disable internal GFX and Enable external GFX. */ +static void rs780_internal_gfx_disable(device_t dev) +{ + u32 l_dword; + device_t nb_dev = dev_find_slot(0, 0); + + /* Disable external GFX and enable internal GFX. */ + l_dword = pci_read_config32(nb_dev, 0x8c); + l_dword |= 1<<0; + l_dword &= ~(1<<1); + pci_write_config32(nb_dev, 0x8c, l_dword); + + dev->enabled = 0; +} /* * Set registers in RS780 and CPU to enable the internal GFX. @@ -999,6 +1013,7 @@ static struct device_operations pcie_ops = { .init = internal_gfx_pci_dev_init, /* The option ROM initializes the device. rs780_gfx_init, */ .scan_bus = 0, .enable = rs780_internal_gfx_enable, + .disable = rs780_internal_gfx_disable, .ops_pci = &lops_pci, };

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Patch set updated for coreboot: dacb01e M4A785T-M: Add support for external GFX.
by Denis Carikli 29 Dec '12

29 Dec '12

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2067 -gerrit commit dacb01e3033f2de9ced95f855d8edd31ce21bc06 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu Dec 20 18:45:53 2012 +0100 M4A785T-M: Add support for external GFX. This commit enables the external graphics card. In order to work, the internal graphic card has to be disabled, that is done in src/device/device.c through: vga_onboard->ops->disable(vga_onboard); which calls the RS780 disable operation introduced in the following commit: "rs780: add .disable pcie_ops" This commit was tested with and without the following card: 02:00.0 VGA compatible controller: nVidia Corporation GT218 [GeForce 210] (rev a2) Thanks Aladyshev for the pointer(in the #coreboot IRC channel on Freenode servers): Dec 20 19:43:32 <Aladyshev> If you list your internal card in devicetree.cb, coreboot will distinguish external and internal VGA and choose external one Change-Id: I92e59dffd158db096a6e99d1ef6e2e248fef933c Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/asus/m4a785t-m/devicetree.cb | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/mainboard/asus/m4a785t-m/devicetree.cb b/src/mainboard/asus/m4a785t-m/devicetree.cb index e8764b1..0299fc2 100644 --- a/src/mainboard/asus/m4a785t-m/devicetree.cb +++ b/src/mainboard/asus/m4a785t-m/devicetree.cb @@ -10,8 +10,10 @@ chip northbridge/amd/amdfam10/root_complex device pci 18.0 on # northbridge chip southbridge/amd/rs780 device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 off end # PCIE P2P bridge (external graphics) 0x9603 + device pci 1.0 on # Internal Graphics P2P bridge 0x9602 + device pci 5.0 on end # onboard VGA + end + device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 device pci 3.0 off end # PCIE P2P bridge 0x960b device pci 4.0 off end # PCIE P2P bridge 0x9604 device pci 5.0 off end # PCIE P2P bridge 0x9605 @@ -24,7 +26,7 @@ chip northbridge/amd/amdfam10/root_complex register "gpp_configuration" = "3" # Configuration D default register "port_enable" = "0x6fc" register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "2" + register "gfx_dual_slot" = "0" register "gfx_lane_reversal" = "0" register "gfx_tmds" = "0"

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Patch merged into coreboot/master: 6c6b2e8 Add AMD Hudson blobs by CONFIG_REQUIRES_BLOBS dependency
by gerrit＠coreboot.org 29 Dec '12

29 Dec '12

the following patch was just integrated into master: commit 6c6b2e8cba863cb39c82ee269c84a32f085c1a19 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Thu Dec 27 15:23:03 2012 -0700 Add AMD Hudson blobs by CONFIG_REQUIRES_BLOBS dependency If a 3rd party blob option is selected, make sure that it makes the user select CONFIG_USE_BLOBS as otherwise the build will fail. Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Change-Id: I04429f23137946525c8577dd9c979bd4a0d17cdc Reviewed-on: http://review.coreboot.org/2080 Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Dec 28 23:28:54 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Sat Dec 29 18:35:14 2012, giving +2 See http://review.coreboot.org/2080 for details. -gerrit

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coreboot December 2012