coreboot December 2012

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Patch set updated for coreboot: fac2629 AGESA: Use `Flag=AGESA_SUCCESS` instead of `TRUE` in DMI related functions
by Paul Menzel 21 Dec '12

21 Dec '12

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2070 -gerrit commit fac2629e57267b8d6b9c193df3afc2e5304547cb Author: Aladyshev Konstantin <aladyshev(a)nicevt.ru> Date: Wed Dec 19 09:31:01 2012 +0400 AGESA: Use `Flag=AGESA_SUCCESS` instead of `TRUE` in DMI related functions Success return value in DMI functions GetDmiInfoMain(..) and GetType4Type7Info(...) of AGESA vendorcode is "Flag = TRUE". This results in a failure of init late function: "agesawrapper_amdinitlate failed: 1" It happens because TRUE = 1 = AGESA_UNSUPPORTED. Replacing TRUE with AGESA_SUCCESS (= 0) fixes this problem. Only family f15tn does not have such bug. This patch just replaces TRUE with AGESA_SUCCESS, but maybe all DMI functions should be copied from Trinity family? Tested on Supermicro H8QGI board with 4 AMD Opteron 6234 processors (f15). Change-Id: I51bf91333c088a825b92d4a44d1ebe4380c8026c Signed-off-by: Aladyshev Konstantin <aladyshev(a)nicevt.ru> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuDmi.c | 4 ++-- src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuDmi.c | 4 ++-- src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuDmi.c | 4 ++-- src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuDmi.c | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuDmi.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuDmi.c index 9e7ea86..2496779 100644 --- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuDmi.c +++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuDmi.c @@ -206,7 +206,7 @@ GetDmiInfoMain ( LOCATE_HEAP_PTR LocateHeapParams; MsrData = 0; - Flag = TRUE; + Flag = AGESA_SUCCESS; DmiBufferPtr = *DmiTable; if (DmiBufferPtr == NULL) { // @@ -387,7 +387,7 @@ GetType4Type7Info ( PROC_FAMILY_TABLE *ProcData; CPU_LOGICAL_ID LogicalID; - Flag = TRUE; + Flag = AGESA_SUCCESS; DmiBufferPtr = (DMI_INFO *) ApExeParams->RelatedDataBlock; GetLogicalIdOfCurrentCore (&LogicalID, &ApExeParams->StdHeader); diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuDmi.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuDmi.c index 60095d0..999ccf5 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuDmi.c +++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuDmi.c @@ -216,7 +216,7 @@ GetDmiInfoMain ( CPU_GET_MEM_INFO CpuGetMemInfo; MsrData = 0; - Flag = TRUE; + Flag = AGESA_SUCCESS; ProcData = NULL; MemInfo = NULL; DmiBufferPtr = *DmiTable; @@ -415,7 +415,7 @@ GetType4Type7Info ( PROC_FAMILY_TABLE *ProcData; CPU_LOGICAL_ID LogicalID; - Flag = TRUE; + Flag = AGESA_SUCCESS; DmiBufferPtr = (DMI_INFO *) ApExeParams->RelatedDataBlock; GetLogicalIdOfCurrentCore (&LogicalID, &ApExeParams->StdHeader); diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuDmi.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuDmi.c index 0bf357d..b816732 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuDmi.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuDmi.c @@ -220,7 +220,7 @@ GetDmiInfoMain ( CPU_GET_MEM_INFO CpuGetMemInfo; MsrData = 0; - Flag = TRUE; + Flag = AGESA_SUCCESS; ProcData = NULL; MemInfo = NULL; DmiBufferPtr = *DmiTable; @@ -429,7 +429,7 @@ GetType4Type7Info ( PROC_FAMILY_TABLE *ProcData; CPU_LOGICAL_ID LogicalID; - Flag = TRUE; + Flag = AGESA_SUCCESS; DmiBufferPtr = (DMI_INFO *) ApExeParams->RelatedDataBlock; GetLogicalIdOfCurrentCore (&LogicalID, &ApExeParams->StdHeader); diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuDmi.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuDmi.c index 5619df3..2385752 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuDmi.c +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuDmi.c @@ -219,7 +219,7 @@ GetDmiInfoMain ( CPU_GET_MEM_INFO CpuGetMemInfo; MsrData = 0; - Flag = TRUE; + Flag = AGESA_SUCCESS; ProcData = NULL; MemInfo = NULL; DmiBufferPtr = *DmiTable; @@ -439,7 +439,7 @@ GetType4Type7Info ( CPU_LOGICAL_ID LogicalID; UINT8 L3Associativity; - Flag = TRUE; + Flag = AGESA_SUCCESS; DmiBufferPtr = (DMI_INFO *) ApExeParams->RelatedDataBlock; GetLogicalIdOfCurrentCore (&LogicalID, &ApExeParams->StdHeader);

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Patch merged into coreboot/master: ceb82da add a return type to test function used by xcompile
by gerrit＠coreboot.org 21 Dec '12

21 Dec '12

the following patch was just integrated into master: commit ceb82da99f9b9bc0629b6e3689dd19c988f4cd0b Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Dec 20 14:24:08 2012 -0800 add a return type to test function used by xcompile This fixes a minor bug that could cause testcc to fail unexpectedly. Change-Id: Ib75d343104b6937682c05acf5232596aac83f105 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2068 Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Fri Dec 21 18:21:06 2012, giving +1 Reviewed-By: David Hendricks <dhendrix(a)chromium.org> at Fri Dec 21 20:18:31 2012, giving +2 See http://review.coreboot.org/2068 for details. -gerrit

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Patch set updated for coreboot: 91a42c6 AGESA: Fix bug in DMI related functions
by Aladyshev Konstantin 21 Dec '12

21 Dec '12

Aladyshev Konstantin (kostr(a)list.ru) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2070 -gerrit commit 91a42c6c8713b38e0bcda00f150d56efb7a54698 Author: Aladyshev Konstantin <aladyshev(a)nicevt.ru> Date: Wed Dec 19 09:31:01 2012 +0400 AGESA: Fix bug in DMI related functions Success return value in DMI functions GetDmiInfoMain(..) and GetType4Type7Info(...) of AGESA vendorcode is "Flag=TRUE" This results fail of init late function: "agesawrapper_amdinitlate failed: 1" It happens because TRUE = 1 = AGESA_UNSUPPORTED. Replacing TRUE with AGESA_SUCCESS (=0) fix this problem. Only family f15tn haven't such bug. This patch just replaces TRUE with AGESA_SUCCESS, but maybe all DMI functions should be copied from trinity family? Tested on Supermicro H8QGI board with 4 AMD Opteron 6234 processors (f15) Change-Id: I51bf91333c088a825b92d4a44d1ebe4380c8026c Signed-off-by: Aladyshev Konstantin <aladyshev(a)nicevt.ru> --- src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuDmi.c | 4 ++-- src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuDmi.c | 4 ++-- src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuDmi.c | 4 ++-- src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuDmi.c | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuDmi.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuDmi.c index 9e7ea86..2496779 100644 --- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuDmi.c +++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuDmi.c @@ -206,7 +206,7 @@ GetDmiInfoMain ( LOCATE_HEAP_PTR LocateHeapParams; MsrData = 0; - Flag = TRUE; + Flag = AGESA_SUCCESS; DmiBufferPtr = *DmiTable; if (DmiBufferPtr == NULL) { // @@ -387,7 +387,7 @@ GetType4Type7Info ( PROC_FAMILY_TABLE *ProcData; CPU_LOGICAL_ID LogicalID; - Flag = TRUE; + Flag = AGESA_SUCCESS; DmiBufferPtr = (DMI_INFO *) ApExeParams->RelatedDataBlock; GetLogicalIdOfCurrentCore (&LogicalID, &ApExeParams->StdHeader); diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuDmi.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuDmi.c index 60095d0..999ccf5 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuDmi.c +++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuDmi.c @@ -216,7 +216,7 @@ GetDmiInfoMain ( CPU_GET_MEM_INFO CpuGetMemInfo; MsrData = 0; - Flag = TRUE; + Flag = AGESA_SUCCESS; ProcData = NULL; MemInfo = NULL; DmiBufferPtr = *DmiTable; @@ -415,7 +415,7 @@ GetType4Type7Info ( PROC_FAMILY_TABLE *ProcData; CPU_LOGICAL_ID LogicalID; - Flag = TRUE; + Flag = AGESA_SUCCESS; DmiBufferPtr = (DMI_INFO *) ApExeParams->RelatedDataBlock; GetLogicalIdOfCurrentCore (&LogicalID, &ApExeParams->StdHeader); diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuDmi.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuDmi.c index 0bf357d..b816732 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuDmi.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuDmi.c @@ -220,7 +220,7 @@ GetDmiInfoMain ( CPU_GET_MEM_INFO CpuGetMemInfo; MsrData = 0; - Flag = TRUE; + Flag = AGESA_SUCCESS; ProcData = NULL; MemInfo = NULL; DmiBufferPtr = *DmiTable; @@ -429,7 +429,7 @@ GetType4Type7Info ( PROC_FAMILY_TABLE *ProcData; CPU_LOGICAL_ID LogicalID; - Flag = TRUE; + Flag = AGESA_SUCCESS; DmiBufferPtr = (DMI_INFO *) ApExeParams->RelatedDataBlock; GetLogicalIdOfCurrentCore (&LogicalID, &ApExeParams->StdHeader); diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuDmi.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuDmi.c index 5619df3..2385752 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuDmi.c +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuDmi.c @@ -219,7 +219,7 @@ GetDmiInfoMain ( CPU_GET_MEM_INFO CpuGetMemInfo; MsrData = 0; - Flag = TRUE; + Flag = AGESA_SUCCESS; ProcData = NULL; MemInfo = NULL; DmiBufferPtr = *DmiTable; @@ -439,7 +439,7 @@ GetType4Type7Info ( CPU_LOGICAL_ID LogicalID; UINT8 L3Associativity; - Flag = TRUE; + Flag = AGESA_SUCCESS; DmiBufferPtr = (DMI_INFO *) ApExeParams->RelatedDataBlock; GetLogicalIdOfCurrentCore (&LogicalID, &ApExeParams->StdHeader);

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New patch to review for coreboot: a63361e AGESA: Fix bug in DMI related functions
by Aladyshev Konstantin 21 Dec '12

21 Dec '12

Aladyshev Konstantin (kostr(a)list.ru) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2070 -gerrit commit a63361e22f166515a7c00d70e558a27435b3bc2f Author: Aladyshev Konstantin <aladyshev(a)nicevt.ru> Date: Wed Dec 19 09:31:01 2012 +0400 AGESA: Fix bug in DMI related functions Success return value in DMI functions GetDmiInfoMain(..) and GetType4Type7Info(...) of AGESA vendorcode is "Flag=TRUE" This results fail of init late function: "agesawrapper_amdinitlate failed: 1" It happens because TRUE = 1 = AGESA_UNSUPPORTED. Replacing TRUE with AGESA_SUCCESS (=0) fix this problem. Only family f15tn haven't such bug. This patch just replaces TRUE with AGESA_SUCCESS, but maybe all DMI functions should be copied from trinity family? Tested on Supermicro Board with 4 AMD Opteron 6234 processors (f15) Change-Id: I51bf91333c088a825b92d4a44d1ebe4380c8026c Signed-off-by: Aladyshev Konstantin <aladyshev(a)nicevt.ru> --- src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuDmi.c | 4 ++-- src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuDmi.c | 4 ++-- src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuDmi.c | 4 ++-- src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuDmi.c | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuDmi.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuDmi.c index 9e7ea86..2496779 100644 --- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuDmi.c +++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuDmi.c @@ -206,7 +206,7 @@ GetDmiInfoMain ( LOCATE_HEAP_PTR LocateHeapParams; MsrData = 0; - Flag = TRUE; + Flag = AGESA_SUCCESS; DmiBufferPtr = *DmiTable; if (DmiBufferPtr == NULL) { // @@ -387,7 +387,7 @@ GetType4Type7Info ( PROC_FAMILY_TABLE *ProcData; CPU_LOGICAL_ID LogicalID; - Flag = TRUE; + Flag = AGESA_SUCCESS; DmiBufferPtr = (DMI_INFO *) ApExeParams->RelatedDataBlock; GetLogicalIdOfCurrentCore (&LogicalID, &ApExeParams->StdHeader); diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuDmi.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuDmi.c index 60095d0..999ccf5 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuDmi.c +++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuDmi.c @@ -216,7 +216,7 @@ GetDmiInfoMain ( CPU_GET_MEM_INFO CpuGetMemInfo; MsrData = 0; - Flag = TRUE; + Flag = AGESA_SUCCESS; ProcData = NULL; MemInfo = NULL; DmiBufferPtr = *DmiTable; @@ -415,7 +415,7 @@ GetType4Type7Info ( PROC_FAMILY_TABLE *ProcData; CPU_LOGICAL_ID LogicalID; - Flag = TRUE; + Flag = AGESA_SUCCESS; DmiBufferPtr = (DMI_INFO *) ApExeParams->RelatedDataBlock; GetLogicalIdOfCurrentCore (&LogicalID, &ApExeParams->StdHeader); diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuDmi.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuDmi.c index 0bf357d..b816732 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuDmi.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuDmi.c @@ -220,7 +220,7 @@ GetDmiInfoMain ( CPU_GET_MEM_INFO CpuGetMemInfo; MsrData = 0; - Flag = TRUE; + Flag = AGESA_SUCCESS; ProcData = NULL; MemInfo = NULL; DmiBufferPtr = *DmiTable; @@ -429,7 +429,7 @@ GetType4Type7Info ( PROC_FAMILY_TABLE *ProcData; CPU_LOGICAL_ID LogicalID; - Flag = TRUE; + Flag = AGESA_SUCCESS; DmiBufferPtr = (DMI_INFO *) ApExeParams->RelatedDataBlock; GetLogicalIdOfCurrentCore (&LogicalID, &ApExeParams->StdHeader); diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuDmi.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuDmi.c index 5619df3..2385752 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuDmi.c +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuDmi.c @@ -219,7 +219,7 @@ GetDmiInfoMain ( CPU_GET_MEM_INFO CpuGetMemInfo; MsrData = 0; - Flag = TRUE; + Flag = AGESA_SUCCESS; ProcData = NULL; MemInfo = NULL; DmiBufferPtr = *DmiTable; @@ -439,7 +439,7 @@ GetType4Type7Info ( CPU_LOGICAL_ID LogicalID; UINT8 L3Associativity; - Flag = TRUE; + Flag = AGESA_SUCCESS; DmiBufferPtr = (DMI_INFO *) ApExeParams->RelatedDataBlock; GetLogicalIdOfCurrentCore (&LogicalID, &ApExeParams->StdHeader);

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Patch set updated for coreboot: 23eb3fb add a return type to test function used by xcompile
by Ronald G. Minnich 21 Dec '12

21 Dec '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2068 -gerrit commit 23eb3fbf9afbc0471efd0e1615e570272b0db734 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Dec 20 14:24:08 2012 -0800 add a return type to test function used by xcompile This fixes a minor bug that could cause testcc to fail unexpectedly. Change-Id: Ib75d343104b6937682c05acf5232596aac83f105 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- util/xcompile/xcompile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index fdc5213..4239176 100644 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -40,7 +40,7 @@ testcc() { local tmp_c="$TMPFILE.c" local tmp_o="$TMPFILE.o" rm -f "$tmp_c" "$tmp_o" - echo "_start(void) {}" >"$tmp_c" + echo "void _start(void) {}" >"$tmp_c" "$1" -nostdlib -Werror $2 "$tmp_c" -o "$tmp_o" >/dev/null 2>&1 }

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Patch merged into coreboot/master: ec3daf7 Supermicro H8QGI: Fix routing from 16 to 55 in ACPI table
by gerrit＠coreboot.org 21 Dec '12

21 Dec '12

the following patch was just integrated into master: commit ec3daf7e08b4c42b45fc2c84b92820af6688e11b Author: Aladyshev Konstantin <aladyshev(a)nicevt.ru> Date: Tue Dec 18 23:15:55 2012 +0400 Supermicro H8QGI: Fix routing from 16 to 55 in ACPI table H8QGI board has 2 IO-APICS with 56 IRQ’s: IOAPIC[0]: GSI 0-23 - SB700 southbridge IOAPIC[1]: GSI 24-55 - RD890 northbridge `gDefaultApicDeviceInfoTable[]` structure in northbridge code vendorcode/amd/cimx/rd890/nbIoApic.c has IO-APIC interrupt mapping for HT and IOMMU set to last 31 IRQ pin (24+31=55). CONST APIC_DEVICE_INFO gDefaultApicDeviceInfoTable[] = { // Group Swizzling Port Int Pin {0, 0, 31}, //HT {0, 0, 31}, //IOMMU […] Also the same value (55) can be found in original Supermicro BIOS ACPI DSDT. Change-Id: Ie26da1f773716d1b7f5f5f884050ae799afc0b7e Signed-off-by: Aladyshev Konstantin <aladyshev(a)nicevt.ru> Reviewed-on: http://review.coreboot.org/2047 Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao(a)amd.com> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Dec 19 23:19:48 2012, giving +1 Reviewed-By: Zheng Bao <zheng.bao(a)amd.com> at Thu Dec 20 10:59:00 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Fri Dec 21 15:43:38 2012, giving +2 See http://review.coreboot.org/2047 for details. -gerrit

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New patch to review for coreboot: 2b607f7 add a return type to test function used by xcompile
by David Hendricks 20 Dec '12

20 Dec '12

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2068 -gerrit commit 2b607f79fca8400bc5c7730b7d60e6dc23b02151 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Dec 20 14:24:08 2012 -0800 add a return type to test function used by xcompile This fixes a minor bug that could cause testcc to fail unexpectedly. Change-Id: Ib75d343104b6937682c05acf5232596aac83f105 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- util/xcompile/xcompile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index fdc5213..4239176 100644 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -40,7 +40,7 @@ testcc() { local tmp_c="$TMPFILE.c" local tmp_o="$TMPFILE.o" rm -f "$tmp_c" "$tmp_o" - echo "_start(void) {}" >"$tmp_c" + echo "void _start(void) {}" >"$tmp_c" "$1" -nostdlib -Werror $2 "$tmp_c" -o "$tmp_o" >/dev/null 2>&1 }

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Re: [coreboot] Asus F2A85-M progress
by Peter Stuge 20 Dec '12

20 Dec '12

Andrey Gursky wrote: > It turned out that I've made not the best choice of my gigabyte dual > bios AM3+-motherboard, because they have changed the procedure of BIOS > restoring from manual user controlled to automatic. And I couldn't > find yet any information where this automatic is located. They have a patent which describes how it works. A separate chip needs firmware to perform a special handshake before a timer expires, at which point the system is reset and the backup flash chip is activated. > Maybe it would be possible to workaround it. You can lift the chip select pins from the mainboard and solder in a switch. Something corresponding to what is described as the simple modification at http://stuge.se/m57sli/ //Peter

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Patch set updated for coreboot: ae62dec M4A785T-M: Add support for external GFX.
by Denis Carikli 20 Dec '12

20 Dec '12

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2067 -gerrit commit ae62decb3cf719e497e725d0829e9a8008b24b32 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu Dec 20 18:45:53 2012 +0100 M4A785T-M: Add support for external GFX. This commit enables the external graphics card. In order to work, the internal graphic card has to be disabled, that is done in src/device/device.c trough: vga_onboard->ops->disable(vga_onboard); which calls the RS780 disable operation introduced in the following commit: "rs780: add .disable pcie_ops" This commit was tested with and without the following card: 02:00.0 VGA compatible controller: nVidia Corporation GT218 [GeForce 210] (rev a2) Thanks Aladyshev for the pointer(in the #coreboot IRC channel on Freenode servers): Dec 20 19:43:32 <Aladyshev> If you list your internal card in devicetree.cb, coreboot will distinguish external and internal VGA and choose external one Change-Id: I92e59dffd158db096a6e99d1ef6e2e248fef933c Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/asus/m4a785t-m/devicetree.cb | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/mainboard/asus/m4a785t-m/devicetree.cb b/src/mainboard/asus/m4a785t-m/devicetree.cb index e8764b1..0299fc2 100644 --- a/src/mainboard/asus/m4a785t-m/devicetree.cb +++ b/src/mainboard/asus/m4a785t-m/devicetree.cb @@ -10,8 +10,10 @@ chip northbridge/amd/amdfam10/root_complex device pci 18.0 on # northbridge chip southbridge/amd/rs780 device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 off end # PCIE P2P bridge (external graphics) 0x9603 + device pci 1.0 on # Internal Graphics P2P bridge 0x9602 + device pci 5.0 on end # onboard VGA + end + device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 device pci 3.0 off end # PCIE P2P bridge 0x960b device pci 4.0 off end # PCIE P2P bridge 0x9604 device pci 5.0 off end # PCIE P2P bridge 0x9605 @@ -24,7 +26,7 @@ chip northbridge/amd/amdfam10/root_complex register "gpp_configuration" = "3" # Configuration D default register "port_enable" = "0x6fc" register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "2" + register "gfx_dual_slot" = "0" register "gfx_lane_reversal" = "0" register "gfx_tmds" = "0"

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New patch to review for coreboot: c2cab04 M4A785T-M: Add support for external GFX.
by Denis Carikli 20 Dec '12

20 Dec '12

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2067 -gerrit commit c2cab0446e67f997b027ac2af52b53ad4a40b416 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu Dec 20 18:45:53 2012 +0100 M4A785T-M: Add support for external GFX. This commit enables the external graphics card. In order to work, the internal graphic card has to be disabled, that is done in src/device/device.c trough: vga_onboard->ops->disable(vga_onboard); which calls the RS780 disable operation introduced in the following commit: "rs780: add .disable pcie_ops" Change-Id: I92e59dffd158db096a6e99d1ef6e2e248fef933c Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/asus/m4a785t-m/devicetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/asus/m4a785t-m/devicetree.cb b/src/mainboard/asus/m4a785t-m/devicetree.cb index e8764b1..905e5d3 100644 --- a/src/mainboard/asus/m4a785t-m/devicetree.cb +++ b/src/mainboard/asus/m4a785t-m/devicetree.cb @@ -11,7 +11,7 @@ chip northbridge/amd/amdfam10/root_complex chip southbridge/amd/rs780 device pci 0.0 on end # HT 0x9600 device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 off end # PCIE P2P bridge (external graphics) 0x9603 + device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 device pci 3.0 off end # PCIE P2P bridge 0x960b device pci 4.0 off end # PCIE P2P bridge 0x9604 device pci 5.0 off end # PCIE P2P bridge 0x9605 @@ -24,7 +24,7 @@ chip northbridge/amd/amdfam10/root_complex register "gpp_configuration" = "3" # Configuration D default register "port_enable" = "0x6fc" register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "2" + register "gfx_dual_slot" = "0" register "gfx_lane_reversal" = "0" register "gfx_tmds" = "0"

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coreboot December 2012