coreboot November 2012

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Patch set updated for coreboot: 147feef SPI/SST: Add OpCode Enable-Write-Status-Register (EWSR)
by Zheng Bao 27 Nov '12

27 Nov '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1919 -gerrit commit 147feef76f425ef3836ec85d734a44ccb28230d6 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Tue Nov 27 16:52:41 2012 +0800 SPI/SST: Add OpCode Enable-Write-Status-Register (EWSR) For SST chips, The Write-Status-Register instruction must be executed immediately after the execution of the Enable-Write-Status-Register instruction, instead of Write-Enable. Change-Id: I4b3473cd671829def3bd1641ececcf8d9dad4a56 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/drivers/spi/sst.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c index 8245f72..ebeb441 100644 --- a/src/drivers/spi/sst.c +++ b/src/drivers/spi/sst.c @@ -20,6 +20,7 @@ #define CMD_SST_WRDI 0x04 /* Write Disable */ #define CMD_SST_RDSR 0x05 /* Read Status Register */ #define CMD_SST_WRSR 0x01 /* Write Status Register */ +#define CMD_SST_EWSR 0x50 /* Enable Write Status Register */ #define CMD_SST_READ 0x03 /* Read Data Bytes */ #define CMD_SST_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ #define CMD_SST_BP 0x02 /* Byte Program */ @@ -101,6 +102,15 @@ sst_enable_writing(struct spi_flash *flash) } static int +sst_enable_writing_status(struct spi_flash *flash) +{ + int ret = spi_flash_cmd(flash->spi, CMD_SST_EWSR, NULL, 0); + if (ret) + printk(BIOS_WARNING, "SF: Enabling Write Status failed\n"); + return ret; +} + +static int sst_disable_writing(struct spi_flash *flash) { int ret = spi_flash_cmd(flash->spi, CMD_SST_WRDI, NULL, 0); @@ -212,7 +222,7 @@ sst_unlock(struct spi_flash *flash) int ret; u8 cmd, status; - ret = sst_enable_writing(flash); + ret = sst_enable_writing_status(flash); if (ret) return ret;

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Patch merged into coreboot/master: 536b53e xcompile: Add missing XGCCPATH
by gerrit＠coreboot.org 27 Nov '12

27 Nov '12

the following patch was just integrated into master: commit 536b53ea6daf23d7c09a35f5633f06e604a64e20 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Tue Nov 27 17:07:22 2012 +0800 xcompile: Add missing XGCCPATH XGCCPATH is missing in new xcompile. Change-Id: I177f54189be445404a4a61419064d3c414b8a30c Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> Reviewed-on: http://review.coreboot.org/1921 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Tue Nov 27 09:22:10 2012, giving +2 See http://review.coreboot.org/1921 for details. -gerrit

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Patch merged into coreboot/master: 021b703 roda/rk9: New mainboard
by gerrit＠coreboot.org 27 Nov '12

27 Nov '12

the following patch was just integrated into master: commit 021b7033fb578258844bf8ecad9f2d34b16b674b Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Nov 6 11:05:38 2012 +0100 roda/rk9: New mainboard Roda RK9 is a notebook based on the GM45/ICH9 platform using DDR3 memory. http://roda-computer.com/products/notebooks/rk9/ Tested with various Linux versions, known to work: - 2x4GB RAM - IGD - HD Audio - UHCI, EHCI - AHCI - NIC - PCI - PS/2 keyboard - serial console - ACPI lid switch - ACPI battery/AC events - power off, reboot Change-Id: I7299dccbff2eea3544363fdd4f49f05aa3dae7bc Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: http://review.coreboot.org/1691 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Tue Nov 27 09:17:05 2012, giving +2 See http://review.coreboot.org/1691 for details. -gerrit

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Patch merged into coreboot/master: e72a8a3 intel/i82801ix: new southbridge, ICH9
by gerrit＠coreboot.org 27 Nov '12

27 Nov '12

the following patch was just integrated into master: commit e72a8a3047c535bda03aecce2eca134608d1a93c Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Nov 6 11:05:09 2012 +0100 intel/i82801ix: new southbridge, ICH9 Add support for ICH9 southbridge Change-Id: I70612431101bf48d9dcc96ee1b37d257c9ad2ee2 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: http://review.coreboot.org/1690 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Tue Nov 27 09:16:58 2012, giving +2 See http://review.coreboot.org/1690 for details. -gerrit

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Patch merged into coreboot/master: 2efc880 intel/gm45: new northbridge
by gerrit＠coreboot.org 27 Nov '12

27 Nov '12

the following patch was just integrated into master: commit 2efc8808b8bfaee0a0e8f3ee387ecd9a3f049705 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Nov 6 11:03:53 2012 +0100 intel/gm45: new northbridge The code supports DDR3 boards only. RAM init for DDR2 is sufficiently different that it requires separate code, and we have no boards to test that. Change-Id: I9076546faf8a2033c89eb95f5eec524439ab9fe1 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: http://review.coreboot.org/1689 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/1689 for details. -gerrit

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Patch merged into coreboot/master: acd7d95 Add initialization hook for chips
by gerrit＠coreboot.org 27 Nov '12

27 Nov '12

the following patch was just integrated into master: commit acd7d952514485dbc41fa04b0d16be4002e31019 Author: Nico Huber <nico.huber(a)secunet.com> Date: Wed Jul 25 10:33:05 2012 +0200 Add initialization hook for chips Add an init() function to the chip_operations which will be called before bus enumeration. This allows to disable unused devices before they get enumerated. Change-Id: I63dd9cbfc7b5995ccafb7bf7a81dc71fc67906a0 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: http://review.coreboot.org/1623 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Marc Jones <marcj303(a)gmail.com> Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Tue Nov 27 09:16:03 2012, giving +2 See http://review.coreboot.org/1623 for details. -gerrit

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Patch set updated for coreboot: 45d5043 AMD S3: Leverage the public SPI routine
by Zheng Bao 27 Nov '12

27 Nov '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1920 -gerrit commit 45d5043969a4ad47af2482dbfbaeca0c3a9d1806 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Tue Nov 27 17:43:24 2012 +0800 AMD S3: Leverage the public SPI routine Remove the old, unflexible code for storing data in SPI flash. Change-Id: I60a10476befb4afab2b4241f01a988f4a8bb22cd Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/cpu/amd/agesa/s3_resume.c | 88 ++++++------- src/southbridge/amd/Kconfig | 4 + src/southbridge/amd/agesa/hudson/spi.c | 234 ++++++++++----------------------- src/southbridge/amd/agesa/hudson/spi.h | 43 ------ src/southbridge/amd/cimx/sb800/spi.c | 230 ++++++++++---------------------- src/southbridge/amd/cimx/sb800/spi.h | 42 ------ 6 files changed, 183 insertions(+), 458 deletions(-) diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 0348a9f..6302c3d 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -41,7 +41,8 @@ #include "agesawrapper.h" #ifndef __PRE_RAM__ -#include "spi.h" +#include <spi.h> +#include <spi_flash.h> #endif void restore_mtrr(void) @@ -151,14 +152,18 @@ void move_stack_high_mem(void) void OemAgesaSaveMtrr(void) { #ifndef __PRE_RAM__ - u32 spi_address; msr_t msr_data; - device_t dev; u32 nvram_pos = S3_DATA_MTRR_POS; u32 i; + struct spi_flash *flash; - dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); - spi_address = pci_read_config32(dev, 0xA0) & ~0x1F; + spi_init(); + + flash = spi_flash_probe(0, 0, 0, 0); + if (!flash) { + printk(BIOS_DEBUG, "Could not find SPI device\n"); + return; + } /* Enable access to AMD RdDram and WrDram extension bits */ msr_data = rdmsr(SYS_CFG); @@ -167,28 +172,29 @@ void OemAgesaSaveMtrr(void) /* Fixed MTRRs */ msr_data = rdmsr(0x250); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; msr_data = rdmsr(0x258); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; msr_data = rdmsr(0x259); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; for (i = 0x268; i < 0x270; i++) { msr_data = rdmsr(i); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; } @@ -200,35 +206,33 @@ void OemAgesaSaveMtrr(void) /* Variable MTRRs */ for (i = 0x200; i < 0x210; i++) { msr_data = rdmsr(i); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; } /* SYS_CFG */ msr_data = rdmsr(0xC0010010); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; /* TOM */ msr_data = rdmsr(0xC001001A); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; /* TOM2 */ msr_data = rdmsr(0xC001001D); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; - write_spi_status((u8 *)spi_address, 0x3c); - spi_write_disable((u8 *) spi_address); #endif } @@ -251,9 +255,9 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) { u32 pos = S3_DATA_VOLATILE_POS; - u32 spi_address, data; + u32 data; u32 nvram_pos; - device_t dev; + struct spi_flash *flash; if (S3DataType == S3DataTypeNonVolatile) { pos = S3_DATA_NONVOLATILE_POS; @@ -261,39 +265,27 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) pos = S3_DATA_VOLATILE_POS; } - dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); - spi_address = pci_read_config32(dev, 0xA0) & ~0x1F; + spi_init(); + flash = spi_flash_probe(0, 0, 0, 0); + if (!flash) { + printk(BIOS_DEBUG, "Could not find SPI device\n"); + /* Dont make flow stop. */ + return AGESA_SUCCESS; + } - /* printk(BIOS_DEBUG, "spi_address=%x\n", spi_address); */ - read_spi_id((u8 *) spi_address); - write_spi_status((u8 *)spi_address, 0); if (S3DataType == S3DataTypeNonVolatile) { - sector_erase_spi((u8 *) spi_address, S3_DATA_NONVOLATILE_POS); + flash->erase(flash, S3_DATA_NONVOLATILE_POS, 0x1000); } else { - sector_erase_spi((u8 *) spi_address, S3_DATA_VOLATILE_POS); - sector_erase_spi((u8 *) spi_address, - S3_DATA_VOLATILE_POS + 0x1000); - sector_erase_spi((u8 *) spi_address, - S3_DATA_VOLATILE_POS + 0x2000); - sector_erase_spi((u8 *) spi_address, - S3_DATA_VOLATILE_POS + 0x3000); - sector_erase_spi((u8 *) spi_address, - S3_DATA_VOLATILE_POS + 0x4000); - sector_erase_spi((u8 *) spi_address, - S3_DATA_VOLATILE_POS + 0x5000); + flash->erase(flash, S3_DATA_VOLATILE_POS, 0x6000); } nvram_pos = 0; - dword_noneAAI_program((u8 *) spi_address, nvram_pos + pos, DataSize); + flash->write(flash, nvram_pos + pos, sizeof(DataSize), &DataSize); for (nvram_pos = 0; nvram_pos < DataSize; nvram_pos += 4) { data = *(u32 *) (Data + nvram_pos); - dword_noneAAI_program((u8 *) spi_address, nvram_pos + pos + 4, - *(u32 *) (Data + nvram_pos)); + flash->write(flash, nvram_pos + pos + 4, sizeof(u32), (u32 *)(Data + nvram_pos)); } - /* write_spi_status((u8 *)spi_address, 0x3c); */ - - /* spi_write_disable((u8 *) spi_address); */ return AGESA_SUCCESS; } diff --git a/src/southbridge/amd/Kconfig b/src/southbridge/amd/Kconfig index 867afca..20d5573 100644 --- a/src/southbridge/amd/Kconfig +++ b/src/southbridge/amd/Kconfig @@ -14,3 +14,7 @@ source src/southbridge/amd/sb800/Kconfig source src/southbridge/amd/cimx/Kconfig source src/southbridge/amd/agesa/Kconfig source src/southbridge/amd/sr5650/Kconfig + +config SPI_FLASH + bool + default y if HAVE_ACPI_RESUME && CPU_AMD_AGESA diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index ad8b6d4..e632113 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -16,203 +16,109 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> +#include <stdint.h> +#include <stdlib.h> #include <arch/io.h> +#include <spi.h> +#include <spi_flash.h> #include <device/device.h> -#include "spi.h" +#include <device/pci.h> +#include <device/pci_ops.h> -void execute_command(volatile u8 * spi_address) -{ - *(spi_address + 2) |= 1; -} +static u32 spibar; -void wait4command_complete(volatile u8 * spi_address) +static void reset_internal_fifo_pointer(void) { -// while (*(spi_address + 2) & 1) - while ((*(spi_address + 2) & 1) && (*(spi_address + 3) & 0x80)) - printk(BIOS_DEBUG, "wait4CommandComplete\n"); + do { + write8(spibar + 2, read8(spibar + 2) | 0x10); + } while (read8(spibar + 0xD) & 0x7); } -void reset_internal_fifo_pointer(volatile u8 * spi_address) +static void execute_command(void) { - u8 val; + write8(spibar + 2, read8(spibar + 2) | 1); - do { - *(spi_address + 2) |= 0x10; - val = *(spi_address + 0xd); - } while (val & 0x7); + while ((read8(spibar + 2) & 1) && (read8(spibar+3) & 0x80)); } -u8 read_spi_status(volatile u8 * spi_address) +void spi_init() { - u8 val; - *spi_address = 0x05; - *(spi_address + 1) = 0x21; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = 0x0; /* dummy */ - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - reset_internal_fifo_pointer(spi_address); - val = *(spi_address + 0xC); - val = *(spi_address + 0xC); - val = *(spi_address + 0xC); - return val; -} + device_t dev; -void wait4flashpart_ready(volatile u8 * spi_address) -{ - while (read_spi_status(spi_address) & 1) ; + dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); + spibar = pci_read_config32(dev, 0xA0) & ~0x1F; } -void write_spi_status(volatile u8 * spi_address, u8 status) +int spi_xfer(struct spi_slave *slave, const void *dout, + unsigned int bitsout, void *din, unsigned int bitsin) { - *spi_address = 0x50; /* EWSR */ - *(spi_address + 1) = 0; /* RxByte=TxByte=0 */ - execute_command(spi_address); - wait4command_complete(spi_address); - - *spi_address = 0x01; /* WRSR */ - *(spi_address + 1) = 0x01; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = status; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); - - read_spi_status(spi_address); -} + /* First byte is cmd which can not being sent through FIFO. */ + u8 cmd = *(u8 *)dout++; + u8 readoffby1; + u8 readwrite; + u8 bytesout, bytesin; + u8 count; -void read_spi_id(volatile u8 * spi_address) -{ - u8 mid = 0, did = 0; - *spi_address = 0x90; - *(spi_address + 1) = 0x23; /* RxByte=2, TxByte=3 */ - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = 0; - *(spi_address + 0xC) = 0; - *(spi_address + 0xC) = 0; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - reset_internal_fifo_pointer(spi_address); - mid = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); - mid = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); - mid = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); - - mid = *(spi_address + 0xC); - did = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); -} + bitsout -= 8; + bytesout = bitsout / 8; + bytesin = bitsin / 8; -void spi_write_enable(volatile u8 * spi_address) -{ - *spi_address = 0x06; /* Write Enable */ - *(spi_address + 1) = 0x0; /* RxByte=0, TxByte=0 */ - execute_command(spi_address); - wait4command_complete(spi_address); -} + readoffby1 = bytesout ? 0 : 1; -void spi_write_disable(volatile u8 * spi_address) + readwrite = (bytesin + readoffby1) << 4 | bytesout; + write8(spibar+1, readwrite); + write8(spibar + 0, cmd); + + reset_internal_fifo_pointer(); + + for (count = 0; count < bytesout; count++, dout++) { + write8(spibar + 0x0C, *(u8 *)dout); + } + + reset_internal_fifo_pointer(); + + execute_command(); + + reset_internal_fifo_pointer(); + + /* Skip the bytes we sent. */ + for (count = 0; count < bytesout; count++) { + cmd = read8(spibar + 0x0C); + } + reset_internal_fifo_pointer(); + for (count = 0; count < bytesin; count++, din++) { + *(u8 *)din = read8(spibar + 0x0C); + } + + return 0; +} +int spi_claim_bus(struct spi_slave *slave) { - *spi_address = 0x04; /* Write Enable */ - *(spi_address + 1) = 0x0; /* RxByte=0, TxByte=0 */ - execute_command(spi_address); - wait4command_complete(spi_address); + return 0; } -void sector_erase_spi(volatile u8 * spi_address, u32 address) +void spi_release_bus(struct spi_slave *slave) { - spi_write_enable(spi_address); - *spi_address = 0x20; - *(spi_address + 1) = 0x03; /* RxByte=0, TxByte=3 */ - - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); } -void chip_erase_spi(volatile u8 * spi_address) +void spi_cs_activate(struct spi_slave *slave) { - spi_write_enable(spi_address); - *spi_address = 0xC7; - *(spi_address + 1) = 0x00; - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); } -void byte_program(volatile u8 * spi_address, u32 address, u32 data) +void spi_cs_deactivate(struct spi_slave *slave) { - spi_write_enable(spi_address); - *spi_address = 0x02; - *(spi_address + 1) = 0x0 << 4 | 4; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - *(spi_address + 0xC) = data & 0xFF; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); } -void dword_noneAAI_program(volatile u8 * spi_address, u32 address, u32 data) +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) { - u8 i; - /* - * printk(BIOS_SPEW, "%s: addr=%x, data=%x\n", __func__, address, data); - */ - for (i = 0; i < 4; i++) { - spi_write_enable(spi_address); - *spi_address = 0x02; - *(spi_address + 1) = 0x0 << 4 | 4; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - *(spi_address + 0xC) = data & 0xFF; - data >>= 8; - address++; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); + struct spi_slave *slave = malloc(sizeof(*slave)); + + if (!slave) { + return NULL; } -} -void dword_program(volatile u8 * spi_address, u32 address, u32 data) -{ - spi_write_enable(spi_address); - *spi_address = 0x02; - *(spi_address + 1) = 0x0 << 4 | 7; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - *(spi_address + 0xC) = data & 0xFF; - *(spi_address + 0xC) = (data >> 8) & 0xFF; - *(spi_address + 0xC) = (data >> 16) & 0xFF; - *(spi_address + 0xC) = (data >> 24) & 0xFF; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); -} + memset(slave, 0, sizeof(*slave)); -void direct_byte_program(volatile u8 * spi_address, volatile u32 * address, u32 data) -{ - spi_write_enable(spi_address); - *address = data; - wait4flashpart_ready(spi_address); + return slave; } diff --git a/src/southbridge/amd/agesa/hudson/spi.h b/src/southbridge/amd/agesa/hudson/spi.h deleted file mode 100644 index 657ce4e..0000000 --- a/src/southbridge/amd/agesa/hudson/spi.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * *************************************************************************** - * - */ - -#ifndef _HUDSON_CIMX_SPI_H_ -#define _HUDSON_CIMX_SPI_H_ - -void execute_command(volatile u8 * spi_address); -void wait4command_complete(volatile u8 * spi_address); -void reset_internal_fifo_pointer(volatile u8 * spi_address); -u8 read_spi_status(volatile u8 * spi_address); -void wait4flashpart_ready(volatile u8 * spi_address); -void write_spi_status(volatile u8 * spi_address, u8 status); -void read_spi_id(volatile u8 * spi_address); -void spi_write_enable(volatile u8 * spi_address); -void spi_write_disable(volatile u8 * spi_address); -void sector_erase_spi(volatile u8 * spi_address, u32 address); -void chip_erase_spi(volatile u8 * spi_address); -void byte_program(volatile u8 * spi_address, u32 address, u32 data); -void dword_noneAAI_program(volatile u8 * spi_address, u32 address, u32 data); -void dword_program(volatile u8 * spi_address, u32 address, u32 data); -void direct_byte_program(volatile u8 * spi_address, volatile u32 * address, u32 data); - -#endif diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index e1c2ecb..e632113 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -16,201 +16,109 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> +#include <stdint.h> +#include <stdlib.h> #include <arch/io.h> +#include <spi.h> +#include <spi_flash.h> #include <device/device.h> -#include "SBPLATFORM.h" +#include <device/pci.h> +#include <device/pci_ops.h> +static u32 spibar; -void execute_command(volatile u8 * spi_address) +static void reset_internal_fifo_pointer(void) { - *(spi_address + 2) |= 1; + do { + write8(spibar + 2, read8(spibar + 2) | 0x10); + } while (read8(spibar + 0xD) & 0x7); } -void wait4command_complete(volatile u8 * spi_address) +static void execute_command(void) { - while (*(spi_address + 2) & 1) - printk(BIOS_DEBUG, "wait4CommandComplete\n"); + write8(spibar + 2, read8(spibar + 2) | 1); + + while ((read8(spibar + 2) & 1) && (read8(spibar+3) & 0x80)); } -void reset_internal_fifo_pointer(volatile u8 * spi_address) +void spi_init() { - u8 val; + device_t dev; - do { - *(spi_address + 2) |= 0x10; - val = *(spi_address + 0xd); - } while (val & 0x7); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); + spibar = pci_read_config32(dev, 0xA0) & ~0x1F; } -u8 read_spi_status(volatile u8 * spi_address) +int spi_xfer(struct spi_slave *slave, const void *dout, + unsigned int bitsout, void *din, unsigned int bitsin) { - u8 val; - *spi_address = 0x05; - *(spi_address + 1) = 0x11; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = 0x0; /* dummy */ - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - reset_internal_fifo_pointer(spi_address); - val = *(spi_address + 0xC); - val = *(spi_address + 0xC); - return val; -} + /* First byte is cmd which can not being sent through FIFO. */ + u8 cmd = *(u8 *)dout++; + u8 readoffby1; + u8 readwrite; + u8 bytesout, bytesin; + u8 count; -void wait4flashpart_ready(volatile u8 * spi_address) -{ - while (read_spi_status(spi_address) & 1) ; -} + bitsout -= 8; + bytesout = bitsout / 8; + bytesin = bitsin / 8; -void write_spi_status(volatile u8 * spi_address, u8 status) -{ - *spi_address = 0x50; /* EWSR */ - *(spi_address + 1) = 0; /* RxByte=TxByte=0 */ - execute_command(spi_address); - wait4command_complete(spi_address); - - *spi_address = 0x01; /* WRSR */ - *(spi_address + 1) = 0x01; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = status; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); - - read_spi_status(spi_address); -} + readoffby1 = bytesout ? 0 : 1; -void read_spi_id(volatile u8 * spi_address) -{ - u8 mid = 0, did = 0; - *spi_address = 0x90; - *(spi_address + 1) = 0x23; /* RxByte=2, TxByte=3 */ - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = 0; - *(spi_address + 0xC) = 0; - *(spi_address + 0xC) = 0; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - reset_internal_fifo_pointer(spi_address); - mid = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); - mid = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); - mid = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); - - mid = *(spi_address + 0xC); - did = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); -} + readwrite = (bytesin + readoffby1) << 4 | bytesout; + write8(spibar+1, readwrite); + write8(spibar + 0, cmd); -void spi_write_enable(volatile u8 * spi_address) -{ - *spi_address = 0x06; /* Write Enable */ - *(spi_address + 1) = 0x0; /* RxByte=0, TxByte=0 */ - execute_command(spi_address); - wait4command_complete(spi_address); + reset_internal_fifo_pointer(); + + for (count = 0; count < bytesout; count++, dout++) { + write8(spibar + 0x0C, *(u8 *)dout); + } + + reset_internal_fifo_pointer(); + + execute_command(); + + reset_internal_fifo_pointer(); + + /* Skip the bytes we sent. */ + for (count = 0; count < bytesout; count++) { + cmd = read8(spibar + 0x0C); + } + reset_internal_fifo_pointer(); + for (count = 0; count < bytesin; count++, din++) { + *(u8 *)din = read8(spibar + 0x0C); + } + + return 0; } -void spi_write_disable(volatile u8 * spi_address) +int spi_claim_bus(struct spi_slave *slave) { - *spi_address = 0x04; /* Write Enable */ - *(spi_address + 1) = 0x0; /* RxByte=0, TxByte=0 */ - execute_command(spi_address); - wait4command_complete(spi_address); + return 0; } -void sector_erase_spi(volatile u8 * spi_address, u32 address) +void spi_release_bus(struct spi_slave *slave) { - spi_write_enable(spi_address); - *spi_address = 0x20; - *(spi_address + 1) = 0x03; /* RxByte=0, TxByte=3 */ - - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); } -void chip_erase_spi(volatile u8 * spi_address) +void spi_cs_activate(struct spi_slave *slave) { - spi_write_enable(spi_address); - *spi_address = 0xC7; - *(spi_address + 1) = 0x00; - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); } -void byte_program(volatile u8 * spi_address, u32 address, u32 data) +void spi_cs_deactivate(struct spi_slave *slave) { - spi_write_enable(spi_address); - *spi_address = 0x02; - *(spi_address + 1) = 0x0 << 4 | 4; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - *(spi_address + 0xC) = data & 0xFF; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); } -void dword_noneAAI_program(volatile u8 * spi_address, u32 address, u32 data) +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) { - u8 i; - /* - * printk(BIOS_SPEW, "%s: addr=%x, data=%x\n", __func__, address, data); - */ - for (i = 0; i < 4; i++) { - spi_write_enable(spi_address); - *spi_address = 0x02; - *(spi_address + 1) = 0x0 << 4 | 4; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - *(spi_address + 0xC) = data & 0xFF; - data >>= 8; - address++; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); + struct spi_slave *slave = malloc(sizeof(*slave)); + + if (!slave) { + return NULL; } -} -void dword_program(volatile u8 * spi_address, u32 address, u32 data) -{ - spi_write_enable(spi_address); - *spi_address = 0x02; - *(spi_address + 1) = 0x0 << 4 | 7; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - *(spi_address + 0xC) = data & 0xFF; - *(spi_address + 0xC) = (data >> 8) & 0xFF; - *(spi_address + 0xC) = (data >> 16) & 0xFF; - *(spi_address + 0xC) = (data >> 24) & 0xFF; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); -} + memset(slave, 0, sizeof(*slave)); -void direct_byte_program(volatile u8 * spi_address, volatile u32 * address, u32 data) -{ - spi_write_enable(spi_address); - *address = data; - wait4flashpart_ready(spi_address); + return slave; } diff --git a/src/southbridge/amd/cimx/sb800/spi.h b/src/southbridge/amd/cimx/sb800/spi.h deleted file mode 100644 index 57921d9..0000000 --- a/src/southbridge/amd/cimx/sb800/spi.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * *************************************************************************** - * - */ - -#ifndef _SB800_CIMX_SPI_H_ -#define _SB800_CIMX_SPI_H_ - -void execute_command(volatile u8 * spi_address); -void wait4command_complete(volatile u8 * spi_address); -void reset_internal_fifo_pointer(volatile u8 * spi_address); -u8 read_spi_status(volatile u8 * spi_address); -void wait4flashpart_ready(volatile u8 * spi_address); -void write_spi_status(volatile u8 * spi_address, u8 status); -void read_spi_id(volatile u8 * spi_address); -void spi_write_enable(volatile u8 * spi_address); -void sector_erase_spi(volatile u8 * spi_address, u32 address); -void chip_erase_spi(volatile u8 * spi_address); -void byte_program(volatile u8 * spi_address, u32 address, u32 data); -void dword_noneAAI_program(volatile u8 * spi_address, u32 address, u32 data); -void dword_program(volatile u8 * spi_address, u32 address, u32 data); -void direct_byte_program(volatile u8 * spi_address, volatile u32 * address, u32 data); - -#endif

1 0

Patch set updated for coreboot: f23bc5c AMD S3: Leverage the public SPI routine
by Zheng Bao 27 Nov '12

27 Nov '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1920 -gerrit commit f23bc5cb3d0991ca8e926984e974c0bc2c4513b2 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Tue Nov 27 17:08:00 2012 +0800 AMD S3: Leverage the public SPI routine Remove the old, unflexible code for storing data in SPI flash. Change-Id: I60a10476befb4afab2b4241f01a988f4a8bb22cd Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/cpu/amd/agesa/s3_resume.c | 88 ++++++------- src/southbridge/amd/Kconfig | 4 + src/southbridge/amd/agesa/hudson/spi.c | 234 ++++++++++----------------------- src/southbridge/amd/agesa/hudson/spi.h | 43 ------ 4 files changed, 114 insertions(+), 255 deletions(-) diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 0348a9f..6302c3d 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -41,7 +41,8 @@ #include "agesawrapper.h" #ifndef __PRE_RAM__ -#include "spi.h" +#include <spi.h> +#include <spi_flash.h> #endif void restore_mtrr(void) @@ -151,14 +152,18 @@ void move_stack_high_mem(void) void OemAgesaSaveMtrr(void) { #ifndef __PRE_RAM__ - u32 spi_address; msr_t msr_data; - device_t dev; u32 nvram_pos = S3_DATA_MTRR_POS; u32 i; + struct spi_flash *flash; - dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); - spi_address = pci_read_config32(dev, 0xA0) & ~0x1F; + spi_init(); + + flash = spi_flash_probe(0, 0, 0, 0); + if (!flash) { + printk(BIOS_DEBUG, "Could not find SPI device\n"); + return; + } /* Enable access to AMD RdDram and WrDram extension bits */ msr_data = rdmsr(SYS_CFG); @@ -167,28 +172,29 @@ void OemAgesaSaveMtrr(void) /* Fixed MTRRs */ msr_data = rdmsr(0x250); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; msr_data = rdmsr(0x258); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; msr_data = rdmsr(0x259); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; for (i = 0x268; i < 0x270; i++) { msr_data = rdmsr(i); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; } @@ -200,35 +206,33 @@ void OemAgesaSaveMtrr(void) /* Variable MTRRs */ for (i = 0x200; i < 0x210; i++) { msr_data = rdmsr(i); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; } /* SYS_CFG */ msr_data = rdmsr(0xC0010010); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; /* TOM */ msr_data = rdmsr(0xC001001A); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; /* TOM2 */ msr_data = rdmsr(0xC001001D); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; - write_spi_status((u8 *)spi_address, 0x3c); - spi_write_disable((u8 *) spi_address); #endif } @@ -251,9 +255,9 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) { u32 pos = S3_DATA_VOLATILE_POS; - u32 spi_address, data; + u32 data; u32 nvram_pos; - device_t dev; + struct spi_flash *flash; if (S3DataType == S3DataTypeNonVolatile) { pos = S3_DATA_NONVOLATILE_POS; @@ -261,39 +265,27 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) pos = S3_DATA_VOLATILE_POS; } - dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); - spi_address = pci_read_config32(dev, 0xA0) & ~0x1F; + spi_init(); + flash = spi_flash_probe(0, 0, 0, 0); + if (!flash) { + printk(BIOS_DEBUG, "Could not find SPI device\n"); + /* Dont make flow stop. */ + return AGESA_SUCCESS; + } - /* printk(BIOS_DEBUG, "spi_address=%x\n", spi_address); */ - read_spi_id((u8 *) spi_address); - write_spi_status((u8 *)spi_address, 0); if (S3DataType == S3DataTypeNonVolatile) { - sector_erase_spi((u8 *) spi_address, S3_DATA_NONVOLATILE_POS); + flash->erase(flash, S3_DATA_NONVOLATILE_POS, 0x1000); } else { - sector_erase_spi((u8 *) spi_address, S3_DATA_VOLATILE_POS); - sector_erase_spi((u8 *) spi_address, - S3_DATA_VOLATILE_POS + 0x1000); - sector_erase_spi((u8 *) spi_address, - S3_DATA_VOLATILE_POS + 0x2000); - sector_erase_spi((u8 *) spi_address, - S3_DATA_VOLATILE_POS + 0x3000); - sector_erase_spi((u8 *) spi_address, - S3_DATA_VOLATILE_POS + 0x4000); - sector_erase_spi((u8 *) spi_address, - S3_DATA_VOLATILE_POS + 0x5000); + flash->erase(flash, S3_DATA_VOLATILE_POS, 0x6000); } nvram_pos = 0; - dword_noneAAI_program((u8 *) spi_address, nvram_pos + pos, DataSize); + flash->write(flash, nvram_pos + pos, sizeof(DataSize), &DataSize); for (nvram_pos = 0; nvram_pos < DataSize; nvram_pos += 4) { data = *(u32 *) (Data + nvram_pos); - dword_noneAAI_program((u8 *) spi_address, nvram_pos + pos + 4, - *(u32 *) (Data + nvram_pos)); + flash->write(flash, nvram_pos + pos + 4, sizeof(u32), (u32 *)(Data + nvram_pos)); } - /* write_spi_status((u8 *)spi_address, 0x3c); */ - - /* spi_write_disable((u8 *) spi_address); */ return AGESA_SUCCESS; } diff --git a/src/southbridge/amd/Kconfig b/src/southbridge/amd/Kconfig index 867afca..20d5573 100644 --- a/src/southbridge/amd/Kconfig +++ b/src/southbridge/amd/Kconfig @@ -14,3 +14,7 @@ source src/southbridge/amd/sb800/Kconfig source src/southbridge/amd/cimx/Kconfig source src/southbridge/amd/agesa/Kconfig source src/southbridge/amd/sr5650/Kconfig + +config SPI_FLASH + bool + default y if HAVE_ACPI_RESUME && CPU_AMD_AGESA diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index ad8b6d4..e632113 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -16,203 +16,109 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> +#include <stdint.h> +#include <stdlib.h> #include <arch/io.h> +#include <spi.h> +#include <spi_flash.h> #include <device/device.h> -#include "spi.h" +#include <device/pci.h> +#include <device/pci_ops.h> -void execute_command(volatile u8 * spi_address) -{ - *(spi_address + 2) |= 1; -} +static u32 spibar; -void wait4command_complete(volatile u8 * spi_address) +static void reset_internal_fifo_pointer(void) { -// while (*(spi_address + 2) & 1) - while ((*(spi_address + 2) & 1) && (*(spi_address + 3) & 0x80)) - printk(BIOS_DEBUG, "wait4CommandComplete\n"); + do { + write8(spibar + 2, read8(spibar + 2) | 0x10); + } while (read8(spibar + 0xD) & 0x7); } -void reset_internal_fifo_pointer(volatile u8 * spi_address) +static void execute_command(void) { - u8 val; + write8(spibar + 2, read8(spibar + 2) | 1); - do { - *(spi_address + 2) |= 0x10; - val = *(spi_address + 0xd); - } while (val & 0x7); + while ((read8(spibar + 2) & 1) && (read8(spibar+3) & 0x80)); } -u8 read_spi_status(volatile u8 * spi_address) +void spi_init() { - u8 val; - *spi_address = 0x05; - *(spi_address + 1) = 0x21; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = 0x0; /* dummy */ - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - reset_internal_fifo_pointer(spi_address); - val = *(spi_address + 0xC); - val = *(spi_address + 0xC); - val = *(spi_address + 0xC); - return val; -} + device_t dev; -void wait4flashpart_ready(volatile u8 * spi_address) -{ - while (read_spi_status(spi_address) & 1) ; + dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); + spibar = pci_read_config32(dev, 0xA0) & ~0x1F; } -void write_spi_status(volatile u8 * spi_address, u8 status) +int spi_xfer(struct spi_slave *slave, const void *dout, + unsigned int bitsout, void *din, unsigned int bitsin) { - *spi_address = 0x50; /* EWSR */ - *(spi_address + 1) = 0; /* RxByte=TxByte=0 */ - execute_command(spi_address); - wait4command_complete(spi_address); - - *spi_address = 0x01; /* WRSR */ - *(spi_address + 1) = 0x01; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = status; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); - - read_spi_status(spi_address); -} + /* First byte is cmd which can not being sent through FIFO. */ + u8 cmd = *(u8 *)dout++; + u8 readoffby1; + u8 readwrite; + u8 bytesout, bytesin; + u8 count; -void read_spi_id(volatile u8 * spi_address) -{ - u8 mid = 0, did = 0; - *spi_address = 0x90; - *(spi_address + 1) = 0x23; /* RxByte=2, TxByte=3 */ - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = 0; - *(spi_address + 0xC) = 0; - *(spi_address + 0xC) = 0; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - reset_internal_fifo_pointer(spi_address); - mid = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); - mid = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); - mid = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); - - mid = *(spi_address + 0xC); - did = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); -} + bitsout -= 8; + bytesout = bitsout / 8; + bytesin = bitsin / 8; -void spi_write_enable(volatile u8 * spi_address) -{ - *spi_address = 0x06; /* Write Enable */ - *(spi_address + 1) = 0x0; /* RxByte=0, TxByte=0 */ - execute_command(spi_address); - wait4command_complete(spi_address); -} + readoffby1 = bytesout ? 0 : 1; -void spi_write_disable(volatile u8 * spi_address) + readwrite = (bytesin + readoffby1) << 4 | bytesout; + write8(spibar+1, readwrite); + write8(spibar + 0, cmd); + + reset_internal_fifo_pointer(); + + for (count = 0; count < bytesout; count++, dout++) { + write8(spibar + 0x0C, *(u8 *)dout); + } + + reset_internal_fifo_pointer(); + + execute_command(); + + reset_internal_fifo_pointer(); + + /* Skip the bytes we sent. */ + for (count = 0; count < bytesout; count++) { + cmd = read8(spibar + 0x0C); + } + reset_internal_fifo_pointer(); + for (count = 0; count < bytesin; count++, din++) { + *(u8 *)din = read8(spibar + 0x0C); + } + + return 0; +} +int spi_claim_bus(struct spi_slave *slave) { - *spi_address = 0x04; /* Write Enable */ - *(spi_address + 1) = 0x0; /* RxByte=0, TxByte=0 */ - execute_command(spi_address); - wait4command_complete(spi_address); + return 0; } -void sector_erase_spi(volatile u8 * spi_address, u32 address) +void spi_release_bus(struct spi_slave *slave) { - spi_write_enable(spi_address); - *spi_address = 0x20; - *(spi_address + 1) = 0x03; /* RxByte=0, TxByte=3 */ - - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); } -void chip_erase_spi(volatile u8 * spi_address) +void spi_cs_activate(struct spi_slave *slave) { - spi_write_enable(spi_address); - *spi_address = 0xC7; - *(spi_address + 1) = 0x00; - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); } -void byte_program(volatile u8 * spi_address, u32 address, u32 data) +void spi_cs_deactivate(struct spi_slave *slave) { - spi_write_enable(spi_address); - *spi_address = 0x02; - *(spi_address + 1) = 0x0 << 4 | 4; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - *(spi_address + 0xC) = data & 0xFF; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); } -void dword_noneAAI_program(volatile u8 * spi_address, u32 address, u32 data) +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) { - u8 i; - /* - * printk(BIOS_SPEW, "%s: addr=%x, data=%x\n", __func__, address, data); - */ - for (i = 0; i < 4; i++) { - spi_write_enable(spi_address); - *spi_address = 0x02; - *(spi_address + 1) = 0x0 << 4 | 4; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - *(spi_address + 0xC) = data & 0xFF; - data >>= 8; - address++; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); + struct spi_slave *slave = malloc(sizeof(*slave)); + + if (!slave) { + return NULL; } -} -void dword_program(volatile u8 * spi_address, u32 address, u32 data) -{ - spi_write_enable(spi_address); - *spi_address = 0x02; - *(spi_address + 1) = 0x0 << 4 | 7; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - *(spi_address + 0xC) = data & 0xFF; - *(spi_address + 0xC) = (data >> 8) & 0xFF; - *(spi_address + 0xC) = (data >> 16) & 0xFF; - *(spi_address + 0xC) = (data >> 24) & 0xFF; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); -} + memset(slave, 0, sizeof(*slave)); -void direct_byte_program(volatile u8 * spi_address, volatile u32 * address, u32 data) -{ - spi_write_enable(spi_address); - *address = data; - wait4flashpart_ready(spi_address); + return slave; } diff --git a/src/southbridge/amd/agesa/hudson/spi.h b/src/southbridge/amd/agesa/hudson/spi.h deleted file mode 100644 index 657ce4e..0000000 --- a/src/southbridge/amd/agesa/hudson/spi.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * *************************************************************************** - * - */ - -#ifndef _HUDSON_CIMX_SPI_H_ -#define _HUDSON_CIMX_SPI_H_ - -void execute_command(volatile u8 * spi_address); -void wait4command_complete(volatile u8 * spi_address); -void reset_internal_fifo_pointer(volatile u8 * spi_address); -u8 read_spi_status(volatile u8 * spi_address); -void wait4flashpart_ready(volatile u8 * spi_address); -void write_spi_status(volatile u8 * spi_address, u8 status); -void read_spi_id(volatile u8 * spi_address); -void spi_write_enable(volatile u8 * spi_address); -void spi_write_disable(volatile u8 * spi_address); -void sector_erase_spi(volatile u8 * spi_address, u32 address); -void chip_erase_spi(volatile u8 * spi_address); -void byte_program(volatile u8 * spi_address, u32 address, u32 data); -void dword_noneAAI_program(volatile u8 * spi_address, u32 address, u32 data); -void dword_program(volatile u8 * spi_address, u32 address, u32 data); -void direct_byte_program(volatile u8 * spi_address, volatile u32 * address, u32 data); - -#endif

1 0

Patch set updated for coreboot: 9eacdb4 xcompile: Add missing XGCCPATH
by Zheng Bao 27 Nov '12

27 Nov '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1921 -gerrit commit 9eacdb49062ec9531a31a49a2d5e4d7c2e972cea Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Tue Nov 27 17:07:22 2012 +0800 xcompile: Add missing XGCCPATH XGCCPATH is missing in new xcompile. Change-Id: I177f54189be445404a4a61419064d3c414b8a30c Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- util/xcompile/xcompile | 1 + 1 file changed, 1 insertion(+) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 558f3f8..cc01631 100644 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -151,6 +151,7 @@ TWIDTH_arm="32" TARCH_x86="i386" TCLIST_x86="i386 x86_64" TWIDTH_x86="32" +XGCCPATH=${1:-"`pwd`/util/crossgcc/xgcc/bin/"} # This loops over all supported architectures. for architecture in $SUPPORTED_ARCHITECTURE; do

1 0

New patch to review for coreboot: 13c2392 xcompile: Add missing XGCCPATH
by Zheng Bao 27 Nov '12

27 Nov '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1921 -gerrit commit 13c239235e04970e8a6f81c75a2fb73acf17ebab Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Tue Nov 27 17:02:06 2012 +0800 xcompile: Add missing XGCCPATH XGCCPATH is missing in new xcompile. Change-Id: I177f54189be445404a4a61419064d3c414b8a30c Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- util/xcompile/xcompile | 1 + 1 file changed, 1 insertion(+) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 558f3f8..cc01631 100644 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -151,6 +151,7 @@ TWIDTH_arm="32" TARCH_x86="i386" TCLIST_x86="i386 x86_64" TWIDTH_x86="32" +XGCCPATH=${1:-"`pwd`/util/crossgcc/xgcc/bin/"} # This loops over all supported architectures. for architecture in $SUPPORTED_ARCHITECTURE; do

1 0

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coreboot November 2012