coreboot November 2012

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Patch merged into coreboot/master: f5e0fd8 roda/rk9: Fix for VGABIOS changes
by gerrit＠coreboot.org 27 Nov '12

27 Nov '12

the following patch was just integrated into master: commit f5e0fd888d4c33b5d5cd55f9ffa43407a416ade1 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Nov 27 12:26:52 2012 +0100 roda/rk9: Fix for VGABIOS changes Forgot to update the rk9 for the unified VGABIOS handling. This applies to rk9 what is done for other boards in commits 3c84261e84318708c9c16ee5df5c2549c609dd0a d5d340695b84ef6351818236dc514cd9734e87b1 Change-Id: I892b7d81927e277778c1c5251d27416fa79c9868 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Reviewed-on: http://review.coreboot.org/1924 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/1924 for details. -gerrit

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Patch set updated for coreboot: 60ea734 roda/rk9: Fix for VGABIOS changes
by Patrick Georgi 27 Nov '12

27 Nov '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1924 -gerrit commit 60ea734a10042802947e849f34f39ebf0d41ced2 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Nov 27 12:26:52 2012 +0100 roda/rk9: Fix for VGABIOS changes Forgot to update the rk9 for the unified VGABIOS handling. This applies to rk9 what is done for other boards in commits 3c84261e84318708c9c16ee5df5c2549c609dd0a d5d340695b84ef6351818236dc514cd9734e87b1 Change-Id: I892b7d81927e277778c1c5251d27416fa79c9868 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- src/mainboard/roda/rk9/mainboard.c | 31 +++++++++++++------------------ 1 file changed, 13 insertions(+), 18 deletions(-) diff --git a/src/mainboard/roda/rk9/mainboard.c b/src/mainboard/roda/rk9/mainboard.c index 5b4285c..2d50e54 100644 --- a/src/mainboard/roda/rk9/mainboard.c +++ b/src/mainboard/roda/rk9/mainboard.c @@ -23,7 +23,8 @@ //#include <pc80/mc146818rtc.h> #include <device/device.h> #include <console/console.h> -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_VGA_ROM_RUN +#include <arch/interrupt.h> #include <x86emu/x86emu.h> #endif #include <pc80/keyboard.h> @@ -36,7 +37,7 @@ #endif -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_VGA_ROM_RUN static int int15_handler(void) { enum { @@ -57,16 +58,16 @@ static int int15_handler(void) PANEL_FIT_GFX_STRETCH = (1 << 2), }; - switch (M.x86.R_AX) { + switch (X86_AX) { case 0x5f34: /* Set Panel Fitting Hook */ - M.x86.R_AX = 0x005f; - M.x86.R_CX = PANEL_FIT_CENTERING; + X86_AX = 0x005f; + X86_CX = PANEL_FIT_CENTERING; break; case 0x5f35: /* Boot Display Device Hook */ - M.x86.R_AX = 0x005f; - M.x86.R_CX = BOOT_DISPLAY_DEFAULT; /* Select automatically. */ + X86_AX = 0x005f; + X86_CX = BOOT_DISPLAY_DEFAULT; /* Select automatically. */ break; case 0x5f40: /* Boot Panel Type Hook */ @@ -75,8 +76,8 @@ static int int15_handler(void) /* LCD panel type is SIO GPIO40-43. It's controlled by a DIP switch but was always set to 4 while only values of 5 and 6 worked. */ - M.x86.R_AX = 0x005f; - M.x86.R_CX = (inb(0x60f) & 0x0f) + 1; + X86_AX = 0x005f; + X86_CX = (inb(0x60f) & 0x0f) + 1; break; case 0x5f70: /* Sandybridge boards return 0 here. */ @@ -89,7 +90,7 @@ static int int15_handler(void) /* Interrupt was not handled. */ printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", __func__, - M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX); + X86_AX, X86_BX, X86_CX, X86_DX); return 0; } @@ -97,12 +98,6 @@ static int int15_handler(void) return 1; } -static void int15_install(void) -{ - typedef int (* yabel_handleIntFunc)(void); - extern yabel_handleIntFunc yabel_intFuncArray[256]; - yabel_intFuncArray[0x15] = int15_handler; -} #endif static void verb_setup(void) @@ -131,9 +126,9 @@ static void mainboard_enable(device_t dev) { ec_setup(); verb_setup(); -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL// || CONFIG_PCI_OPTION_ROM_RUN_REALMODE +#if CONFIG_VGA_ROM_RUN /* Install custom int15 handler for VGA OPROM */ - int15_install(); + mainboard_interrupt_handlers(0x15, &int15_handler); #endif /* We have no driver for the embedded controller since the firmware

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New patch to review for coreboot: f5e594f roda/rk9: Fix for VGABIOS changes
by Patrick Georgi 27 Nov '12

27 Nov '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1924 -gerrit commit f5e594f6013392d6d7e5facf1a8858f7fecbd67d Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Nov 27 12:26:52 2012 +0100 roda/rk9: Fix for VGABIOS changes Forgot to update the rk9 for the unified VGABIOS handling. Change-Id: I892b7d81927e277778c1c5251d27416fa79c9868 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- src/mainboard/roda/rk9/mainboard.c | 31 +++++++++++++------------------ 1 file changed, 13 insertions(+), 18 deletions(-) diff --git a/src/mainboard/roda/rk9/mainboard.c b/src/mainboard/roda/rk9/mainboard.c index 5b4285c..2d50e54 100644 --- a/src/mainboard/roda/rk9/mainboard.c +++ b/src/mainboard/roda/rk9/mainboard.c @@ -23,7 +23,8 @@ //#include <pc80/mc146818rtc.h> #include <device/device.h> #include <console/console.h> -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_VGA_ROM_RUN +#include <arch/interrupt.h> #include <x86emu/x86emu.h> #endif #include <pc80/keyboard.h> @@ -36,7 +37,7 @@ #endif -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_VGA_ROM_RUN static int int15_handler(void) { enum { @@ -57,16 +58,16 @@ static int int15_handler(void) PANEL_FIT_GFX_STRETCH = (1 << 2), }; - switch (M.x86.R_AX) { + switch (X86_AX) { case 0x5f34: /* Set Panel Fitting Hook */ - M.x86.R_AX = 0x005f; - M.x86.R_CX = PANEL_FIT_CENTERING; + X86_AX = 0x005f; + X86_CX = PANEL_FIT_CENTERING; break; case 0x5f35: /* Boot Display Device Hook */ - M.x86.R_AX = 0x005f; - M.x86.R_CX = BOOT_DISPLAY_DEFAULT; /* Select automatically. */ + X86_AX = 0x005f; + X86_CX = BOOT_DISPLAY_DEFAULT; /* Select automatically. */ break; case 0x5f40: /* Boot Panel Type Hook */ @@ -75,8 +76,8 @@ static int int15_handler(void) /* LCD panel type is SIO GPIO40-43. It's controlled by a DIP switch but was always set to 4 while only values of 5 and 6 worked. */ - M.x86.R_AX = 0x005f; - M.x86.R_CX = (inb(0x60f) & 0x0f) + 1; + X86_AX = 0x005f; + X86_CX = (inb(0x60f) & 0x0f) + 1; break; case 0x5f70: /* Sandybridge boards return 0 here. */ @@ -89,7 +90,7 @@ static int int15_handler(void) /* Interrupt was not handled. */ printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", __func__, - M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX); + X86_AX, X86_BX, X86_CX, X86_DX); return 0; } @@ -97,12 +98,6 @@ static int int15_handler(void) return 1; } -static void int15_install(void) -{ - typedef int (* yabel_handleIntFunc)(void); - extern yabel_handleIntFunc yabel_intFuncArray[256]; - yabel_intFuncArray[0x15] = int15_handler; -} #endif static void verb_setup(void) @@ -131,9 +126,9 @@ static void mainboard_enable(device_t dev) { ec_setup(); verb_setup(); -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL// || CONFIG_PCI_OPTION_ROM_RUN_REALMODE +#if CONFIG_VGA_ROM_RUN /* Install custom int15 handler for VGA OPROM */ - int15_install(); + mainboard_interrupt_handlers(0x15, &int15_handler); #endif /* We have no driver for the embedded controller since the firmware

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Patch set updated for coreboot: 4a4d496 AMD S3: Leverage the public SPI routine
by Zheng Bao 27 Nov '12

27 Nov '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1920 -gerrit commit 4a4d496f07f7dadbe02e4c2fff9f5ed0e9f3ee74 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Tue Nov 27 18:10:08 2012 +0800 AMD S3: Leverage the public SPI routine Remove the old, unflexible code for storing S3 data in SPI flash. Tested on Parmer. Change-Id: I60a10476befb4afab2b4241f01a988f4a8bb22cd Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/cpu/amd/agesa/s3_resume.c | 88 ++++++------- src/southbridge/amd/Kconfig | 4 + src/southbridge/amd/agesa/hudson/spi.c | 234 ++++++++++----------------------- src/southbridge/amd/agesa/hudson/spi.h | 43 ------ src/southbridge/amd/cimx/sb800/spi.c | 230 ++++++++++---------------------- src/southbridge/amd/cimx/sb800/spi.h | 42 ------ 6 files changed, 183 insertions(+), 458 deletions(-) diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 0348a9f..6302c3d 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -41,7 +41,8 @@ #include "agesawrapper.h" #ifndef __PRE_RAM__ -#include "spi.h" +#include <spi.h> +#include <spi_flash.h> #endif void restore_mtrr(void) @@ -151,14 +152,18 @@ void move_stack_high_mem(void) void OemAgesaSaveMtrr(void) { #ifndef __PRE_RAM__ - u32 spi_address; msr_t msr_data; - device_t dev; u32 nvram_pos = S3_DATA_MTRR_POS; u32 i; + struct spi_flash *flash; - dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); - spi_address = pci_read_config32(dev, 0xA0) & ~0x1F; + spi_init(); + + flash = spi_flash_probe(0, 0, 0, 0); + if (!flash) { + printk(BIOS_DEBUG, "Could not find SPI device\n"); + return; + } /* Enable access to AMD RdDram and WrDram extension bits */ msr_data = rdmsr(SYS_CFG); @@ -167,28 +172,29 @@ void OemAgesaSaveMtrr(void) /* Fixed MTRRs */ msr_data = rdmsr(0x250); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; msr_data = rdmsr(0x258); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; msr_data = rdmsr(0x259); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; for (i = 0x268; i < 0x270; i++) { msr_data = rdmsr(i); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; } @@ -200,35 +206,33 @@ void OemAgesaSaveMtrr(void) /* Variable MTRRs */ for (i = 0x200; i < 0x210; i++) { msr_data = rdmsr(i); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; } /* SYS_CFG */ msr_data = rdmsr(0xC0010010); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; /* TOM */ msr_data = rdmsr(0xC001001A); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; /* TOM2 */ msr_data = rdmsr(0xC001001D); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; - write_spi_status((u8 *)spi_address, 0x3c); - spi_write_disable((u8 *) spi_address); #endif } @@ -251,9 +255,9 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) { u32 pos = S3_DATA_VOLATILE_POS; - u32 spi_address, data; + u32 data; u32 nvram_pos; - device_t dev; + struct spi_flash *flash; if (S3DataType == S3DataTypeNonVolatile) { pos = S3_DATA_NONVOLATILE_POS; @@ -261,39 +265,27 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) pos = S3_DATA_VOLATILE_POS; } - dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); - spi_address = pci_read_config32(dev, 0xA0) & ~0x1F; + spi_init(); + flash = spi_flash_probe(0, 0, 0, 0); + if (!flash) { + printk(BIOS_DEBUG, "Could not find SPI device\n"); + /* Dont make flow stop. */ + return AGESA_SUCCESS; + } - /* printk(BIOS_DEBUG, "spi_address=%x\n", spi_address); */ - read_spi_id((u8 *) spi_address); - write_spi_status((u8 *)spi_address, 0); if (S3DataType == S3DataTypeNonVolatile) { - sector_erase_spi((u8 *) spi_address, S3_DATA_NONVOLATILE_POS); + flash->erase(flash, S3_DATA_NONVOLATILE_POS, 0x1000); } else { - sector_erase_spi((u8 *) spi_address, S3_DATA_VOLATILE_POS); - sector_erase_spi((u8 *) spi_address, - S3_DATA_VOLATILE_POS + 0x1000); - sector_erase_spi((u8 *) spi_address, - S3_DATA_VOLATILE_POS + 0x2000); - sector_erase_spi((u8 *) spi_address, - S3_DATA_VOLATILE_POS + 0x3000); - sector_erase_spi((u8 *) spi_address, - S3_DATA_VOLATILE_POS + 0x4000); - sector_erase_spi((u8 *) spi_address, - S3_DATA_VOLATILE_POS + 0x5000); + flash->erase(flash, S3_DATA_VOLATILE_POS, 0x6000); } nvram_pos = 0; - dword_noneAAI_program((u8 *) spi_address, nvram_pos + pos, DataSize); + flash->write(flash, nvram_pos + pos, sizeof(DataSize), &DataSize); for (nvram_pos = 0; nvram_pos < DataSize; nvram_pos += 4) { data = *(u32 *) (Data + nvram_pos); - dword_noneAAI_program((u8 *) spi_address, nvram_pos + pos + 4, - *(u32 *) (Data + nvram_pos)); + flash->write(flash, nvram_pos + pos + 4, sizeof(u32), (u32 *)(Data + nvram_pos)); } - /* write_spi_status((u8 *)spi_address, 0x3c); */ - - /* spi_write_disable((u8 *) spi_address); */ return AGESA_SUCCESS; } diff --git a/src/southbridge/amd/Kconfig b/src/southbridge/amd/Kconfig index 867afca..20d5573 100644 --- a/src/southbridge/amd/Kconfig +++ b/src/southbridge/amd/Kconfig @@ -14,3 +14,7 @@ source src/southbridge/amd/sb800/Kconfig source src/southbridge/amd/cimx/Kconfig source src/southbridge/amd/agesa/Kconfig source src/southbridge/amd/sr5650/Kconfig + +config SPI_FLASH + bool + default y if HAVE_ACPI_RESUME && CPU_AMD_AGESA diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index ad8b6d4..e632113 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -16,203 +16,109 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> +#include <stdint.h> +#include <stdlib.h> #include <arch/io.h> +#include <spi.h> +#include <spi_flash.h> #include <device/device.h> -#include "spi.h" +#include <device/pci.h> +#include <device/pci_ops.h> -void execute_command(volatile u8 * spi_address) -{ - *(spi_address + 2) |= 1; -} +static u32 spibar; -void wait4command_complete(volatile u8 * spi_address) +static void reset_internal_fifo_pointer(void) { -// while (*(spi_address + 2) & 1) - while ((*(spi_address + 2) & 1) && (*(spi_address + 3) & 0x80)) - printk(BIOS_DEBUG, "wait4CommandComplete\n"); + do { + write8(spibar + 2, read8(spibar + 2) | 0x10); + } while (read8(spibar + 0xD) & 0x7); } -void reset_internal_fifo_pointer(volatile u8 * spi_address) +static void execute_command(void) { - u8 val; + write8(spibar + 2, read8(spibar + 2) | 1); - do { - *(spi_address + 2) |= 0x10; - val = *(spi_address + 0xd); - } while (val & 0x7); + while ((read8(spibar + 2) & 1) && (read8(spibar+3) & 0x80)); } -u8 read_spi_status(volatile u8 * spi_address) +void spi_init() { - u8 val; - *spi_address = 0x05; - *(spi_address + 1) = 0x21; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = 0x0; /* dummy */ - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - reset_internal_fifo_pointer(spi_address); - val = *(spi_address + 0xC); - val = *(spi_address + 0xC); - val = *(spi_address + 0xC); - return val; -} + device_t dev; -void wait4flashpart_ready(volatile u8 * spi_address) -{ - while (read_spi_status(spi_address) & 1) ; + dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); + spibar = pci_read_config32(dev, 0xA0) & ~0x1F; } -void write_spi_status(volatile u8 * spi_address, u8 status) +int spi_xfer(struct spi_slave *slave, const void *dout, + unsigned int bitsout, void *din, unsigned int bitsin) { - *spi_address = 0x50; /* EWSR */ - *(spi_address + 1) = 0; /* RxByte=TxByte=0 */ - execute_command(spi_address); - wait4command_complete(spi_address); - - *spi_address = 0x01; /* WRSR */ - *(spi_address + 1) = 0x01; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = status; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); - - read_spi_status(spi_address); -} + /* First byte is cmd which can not being sent through FIFO. */ + u8 cmd = *(u8 *)dout++; + u8 readoffby1; + u8 readwrite; + u8 bytesout, bytesin; + u8 count; -void read_spi_id(volatile u8 * spi_address) -{ - u8 mid = 0, did = 0; - *spi_address = 0x90; - *(spi_address + 1) = 0x23; /* RxByte=2, TxByte=3 */ - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = 0; - *(spi_address + 0xC) = 0; - *(spi_address + 0xC) = 0; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - reset_internal_fifo_pointer(spi_address); - mid = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); - mid = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); - mid = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); - - mid = *(spi_address + 0xC); - did = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); -} + bitsout -= 8; + bytesout = bitsout / 8; + bytesin = bitsin / 8; -void spi_write_enable(volatile u8 * spi_address) -{ - *spi_address = 0x06; /* Write Enable */ - *(spi_address + 1) = 0x0; /* RxByte=0, TxByte=0 */ - execute_command(spi_address); - wait4command_complete(spi_address); -} + readoffby1 = bytesout ? 0 : 1; -void spi_write_disable(volatile u8 * spi_address) + readwrite = (bytesin + readoffby1) << 4 | bytesout; + write8(spibar+1, readwrite); + write8(spibar + 0, cmd); + + reset_internal_fifo_pointer(); + + for (count = 0; count < bytesout; count++, dout++) { + write8(spibar + 0x0C, *(u8 *)dout); + } + + reset_internal_fifo_pointer(); + + execute_command(); + + reset_internal_fifo_pointer(); + + /* Skip the bytes we sent. */ + for (count = 0; count < bytesout; count++) { + cmd = read8(spibar + 0x0C); + } + reset_internal_fifo_pointer(); + for (count = 0; count < bytesin; count++, din++) { + *(u8 *)din = read8(spibar + 0x0C); + } + + return 0; +} +int spi_claim_bus(struct spi_slave *slave) { - *spi_address = 0x04; /* Write Enable */ - *(spi_address + 1) = 0x0; /* RxByte=0, TxByte=0 */ - execute_command(spi_address); - wait4command_complete(spi_address); + return 0; } -void sector_erase_spi(volatile u8 * spi_address, u32 address) +void spi_release_bus(struct spi_slave *slave) { - spi_write_enable(spi_address); - *spi_address = 0x20; - *(spi_address + 1) = 0x03; /* RxByte=0, TxByte=3 */ - - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); } -void chip_erase_spi(volatile u8 * spi_address) +void spi_cs_activate(struct spi_slave *slave) { - spi_write_enable(spi_address); - *spi_address = 0xC7; - *(spi_address + 1) = 0x00; - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); } -void byte_program(volatile u8 * spi_address, u32 address, u32 data) +void spi_cs_deactivate(struct spi_slave *slave) { - spi_write_enable(spi_address); - *spi_address = 0x02; - *(spi_address + 1) = 0x0 << 4 | 4; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - *(spi_address + 0xC) = data & 0xFF; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); } -void dword_noneAAI_program(volatile u8 * spi_address, u32 address, u32 data) +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) { - u8 i; - /* - * printk(BIOS_SPEW, "%s: addr=%x, data=%x\n", __func__, address, data); - */ - for (i = 0; i < 4; i++) { - spi_write_enable(spi_address); - *spi_address = 0x02; - *(spi_address + 1) = 0x0 << 4 | 4; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - *(spi_address + 0xC) = data & 0xFF; - data >>= 8; - address++; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); + struct spi_slave *slave = malloc(sizeof(*slave)); + + if (!slave) { + return NULL; } -} -void dword_program(volatile u8 * spi_address, u32 address, u32 data) -{ - spi_write_enable(spi_address); - *spi_address = 0x02; - *(spi_address + 1) = 0x0 << 4 | 7; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - *(spi_address + 0xC) = data & 0xFF; - *(spi_address + 0xC) = (data >> 8) & 0xFF; - *(spi_address + 0xC) = (data >> 16) & 0xFF; - *(spi_address + 0xC) = (data >> 24) & 0xFF; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); -} + memset(slave, 0, sizeof(*slave)); -void direct_byte_program(volatile u8 * spi_address, volatile u32 * address, u32 data) -{ - spi_write_enable(spi_address); - *address = data; - wait4flashpart_ready(spi_address); + return slave; } diff --git a/src/southbridge/amd/agesa/hudson/spi.h b/src/southbridge/amd/agesa/hudson/spi.h deleted file mode 100644 index 657ce4e..0000000 --- a/src/southbridge/amd/agesa/hudson/spi.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * *************************************************************************** - * - */ - -#ifndef _HUDSON_CIMX_SPI_H_ -#define _HUDSON_CIMX_SPI_H_ - -void execute_command(volatile u8 * spi_address); -void wait4command_complete(volatile u8 * spi_address); -void reset_internal_fifo_pointer(volatile u8 * spi_address); -u8 read_spi_status(volatile u8 * spi_address); -void wait4flashpart_ready(volatile u8 * spi_address); -void write_spi_status(volatile u8 * spi_address, u8 status); -void read_spi_id(volatile u8 * spi_address); -void spi_write_enable(volatile u8 * spi_address); -void spi_write_disable(volatile u8 * spi_address); -void sector_erase_spi(volatile u8 * spi_address, u32 address); -void chip_erase_spi(volatile u8 * spi_address); -void byte_program(volatile u8 * spi_address, u32 address, u32 data); -void dword_noneAAI_program(volatile u8 * spi_address, u32 address, u32 data); -void dword_program(volatile u8 * spi_address, u32 address, u32 data); -void direct_byte_program(volatile u8 * spi_address, volatile u32 * address, u32 data); - -#endif diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index e1c2ecb..e632113 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -16,201 +16,109 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> +#include <stdint.h> +#include <stdlib.h> #include <arch/io.h> +#include <spi.h> +#include <spi_flash.h> #include <device/device.h> -#include "SBPLATFORM.h" +#include <device/pci.h> +#include <device/pci_ops.h> +static u32 spibar; -void execute_command(volatile u8 * spi_address) +static void reset_internal_fifo_pointer(void) { - *(spi_address + 2) |= 1; + do { + write8(spibar + 2, read8(spibar + 2) | 0x10); + } while (read8(spibar + 0xD) & 0x7); } -void wait4command_complete(volatile u8 * spi_address) +static void execute_command(void) { - while (*(spi_address + 2) & 1) - printk(BIOS_DEBUG, "wait4CommandComplete\n"); + write8(spibar + 2, read8(spibar + 2) | 1); + + while ((read8(spibar + 2) & 1) && (read8(spibar+3) & 0x80)); } -void reset_internal_fifo_pointer(volatile u8 * spi_address) +void spi_init() { - u8 val; + device_t dev; - do { - *(spi_address + 2) |= 0x10; - val = *(spi_address + 0xd); - } while (val & 0x7); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); + spibar = pci_read_config32(dev, 0xA0) & ~0x1F; } -u8 read_spi_status(volatile u8 * spi_address) +int spi_xfer(struct spi_slave *slave, const void *dout, + unsigned int bitsout, void *din, unsigned int bitsin) { - u8 val; - *spi_address = 0x05; - *(spi_address + 1) = 0x11; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = 0x0; /* dummy */ - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - reset_internal_fifo_pointer(spi_address); - val = *(spi_address + 0xC); - val = *(spi_address + 0xC); - return val; -} + /* First byte is cmd which can not being sent through FIFO. */ + u8 cmd = *(u8 *)dout++; + u8 readoffby1; + u8 readwrite; + u8 bytesout, bytesin; + u8 count; -void wait4flashpart_ready(volatile u8 * spi_address) -{ - while (read_spi_status(spi_address) & 1) ; -} + bitsout -= 8; + bytesout = bitsout / 8; + bytesin = bitsin / 8; -void write_spi_status(volatile u8 * spi_address, u8 status) -{ - *spi_address = 0x50; /* EWSR */ - *(spi_address + 1) = 0; /* RxByte=TxByte=0 */ - execute_command(spi_address); - wait4command_complete(spi_address); - - *spi_address = 0x01; /* WRSR */ - *(spi_address + 1) = 0x01; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = status; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); - - read_spi_status(spi_address); -} + readoffby1 = bytesout ? 0 : 1; -void read_spi_id(volatile u8 * spi_address) -{ - u8 mid = 0, did = 0; - *spi_address = 0x90; - *(spi_address + 1) = 0x23; /* RxByte=2, TxByte=3 */ - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = 0; - *(spi_address + 0xC) = 0; - *(spi_address + 0xC) = 0; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - reset_internal_fifo_pointer(spi_address); - mid = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); - mid = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); - mid = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); - - mid = *(spi_address + 0xC); - did = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); -} + readwrite = (bytesin + readoffby1) << 4 | bytesout; + write8(spibar+1, readwrite); + write8(spibar + 0, cmd); -void spi_write_enable(volatile u8 * spi_address) -{ - *spi_address = 0x06; /* Write Enable */ - *(spi_address + 1) = 0x0; /* RxByte=0, TxByte=0 */ - execute_command(spi_address); - wait4command_complete(spi_address); + reset_internal_fifo_pointer(); + + for (count = 0; count < bytesout; count++, dout++) { + write8(spibar + 0x0C, *(u8 *)dout); + } + + reset_internal_fifo_pointer(); + + execute_command(); + + reset_internal_fifo_pointer(); + + /* Skip the bytes we sent. */ + for (count = 0; count < bytesout; count++) { + cmd = read8(spibar + 0x0C); + } + reset_internal_fifo_pointer(); + for (count = 0; count < bytesin; count++, din++) { + *(u8 *)din = read8(spibar + 0x0C); + } + + return 0; } -void spi_write_disable(volatile u8 * spi_address) +int spi_claim_bus(struct spi_slave *slave) { - *spi_address = 0x04; /* Write Enable */ - *(spi_address + 1) = 0x0; /* RxByte=0, TxByte=0 */ - execute_command(spi_address); - wait4command_complete(spi_address); + return 0; } -void sector_erase_spi(volatile u8 * spi_address, u32 address) +void spi_release_bus(struct spi_slave *slave) { - spi_write_enable(spi_address); - *spi_address = 0x20; - *(spi_address + 1) = 0x03; /* RxByte=0, TxByte=3 */ - - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); } -void chip_erase_spi(volatile u8 * spi_address) +void spi_cs_activate(struct spi_slave *slave) { - spi_write_enable(spi_address); - *spi_address = 0xC7; - *(spi_address + 1) = 0x00; - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); } -void byte_program(volatile u8 * spi_address, u32 address, u32 data) +void spi_cs_deactivate(struct spi_slave *slave) { - spi_write_enable(spi_address); - *spi_address = 0x02; - *(spi_address + 1) = 0x0 << 4 | 4; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - *(spi_address + 0xC) = data & 0xFF; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); } -void dword_noneAAI_program(volatile u8 * spi_address, u32 address, u32 data) +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) { - u8 i; - /* - * printk(BIOS_SPEW, "%s: addr=%x, data=%x\n", __func__, address, data); - */ - for (i = 0; i < 4; i++) { - spi_write_enable(spi_address); - *spi_address = 0x02; - *(spi_address + 1) = 0x0 << 4 | 4; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - *(spi_address + 0xC) = data & 0xFF; - data >>= 8; - address++; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); + struct spi_slave *slave = malloc(sizeof(*slave)); + + if (!slave) { + return NULL; } -} -void dword_program(volatile u8 * spi_address, u32 address, u32 data) -{ - spi_write_enable(spi_address); - *spi_address = 0x02; - *(spi_address + 1) = 0x0 << 4 | 7; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - *(spi_address + 0xC) = data & 0xFF; - *(spi_address + 0xC) = (data >> 8) & 0xFF; - *(spi_address + 0xC) = (data >> 16) & 0xFF; - *(spi_address + 0xC) = (data >> 24) & 0xFF; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); -} + memset(slave, 0, sizeof(*slave)); -void direct_byte_program(volatile u8 * spi_address, volatile u32 * address, u32 data) -{ - spi_write_enable(spi_address); - *address = data; - wait4flashpart_ready(spi_address); + return slave; } diff --git a/src/southbridge/amd/cimx/sb800/spi.h b/src/southbridge/amd/cimx/sb800/spi.h deleted file mode 100644 index 57921d9..0000000 --- a/src/southbridge/amd/cimx/sb800/spi.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * *************************************************************************** - * - */ - -#ifndef _SB800_CIMX_SPI_H_ -#define _SB800_CIMX_SPI_H_ - -void execute_command(volatile u8 * spi_address); -void wait4command_complete(volatile u8 * spi_address); -void reset_internal_fifo_pointer(volatile u8 * spi_address); -u8 read_spi_status(volatile u8 * spi_address); -void wait4flashpart_ready(volatile u8 * spi_address); -void write_spi_status(volatile u8 * spi_address, u8 status); -void read_spi_id(volatile u8 * spi_address); -void spi_write_enable(volatile u8 * spi_address); -void sector_erase_spi(volatile u8 * spi_address, u32 address); -void chip_erase_spi(volatile u8 * spi_address); -void byte_program(volatile u8 * spi_address, u32 address, u32 data); -void dword_noneAAI_program(volatile u8 * spi_address, u32 address, u32 data); -void dword_program(volatile u8 * spi_address, u32 address, u32 data); -void direct_byte_program(volatile u8 * spi_address, volatile u32 * address, u32 data); - -#endif

1 0

Patch merged into coreboot/master: b8117b0 SPI/SST: Add OpCode Enable-Write-Status-Register (EWSR)
by gerrit＠coreboot.org 27 Nov '12

27 Nov '12

the following patch was just integrated into master: commit b8117b062266eda6b8ac9a8b60881a99f0323a48 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Tue Nov 27 18:08:53 2012 +0800 SPI/SST: Add OpCode Enable-Write-Status-Register (EWSR) For SST chips, the Write-Status-Register instruction must be executed immediately after the execution of the Enable-Write-Status-Register instruction, instead of Write-Enable. Change-Id: I4b3473cd671829def3bd1641ececcf8d9dad4a56 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> Reviewed-on: http://review.coreboot.org/1919 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Tue Nov 27 11:03:52 2012, giving +2 See http://review.coreboot.org/1919 for details. -gerrit

1 0

New patch to review for coreboot: 5b5b3de roda/rk886ex: Correct COMB irq reading / reduce warnings
by Patrick Georgi 27 Nov '12

27 Nov '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1923 -gerrit commit 5b5b3de9984f742f7569d9e2f21be1181e033177 Author: Nico Huber <nico.huber(a)secunet.com> Date: Fri Sep 7 10:40:36 2012 +0200 roda/rk886ex: Correct COMB irq reading / reduce warnings The calculation of COMB's irq reading was wrong by the 4-bit shift. Also, the asl compiler warned about the splitting in lo/hi bytes which seems unnecessary. Change-Id: Ia5101d5a19f68c2da827d7e37a18922f959604c7 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- src/mainboard/roda/rk886ex/acpi/superio.asl | 57 ++++++++++++----------------- 1 file changed, 23 insertions(+), 34 deletions(-) diff --git a/src/mainboard/roda/rk886ex/acpi/superio.asl b/src/mainboard/roda/rk886ex/acpi/superio.asl index 184ff29..174f2f1 100644 --- a/src/mainboard/roda/rk886ex/acpi/superio.asl +++ b/src/mainboard/roda/rk886ex/acpi/superio.asl @@ -130,28 +130,23 @@ Device (SIO1) Return(NONE) } - CreateByteField(RSRC, - \_SB.PCI0.LPCB.SIO1.COMA._CRS._IOA._MIN, IOLO) - CreateByteField(RSRC, 0x03, IOHI) // Why? - CreateByteField(RSRC, - \_SB.PCI0.LPCB.SIO1.COMA._CRS._IOA._MAX, IORL) - CreateByteField(RSRC, 0x05, IORH) // Why? - CreateByteField(RSRC, - \_SB.PCI0.LPCB.SIO1.COMA._CRS._IRA._INT, IRQL) - - Store (READ(0, 0x24, 0xff), Local0) - And (Local0, 0xc0, Local1) - ShiftRight(Local1, 0x06, Local1) + CreateWordField(RSRC, + \_SB.PCI0.LPCB.SIO1.COMA._CRS._IOA._MIN, IOMN) + CreateWordField(RSRC, + \_SB.PCI0.LPCB.SIO1.COMA._CRS._IOA._MAX, IOMX) + CreateWordField(RSRC, + \_SB.PCI0.LPCB.SIO1.COMA._CRS._IRA._INT, IRQ) + + /* I/O Base */ + Store (READ(0, 0x24, 0xfe), Local0) ShiftLeft(Local0, 0x02, Local0) - Store(Local0, IOLO) - Store(Local1, IOHI) - Store(IOLO, IORL) - Store(IOHI, IORH) + Store(Local0, IOMN) + Store(Local0, IOMX) /* Interrupt */ Store(READ(0, 0x28, 0xf0), Local0) ShiftRight(Local0, 4, Local0) - ShiftLeft(1, Local0, IRQL) + ShiftLeft(1, Local0, IRQ) Return(RSRC) } @@ -289,28 +284,22 @@ Device (SIO1) Return(NONE) } - CreateByteField(RSRC, - \_SB.PCI0.LPCB.SIO1.COMB._CRS._IOB._MIN, IOLO) - CreateByteField(RSRC, 0x03, IOHI) - CreateByteField(RSRC, - \_SB.PCI0.LPCB.SIO1.COMB._CRS._IOB._MAX, IORL) - CreateByteField(RSRC, 0x05, IORH) - CreateByteField(RSRC, - \_SB.PCI0.LPCB.SIO1.COMB._CRS._IRB._INT, IRQL) + CreateWordField(RSRC, + \_SB.PCI0.LPCB.SIO1.COMA._CRS._IOA._MIN, IOMN) + CreateWordField(RSRC, + \_SB.PCI0.LPCB.SIO1.COMA._CRS._IOA._MAX, IOMX) + CreateWordField(RSRC, + \_SB.PCI0.LPCB.SIO1.COMA._CRS._IRA._INT, IRQ) - Store (READ(0, 0x25, 0xff), Local0) - And (Local0, 0xc0, Local1) - ShiftRight(Local1, 0x06, Local1) + /* I/O Base */ + Store (READ(0, 0x25, 0xfe), Local0) ShiftLeft(Local0, 0x02, Local0) - Store(Local0, IOLO) - Store(Local1, IOHI) - Store(IOLO, IORL) - Store(IOHI, IORH) + Store(Local0, IOMN) + Store(Local0, IOMX) /* Interrupt */ Store(READ(0, 0x28, 0x0f), Local0) - ShiftRight(Local0, 4, Local0) - ShiftLeft(1, Local0, IRQL) + ShiftLeft(1, Local0, IRQ) Return(RSRC) }

1 0

New patch to review for coreboot: 287d190 libpayload: Add _ and + to USB HID keymap
by Patrick Georgi 27 Nov '12

27 Nov '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1922 -gerrit commit 287d190ae39dfb0ca084e3291814002639365b02 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Nov 27 10:19:59 2012 +0100 libpayload: Add _ and + to USB HID keymap Slightly more complete keymap Change-Id: I4fef6b8f75ab07cb20a3a8ccd7eaad81c9fe719f Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- payloads/libpayload/drivers/usb/usbhid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/libpayload/drivers/usb/usbhid.c b/payloads/libpayload/drivers/usb/usbhid.c index 9464680..6af2568 100644 --- a/payloads/libpayload/drivers/usb/usbhid.c +++ b/payloads/libpayload/drivers/usb/usbhid.c @@ -173,7 +173,7 @@ static const struct layout_maps keyboard_layouts[] = { 'U', 'V', 'W', 'X', 'Y', 'Z', '!', '@', /* 0x20 */ '#', '$', '%', '^', '&', '*', '(', ')', - '\n', '\e', '\b', '\t', ' ', '-', '=', '[', + '\n', '\e', '\b', '\t', ' ', '_', '+', '[', /* 0x30 */ ']', '\\', -1, ':', '\'', '`', ',', '.', '/', -1 /* CapsLk */, KEY_F(1), KEY_F(2), KEY_F(3), KEY_F(4), KEY_F(5), KEY_F(6),

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Patch merged into coreboot/master: 1a5301d abuild: only rebuild boards if requested or after a broken build
by gerrit＠coreboot.org 27 Nov '12

27 Nov '12

the following patch was just integrated into master: commit 1a5301dd3373e7def334fc34787f79073f49029a Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Nov 22 14:19:43 2012 +0100 abuild: only rebuild boards if requested or after a broken build That used to be the behaviour, and it's quite useful to incrementally fix bugs across the tree. Change-Id: I3e30cbdcf01631bc29f892054caa3babb0969beb Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Reviewed-on: http://review.coreboot.org/1888 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/1888 for details. -gerrit

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Patch set updated for coreboot: 97ce68e AMD S3: Leverage the public SPI routine
by Zheng Bao 27 Nov '12

27 Nov '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1920 -gerrit commit 97ce68eb4127e1306dd43a303e16247126ae5bff Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Tue Nov 27 18:10:08 2012 +0800 AMD S3: Leverage the public SPI routine Remove the old, unflexible code for storing S3 data in SPI flash. Tested on Parmer. Change-Id: I60a10476befb4afab2b4241f01a988f4a8bb22cd Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/cpu/amd/agesa/s3_resume.c | 88 ++++++------- src/southbridge/amd/Kconfig | 4 + src/southbridge/amd/agesa/hudson/spi.c | 234 ++++++++++----------------------- src/southbridge/amd/agesa/hudson/spi.h | 43 ------ src/southbridge/amd/cimx/sb800/spi.c | 230 ++++++++++---------------------- src/southbridge/amd/cimx/sb800/spi.h | 42 ------ 6 files changed, 183 insertions(+), 458 deletions(-) diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 0348a9f..6302c3d 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -41,7 +41,8 @@ #include "agesawrapper.h" #ifndef __PRE_RAM__ -#include "spi.h" +#include <spi.h> +#include <spi_flash.h> #endif void restore_mtrr(void) @@ -151,14 +152,18 @@ void move_stack_high_mem(void) void OemAgesaSaveMtrr(void) { #ifndef __PRE_RAM__ - u32 spi_address; msr_t msr_data; - device_t dev; u32 nvram_pos = S3_DATA_MTRR_POS; u32 i; + struct spi_flash *flash; - dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); - spi_address = pci_read_config32(dev, 0xA0) & ~0x1F; + spi_init(); + + flash = spi_flash_probe(0, 0, 0, 0); + if (!flash) { + printk(BIOS_DEBUG, "Could not find SPI device\n"); + return; + } /* Enable access to AMD RdDram and WrDram extension bits */ msr_data = rdmsr(SYS_CFG); @@ -167,28 +172,29 @@ void OemAgesaSaveMtrr(void) /* Fixed MTRRs */ msr_data = rdmsr(0x250); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; msr_data = rdmsr(0x258); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; msr_data = rdmsr(0x259); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; for (i = 0x268; i < 0x270; i++) { msr_data = rdmsr(i); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; } @@ -200,35 +206,33 @@ void OemAgesaSaveMtrr(void) /* Variable MTRRs */ for (i = 0x200; i < 0x210; i++) { msr_data = rdmsr(i); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; } /* SYS_CFG */ msr_data = rdmsr(0xC0010010); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; /* TOM */ msr_data = rdmsr(0xC001001A); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; /* TOM2 */ msr_data = rdmsr(0xC001001D); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; - write_spi_status((u8 *)spi_address, 0x3c); - spi_write_disable((u8 *) spi_address); #endif } @@ -251,9 +255,9 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) { u32 pos = S3_DATA_VOLATILE_POS; - u32 spi_address, data; + u32 data; u32 nvram_pos; - device_t dev; + struct spi_flash *flash; if (S3DataType == S3DataTypeNonVolatile) { pos = S3_DATA_NONVOLATILE_POS; @@ -261,39 +265,27 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) pos = S3_DATA_VOLATILE_POS; } - dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); - spi_address = pci_read_config32(dev, 0xA0) & ~0x1F; + spi_init(); + flash = spi_flash_probe(0, 0, 0, 0); + if (!flash) { + printk(BIOS_DEBUG, "Could not find SPI device\n"); + /* Dont make flow stop. */ + return AGESA_SUCCESS; + } - /* printk(BIOS_DEBUG, "spi_address=%x\n", spi_address); */ - read_spi_id((u8 *) spi_address); - write_spi_status((u8 *)spi_address, 0); if (S3DataType == S3DataTypeNonVolatile) { - sector_erase_spi((u8 *) spi_address, S3_DATA_NONVOLATILE_POS); + flash->erase(flash, S3_DATA_NONVOLATILE_POS, 0x1000); } else { - sector_erase_spi((u8 *) spi_address, S3_DATA_VOLATILE_POS); - sector_erase_spi((u8 *) spi_address, - S3_DATA_VOLATILE_POS + 0x1000); - sector_erase_spi((u8 *) spi_address, - S3_DATA_VOLATILE_POS + 0x2000); - sector_erase_spi((u8 *) spi_address, - S3_DATA_VOLATILE_POS + 0x3000); - sector_erase_spi((u8 *) spi_address, - S3_DATA_VOLATILE_POS + 0x4000); - sector_erase_spi((u8 *) spi_address, - S3_DATA_VOLATILE_POS + 0x5000); + flash->erase(flash, S3_DATA_VOLATILE_POS, 0x6000); } nvram_pos = 0; - dword_noneAAI_program((u8 *) spi_address, nvram_pos + pos, DataSize); + flash->write(flash, nvram_pos + pos, sizeof(DataSize), &DataSize); for (nvram_pos = 0; nvram_pos < DataSize; nvram_pos += 4) { data = *(u32 *) (Data + nvram_pos); - dword_noneAAI_program((u8 *) spi_address, nvram_pos + pos + 4, - *(u32 *) (Data + nvram_pos)); + flash->write(flash, nvram_pos + pos + 4, sizeof(u32), (u32 *)(Data + nvram_pos)); } - /* write_spi_status((u8 *)spi_address, 0x3c); */ - - /* spi_write_disable((u8 *) spi_address); */ return AGESA_SUCCESS; } diff --git a/src/southbridge/amd/Kconfig b/src/southbridge/amd/Kconfig index 867afca..20d5573 100644 --- a/src/southbridge/amd/Kconfig +++ b/src/southbridge/amd/Kconfig @@ -14,3 +14,7 @@ source src/southbridge/amd/sb800/Kconfig source src/southbridge/amd/cimx/Kconfig source src/southbridge/amd/agesa/Kconfig source src/southbridge/amd/sr5650/Kconfig + +config SPI_FLASH + bool + default y if HAVE_ACPI_RESUME && CPU_AMD_AGESA diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index ad8b6d4..e632113 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -16,203 +16,109 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> +#include <stdint.h> +#include <stdlib.h> #include <arch/io.h> +#include <spi.h> +#include <spi_flash.h> #include <device/device.h> -#include "spi.h" +#include <device/pci.h> +#include <device/pci_ops.h> -void execute_command(volatile u8 * spi_address) -{ - *(spi_address + 2) |= 1; -} +static u32 spibar; -void wait4command_complete(volatile u8 * spi_address) +static void reset_internal_fifo_pointer(void) { -// while (*(spi_address + 2) & 1) - while ((*(spi_address + 2) & 1) && (*(spi_address + 3) & 0x80)) - printk(BIOS_DEBUG, "wait4CommandComplete\n"); + do { + write8(spibar + 2, read8(spibar + 2) | 0x10); + } while (read8(spibar + 0xD) & 0x7); } -void reset_internal_fifo_pointer(volatile u8 * spi_address) +static void execute_command(void) { - u8 val; + write8(spibar + 2, read8(spibar + 2) | 1); - do { - *(spi_address + 2) |= 0x10; - val = *(spi_address + 0xd); - } while (val & 0x7); + while ((read8(spibar + 2) & 1) && (read8(spibar+3) & 0x80)); } -u8 read_spi_status(volatile u8 * spi_address) +void spi_init() { - u8 val; - *spi_address = 0x05; - *(spi_address + 1) = 0x21; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = 0x0; /* dummy */ - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - reset_internal_fifo_pointer(spi_address); - val = *(spi_address + 0xC); - val = *(spi_address + 0xC); - val = *(spi_address + 0xC); - return val; -} + device_t dev; -void wait4flashpart_ready(volatile u8 * spi_address) -{ - while (read_spi_status(spi_address) & 1) ; + dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); + spibar = pci_read_config32(dev, 0xA0) & ~0x1F; } -void write_spi_status(volatile u8 * spi_address, u8 status) +int spi_xfer(struct spi_slave *slave, const void *dout, + unsigned int bitsout, void *din, unsigned int bitsin) { - *spi_address = 0x50; /* EWSR */ - *(spi_address + 1) = 0; /* RxByte=TxByte=0 */ - execute_command(spi_address); - wait4command_complete(spi_address); - - *spi_address = 0x01; /* WRSR */ - *(spi_address + 1) = 0x01; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = status; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); - - read_spi_status(spi_address); -} + /* First byte is cmd which can not being sent through FIFO. */ + u8 cmd = *(u8 *)dout++; + u8 readoffby1; + u8 readwrite; + u8 bytesout, bytesin; + u8 count; -void read_spi_id(volatile u8 * spi_address) -{ - u8 mid = 0, did = 0; - *spi_address = 0x90; - *(spi_address + 1) = 0x23; /* RxByte=2, TxByte=3 */ - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = 0; - *(spi_address + 0xC) = 0; - *(spi_address + 0xC) = 0; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - reset_internal_fifo_pointer(spi_address); - mid = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); - mid = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); - mid = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); - - mid = *(spi_address + 0xC); - did = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); -} + bitsout -= 8; + bytesout = bitsout / 8; + bytesin = bitsin / 8; -void spi_write_enable(volatile u8 * spi_address) -{ - *spi_address = 0x06; /* Write Enable */ - *(spi_address + 1) = 0x0; /* RxByte=0, TxByte=0 */ - execute_command(spi_address); - wait4command_complete(spi_address); -} + readoffby1 = bytesout ? 0 : 1; -void spi_write_disable(volatile u8 * spi_address) + readwrite = (bytesin + readoffby1) << 4 | bytesout; + write8(spibar+1, readwrite); + write8(spibar + 0, cmd); + + reset_internal_fifo_pointer(); + + for (count = 0; count < bytesout; count++, dout++) { + write8(spibar + 0x0C, *(u8 *)dout); + } + + reset_internal_fifo_pointer(); + + execute_command(); + + reset_internal_fifo_pointer(); + + /* Skip the bytes we sent. */ + for (count = 0; count < bytesout; count++) { + cmd = read8(spibar + 0x0C); + } + reset_internal_fifo_pointer(); + for (count = 0; count < bytesin; count++, din++) { + *(u8 *)din = read8(spibar + 0x0C); + } + + return 0; +} +int spi_claim_bus(struct spi_slave *slave) { - *spi_address = 0x04; /* Write Enable */ - *(spi_address + 1) = 0x0; /* RxByte=0, TxByte=0 */ - execute_command(spi_address); - wait4command_complete(spi_address); + return 0; } -void sector_erase_spi(volatile u8 * spi_address, u32 address) +void spi_release_bus(struct spi_slave *slave) { - spi_write_enable(spi_address); - *spi_address = 0x20; - *(spi_address + 1) = 0x03; /* RxByte=0, TxByte=3 */ - - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); } -void chip_erase_spi(volatile u8 * spi_address) +void spi_cs_activate(struct spi_slave *slave) { - spi_write_enable(spi_address); - *spi_address = 0xC7; - *(spi_address + 1) = 0x00; - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); } -void byte_program(volatile u8 * spi_address, u32 address, u32 data) +void spi_cs_deactivate(struct spi_slave *slave) { - spi_write_enable(spi_address); - *spi_address = 0x02; - *(spi_address + 1) = 0x0 << 4 | 4; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - *(spi_address + 0xC) = data & 0xFF; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); } -void dword_noneAAI_program(volatile u8 * spi_address, u32 address, u32 data) +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) { - u8 i; - /* - * printk(BIOS_SPEW, "%s: addr=%x, data=%x\n", __func__, address, data); - */ - for (i = 0; i < 4; i++) { - spi_write_enable(spi_address); - *spi_address = 0x02; - *(spi_address + 1) = 0x0 << 4 | 4; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - *(spi_address + 0xC) = data & 0xFF; - data >>= 8; - address++; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); + struct spi_slave *slave = malloc(sizeof(*slave)); + + if (!slave) { + return NULL; } -} -void dword_program(volatile u8 * spi_address, u32 address, u32 data) -{ - spi_write_enable(spi_address); - *spi_address = 0x02; - *(spi_address + 1) = 0x0 << 4 | 7; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - *(spi_address + 0xC) = data & 0xFF; - *(spi_address + 0xC) = (data >> 8) & 0xFF; - *(spi_address + 0xC) = (data >> 16) & 0xFF; - *(spi_address + 0xC) = (data >> 24) & 0xFF; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); -} + memset(slave, 0, sizeof(*slave)); -void direct_byte_program(volatile u8 * spi_address, volatile u32 * address, u32 data) -{ - spi_write_enable(spi_address); - *address = data; - wait4flashpart_ready(spi_address); + return slave; } diff --git a/src/southbridge/amd/agesa/hudson/spi.h b/src/southbridge/amd/agesa/hudson/spi.h deleted file mode 100644 index 657ce4e..0000000 --- a/src/southbridge/amd/agesa/hudson/spi.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * *************************************************************************** - * - */ - -#ifndef _HUDSON_CIMX_SPI_H_ -#define _HUDSON_CIMX_SPI_H_ - -void execute_command(volatile u8 * spi_address); -void wait4command_complete(volatile u8 * spi_address); -void reset_internal_fifo_pointer(volatile u8 * spi_address); -u8 read_spi_status(volatile u8 * spi_address); -void wait4flashpart_ready(volatile u8 * spi_address); -void write_spi_status(volatile u8 * spi_address, u8 status); -void read_spi_id(volatile u8 * spi_address); -void spi_write_enable(volatile u8 * spi_address); -void spi_write_disable(volatile u8 * spi_address); -void sector_erase_spi(volatile u8 * spi_address, u32 address); -void chip_erase_spi(volatile u8 * spi_address); -void byte_program(volatile u8 * spi_address, u32 address, u32 data); -void dword_noneAAI_program(volatile u8 * spi_address, u32 address, u32 data); -void dword_program(volatile u8 * spi_address, u32 address, u32 data); -void direct_byte_program(volatile u8 * spi_address, volatile u32 * address, u32 data); - -#endif diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index e1c2ecb..e632113 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -16,201 +16,109 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> +#include <stdint.h> +#include <stdlib.h> #include <arch/io.h> +#include <spi.h> +#include <spi_flash.h> #include <device/device.h> -#include "SBPLATFORM.h" +#include <device/pci.h> +#include <device/pci_ops.h> +static u32 spibar; -void execute_command(volatile u8 * spi_address) +static void reset_internal_fifo_pointer(void) { - *(spi_address + 2) |= 1; + do { + write8(spibar + 2, read8(spibar + 2) | 0x10); + } while (read8(spibar + 0xD) & 0x7); } -void wait4command_complete(volatile u8 * spi_address) +static void execute_command(void) { - while (*(spi_address + 2) & 1) - printk(BIOS_DEBUG, "wait4CommandComplete\n"); + write8(spibar + 2, read8(spibar + 2) | 1); + + while ((read8(spibar + 2) & 1) && (read8(spibar+3) & 0x80)); } -void reset_internal_fifo_pointer(volatile u8 * spi_address) +void spi_init() { - u8 val; + device_t dev; - do { - *(spi_address + 2) |= 0x10; - val = *(spi_address + 0xd); - } while (val & 0x7); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); + spibar = pci_read_config32(dev, 0xA0) & ~0x1F; } -u8 read_spi_status(volatile u8 * spi_address) +int spi_xfer(struct spi_slave *slave, const void *dout, + unsigned int bitsout, void *din, unsigned int bitsin) { - u8 val; - *spi_address = 0x05; - *(spi_address + 1) = 0x11; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = 0x0; /* dummy */ - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - reset_internal_fifo_pointer(spi_address); - val = *(spi_address + 0xC); - val = *(spi_address + 0xC); - return val; -} + /* First byte is cmd which can not being sent through FIFO. */ + u8 cmd = *(u8 *)dout++; + u8 readoffby1; + u8 readwrite; + u8 bytesout, bytesin; + u8 count; -void wait4flashpart_ready(volatile u8 * spi_address) -{ - while (read_spi_status(spi_address) & 1) ; -} + bitsout -= 8; + bytesout = bitsout / 8; + bytesin = bitsin / 8; -void write_spi_status(volatile u8 * spi_address, u8 status) -{ - *spi_address = 0x50; /* EWSR */ - *(spi_address + 1) = 0; /* RxByte=TxByte=0 */ - execute_command(spi_address); - wait4command_complete(spi_address); - - *spi_address = 0x01; /* WRSR */ - *(spi_address + 1) = 0x01; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = status; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); - - read_spi_status(spi_address); -} + readoffby1 = bytesout ? 0 : 1; -void read_spi_id(volatile u8 * spi_address) -{ - u8 mid = 0, did = 0; - *spi_address = 0x90; - *(spi_address + 1) = 0x23; /* RxByte=2, TxByte=3 */ - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = 0; - *(spi_address + 0xC) = 0; - *(spi_address + 0xC) = 0; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - reset_internal_fifo_pointer(spi_address); - mid = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); - mid = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); - mid = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); - - mid = *(spi_address + 0xC); - did = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); -} + readwrite = (bytesin + readoffby1) << 4 | bytesout; + write8(spibar+1, readwrite); + write8(spibar + 0, cmd); -void spi_write_enable(volatile u8 * spi_address) -{ - *spi_address = 0x06; /* Write Enable */ - *(spi_address + 1) = 0x0; /* RxByte=0, TxByte=0 */ - execute_command(spi_address); - wait4command_complete(spi_address); + reset_internal_fifo_pointer(); + + for (count = 0; count < bytesout; count++, dout++) { + write8(spibar + 0x0C, *(u8 *)dout); + } + + reset_internal_fifo_pointer(); + + execute_command(); + + reset_internal_fifo_pointer(); + + /* Skip the bytes we sent. */ + for (count = 0; count < bytesout; count++) { + cmd = read8(spibar + 0x0C); + } + reset_internal_fifo_pointer(); + for (count = 0; count < bytesin; count++, din++) { + *(u8 *)din = read8(spibar + 0x0C); + } + + return 0; } -void spi_write_disable(volatile u8 * spi_address) +int spi_claim_bus(struct spi_slave *slave) { - *spi_address = 0x04; /* Write Enable */ - *(spi_address + 1) = 0x0; /* RxByte=0, TxByte=0 */ - execute_command(spi_address); - wait4command_complete(spi_address); + return 0; } -void sector_erase_spi(volatile u8 * spi_address, u32 address) +void spi_release_bus(struct spi_slave *slave) { - spi_write_enable(spi_address); - *spi_address = 0x20; - *(spi_address + 1) = 0x03; /* RxByte=0, TxByte=3 */ - - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); } -void chip_erase_spi(volatile u8 * spi_address) +void spi_cs_activate(struct spi_slave *slave) { - spi_write_enable(spi_address); - *spi_address = 0xC7; - *(spi_address + 1) = 0x00; - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); } -void byte_program(volatile u8 * spi_address, u32 address, u32 data) +void spi_cs_deactivate(struct spi_slave *slave) { - spi_write_enable(spi_address); - *spi_address = 0x02; - *(spi_address + 1) = 0x0 << 4 | 4; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - *(spi_address + 0xC) = data & 0xFF; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); } -void dword_noneAAI_program(volatile u8 * spi_address, u32 address, u32 data) +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) { - u8 i; - /* - * printk(BIOS_SPEW, "%s: addr=%x, data=%x\n", __func__, address, data); - */ - for (i = 0; i < 4; i++) { - spi_write_enable(spi_address); - *spi_address = 0x02; - *(spi_address + 1) = 0x0 << 4 | 4; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - *(spi_address + 0xC) = data & 0xFF; - data >>= 8; - address++; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); + struct spi_slave *slave = malloc(sizeof(*slave)); + + if (!slave) { + return NULL; } -} -void dword_program(volatile u8 * spi_address, u32 address, u32 data) -{ - spi_write_enable(spi_address); - *spi_address = 0x02; - *(spi_address + 1) = 0x0 << 4 | 7; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - *(spi_address + 0xC) = data & 0xFF; - *(spi_address + 0xC) = (data >> 8) & 0xFF; - *(spi_address + 0xC) = (data >> 16) & 0xFF; - *(spi_address + 0xC) = (data >> 24) & 0xFF; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); -} + memset(slave, 0, sizeof(*slave)); -void direct_byte_program(volatile u8 * spi_address, volatile u32 * address, u32 data) -{ - spi_write_enable(spi_address); - *address = data; - wait4flashpart_ready(spi_address); + return slave; } diff --git a/src/southbridge/amd/cimx/sb800/spi.h b/src/southbridge/amd/cimx/sb800/spi.h deleted file mode 100644 index 57921d9..0000000 --- a/src/southbridge/amd/cimx/sb800/spi.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * *************************************************************************** - * - */ - -#ifndef _SB800_CIMX_SPI_H_ -#define _SB800_CIMX_SPI_H_ - -void execute_command(volatile u8 * spi_address); -void wait4command_complete(volatile u8 * spi_address); -void reset_internal_fifo_pointer(volatile u8 * spi_address); -u8 read_spi_status(volatile u8 * spi_address); -void wait4flashpart_ready(volatile u8 * spi_address); -void write_spi_status(volatile u8 * spi_address, u8 status); -void read_spi_id(volatile u8 * spi_address); -void spi_write_enable(volatile u8 * spi_address); -void sector_erase_spi(volatile u8 * spi_address, u32 address); -void chip_erase_spi(volatile u8 * spi_address); -void byte_program(volatile u8 * spi_address, u32 address, u32 data); -void dword_noneAAI_program(volatile u8 * spi_address, u32 address, u32 data); -void dword_program(volatile u8 * spi_address, u32 address, u32 data); -void direct_byte_program(volatile u8 * spi_address, volatile u32 * address, u32 data); - -#endif

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Patch set updated for coreboot: e3e7dad SPI/SST: Add OpCode Enable-Write-Status-Register (EWSR)
by Zheng Bao 27 Nov '12

27 Nov '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1919 -gerrit commit e3e7dad5e6389354125108a41bd25c673a556d64 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Tue Nov 27 18:08:53 2012 +0800 SPI/SST: Add OpCode Enable-Write-Status-Register (EWSR) For SST chips, the Write-Status-Register instruction must be executed immediately after the execution of the Enable-Write-Status-Register instruction, instead of Write-Enable. Change-Id: I4b3473cd671829def3bd1641ececcf8d9dad4a56 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/drivers/spi/sst.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c index 8245f72..ebeb441 100644 --- a/src/drivers/spi/sst.c +++ b/src/drivers/spi/sst.c @@ -20,6 +20,7 @@ #define CMD_SST_WRDI 0x04 /* Write Disable */ #define CMD_SST_RDSR 0x05 /* Read Status Register */ #define CMD_SST_WRSR 0x01 /* Write Status Register */ +#define CMD_SST_EWSR 0x50 /* Enable Write Status Register */ #define CMD_SST_READ 0x03 /* Read Data Bytes */ #define CMD_SST_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ #define CMD_SST_BP 0x02 /* Byte Program */ @@ -101,6 +102,15 @@ sst_enable_writing(struct spi_flash *flash) } static int +sst_enable_writing_status(struct spi_flash *flash) +{ + int ret = spi_flash_cmd(flash->spi, CMD_SST_EWSR, NULL, 0); + if (ret) + printk(BIOS_WARNING, "SF: Enabling Write Status failed\n"); + return ret; +} + +static int sst_disable_writing(struct spi_flash *flash) { int ret = spi_flash_cmd(flash->spi, CMD_SST_WRDI, NULL, 0); @@ -212,7 +222,7 @@ sst_unlock(struct spi_flash *flash) int ret; u8 cmd, status; - ret = sst_enable_writing(flash); + ret = sst_enable_writing_status(flash); if (ret) return ret;

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coreboot November 2012