coreboot October 2012

coreboot@coreboot.org

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New patch to review for coreboot: af39c1c crossgcc: fix compilation of acpica
by Idwer Vollering 23 Oct '12

23 Oct '12

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1607 -gerrit commit af39c1c92fbd52605b772d2f3ab667b1d439f149 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Tue Oct 23 19:49:36 2012 +0200 crossgcc: fix compilation of acpica Compilation of acpica-2012042 is broken (and old, but I'll take care of that in a future patch), let's fix that ("Building IASL 20120420 ... failed"). Increase CROSSGCC_VERSION to 1.08 Change-Id: If5fd5cd93d748f78b7c059323f9f810666e32cc7 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- util/crossgcc/buildgcc | 4 ++-- .../patches/acpica-unix-20120420_unknown_warnings.patch | 10 +++++----- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 71f4e16..f71bf66 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -20,8 +20,8 @@ # Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA # -CROSSGCC_DATE="November 1st, 2011" -CROSSGCC_VERSION="1.07" +CROSSGCC_DATE="October 23rd, 2012" +CROSSGCC_VERSION="1.08" # default settings TARGETDIR=`pwd`/xgcc diff --git a/util/crossgcc/patches/acpica-unix-20120420_unknown_warnings.patch b/util/crossgcc/patches/acpica-unix-20120420_unknown_warnings.patch index d1c954f..c027f17 100644 --- a/util/crossgcc/patches/acpica-unix-20120420_unknown_warnings.patch +++ b/util/crossgcc/patches/acpica-unix-20120420_unknown_warnings.patch @@ -1,6 +1,6 @@ ---- acpica-unix-20120420/source/compiler/Makefile 2012-04-21 04:02:33.000000000 +0800 -+++ acpica-unix-20120420/source/compiler/Makefile 2012-08-08 18:06:11.000000000 +0800 -@@ -257,19 +257,12 @@ +--- acpica-unix-20120420/source/compiler/Makefile 2012-04-20 22:02:33.000000000 +0200 ++++ acpica-unix-20120420.patched/source/compiler/Makefile 2012-10-21 00:30:38.634470788 +0200 +@@ -257,19 +257,11 @@ # gcc 4+ flags # CWARNINGFLAGS += \ @@ -14,10 +14,10 @@ - -Wmissing-parameter-type \ -Wnested-externs \ - -Wold-style-declaration \ - -Wold-style-definition \ +- -Wold-style-definition \ - -Wredundant-decls \ - -Wtype-limits -+ -Wredundant-decls ++ -Wold-style-definition # # Bison/Flex configuration

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Patch set updated for coreboot: 60c1b92 crossgcc: update to gcc 4.7.2
by Idwer Vollering 23 Oct '12

23 Oct '12

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1597 -gerrit commit 60c1b92aa68ef44bb7556415e4366929080d003a Author: Idwer Vollering <vidwer(a)gmail.com> Date: Sun Oct 21 03:00:45 2012 +0200 crossgcc: update to gcc 4.7.2 Update crossgcc to use gcc 4.7.2. This requires a minor change to util/crossgcc/buildgcc as well. Increase CROSSGCC_VERSION to 1.10 Tested on hardware with asus/p2b and lenovo/x60. Change-Id: I1e016831e6e467b818b454e6db67ea4db862c1d6 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- util/crossgcc/buildgcc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index ff67e02..6363ce2 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -20,8 +20,8 @@ # Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA # -CROSSGCC_DATE="November 1st, 2011" -CROSSGCC_VERSION="1.07" +CROSSGCC_DATE="October 23rd, 2012" +CROSSGCC_VERSION="1.10" # default settings TARGETDIR=`pwd`/xgcc @@ -33,7 +33,7 @@ GMP_VERSION=5.0.5 MPFR_VERSION=3.1.0 MPC_VERSION=0.9 LIBELF_VERSION=0.8.13 -GCC_VERSION=4.6.3 +GCC_VERSION=4.7.2 GCC_AUTOCONF_VERSION=2.64 BINUTILS_VERSION=2.22 GDB_VERSION=7.4.1 @@ -49,7 +49,7 @@ GMP_ARCHIVE="http://ftpmirror.gnu.org/gmp/gmp-${GMP_VERSION}.tar.bz2" MPFR_ARCHIVE="http://ftpmirror.gnu.org/mpfr/mpfr-${MPFR_VERSION}.tar.bz2" MPC_ARCHIVE="http://www.multiprecision.org/mpc/download/mpc-${MPC_VERSION}.tar.gz" LIBELF_ARCHIVE="http://www.mr511.de/software/libelf-${LIBELF_VERSION}.tar.gz" -GCC_ARCHIVE="http://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}/gcc-core-${GCC_VERSION}.tar…" +GCC_ARCHIVE="http://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}/gcc-${GCC_VERSION}.tar.bz2" BINUTILS_ARCHIVE="http://ftpmirror.gnu.org/binutils/binutils-${BINUTILS_VERSION}.tar.bz2" GDB_ARCHIVE="http://ftpmirror.gnu.org/gdb/gdb-${GDB_VERSION}.tar.bz2" W32API_ARCHIVE="http://downloads.sourceforge.net/project/mingw/MinGW/BaseSystem/RuntimeLibr…"

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Patch set updated for coreboot: eed6826 crossgcc: update to acpica-20121018
by Idwer Vollering 23 Oct '12

23 Oct '12

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1596 -gerrit commit eed6826f25b6e0b34cba18fd6f360397f5825ffa Author: Idwer Vollering <vidwer(a)gmail.com> Date: Sun Oct 21 02:43:47 2012 +0200 crossgcc: update to acpica-20121018 This patch updates crossgcc to download acpica-20121018 and compile iasl. To do this, changes to util/crossgcc/buildgcc are necessary. Increase CROSSGCC_VERSION to 1.09 Change-Id: Ib565c7185eccdce76783f4520bed04539de50962 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- util/crossgcc/buildgcc | 19 +++++----- .../acpica-unix-20120420_unknown_warnings.patch | 23 ----------- .../acpica-unix-20121018_unknown_warnings.patch | 44 ++++++++++++++++++++++ 3 files changed, 54 insertions(+), 32 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 71f4e16..eee215a 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -20,8 +20,8 @@ # Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA # -CROSSGCC_DATE="November 1st, 2011" -CROSSGCC_VERSION="1.07" +CROSSGCC_DATE="October 23rd, 2012" +CROSSGCC_VERSION="1.09" # default settings TARGETDIR=`pwd`/xgcc @@ -40,7 +40,7 @@ GDB_VERSION=7.4.1 W32API_VERSION=3.17-2 W32API_VERSION_SHORT=3.17 MINGWRT_VERSION=3.18 -IASL_VERSION=20120420 +IASL_VERSION=20121018 PYTHON_VERSION=2.7.2 EXPAT_VERSION=2.0.1 @@ -591,14 +591,15 @@ if [ -f $IASL_DIR/source/compiler/.success ]; then else printf "Building IASL ${IASL_VERSION} ... " ( - cd $IASL_DIR/source/compiler + cd $IASL_DIR/generate/unix export PATH=$PATH:$DESTDIR$TARGETDIR/bin - rm -f .failed + rm -f ../../source/compiler/.failed CFLAGS="$HOSTCFLAGS" - $MAKE CC="$CC" || touch .failed - rm -f $DESTDIR$TARGETDIR/bin/iasl || touch .failed - cp iasl $DESTDIR$TARGETDIR/bin || touch .failed - if [ ! -f .failed ]; then touch .success; fi + $MAKE CC="$CC" iasl || touch ../../source/compiler/.failed + rm -f $DESTDIR$TARGETDIR/bin/iasl || touch ../../source/compiler/.failed + if [ -d bin32 ] ; then cp bin32/iasl $DESTDIR$TARGETDIR/bin || touch ../../source/compiler/.failed ; fi + if [ -d bin64 ] ; then cp bin64/iasl $DESTDIR$TARGETDIR/bin || touch ../../source/compiler/.failed ; fi + if [ ! -f ../../source/compiler/.failed ]; then touch ../../source/compiler/.success; fi ) > $IASL_DIR/source/compiler/crossgcc-build.log 2>&1 test -r $IASL_DIR/source/compiler/.failed && printf "${RED}failed${NC}\n" || \ printf "${green}ok${NC}\n" diff --git a/util/crossgcc/patches/acpica-unix-20120420_unknown_warnings.patch b/util/crossgcc/patches/acpica-unix-20120420_unknown_warnings.patch deleted file mode 100644 index c027f17..0000000 --- a/util/crossgcc/patches/acpica-unix-20120420_unknown_warnings.patch +++ /dev/null @@ -1,23 +0,0 @@ ---- acpica-unix-20120420/source/compiler/Makefile 2012-04-20 22:02:33.000000000 +0200 -+++ acpica-unix-20120420.patched/source/compiler/Makefile 2012-10-21 00:30:38.634470788 +0200 -@@ -257,19 +257,11 @@ - # gcc 4+ flags - # - CWARNINGFLAGS += \ -- -Waddress \ - -Waggregate-return \ - -Wchar-subscripts \ -- -Wempty-body \ -- -Wlogical-op \ - -Wmissing-declarations \ -- -Wmissing-field-initializers \ -- -Wmissing-parameter-type \ - -Wnested-externs \ -- -Wold-style-declaration \ -- -Wold-style-definition \ -- -Wredundant-decls \ -- -Wtype-limits -+ -Wold-style-definition - - # - # Bison/Flex configuration diff --git a/util/crossgcc/patches/acpica-unix-20121018_unknown_warnings.patch b/util/crossgcc/patches/acpica-unix-20121018_unknown_warnings.patch new file mode 100644 index 0000000..240775b --- /dev/null +++ b/util/crossgcc/patches/acpica-unix-20121018_unknown_warnings.patch @@ -0,0 +1,44 @@ +diff -ur acpica-unix-20121018/generate/unix/Makefile.config acpica-unix-20121018.patched/generate/unix/Makefile.config +--- acpica-unix-20121018/generate/unix/Makefile.config 2012-10-18 21:23:26.000000000 +0200 ++++ acpica-unix-20121018.patched/generate/unix/Makefile.config 2012-10-22 15:05:31.732485690 +0200 +@@ -104,6 +104,7 @@ + # automatically included in -Wall. + # + CFLAGS += \ ++ -O \ + $(BITSFLAG) \ + -D$(HOST) \ + -D_GNU_SOURCE \ +@@ -114,10 +115,8 @@ + + CWARNINGFLAGS = \ + -ansi \ +- -Wall \ + -Wbad-function-cast \ + -Wdeclaration-after-statement \ +- -Werror \ + -Wformat=2 \ + -Wmissing-declarations \ + -Wmissing-prototypes \ +@@ -131,19 +130,11 @@ + # gcc 4+ flags + # + CWARNINGFLAGS += \ +- -Waddress \ + -Waggregate-return \ + -Wchar-subscripts \ +- -Wempty-body \ +- -Wlogical-op \ + -Wmissing-declarations \ +- -Wmissing-field-initializers \ +- -Wmissing-parameter-type \ + -Wnested-externs \ +- -Wold-style-declaration \ +- -Wold-style-definition \ +- -Wredundant-decls \ +- -Wtype-limits ++ -Wold-style-definition + + # + # Extra warning flags (possible future use) +Only in acpica-unix-20121018/generate/unix: iasl

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Patch set updated for coreboot: d3644bf crossgcc: fix the building of acpica
by Idwer Vollering 23 Oct '12

23 Oct '12

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1595 -gerrit commit d3644bf420248faa861e65d6224cd34090fa3b91 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Sun Oct 21 01:02:20 2012 +0200 crossgcc: fix the building of acpica Compilation of acpica-2012042 is broken (and old, but I'll take care of that in a future patch), let's fix that ("Building IASL 20120420 ... failed"). Increase CROSSGCC_VERSION to 1.08 Change-Id: I8940e9af6570ef3498cdfab4e63adf9251bc1106 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- util/crossgcc/buildgcc | 4 ++-- .../patches/acpica-unix-20120420_unknown_warnings.patch | 10 +++++----- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 71f4e16..f71bf66 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -20,8 +20,8 @@ # Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA # -CROSSGCC_DATE="November 1st, 2011" -CROSSGCC_VERSION="1.07" +CROSSGCC_DATE="October 23rd, 2012" +CROSSGCC_VERSION="1.08" # default settings TARGETDIR=`pwd`/xgcc diff --git a/util/crossgcc/patches/acpica-unix-20120420_unknown_warnings.patch b/util/crossgcc/patches/acpica-unix-20120420_unknown_warnings.patch index d1c954f..c027f17 100644 --- a/util/crossgcc/patches/acpica-unix-20120420_unknown_warnings.patch +++ b/util/crossgcc/patches/acpica-unix-20120420_unknown_warnings.patch @@ -1,6 +1,6 @@ ---- acpica-unix-20120420/source/compiler/Makefile 2012-04-21 04:02:33.000000000 +0800 -+++ acpica-unix-20120420/source/compiler/Makefile 2012-08-08 18:06:11.000000000 +0800 -@@ -257,19 +257,12 @@ +--- acpica-unix-20120420/source/compiler/Makefile 2012-04-20 22:02:33.000000000 +0200 ++++ acpica-unix-20120420.patched/source/compiler/Makefile 2012-10-21 00:30:38.634470788 +0200 +@@ -257,19 +257,11 @@ # gcc 4+ flags # CWARNINGFLAGS += \ @@ -14,10 +14,10 @@ - -Wmissing-parameter-type \ -Wnested-externs \ - -Wold-style-declaration \ - -Wold-style-definition \ +- -Wold-style-definition \ - -Wredundant-decls \ - -Wtype-limits -+ -Wredundant-decls ++ -Wold-style-definition # # Bison/Flex configuration

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Patch set updated for coreboot: 7b9e221 crossgcc: fix the building of acpica
by Idwer Vollering 23 Oct '12

23 Oct '12

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1595 -gerrit commit 7b9e2217dfddb9f0777378eb706b7449add7f632 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Sun Oct 21 01:02:20 2012 +0200 crossgcc: fix the building of acpica Compilation of acpica-2012042 is broken (and old, but I'll take care of that in a future patch), let's fix that ("Building IASL 20120420 ... failed"). Increase CROSSGCC_VERSION to 1.08 Change-Id: I8940e9af6570ef3498cdfab4e63adf9251bc1106 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- .../patches/acpica-unix-20120420_unknown_warnings.patch | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/util/crossgcc/patches/acpica-unix-20120420_unknown_warnings.patch b/util/crossgcc/patches/acpica-unix-20120420_unknown_warnings.patch index d1c954f..c027f17 100644 --- a/util/crossgcc/patches/acpica-unix-20120420_unknown_warnings.patch +++ b/util/crossgcc/patches/acpica-unix-20120420_unknown_warnings.patch @@ -1,6 +1,6 @@ ---- acpica-unix-20120420/source/compiler/Makefile 2012-04-21 04:02:33.000000000 +0800 -+++ acpica-unix-20120420/source/compiler/Makefile 2012-08-08 18:06:11.000000000 +0800 -@@ -257,19 +257,12 @@ +--- acpica-unix-20120420/source/compiler/Makefile 2012-04-20 22:02:33.000000000 +0200 ++++ acpica-unix-20120420.patched/source/compiler/Makefile 2012-10-21 00:30:38.634470788 +0200 +@@ -257,19 +257,11 @@ # gcc 4+ flags # CWARNINGFLAGS += \ @@ -14,10 +14,10 @@ - -Wmissing-parameter-type \ -Wnested-externs \ - -Wold-style-declaration \ - -Wold-style-definition \ +- -Wold-style-definition \ - -Wredundant-decls \ - -Wtype-limits -+ -Wredundant-decls ++ -Wold-style-definition # # Bison/Flex configuration

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Patch set updated for coreboot: 563afcd buildgcc: redirect error output to /dev/null
by Zheng Bao 23 Oct '12

23 Oct '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1548 -gerrit commit 563afcd6d28d8cca80392bf4c893096a8be4d28a Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Tue Oct 23 19:41:25 2012 +0800 buildgcc: redirect error output to /dev/null Change-Id: I7cd63248eb8abb711cecce41e3f8a282b34aa126 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- util/crossgcc/buildgcc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 71f4e16..7b7da53 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -324,7 +324,7 @@ if [ `uname` = "Darwin" ]; then # binaries in 10.6 (even if the kernel is 32bit) # For some weird reason, 10.5 autodetects an ABI=64 though # so we're setting the ABI explicitly here. - if [ `sysctl -n hw.optional.x86_64` -eq 1 ]; then + if [ `sysctl -n hw.optional.x86_64 2>/dev/null` -eq 1 ] 2>/dev/null; then OPTIONS="ABI=64" else OPTIONS="ABI=32"

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Patch set updated for coreboot: 5cc2899 Trinity: Move the use of the pointer upward to its initialization
by Zheng Bao 23 Oct '12

23 Oct '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1606 -gerrit commit 5cc2899629e796054a41cd47a7a7ea716b080ef0 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Tue Oct 23 19:03:27 2012 +0800 Trinity: Move the use of the pointer upward to its initialization Change-Id: I2f10909a626fb64c7f95663ddd79a3b899f73bc4 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/mainboard/amd/parmer/BiosCallOuts.c | 4 ++-- src/mainboard/amd/thatcher/BiosCallOuts.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c index a5e274a..24268d7 100644 --- a/src/mainboard/amd/parmer/BiosCallOuts.c +++ b/src/mainboard/amd/parmer/BiosCallOuts.c @@ -297,11 +297,11 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) BIOS_HEAP_MANAGER *BiosHeapBasePtr; AGESA_BUFFER_PARAMS *AllocParams; + AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; - AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; - /* Find target node to deallocate in list of allocated nodes. Return AGESA_BOUNDS_CHK if the BufferHandle is not found */ diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.c b/src/mainboard/amd/thatcher/BiosCallOuts.c index 8660e05..d4da61a 100644 --- a/src/mainboard/amd/thatcher/BiosCallOuts.c +++ b/src/mainboard/amd/thatcher/BiosCallOuts.c @@ -297,11 +297,11 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) BIOS_HEAP_MANAGER *BiosHeapBasePtr; AGESA_BUFFER_PARAMS *AllocParams; + AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; - AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; - /* Find target node to deallocate in list of allocated nodes. Return AGESA_BOUNDS_CHK if the BufferHandle is not found */

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New patch to review for coreboot: 2124508 Trinity: Move the use of the pointer forward to its initialization
by Zheng Bao 23 Oct '12

23 Oct '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1606 -gerrit commit 2124508be5823028f7a80721b2ac69c11c2773cf Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Tue Oct 23 18:25:39 2012 +0800 Trinity: Move the use of the pointer forward to its initialization Change-Id: I2f10909a626fb64c7f95663ddd79a3b899f73bc4 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/mainboard/amd/parmer/BiosCallOuts.c | 4 ++-- src/mainboard/amd/thatcher/BiosCallOuts.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c index a5e274a..24268d7 100644 --- a/src/mainboard/amd/parmer/BiosCallOuts.c +++ b/src/mainboard/amd/parmer/BiosCallOuts.c @@ -297,11 +297,11 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) BIOS_HEAP_MANAGER *BiosHeapBasePtr; AGESA_BUFFER_PARAMS *AllocParams; + AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; - AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; - /* Find target node to deallocate in list of allocated nodes. Return AGESA_BOUNDS_CHK if the BufferHandle is not found */ diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.c b/src/mainboard/amd/thatcher/BiosCallOuts.c index 8660e05..d4da61a 100644 --- a/src/mainboard/amd/thatcher/BiosCallOuts.c +++ b/src/mainboard/amd/thatcher/BiosCallOuts.c @@ -297,11 +297,11 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) BIOS_HEAP_MANAGER *BiosHeapBasePtr; AGESA_BUFFER_PARAMS *AllocParams; + AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; - AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; - /* Find target node to deallocate in list of allocated nodes. Return AGESA_BOUNDS_CHK if the BufferHandle is not found */

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Patch set updated for coreboot: 1bac59d pcie init: move to romstage
by Siyuan Wang 23 Oct '12

23 Oct '12

Siyuan Wang (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1593 -gerrit commit 1bac59ddc96ed91845725c4d181b4a9e838c35f8 Author: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Date: Tue Oct 23 14:13:38 2012 +0800 pcie init: move to romstage We move 2 cimx wrappers to romstage: Pcie_Early_Init, Pcie_Late_Init The reasons we do these changes are: 1) The pcie bridge with devices shoud be on and without devices should be off before device enumerate. 2) Now, the code do pcie training in device enable. So the pcie bridge is scanned whether there is a device or not. This could lead to some errors. For example: coreboot scans device tree twice and gets two different VGA devices, so the VGA bios could not be loaded correctly. Change-Id: I4bb6b54823cd08eae94b224130b46cc20b3ec43f Signed-off-by: Siyuan Wang <SiYuan.Wang(a)amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> --- src/northbridge/amd/cimx/rd890/Makefile.inc | 2 + src/northbridge/amd/cimx/rd890/early.c | 10 ++ src/northbridge/amd/cimx/rd890/late.c | 159 +++++----------------------- src/northbridge/amd/cimx/rd890/nb_cimx.c | 105 ++++++++++++++++++ src/northbridge/amd/cimx/rd890/nb_cimx.h | 13 ++- 5 files changed, 149 insertions(+), 140 deletions(-) diff --git a/src/northbridge/amd/cimx/rd890/Makefile.inc b/src/northbridge/amd/cimx/rd890/Makefile.inc index 5eaefd1..546221d 100644 --- a/src/northbridge/amd/cimx/rd890/Makefile.inc +++ b/src/northbridge/amd/cimx/rd890/Makefile.inc @@ -20,6 +20,8 @@ # RD890 Platform Files romstage-y += early.c +romstage-y += nb_cimx.c ramstage-y += late.c +ramstage-y += nb_cimx.c diff --git a/src/northbridge/amd/cimx/rd890/early.c b/src/northbridge/amd/cimx/rd890/early.c index 8008223..1b325d3 100644 --- a/src/northbridge/amd/cimx/rd890/early.c +++ b/src/northbridge/amd/cimx/rd890/early.c @@ -111,3 +111,13 @@ void nb_S3_Init(void) { //TODO } + +void nb_Pcie_Early_Init(AMD_NB_CONFIG_BLOCK *pConfig) +{ + LibSystemApiCall(AmdPcieEarlyInit, pConfig); +} + +void nb_Pcie_Late_Init(AMD_NB_CONFIG_BLOCK *pConfig) +{ + LibSystemApiCall(AmdPcieLateInit, pConfig); +} diff --git a/src/northbridge/amd/cimx/rd890/late.c b/src/northbridge/amd/cimx/rd890/late.c index 33da2b4..801f3cd 100644 --- a/src/northbridge/amd/cimx/rd890/late.c +++ b/src/northbridge/amd/cimx/rd890/late.c @@ -27,150 +27,41 @@ #include "nb_cimx.h" #include "rd890_cfg.h" - -/** - * Global RD890 CIMX Configuration structure - */ -static NB_CONFIG nb_cfg[MAX_NB_COUNT]; -static HT_CONFIG ht_cfg[MAX_NB_COUNT]; -static PCIE_CONFIG pcie_cfg[MAX_NB_COUNT]; -static AMD_NB_CONFIG_BLOCK gConfig; - - -/** - * Reset PCIE Cores, Training the Ports selected by port_enable of devicetree - * After this call EP are fully operational on particular NB - */ -void nb_Pcie_Early_Init(void) -{ - LibSystemApiCall(AmdPcieEarlyInit, &gConfig); //AmdPcieEarlyInit(&gConfig); -} - -void nb_Pcie_Late_Init(void) +void nb_Early_Post_Init(AMD_NB_CONFIG_BLOCK *pConfig) { - LibSystemApiCall(AmdPcieLateInit, &gConfig); + LibSystemApiCall(AmdEarlyPostInit, pConfig); } -void nb_Early_Post_Init(void) +void nb_Mid_Post_Init(AMD_NB_CONFIG_BLOCK *pConfig) { - LibSystemApiCall(AmdEarlyPostInit, &gConfig); + LibSystemApiCall(AmdMidPostInit, pConfig); } -void nb_Mid_Post_Init(void) +void nb_Late_Post_Init(AMD_NB_CONFIG_BLOCK *pConfig) { - LibSystemApiCall(AmdMidPostInit, &gConfig); -} - -void nb_Late_Post_Init(void) -{ - LibSystemApiCall(AmdLatePostInit, &gConfig); + LibSystemApiCall(AmdLatePostInit, pConfig); } static void rd890_enable(device_t dev) { - u32 address = 0; - u32 mask; - u32 val; - u32 devfn; - u32 port; - AMD_NB_CONFIG *NbConfigPtr = NULL; - - u8 nb_index = 0; /* The first IO Hub, TODO: other NBs */ - address = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); - NbConfigPtr = &(gConfig.Northbridges[nb_index]); - - devfn = dev->path.pci.devfn; - port = devfn >> 3; - printk(BIOS_INFO, "rd890_enable "); - printk(BIOS_INFO, "Bus-%x Dev-%X Fun-%X, enable=%x\n", - 0, (devfn >> 3), (devfn & 0x07), dev->enabled); - if (port != 0) { - if (dev->enabled) { - NbConfigPtr->pPcieConfig->PortConfiguration[port].ForcePortDisable = OFF; - } else { - NbConfigPtr->pPcieConfig->PortConfiguration[port].ForcePortDisable = ON; - } - } - - switch (port) { - case 0x0: /* Root Complex, and ClkConfig */ - - if ((devfn & 0x07) == 1) { /* skip dev-0 fun-1 */ - break; - } - - /* CIMX configuration defualt initialize */ - rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); - if (gConfig.StandardHeader.CalloutPtr != NULL) { - /* NOTE: not use LibNbCallBack */ - gConfig.StandardHeader.CalloutPtr(CB_AmdSetPcieEarlyConfig, (u32)dev, (VOID*)NbConfigPtr); - } - /* Reset PCIE Cores, Training the Ports selected by port_enable of devicetree - * After this call EP are fully operational on particular NB - */ - nb_Pcie_Early_Init(); - break; - - case 0x2: /* Gpp1 Port0 */ - case 0x3: /* Gpp1 Port1 */ - mask = ~(1 << port); - val = (dev->enabled ? 0 : 1) << port; - LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); - break; - - case 0x4: /* Gpp3a Port0 */ - case 0x5: /* Gpp3a Port1 */ - case 0x6: /* Gpp3a Port2 */ - case 0x7: /* Gpp3a Port3 */ - mask = ~(1 << port); - val = (dev->enabled ? 0 : 1) << port; - LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); - break; - - case 0x8: /* SB ALink */ - mask = ~(1 << 6); - val = (dev->enabled ? 1 : 0) << 6; - LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); - break; - - case 0x9: /* Gpp3a Port4 */ - case 0xa: /* Gpp3a Port5 */ - mask = ~(1 << (7 + port)); - val = (dev->enabled ? 0 : 1) << (7 + port); - LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); - break; - - case 0xb: /* Gpp2 Port0 */ - case 0xc: /* Gpp2 Port1 */ - mask = ~(1 << (7 + port)); - val = (dev->enabled ? 0 : 1) << (7 + port); - LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); - break; - - case 0xd: /* Gpp3b */ - mask = ~(1 << (7 + port)); - val = (dev->enabled ? 0 : 1) << (7 + port); - LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); - - /* Init NB at Early Post */ - if (gConfig.StandardHeader.CalloutPtr != NULL) { - gConfig.StandardHeader.CalloutPtr(CB_AmdSetEarlyPostConfig, 0, (VOID*)NbConfigPtr); - } - nb_Early_Post_Init();// - if (gConfig.StandardHeader.CalloutPtr != NULL) { - gConfig.StandardHeader.CalloutPtr(CB_AmdSetMidPostConfig, 0, (VOID*)NbConfigPtr); - } - nb_Mid_Post_Init(); - nb_Pcie_Late_Init(); - if (gConfig.StandardHeader.CalloutPtr != NULL) { - gConfig.StandardHeader.CalloutPtr(CB_AmdSetLatePostConfig, 0, (VOID*)NbConfigPtr); - } - nb_Late_Post_Init(); - break; - - default: - printk(BIOS_INFO, "Buggy Device Tree\n"); - break; + NB_CONFIG nb_cfg[MAX_NB_COUNT]; + HT_CONFIG ht_cfg[MAX_NB_COUNT]; + PCIE_CONFIG pcie_cfg[MAX_NB_COUNT]; + AMD_NB_CONFIG_BLOCK gConfig; + u32 devfn = dev->path.pci.devfn; + + /* only do Post init once */ + if(devfn == 0) + { + printk(BIOS_INFO, "cimx Post init start...\n"); + rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); + nb_pcie_config(&gConfig); + + //nb_Pcie_Late_Init(&gConfig); + nb_Early_Post_Init(&gConfig); + nb_Mid_Post_Init(&gConfig); + nb_Late_Post_Init(&gConfig); + printk(BIOS_INFO, "cimx Post init exit...\n"); } } @@ -179,7 +70,6 @@ struct chip_operations northbridge_amd_cimx_rd890_ops = { .enable_dev = rd890_enable, }; - static void ioapic_init(struct device *dev) { u32 ioapic_base; @@ -196,7 +86,6 @@ static void rd890_read_resource(struct device *dev) /* rpr6.2.(1). Write the Base Address Register (BAR) */ pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */ pci_get_resource(dev, 0xFC); /* APIC located in sr5690 */ - compact_resources(dev); } diff --git a/src/northbridge/amd/cimx/rd890/nb_cimx.c b/src/northbridge/amd/cimx/rd890/nb_cimx.c new file mode 100644 index 0000000..56bac9d --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/nb_cimx.c @@ -0,0 +1,105 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "NbPlatform.h" +#include "rd890_cfg.h" +#include "northbridge/amd/cimx/rd890/chip.h" +#include "nbInitializer.h" +#include <string.h> +#include <arch/ioapic.h> +#include <device/device.h> + +extern ROMSTAGE_CONST struct device dev_root; + +/** + * Platform dependent configuration at ramstage + */ +void nb_pcie_config(AMD_NB_CONFIG_BLOCK *pConfig) +{ + u16 i; + struct device *pdev; + AMD_NB_CONFIG *NbConfigPtr = &(pConfig->Northbridges[0]); + PCIE_CONFIG *pPcieConfig = NbConfigPtr->pPcieConfig; + struct northbridge_amd_cimx_rd890_config *rd890_info = NULL; + DEFAULT_PLATFORM_CONFIG(platform_config); + + /* find rd890 in device list */ + for (pdev = &dev_root; pdev; pdev=pdev->next) { + if ((pdev->path.type == DEVICE_PATH_PCI) && (pdev->path.pci.devfn == 0)) + break; + } + rd890_info = pdev->chip_info; + + /* update the platform depentent configuration by devicetree */ + platform_config.PortEnableMap = rd890_info->port_enable; + if (rd890_info->gpp1_configuration == 0) { + platform_config.Gpp1Config = GFX_CONFIG_AAAA; + } else if (rd890_info->gpp1_configuration == 1) { + platform_config.Gpp1Config = GFX_CONFIG_AABB; + } + if (rd890_info->gpp2_configuration == 0) { + platform_config.Gpp2Config = GFX_CONFIG_AAAA; + } else if (rd890_info->gpp2_configuration == 1) { + platform_config.Gpp2Config = GFX_CONFIG_AABB; + } + platform_config.Gpp3aConfig = rd890_info->gpp3a_configuration; + + if (platform_config.Gpp1Config != 0) { + pPcieConfig->CoreConfiguration[0] = platform_config.Gpp1Config; + } + if (platform_config.Gpp2Config != 0) { + pPcieConfig->CoreConfiguration[1] = platform_config.Gpp2Config; + } + if (platform_config.Gpp3aConfig != 0) { + pPcieConfig->CoreConfiguration[2] = platform_config.Gpp3aConfig; + } + + pPcieConfig->TempMmioBaseAddress = (UINT16)(platform_config.TemporaryMmio >> 20); + for (i = 0; i <= MAX_CORE_ID; i++) { + NbConfigPtr->pPcieConfig->CoreSetting[i].SkipConfiguration = OFF; + NbConfigPtr->pPcieConfig->CoreSetting[i].PerformanceMode = OFF; + } + for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) { + NbConfigPtr->pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen2; + } + + for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) { + if ((platform_config.PortEnableMap & (1 << i)) != 0) { + pPcieConfig->PortConfiguration[i].PortPresent = ON; + if ((platform_config.PortGen1Map & (1 << i)) != 0) { + pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen1; + } + if ((platform_config.PortHotplugMap & (1 << i)) != 0) { + u16 j; + pPcieConfig->PortConfiguration[j].PortHotplug = ON; /* Enable Hotplug */ + /* Set Hotplug descriptor info */ + for (j = 0; j < 8; j++) { + u32 PortDescriptor; + PortDescriptor = platform_config.PortHotplugDescriptors[j]; + if ((PortDescriptor & 0xF) == j) { + pPcieConfig->ExtPortConfiguration[j].PortHotplugDevMap = (PortDescriptor >> 4) & 3; + pPcieConfig->ExtPortConfiguration[j].PortHotplugByteMap = (PortDescriptor >> 6) & 1; + break; + } + } + } + } + } +} + diff --git a/src/northbridge/amd/cimx/rd890/nb_cimx.h b/src/northbridge/amd/cimx/rd890/nb_cimx.h index a6f77db..86e67b5 100644 --- a/src/northbridge/amd/cimx/rd890/nb_cimx.h +++ b/src/northbridge/amd/cimx/rd890/nb_cimx.h @@ -20,6 +20,8 @@ #ifndef _NB_CIMX_H_ #define _NB_CIMX_H_ +#include "NbPlatform.h" + /** * @brief disable GPP1 Port0,1, GPP2, GPP3a Port0,1,2,3,4,5, GPP3b * @@ -34,11 +36,12 @@ void sr56x0_rd890_disable_pcie_bridge(void); void nb_Poweron_Init(void); void nb_Ht_Init(void); void nb_S3_Init(void); -void nb_Early_Post_Init(void); -void nb_Mid_Post_Init(void); -void nb_Late_Post_Init(void); -void nb_Pcie_Early_Init(void); -void nb_Pcie_Late_Init(void); +void nb_Pcie_Early_Init(AMD_NB_CONFIG_BLOCK *pConfig); +void nb_Pcie_Late_Init(AMD_NB_CONFIG_BLOCK *pConfig); +void nb_Early_Post_Init(AMD_NB_CONFIG_BLOCK *pConfig); +void nb_Mid_Post_Init(AMD_NB_CONFIG_BLOCK *pConfig); +void nb_Late_Post_Init(AMD_NB_CONFIG_BLOCK *pConfig); +void nb_platform_config(AMD_NB_CONFIG_BLOCK *pConfig); #endif//_RD890_EARLY_H_

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Patch set updated for coreboot: cf21f9d tyan s8226: move pcie training to romstage
by Siyuan Wang 23 Oct '12

23 Oct '12

Siyuan Wang (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1594 -gerrit commit cf21f9dbe8b5607cf40056e9805b58025bcf48f2 Author: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Date: Tue Oct 23 14:14:46 2012 +0800 tyan s8226: move pcie training to romstage We move s8226's 2 cimx wrappers to romstage due to last commit. The changes are include Pcie_Early_Init and Pcie_Late_Init. In order to config rd890 in romstage, we modify rd890_cfg.c too. We find the rd890 in device list and get the config. Change-Id: I4ff70d0e6a0235b87806a64376f3ecee6487fdee Signed-off-by: Siyuan Wang <SiYuan.Wang(a)amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> --- src/mainboard/tyan/s8226/rd890_cfg.c | 78 ++---------------------------------- src/mainboard/tyan/s8226/rd890_cfg.h | 1 + src/mainboard/tyan/s8226/romstage.c | 10 +++++ 3 files changed, 14 insertions(+), 75 deletions(-) diff --git a/src/mainboard/tyan/s8226/rd890_cfg.c b/src/mainboard/tyan/s8226/rd890_cfg.c index 7a947b3..79238a5 100644 --- a/src/mainboard/tyan/s8226/rd890_cfg.c +++ b/src/mainboard/tyan/s8226/rd890_cfg.c @@ -23,83 +23,13 @@ #include "nbInitializer.h" #include <string.h> #include <arch/ioapic.h> - -#ifndef __PRE_RAM__ #include <device/device.h> + +extern ROMSTAGE_CONST struct device dev_root; extern void set_pcie_reset(void *config); extern void set_pcie_dereset(void *config); /** - * Platform dependent configuration at ramstage - */ -static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr) -{ - u16 i; - PCIE_CONFIG *pPcieConfig = NbConfigPtr->pPcieConfig; - //AMD_NB_CONFIG_BLOCK *ConfigPtr = GET_BLOCK_CONFIG_PTR(NbConfigPtr); - struct northbridge_amd_cimx_rd890_config *rd890_info = NULL; - DEFAULT_PLATFORM_CONFIG(platform_config); - - /* update the platform depentent configuration by devicetree */ - rd890_info = nb_dev->chip_info; - platform_config.PortEnableMap = rd890_info->port_enable; - if (rd890_info->gpp1_configuration == 0) { - platform_config.Gpp1Config = GFX_CONFIG_AAAA; - } else if (rd890_info->gpp1_configuration == 1) { - platform_config.Gpp1Config = GFX_CONFIG_AABB; - } - if (rd890_info->gpp2_configuration == 0) { - platform_config.Gpp2Config = GFX_CONFIG_AAAA; - } else if (rd890_info->gpp2_configuration == 1) { - platform_config.Gpp2Config = GFX_CONFIG_AABB; - } - platform_config.Gpp3aConfig = rd890_info->gpp3a_configuration; - - if (platform_config.Gpp1Config != 0) { - pPcieConfig->CoreConfiguration[0] = platform_config.Gpp1Config; - } - if (platform_config.Gpp2Config != 0) { - pPcieConfig->CoreConfiguration[1] = platform_config.Gpp2Config; - } - if (platform_config.Gpp3aConfig != 0) { - pPcieConfig->CoreConfiguration[2] = platform_config.Gpp3aConfig; - } - - pPcieConfig->TempMmioBaseAddress = (UINT16)(platform_config.TemporaryMmio >> 20); - for (i = 0; i <= MAX_CORE_ID; i++) { - NbConfigPtr->pPcieConfig->CoreSetting[i].SkipConfiguration = OFF; - NbConfigPtr->pPcieConfig->CoreSetting[i].PerformanceMode = OFF; - } - for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) { - NbConfigPtr->pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen2; - } - - for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) { - if ((platform_config.PortEnableMap & (1 << i)) != 0) { - pPcieConfig->PortConfiguration[i].PortPresent = ON; - if ((platform_config.PortGen1Map & (1 << i)) != 0) { - pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen1; - } - if ((platform_config.PortHotplugMap & (1 << i)) != 0) { - u16 j; - pPcieConfig->PortConfiguration[j].PortHotplug = ON; /* Enable Hotplug */ - /* Set Hotplug descriptor info */ - for (j = 0; j < 8; j++) { - u32 PortDescriptor; - PortDescriptor = platform_config.PortHotplugDescriptors[j]; - if ((PortDescriptor & 0xF) == j) { - pPcieConfig->ExtPortConfiguration[j].PortHotplugDevMap = (PortDescriptor >> 4) & 3; - pPcieConfig->ExtPortConfiguration[j].PortHotplugByteMap = (PortDescriptor >> 6) & 1; - break; - } - } - } - } - } -} -#endif // __PRE_RAM__ - -/** * @brief Entry point of Northbridge CIMx callout/CallBack * * prototype AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr); @@ -160,9 +90,6 @@ static u32 rd890_callout_entry(u32 func, u32 data, void *config) break; case CB_AmdSetPcieEarlyConfig: -#ifndef __PRE_RAM__ - nb_platform_config(nb_dev, nbConfigPtr); -#endif break; case CB_AmdSetEarlyPostConfig: @@ -244,6 +171,7 @@ void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CON pConfig->Northbridges[0].NbHtPath.NodeID = sbNode; pConfig->Northbridges[0].NbHtPath.LinkID = sbLink; //TODO: other NBs + pConfig->Northbridges[0].pNbConfig->IoApicBaseAddress = IO_APIC_ADDR; #ifndef __PRE_RAM__ /* If temporrary MMIO enable set up CPU MMIO */ diff --git a/src/mainboard/tyan/s8226/rd890_cfg.h b/src/mainboard/tyan/s8226/rd890_cfg.h index 8f45019..b11928f 100644 --- a/src/mainboard/tyan/s8226/rd890_cfg.h +++ b/src/mainboard/tyan/s8226/rd890_cfg.h @@ -170,5 +170,6 @@ typedef struct { * Bridge CIMx configuration */ void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig); +void nb_platform_config(AMD_NB_CONFIG_BLOCK *pConfigPtr); #endif //_RD890_CFG_H_ diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index 7076eed..f80d347 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -45,6 +45,10 @@ extern void disable_cache_as_ram(void); /* cache_as_ram.inc */ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + NB_CONFIG nb_cfg[MAX_NB_COUNT]; + HT_CONFIG ht_cfg[MAX_NB_COUNT]; + PCIE_CONFIG pcie_cfg[MAX_NB_COUNT]; + AMD_NB_CONFIG_BLOCK gConfig; post_code(0x30); agesawrapper_amdinitmmio(); @@ -139,6 +143,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x51); setup_i8259 (); setup_i8254 (); + + rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); + nb_pcie_config(&gConfig); + nb_Pcie_Early_Init(&gConfig); + nb_Pcie_Late_Init(&gConfig); + copy_and_run(0); /* We will not return, Should never see this message and post code. */

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coreboot October 2012