coreboot January 2012

coreboot@coreboot.org

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Patch set updated for coreboot: d579042 Remove duplicated line of code in AMD wrappers.
by Marc Jones 18 Jan '12

18 Jan '12

Marc Jones (marcj303(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/541 -gerrit commit d579042843cb3faf2e240730a1f7ef9ecba9ff89 Author: Marc Jones <marcj303(a)gmail.com> Date: Tue Jan 17 17:34:03 2012 -0700 Remove duplicated line of code in AMD wrappers. This line was unnecessary and was duplicated on several mainboards. Change-Id: I438da05c770ded0bd32256f1c157cabcc383667a Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/mainboard/amd/inagua/agesawrapper.c | 1 - src/mainboard/amd/persimmon/agesawrapper.c | 1 - src/mainboard/amd/south_station/agesawrapper.c | 1 - src/mainboard/amd/union_station/agesawrapper.c | 1 - src/mainboard/asrock/e350m1/agesawrapper.c | 1 - 5 files changed, 0 insertions(+), 5 deletions(-) diff --git a/src/mainboard/amd/inagua/agesawrapper.c b/src/mainboard/amd/inagua/agesawrapper.c index c33d20f..715202a 100644 --- a/src/mainboard/amd/inagua/agesawrapper.c +++ b/src/mainboard/amd/inagua/agesawrapper.c @@ -511,7 +511,6 @@ agesawrapper_amdlaterunaptask ( ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; ApExeParams.StdHeader.Func = 0; ApExeParams.StdHeader.ImageBasePtr = 0; - ApExeParams.StdHeader.ImageBasePtr = 0; ApExeParams.FunctionNumber = Func; ApExeParams.RelatedDataBlock = ConfigPtr; diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c index f9847c2..6e9997f 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.c +++ b/src/mainboard/amd/persimmon/agesawrapper.c @@ -515,7 +515,6 @@ agesawrapper_amdlaterunaptask ( ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; ApExeParams.StdHeader.Func = 0; ApExeParams.StdHeader.ImageBasePtr = 0; - ApExeParams.StdHeader.ImageBasePtr = 0; ApExeParams.FunctionNumber = Func; ApExeParams.RelatedDataBlock = ConfigPtr; diff --git a/src/mainboard/amd/south_station/agesawrapper.c b/src/mainboard/amd/south_station/agesawrapper.c index 0fbb3e4..7750e7d 100644 --- a/src/mainboard/amd/south_station/agesawrapper.c +++ b/src/mainboard/amd/south_station/agesawrapper.c @@ -510,7 +510,6 @@ agesawrapper_amdlaterunaptask ( ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; ApExeParams.StdHeader.Func = 0; ApExeParams.StdHeader.ImageBasePtr = 0; - ApExeParams.StdHeader.ImageBasePtr = 0; ApExeParams.FunctionNumber = Func; ApExeParams.RelatedDataBlock = ConfigPtr; diff --git a/src/mainboard/amd/union_station/agesawrapper.c b/src/mainboard/amd/union_station/agesawrapper.c index 0fbb3e4..7750e7d 100644 --- a/src/mainboard/amd/union_station/agesawrapper.c +++ b/src/mainboard/amd/union_station/agesawrapper.c @@ -510,7 +510,6 @@ agesawrapper_amdlaterunaptask ( ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; ApExeParams.StdHeader.Func = 0; ApExeParams.StdHeader.ImageBasePtr = 0; - ApExeParams.StdHeader.ImageBasePtr = 0; ApExeParams.FunctionNumber = Func; ApExeParams.RelatedDataBlock = ConfigPtr; diff --git a/src/mainboard/asrock/e350m1/agesawrapper.c b/src/mainboard/asrock/e350m1/agesawrapper.c index fc87029..742344a 100644 --- a/src/mainboard/asrock/e350m1/agesawrapper.c +++ b/src/mainboard/asrock/e350m1/agesawrapper.c @@ -510,7 +510,6 @@ agesawrapper_amdlaterunaptask ( ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; ApExeParams.StdHeader.Func = 0; ApExeParams.StdHeader.ImageBasePtr = 0; - ApExeParams.StdHeader.ImageBasePtr = 0; ApExeParams.FunctionNumber = Func; ApExeParams.RelatedDataBlock = ConfigPtr;

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Patch merged into coreboot/master: 44085b2 Clean up AMD romstage.c whitespace indent issues
by gerrit＠coreboot.org 18 Jan '12

18 Jan '12

the following patch was just integrated into master: commit 44085b2509c0422a43b2c5a88b93f81e2be3a9c7 Author: Marc Jones <marcj303(a)gmail.com> Date: Tue Jan 17 15:41:03 2012 -0700 Clean up AMD romstage.c whitespace indent issues Change-Id: I1713f1a3b548cb8e8ea5cf57eef95486ceb05ab9 Signed-off-by: Marc Jones <marcj303(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Jan 18 02:09:35 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Wed Jan 18 20:08:48 2012, giving +2 See http://review.coreboot.org/538 for details. -gerrit

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Re: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization
by Marc Jones 18 Jan '12

18 Jan '12

On Wed, Jan 18, 2012 at 8:11 AM, Wolfgang Kamp - datakamp <wmkamp(a)datakamp.de> wrote: > Hello Kerry, hello Marc, > > sounds good but solves not my problem. The enumeration of the SB800 GPP ports works fine with Linux. > But coreboot fails because the SB GPP ports are not yet initialized when coreboot probes them. > The function sbPcieGppEarlyInit will be executed after coreboot PCI probing of the SB GPP ports. > You can see that in late.c. > I put that function now in the right place in the case (0x15<<0 | 0) statement so probing succeeds. > And my Intel LAN GB82574 will be enumerated as I can see in the log. > But if I do that coreboot hangs in tables.c with postcode 0x9c and I can't imagine why. > I need the correct enumeration in coreboot because the Intel LAN chip tools only works under DOS. > > Wolfgang > Kerry, I agree with Wolfgang. I think that the sb800 has an issue. >> > The sb900 wrapper appears to fix this issue with cimx setup in early init. The device isn't visible in late init. The coreboot chip device scan will disable the device when it isn't found. The configuration needs to be set in early init like the sb900. Do you agree? Marc > -----Ursprüngliche Nachricht----- > Von: She, Kerry [mailto:Kerry.She@amd.com] > Gesendet: Mittwoch, 18. Januar 2012 08:49 > An: She, Kerry; Marc Jones; Wolfgang Kamp - datakamp > Cc: coreboot(a)coreboot.org; chia, kenneth > Betreff: Re: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization > > Hello Marc and Wolfgang > >> -----Original Message----- >> From: coreboot-bounces(a)coreboot.org >> [mailto:coreboot-bounces@coreboot.org] >> On Behalf Of She, Kerry >> Sent: Tuesday, January 17, 2012 4:07 PM >> To: Marc Jones; Wolfgang Kamp - datakamp >> Cc: coreboot(a)coreboot.org >> Subject: Re: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization >> >> Hello Walfqang, >> >> > -----Original Message----- >> > From: coreboot-bounces(a)coreboot.org [mailto:coreboot- >> bounces(a)coreboot.org] >> > On Behalf Of Marc Jones >> > Sent: Tuesday, January 17, 2012 3:23 AM >> > To: Wolfgang Kamp - datakamp >> > Cc: coreboot(a)coreboot.org >> > Subject: Re: [coreboot] Issue with CIMX/SB800 PCIe Port >> > Initialization >> > >> > On Mon, Jan 16, 2012 at 10:18 AM, Wolfgang Kamp - datakamp >> > <wmkamp(a)datakamp.de> wrote: >> > > Hello, >> > > >> > > >> > > >> > > I found a problem with the PCI enumeration of the PCIe Ports in >> > > the CIMX/SB800 Southbridge for the INAGUA platform. >> > > >> > > The .../southbridge/amd/cimx/sb800/late.c routine calls the >> > > function sb_Before_PCI_Init after >> > > >> > > case (0x16 >>3) | 2. This means when the PCI Express ports (0x15 >> > > <<3) >> | >> > 0 >> > > are probed in the routine ../devices/pci_device.c function >> > > >> > > pci_probe_dev they are not yet initialized. The probing fails and >> also >> > > devices behind the bridge are not recognized. >> > > >> > > Behind the PCIe bridge I have an Intel 82574 LAN chip. >> > > >> > > But if I move the call to sb_Before_PCI_Init behind case (0x15 >> > > <<3) >> | >> > 0 the >> > > enumeration succeed but coreboot crashes later into nothing. The >> > > Sage Debugger fails. >> > > >> > > I can't imagine why. >> > > >> > > >> > > >> > > Marc have you any idea? >> > >> > This looks like a problem in the sb800 cimx wrapper logic. Cimx >> > doesn't treat the devices separately. it lumps all the configuration >> > and enables together, making the coreboot chipset device enable >> > callback fail to enable the device, so it gets disabled. The sb900 >> > wrapper appears to fix this issue with cimx setup in early init. You >> > may want to try porting those changes to the sb800. >> > >> > I don't know why it fails later, but I assume it is due to the >> > missing config since you moved the call earlier in the process. You >> > could try calling it multiple times. I'm not sure how it handles that, though. >> > >> > Kerry, >> > Do you have any comments? >> If the enumeration fail, I suggest you should check the PCIE deassert >> GPIO setting. >> Thanks > > I found the recent amd/inagua code in the git tree is not boot on my platform and more. > I made an update to make my platform works now. > The missing mainboard specific GPIO setting also added back, So the sb800 GPP enumeration works now. > > Please reference following link and the attachment. > http://review.coreboot.org/#change,542 > http://review.coreboot.org/#change,543 > http://review.coreboot.org/#change,544 > http://review.coreboot.org/#change,545 > http://review.coreboot.org/#change,546 > > Thanks > Kerry > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot -- http://se-eng.com

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ASRock 775i65G (Intel 865g): log files
by Paul Menzel 18 Jan '12

18 Jan '12

Dear coreboot folks, I got the ASRock 775i65G [1] which has an Intel 865 chipset which is not yet supported by coreboot. Idwer is trying to port coreboot to the 856 chipset though and as a possible target and for the archive, here are the log files. For the record, this board seems to have problems so that the MOSFET () on the one corner looks burned [2]. In contrast to the person from the forum post [2] my board still boots. The MOSFET on my board has the part number APM038N WI7DS and the board in the forum APM2030N WI8BW. Peter wrote it would be possible to replace it. Proper MOSFET can be bought at Ebay [3][4]. Thanks, Paul [1] http://www.asrock.com/MB/overview.asp?Model=775i65G [2] http://forums.ncix.com/forums/topic.php?id=2371121 [3] http://www.ebay.de/itm/270747024710 [4] http://www.ebay.de/itm/250708848592

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Re: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization
by She, Kerry 18 Jan '12

18 Jan '12

Hello Walfqang, > -----Original Message----- > From: coreboot-bounces(a)coreboot.org [mailto:coreboot-bounces@coreboot.org] > On Behalf Of Marc Jones > Sent: Tuesday, January 17, 2012 3:23 AM > To: Wolfgang Kamp - datakamp > Cc: coreboot(a)coreboot.org > Subject: Re: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization > > On Mon, Jan 16, 2012 at 10:18 AM, Wolfgang Kamp - datakamp > <wmkamp(a)datakamp.de> wrote: > > Hello, > > > > > > > > I found a problem with the PCI enumeration of the PCIe Ports in the > > CIMX/SB800 Southbridge for the INAGUA platform. > > > > The .../southbridge/amd/cimx/sb800/late.c routine calls the function > > sb_Before_PCI_Init after > > > > case (0x16 >>3) | 2. This means when the PCI Express ports (0x15 <<3) | > 0 > > are probed in the routine ../devices/pci_device.c function > > > > pci_probe_dev they are not yet initialized. The probing fails and also > > devices behind the bridge are not recognized. > > > > Behind the PCIe bridge I have an Intel 82574 LAN chip. > > > > But if I move the call to sb_Before_PCI_Init behind case (0x15 <<3) | > 0 the > > enumeration succeed but coreboot crashes later into nothing. The Sage > > Debugger fails. > > > > I can't imagine why. > > > > > > > > Marc have you any idea? > > This looks like a problem in the sb800 cimx wrapper logic. Cimx > doesn't treat the devices separately. it lumps all the configuration > and enables together, making the coreboot chipset device enable > callback fail to enable the device, so it gets disabled. The sb900 > wrapper appears to fix this issue with cimx setup in early init. You > may want to try porting those changes to the sb800. > > I don't know why it fails later, but I assume it is due to the missing > config since you moved the call earlier in the process. You could try > calling it multiple times. I'm not sure how it handles that, though. > > Kerry, > Do you have any comments? If the enumeration fail, I suggest you should check the PCIE deassert GPIO setting. Thanks Kerry > > > Marc > > -- > http://se-eng.com > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] Finding motherboard specs
by Peter Stuge 18 Jan '12

18 Jan '12

Kim C. Callis wrote: > Is there a way to check under knoppix the specs on the motherboard > to see if this machine is a viable candidate for coreboot > replacement? Start with lspci //Peter

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Patch merged into coreboot/master: 5d901c1 libpayload: style: compare null-pointers with NULL, not 0
by gerrit＠coreboot.org 18 Jan '12

18 Jan '12

the following patch was just integrated into master: commit 5d901c1f09cbf1c7b633c96bdcd6d654581bcfbf Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Fri Nov 18 11:56:38 2011 +0100 libpayload: style: compare null-pointers with NULL, not 0 Change-Id: I5efbfb75e2894bc8d8e50c8737cfee9738d15eda Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Build-Tested: build bot (Jenkins) at Wed Jan 18 13:55:15 2012, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Wed Jan 18 14:00:04 2012, giving +2 See http://review.coreboot.org/551 for details. -gerrit

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New patch to review for coreboot: 5d901c1 libpayload: style: compare null-pointers with NULL, not 0
by Patrick Georgi 18 Jan '12

18 Jan '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/551 -gerrit commit 5d901c1f09cbf1c7b633c96bdcd6d654581bcfbf Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Fri Nov 18 11:56:38 2011 +0100 libpayload: style: compare null-pointers with NULL, not 0 Change-Id: I5efbfb75e2894bc8d8e50c8737cfee9738d15eda Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- payloads/libpayload/drivers/usb/usb.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/drivers/usb/usb.c b/payloads/libpayload/drivers/usb/usb.c index 995b4c2..1f21e6a 100644 --- a/payloads/libpayload/drivers/usb/usb.c +++ b/payloads/libpayload/drivers/usb/usb.c @@ -76,7 +76,7 @@ usb_exit (void) if (usb_hcs == 0) return 0; hci_t *controller = usb_hcs; - while (controller != 0) { + while (controller != NULL) { controller->shutdown(controller); controller = controller->next; } @@ -92,7 +92,7 @@ usb_poll (void) if (usb_hcs == 0) return; hci_t *controller = usb_hcs; - while (controller != 0) { + while (controller != NULL) { int i; for (i = 0; i < 128; i++) { if (controller->devices[i] != 0) {

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New patch to review for coreboot: 7c8cf66 libpayload: Allow using CBFS functions on images in RAM
by Patrick Georgi 18 Jan '12

18 Jan '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/550 -gerrit commit 7c8cf667e1f1eb785d6bcf1a94b346c1a5cc00d5 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Jan 17 15:52:05 2012 +0100 libpayload: Allow using CBFS functions on images in RAM Two new functions allow switching the CBFS functions from using RAM or ROM, with ROM as default. Change-Id: I04d67ad622d25c5728ae9a63f5b8a3dc9bbacce6 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- payloads/libpayload/include/cbfs.h | 2 ++ payloads/libpayload/libcbfs/cbfs.c | 31 +++++++++++++++++++++++++++---- 2 files changed, 29 insertions(+), 4 deletions(-) diff --git a/payloads/libpayload/include/cbfs.h b/payloads/libpayload/include/cbfs.h index 681caeb..8b8b024 100644 --- a/payloads/libpayload/include/cbfs.h +++ b/payloads/libpayload/include/cbfs.h @@ -1,2 +1,4 @@ #include <arch/types.h> #include "cbfs_core.h" +void setup_cbfs_from_ram(void* start, uint32_t size); +void setup_cbfs_from_flash(void); diff --git a/payloads/libpayload/libcbfs/cbfs.c b/payloads/libpayload/libcbfs/cbfs.c index c7173e0..7da2d58 100644 --- a/payloads/libpayload/libcbfs/cbfs.c +++ b/payloads/libpayload/libcbfs/cbfs.c @@ -40,18 +40,18 @@ #define ERROR(x...) printf(x) #define LOG(x...) -uint32_t host_virt_to_phys(void *addr); -void *host_phys_to_virt(uint32_t addr); +static uint32_t host_virt_to_phys(void *addr); +static void *host_phys_to_virt(uint32_t addr); uint32_t romstart(void); uint32_t romend(void); #include <arch/virtual.h> -uint32_t host_virt_to_phys(void *addr) { +static uint32_t host_virt_to_phys(void *addr) { return virt_to_phys(addr); } -void *host_phys_to_virt(uint32_t addr) { +static void *host_phys_to_virt(uint32_t addr) { return phys_to_virt(addr); } #undef virt_to_phys @@ -76,3 +76,26 @@ uint32_t romend(void) #include "cbfs_core.c" +static uint32_t ram_cbfs_offset; + +static uint32_t ram_virt_to_phys(void *addr) { + return (uint32_t)addr - ram_cbfs_offset; +} + +static void *ram_phys_to_virt(uint32_t addr) { + return (void*)addr + ram_cbfs_offset; +} + +void setup_cbfs_from_ram(void* start, uint32_t size) +{ + /* assumes rollover */ + ram_cbfs_offset = (uint32_t)start + size; + virt_to_phys = ram_virt_to_phys; + phys_to_virt = ram_phys_to_virt; +} + +void setup_cbfs_from_flash() +{ + virt_to_phys = host_virt_to_phys; + phys_to_virt = host_phys_to_virt; +}

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Patch merged into coreboot/master: fd8418f Add coreboot version to id area
by gerrit＠coreboot.org 18 Jan '12

18 Jan '12

the following patch was just integrated into master: commit fd8418ff2850ac95024bd800f78e00d0efa99811 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Jan 17 13:13:59 2012 +0100 Add coreboot version to id area There was no good way to extract the build version from an image. This change will be mostly backward compatible: The only assumption that could break is that the board name string ends directly before the 3 dwords that represent .id's "header". Change-Id: I325491a0c42911d9d6ecd59e21ee1b756c987693 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Build-Tested: build bot (Jenkins) at Wed Jan 18 10:44:34 2012, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Wed Jan 18 10:30:16 2012, giving +2 See http://review.coreboot.org/537 for details. -gerrit

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coreboot January 2012