coreboot January 2012

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Patch set updated for coreboot: f8df726 Inagua: Inagua GNB ddi lanes and pcie lanes config update
by Kerry Sheh 19 Jan '12

19 Jan '12

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/544 -gerrit commit f8df7260201d3f579e552ba3239a94d70f631d0b Author: Kerry Sheh <shekairui(a)gmail.com> Date: Thu Jan 19 13:18:37 2012 +0800 Inagua: Inagua GNB ddi lanes and pcie lanes config update DDI lanes configuration update to make LVDS works. Pcie lanes configuration update to make MiniPcie slot 1 works. Change-Id: I40aaf28119b946b3a6383ceff7c734c9c3fd313e Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> --- src/mainboard/amd/inagua/PlatformGnbPcie.c | 24 ++++++++---------------- 1 files changed, 8 insertions(+), 16 deletions(-) diff --git a/src/mainboard/amd/inagua/PlatformGnbPcie.c b/src/mainboard/amd/inagua/PlatformGnbPcie.c index ea080a5..f758006 100644 --- a/src/mainboard/amd/inagua/PlatformGnbPcie.c +++ b/src/mainboard/amd/inagua/PlatformGnbPcie.c @@ -55,25 +55,19 @@ OemCustomizeInitEarly ( ALLOCATE_HEAP_PARAMS AllocHeapParams; PCIe_PORT_DESCRIPTOR PortList [] = { - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) + // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) MXM { 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 5), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) }, - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) - { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5) - }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) + // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) PCIE LAN { 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) + // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) MINIPCIE SLOT1 { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), @@ -88,19 +82,17 @@ PCIe_PORT_DESCRIPTOR PortList [] = { }; PCIe_DDI_DESCRIPTOR DdiList [] = { - // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) + // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 to LVDS { 0, //Descriptor flags PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) - {ConnectorTypeDP, Aux1, Hdp1} + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeLvds, Aux1, Hdp1) }, - // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) + // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 to VGA { DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) - {ConnectorTypeDP, Aux2, Hdp2} + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeAutoDetect, Aux2, Hdp2) } };

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Patch set updated for coreboot: 9f6afb5 Inagua: Indent and wihtespace cleanup
by Kerry Sheh 19 Jan '12

19 Jan '12

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/547 -gerrit commit 9f6afb597ae330d2246182bb0878fb76bc1212bd Author: Kerry Sheh <shekairui(a)gmail.com> Date: Thu Jan 19 13:25:55 2012 +0800 Inagua: Indent and wihtespace cleanup Change-Id: Ie574e08f138c88084c8ce06d0d0acc489013e3d7 Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> --- src/mainboard/amd/inagua/BiosCallOuts.c | 980 ++++++++++---------- src/mainboard/amd/inagua/BiosCallOuts.h | 12 +- src/mainboard/amd/inagua/Kconfig | 135 ++-- src/mainboard/amd/inagua/PlatformGnbPcie.c | 204 +++--- src/mainboard/amd/inagua/PlatformGnbPcieComplex.h | 15 +- src/mainboard/amd/inagua/acpi_tables.c | 2 +- src/mainboard/amd/inagua/agesawrapper.c | 148 ++-- src/mainboard/amd/inagua/agesawrapper.h | 18 +- src/mainboard/amd/inagua/buildOpts.c | 208 +++--- src/mainboard/amd/inagua/devicetree.cb | 120 ++-- src/mainboard/amd/inagua/dimmSpd.c | 146 ++-- src/mainboard/amd/inagua/get_bus_conf.c | 158 ++-- src/mainboard/amd/inagua/irq_tables.c | 6 +- src/mainboard/amd/inagua/mainboard.c | 30 +- src/mainboard/amd/inagua/mptable.c | 140 ++-- src/mainboard/amd/inagua/platform_cfg.h | 8 +- 16 files changed, 1163 insertions(+), 1167 deletions(-) diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c index 434e83f..3c38239 100644 --- a/src/mainboard/amd/inagua/BiosCallOuts.c +++ b/src/mainboard/amd/inagua/BiosCallOuts.c @@ -26,494 +26,494 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_ALLOCATE_BUFFER, - BiosAllocateBuffer - }, + {AGESA_ALLOCATE_BUFFER, + BiosAllocateBuffer + }, - {AGESA_DEALLOCATE_BUFFER, - BiosDeallocateBuffer - }, + {AGESA_DEALLOCATE_BUFFER, + BiosDeallocateBuffer + }, - {AGESA_DO_RESET, - BiosReset - }, + {AGESA_DO_RESET, + BiosReset + }, - {AGESA_LOCATE_BUFFER, - BiosLocateBuffer - }, + {AGESA_LOCATE_BUFFER, + BiosLocateBuffer + }, - {AGESA_READ_SPD, - BiosReadSpd - }, + {AGESA_READ_SPD, + BiosReadSpd + }, - {AGESA_READ_SPD_RECOVERY, - BiosDefaultRet - }, + {AGESA_READ_SPD_RECOVERY, + BiosDefaultRet + }, - {AGESA_RUNFUNC_ONAP, - BiosRunFuncOnAp - }, + {AGESA_RUNFUNC_ONAP, + BiosRunFuncOnAp + }, {AGESA_GNB_PCIE_SLOT_RESET, - BiosGnbPcieSlotReset + BiosGnbPcieSlotReset }, {AGESA_HOOKBEFORE_DRAM_INIT, - BiosHookBeforeDramInit + BiosHookBeforeDramInit }, {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, - BiosHookBeforeDramInitRecovery - }, + BiosHookBeforeDramInitRecovery + }, - {AGESA_HOOKBEFORE_DQS_TRAINING, - BiosHookBeforeDQSTraining - }, + {AGESA_HOOKBEFORE_DQS_TRAINING, + BiosHookBeforeDQSTraining + }, - {AGESA_HOOKBEFORE_EXIT_SELF_REF, - BiosHookBeforeExitSelfRefresh - }, + {AGESA_HOOKBEFORE_EXIT_SELF_REF, + BiosHookBeforeExitSelfRefresh + }, }; AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINTN i; - AGESA_STATUS CalloutStatus; + UINTN i; + AGESA_STATUS CalloutStatus; UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]); CalloutStatus = AGESA_UNSUPPORTED; for (i = 0; i < CallOutCount; i++) { if (BiosCallouts[i].CalloutName == Func) { - CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr); - return CalloutStatus; - } - } + CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr); + return CalloutStatus; + } + } return CalloutStatus; } AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT32 AvailableHeapSize; - UINT8 *BiosHeapBaseAddr; - UINT32 CurrNodeOffset; - UINT32 PrevNodeOffset; - UINT32 FreedNodeOffset; - UINT32 BestFitNodeOffset; - UINT32 BestFitPrevNodeOffset; - UINT32 NextFreeOffset; - BIOS_BUFFER_NODE *CurrNodePtr; - BIOS_BUFFER_NODE *FreedNodePtr; - BIOS_BUFFER_NODE *BestFitNodePtr; - BIOS_BUFFER_NODE *BestFitPrevNodePtr; - BIOS_BUFFER_NODE *NextFreePtr; - BIOS_HEAP_MANAGER *BiosHeapBasePtr; - AGESA_BUFFER_PARAMS *AllocParams; - - AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr); - AllocParams->BufferPointer = NULL; - - AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER); - BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; - - if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) { - /* First allocation */ - CurrNodeOffset = sizeof (BIOS_HEAP_MANAGER); - CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); - CurrNodePtr->BufferHandle = AllocParams->BufferHandle; - CurrNodePtr->BufferSize = AllocParams->BufferLength; - CurrNodePtr->NextNodeOffset = 0; - AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof (BIOS_BUFFER_NODE); - - /* Update the remaining free space */ - FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof (BIOS_BUFFER_NODE); - FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); - FreedNodePtr->BufferSize = AvailableHeapSize - sizeof (BIOS_BUFFER_NODE) - CurrNodePtr->BufferSize; - FreedNodePtr->NextNodeOffset = 0; - - /* Update the offsets for Allocated and Freed nodes */ - BiosHeapBasePtr->StartOfAllocatedNodes = CurrNodeOffset; - BiosHeapBasePtr->StartOfFreedNodes = FreedNodeOffset; - } else { - /* Find out whether BufferHandle has been allocated on the heap. */ - /* If it has, return AGESA_BOUNDS_CHK */ - CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; - CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); - - while (CurrNodeOffset != 0) { - CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); - if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) { - return AGESA_BOUNDS_CHK; - } - CurrNodeOffset = CurrNodePtr->NextNodeOffset; - /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points - to the end of the allocated nodes list. - */ - } - /* Find the node that best fits the requested buffer size */ - FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; - PrevNodeOffset = FreedNodeOffset; - BestFitNodeOffset = 0; - BestFitPrevNodeOffset = 0; - while (FreedNodeOffset != 0) { - FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); - if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { - if (BestFitNodeOffset == 0) { - /* First node that fits the requested buffer size */ - BestFitNodeOffset = FreedNodeOffset; - BestFitPrevNodeOffset = PrevNodeOffset; - } else { - /* Find out whether current node is a better fit than the previous nodes */ - BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); - if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) { - BestFitNodeOffset = FreedNodeOffset; - BestFitPrevNodeOffset = PrevNodeOffset; - } - } - } - PrevNodeOffset = FreedNodeOffset; - FreedNodeOffset = FreedNodePtr->NextNodeOffset; - } /* end of while loop */ - - - if (BestFitNodeOffset == 0) { - /* If we could not find a node that fits the requested buffer */ - /* size, return AGESA_BOUNDS_CHK */ - return AGESA_BOUNDS_CHK; - } else { - BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); - BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset); - - /* If BestFitNode is larger than the requested buffer, fragment the node further */ - if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { - NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE); - - NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset); - NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE)); - NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset; - } else { - /* Otherwise, next free node is NextNodeOffset of BestFitNode */ - NextFreeOffset = BestFitNodePtr->NextNodeOffset; - } - - /* If BestFitNode is the first buffer in the list, then update - StartOfFreedNodes to reflect the new free node - */ - if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) { - BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset; - } else { - BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset; - } - - /* Add BestFitNode to the list of Allocated nodes */ - CurrNodePtr->NextNodeOffset = BestFitNodeOffset; - BestFitNodePtr->BufferSize = AllocParams->BufferLength; - BestFitNodePtr->BufferHandle = AllocParams->BufferHandle; - BestFitNodePtr->NextNodeOffset = 0; - - /* Remove BestFitNode from list of Freed nodes */ - AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof (BIOS_BUFFER_NODE); - } - } - - return AGESA_SUCCESS; + UINT32 AvailableHeapSize; + UINT8 *BiosHeapBaseAddr; + UINT32 CurrNodeOffset; + UINT32 PrevNodeOffset; + UINT32 FreedNodeOffset; + UINT32 BestFitNodeOffset; + UINT32 BestFitPrevNodeOffset; + UINT32 NextFreeOffset; + BIOS_BUFFER_NODE *CurrNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *BestFitNodePtr; + BIOS_BUFFER_NODE *BestFitPrevNodePtr; + BIOS_BUFFER_NODE *NextFreePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr); + AllocParams->BufferPointer = NULL; + + AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER); + BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + + if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) { + /* First allocation */ + CurrNodeOffset = sizeof (BIOS_HEAP_MANAGER); + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + CurrNodePtr->BufferHandle = AllocParams->BufferHandle; + CurrNodePtr->BufferSize = AllocParams->BufferLength; + CurrNodePtr->NextNodeOffset = 0; + AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof (BIOS_BUFFER_NODE); + + /* Update the remaining free space */ + FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof (BIOS_BUFFER_NODE); + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + FreedNodePtr->BufferSize = AvailableHeapSize - sizeof (BIOS_BUFFER_NODE) - CurrNodePtr->BufferSize; + FreedNodePtr->NextNodeOffset = 0; + + /* Update the offsets for Allocated and Freed nodes */ + BiosHeapBasePtr->StartOfAllocatedNodes = CurrNodeOffset; + BiosHeapBasePtr->StartOfFreedNodes = FreedNodeOffset; + } else { + /* Find out whether BufferHandle has been allocated on the heap. */ + /* If it has, return AGESA_BOUNDS_CHK */ + CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + + while (CurrNodeOffset != 0) { + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) { + return AGESA_BOUNDS_CHK; + } + CurrNodeOffset = CurrNodePtr->NextNodeOffset; + /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points + to the end of the allocated nodes list. + */ + } + /* Find the node that best fits the requested buffer size */ + FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; + PrevNodeOffset = FreedNodeOffset; + BestFitNodeOffset = 0; + BestFitPrevNodeOffset = 0; + while (FreedNodeOffset != 0) { + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { + if (BestFitNodeOffset == 0) { + /* First node that fits the requested buffer size */ + BestFitNodeOffset = FreedNodeOffset; + BestFitPrevNodeOffset = PrevNodeOffset; + } else { + /* Find out whether current node is a better fit than the previous nodes */ + BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); + if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) { + BestFitNodeOffset = FreedNodeOffset; + BestFitPrevNodeOffset = PrevNodeOffset; + } + } + } + PrevNodeOffset = FreedNodeOffset; + FreedNodeOffset = FreedNodePtr->NextNodeOffset; + } /* end of while loop */ + + + if (BestFitNodeOffset == 0) { + /* If we could not find a node that fits the requested buffer */ + /* size, return AGESA_BOUNDS_CHK */ + return AGESA_BOUNDS_CHK; + } else { + BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); + BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset); + + /* If BestFitNode is larger than the requested buffer, fragment the node further */ + if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { + NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE); + + NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset); + NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE)); + NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset; + } else { + /* Otherwise, next free node is NextNodeOffset of BestFitNode */ + NextFreeOffset = BestFitNodePtr->NextNodeOffset; + } + + /* If BestFitNode is the first buffer in the list, then update + StartOfFreedNodes to reflect the new free node + */ + if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) { + BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset; + } else { + BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset; + } + + /* Add BestFitNode to the list of Allocated nodes */ + CurrNodePtr->NextNodeOffset = BestFitNodeOffset; + BestFitNodePtr->BufferSize = AllocParams->BufferLength; + BestFitNodePtr->BufferHandle = AllocParams->BufferHandle; + BestFitNodePtr->NextNodeOffset = 0; + + /* Remove BestFitNode from list of Freed nodes */ + AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof (BIOS_BUFFER_NODE); + } + } + + return AGESA_SUCCESS; } AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT8 *BiosHeapBaseAddr; - UINT32 AllocNodeOffset; - UINT32 PrevNodeOffset; - UINT32 NextNodeOffset; - UINT32 FreedNodeOffset; - UINT32 EndNodeOffset; - BIOS_BUFFER_NODE *AllocNodePtr; - BIOS_BUFFER_NODE *PrevNodePtr; - BIOS_BUFFER_NODE *FreedNodePtr; - BIOS_BUFFER_NODE *NextNodePtr; - BIOS_HEAP_MANAGER *BiosHeapBasePtr; - AGESA_BUFFER_PARAMS *AllocParams; - - BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; - - AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; - - /* Find target node to deallocate in list of allocated nodes. - Return AGESA_BOUNDS_CHK if the BufferHandle is not found - */ - AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; - AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); - PrevNodeOffset = AllocNodeOffset; - - while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) { - if (AllocNodePtr->NextNodeOffset == 0) { - return AGESA_BOUNDS_CHK; - } - PrevNodeOffset = AllocNodeOffset; - AllocNodeOffset = AllocNodePtr->NextNodeOffset; - AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); - } - - /* Remove target node from list of allocated nodes */ - PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); - PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; - - /* Zero out the buffer, and clear the BufferHandle */ - LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof (BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader)); - AllocNodePtr->BufferHandle = 0; - AllocNodePtr->BufferSize += sizeof (BIOS_BUFFER_NODE); - - /* Add deallocated node in order to the list of freed nodes */ - FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; - FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); - - EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize; - - if (AllocNodeOffset < FreedNodeOffset) { - /* Add to the start of the freed list */ - if (EndNodeOffset == FreedNodeOffset) { - /* If the freed node is adjacent to the first node in the list, concatenate both nodes */ - AllocNodePtr->BufferSize += FreedNodePtr->BufferSize; - AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; - - /* Clear the BufferSize and NextNodeOffset of the previous first node */ - FreedNodePtr->BufferSize = 0; - FreedNodePtr->NextNodeOffset = 0; - } else { - /* Otherwise, add freed node to the start of the list - Update NextNodeOffset and BufferSize to include the - size of BIOS_BUFFER_NODE - */ - AllocNodePtr->NextNodeOffset = FreedNodeOffset; - } - /* Update StartOfFreedNodes to the new first node */ - BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset; - } else { - /* Traverse list of freed nodes to find where the deallocated node - should be place - */ - NextNodeOffset = FreedNodeOffset; - NextNodePtr = FreedNodePtr; - while (AllocNodeOffset > NextNodeOffset) { - PrevNodeOffset = NextNodeOffset; - if (NextNodePtr->NextNodeOffset == 0) { - break; - } - NextNodeOffset = NextNodePtr->NextNodeOffset; - NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); - } - - /* If deallocated node is adjacent to the next node, - concatenate both nodes - */ - if (NextNodeOffset == EndNodeOffset) { - NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); - AllocNodePtr->BufferSize += NextNodePtr->BufferSize; - AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset; - - NextNodePtr->BufferSize = 0; - NextNodePtr->NextNodeOffset = 0; - } else { - /*AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; */ - AllocNodePtr->NextNodeOffset = NextNodeOffset; - } - /* If deallocated node is adjacent to the previous node, - concatenate both nodes - */ - PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); - EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize; - if (AllocNodeOffset == EndNodeOffset) { - PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; - PrevNodePtr->BufferSize += AllocNodePtr->BufferSize; - AllocNodePtr->BufferSize = 0; - AllocNodePtr->NextNodeOffset = 0; - } else { - PrevNodePtr->NextNodeOffset = AllocNodeOffset; - } - } - return AGESA_SUCCESS; + UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT32 PrevNodeOffset; + UINT32 NextNodeOffset; + UINT32 FreedNodeOffset; + UINT32 EndNodeOffset; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_BUFFER_NODE *PrevNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *NextNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + + AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + + /* Find target node to deallocate in list of allocated nodes. + Return AGESA_BOUNDS_CHK if the BufferHandle is not found + */ + AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + PrevNodeOffset = AllocNodeOffset; + + while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) { + if (AllocNodePtr->NextNodeOffset == 0) { + return AGESA_BOUNDS_CHK; + } + PrevNodeOffset = AllocNodeOffset; + AllocNodeOffset = AllocNodePtr->NextNodeOffset; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + } + + /* Remove target node from list of allocated nodes */ + PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); + PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; + + /* Zero out the buffer, and clear the BufferHandle */ + LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof (BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader)); + AllocNodePtr->BufferHandle = 0; + AllocNodePtr->BufferSize += sizeof (BIOS_BUFFER_NODE); + + /* Add deallocated node in order to the list of freed nodes */ + FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + + EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize; + + if (AllocNodeOffset < FreedNodeOffset) { + /* Add to the start of the freed list */ + if (EndNodeOffset == FreedNodeOffset) { + /* If the freed node is adjacent to the first node in the list, concatenate both nodes */ + AllocNodePtr->BufferSize += FreedNodePtr->BufferSize; + AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; + + /* Clear the BufferSize and NextNodeOffset of the previous first node */ + FreedNodePtr->BufferSize = 0; + FreedNodePtr->NextNodeOffset = 0; + } else { + /* Otherwise, add freed node to the start of the list + Update NextNodeOffset and BufferSize to include the + size of BIOS_BUFFER_NODE + */ + AllocNodePtr->NextNodeOffset = FreedNodeOffset; + } + /* Update StartOfFreedNodes to the new first node */ + BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset; + } else { + /* Traverse list of freed nodes to find where the deallocated node + should be place + */ + NextNodeOffset = FreedNodeOffset; + NextNodePtr = FreedNodePtr; + while (AllocNodeOffset > NextNodeOffset) { + PrevNodeOffset = NextNodeOffset; + if (NextNodePtr->NextNodeOffset == 0) { + break; + } + NextNodeOffset = NextNodePtr->NextNodeOffset; + NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); + } + + /* If deallocated node is adjacent to the next node, + concatenate both nodes + */ + if (NextNodeOffset == EndNodeOffset) { + NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); + AllocNodePtr->BufferSize += NextNodePtr->BufferSize; + AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset; + + NextNodePtr->BufferSize = 0; + NextNodePtr->NextNodeOffset = 0; + } else { + /*AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; */ + AllocNodePtr->NextNodeOffset = NextNodeOffset; + } + /* If deallocated node is adjacent to the previous node, + concatenate both nodes + */ + PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); + EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize; + if (AllocNodeOffset == EndNodeOffset) { + PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; + PrevNodePtr->BufferSize += AllocNodePtr->BufferSize; + AllocNodePtr->BufferSize = 0; + AllocNodePtr->NextNodeOffset = 0; + } else { + PrevNodePtr->NextNodeOffset = AllocNodeOffset; + } + } + return AGESA_SUCCESS; } AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT32 AllocNodeOffset; - UINT8 *BiosHeapBaseAddr; - BIOS_BUFFER_NODE *AllocNodePtr; - BIOS_HEAP_MANAGER *BiosHeapBasePtr; - AGESA_BUFFER_PARAMS *AllocParams; - - AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; - - BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; - - AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; - AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + UINT32 AllocNodeOffset; + UINT8 *BiosHeapBaseAddr; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + + BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + + AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + + while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) { + if (AllocNodePtr->NextNodeOffset == 0) { + AllocParams->BufferPointer = NULL; + AllocParams->BufferLength = 0; + return AGESA_BOUNDS_CHK; + } else { + AllocNodeOffset = AllocNodePtr->NextNodeOffset; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + } + } + + AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof (BIOS_BUFFER_NODE)); + AllocParams->BufferLength = AllocNodePtr->BufferSize; - while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) { - if (AllocNodePtr->NextNodeOffset == 0) { - AllocParams->BufferPointer = NULL; - AllocParams->BufferLength = 0; - return AGESA_BOUNDS_CHK; - } else { - AllocNodeOffset = AllocNodePtr->NextNodeOffset; - AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); - } - } - - AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof (BIOS_BUFFER_NODE)); - AllocParams->BufferLength = AllocNodePtr->BufferSize; - - return AGESA_SUCCESS; + return AGESA_SUCCESS; } AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; + AGESA_STATUS Status; Status = agesawrapper_amdlaterunaptask (Func, Data, ConfigPtr); - return Status; + return Status; } AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; - UINT8 Value; - UINTN ResetType; - AMD_CONFIG_PARAMS *StdHeader; - - ResetType = Data; - StdHeader = ConfigPtr; - - // - // Perform the RESET based upon the ResetType. In case of - // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to - // AmdResetManager. During the critical condition, where reset is required - // immediately, the reset will be invoked directly by writing 0x04 to port - // 0xCF9 (Reset Port). - // - switch (ResetType) { - case WARM_RESET_WHENEVER: - case COLD_RESET_WHENEVER: - break; - - case WARM_RESET_IMMEDIATELY: - case COLD_RESET_IMMEDIATELY: - Value = 0x06; - LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader); - break; - - default: - break; - } - - Status = 0; - return Status; + AGESA_STATUS Status; + UINT8 Value; + UINTN ResetType; + AMD_CONFIG_PARAMS *StdHeader; + + ResetType = Data; + StdHeader = ConfigPtr; + + // + // Perform the RESET based upon the ResetType. In case of + // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to + // AmdResetManager. During the critical condition, where reset is required + // immediately, the reset will be invoked directly by writing 0x04 to port + // 0xCF9 (Reset Port). + // + switch (ResetType) { + case WARM_RESET_WHENEVER: + case COLD_RESET_WHENEVER: + break; + + case WARM_RESET_IMMEDIATELY: + case COLD_RESET_IMMEDIATELY: + Value = 0x06; + LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader); + break; + + default: + break; + } + + Status = 0; + return Status; } AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; + AGESA_STATUS Status; Status = AmdMemoryReadSPD (Func, Data, (AGESA_READ_SPD_PARAMS *)ConfigPtr); - return Status; + return Status; } AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - return AGESA_UNSUPPORTED; + return AGESA_UNSUPPORTED; } /* Call the host environment interface to provide a user hook opportunity. */ AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - return AGESA_SUCCESS; + return AGESA_SUCCESS; } /* Call the host environment interface to provide a user hook opportunity. */ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; - UINTN FcnData; - MEM_DATA_STRUCT *MemData; - UINT32 AcpiMmioAddr; - UINT32 GpioMmioAddr; - UINT8 Data8; - UINT16 Data16; - UINT8 TempData8; - - FcnData = Data; - MemData = ConfigPtr; - - Status = AGESA_SUCCESS; + AGESA_STATUS Status; + UINTN FcnData; + MEM_DATA_STRUCT *MemData; + UINT32 AcpiMmioAddr; + UINT32 GpioMmioAddr; + UINT8 Data8; + UINT16 Data16; + UINT8 TempData8; + + FcnData = Data; + MemData = ConfigPtr; + + Status = AGESA_SUCCESS; /* Get SB MMIO Base (AcpiMmioAddr) */ - WriteIo8 (0xCD6, 0x27); - Data8 = ReadIo8(0xCD7); - Data16 = Data8<<8; - WriteIo8 (0xCD6, 0x26); - Data8 = ReadIo8(0xCD7); - Data16 |= Data8; - AcpiMmioAddr = (UINT32)Data16 << 16; - GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; - - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178); - Data8 &= ~BIT5; - TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); - TempData8 &= 0x03; - TempData8 |= Data8; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8); - - Data8 |= BIT2+BIT3; - Data8 &= ~BIT4; - TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); - TempData8 &= 0x23; - TempData8 |= Data8; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8); - - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179); - Data8 &= ~BIT5; - TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); - TempData8 &= 0x03; - TempData8 |= Data8; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); - - Data8 |= BIT2+BIT3; - Data8 &= ~BIT4; - TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); - TempData8 &= 0x23; - TempData8 |= Data8; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); - - switch(MemData->ParameterListPtr->DDR3Voltage){ - case VOLT1_35: - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); - Data8 |= (UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); - break; - case VOLT1_25: - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); - break; - case VOLT1_5: - default: - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); - Data8 |= (UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); - } - return Status; + WriteIo8 (0xCD6, 0x27); + Data8 = ReadIo8(0xCD7); + Data16 = Data8<<8; + WriteIo8 (0xCD6, 0x26); + Data8 = ReadIo8(0xCD7); + Data16 |= Data8; + AcpiMmioAddr = (UINT32)Data16 << 16; + GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178); + Data8 &= ~BIT5; + TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); + TempData8 &= 0x03; + TempData8 |= Data8; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8); + + Data8 |= BIT2+BIT3; + Data8 &= ~BIT4; + TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); + TempData8 &= 0x23; + TempData8 |= Data8; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8); + + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179); + Data8 &= ~BIT5; + TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); + TempData8 &= 0x03; + TempData8 |= Data8; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); + + Data8 |= BIT2+BIT3; + Data8 &= ~BIT4; + TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); + TempData8 &= 0x23; + TempData8 |= Data8; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); + + switch(MemData->ParameterListPtr->DDR3Voltage){ + case VOLT1_35: + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); + Data8 &= ~(UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); + Data8 |= (UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); + break; + case VOLT1_25: + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); + Data8 &= ~(UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); + Data8 &= ~(UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); + break; + case VOLT1_5: + default: + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); + Data8 |= (UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); + Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); + Data8 &= ~(UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); + } + return Status; } /* Call the host environment interface to provide a user hook opportunity. */ @@ -525,82 +525,82 @@ AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *Con /* Call the host environment interface to provide a user hook opportunity. */ AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - return AGESA_SUCCESS; + return AGESA_SUCCESS; } /* PCIE slot reset control */ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; - UINTN FcnData; - PCIe_SLOT_RESET_INFO *ResetInfo; - - UINT32 GpioMmioAddr; - UINT32 AcpiMmioAddr; - UINT8 Data8; - UINT16 Data16; - - FcnData = Data; - ResetInfo = ConfigPtr; - // Get SB800 MMIO Base (AcpiMmioAddr) - WriteIo8(0xCD6, 0x27); - Data8 = ReadIo8(0xCD7); - Data16=Data8<<8; - WriteIo8(0xCD6, 0x26); - Data8 = ReadIo8(0xCD7); - Data16|=Data8; - AcpiMmioAddr = (UINT32)Data16 << 16; - Status = AGESA_UNSUPPORTED; - GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; - switch (ResetInfo->ResetId) - { - case 4: - switch (ResetInfo->ResetControl) { - case AssertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); - Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 - Status = AGESA_SUCCESS; - break; - case DeassertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); - Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 - Status = AGESA_SUCCESS; - break; - } - break; - case 6: - switch (ResetInfo->ResetControl) { - case AssertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 - Status = AGESA_SUCCESS; - break; - case DeassertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 - Status = AGESA_SUCCESS; - break; - } - break; - case 7: - switch (ResetInfo->ResetControl) { - case AssertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); - Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 - Status = AGESA_SUCCESS; - break; - case DeassertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 - Status = AGESA_SUCCESS; - break; - } - break; - } - return Status; + AGESA_STATUS Status; + UINTN FcnData; + PCIe_SLOT_RESET_INFO *ResetInfo; + + UINT32 GpioMmioAddr; + UINT32 AcpiMmioAddr; + UINT8 Data8; + UINT16 Data16; + + FcnData = Data; + ResetInfo = ConfigPtr; + // Get SB800 MMIO Base (AcpiMmioAddr) + WriteIo8(0xCD6, 0x27); + Data8 = ReadIo8(0xCD7); + Data16=Data8<<8; + WriteIo8(0xCD6, 0x26); + Data8 = ReadIo8(0xCD7); + Data16|=Data8; + AcpiMmioAddr = (UINT32)Data16 << 16; + Status = AGESA_UNSUPPORTED; + GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + switch (ResetInfo->ResetId) + { + case 4: + switch (ResetInfo->ResetControl) { + case AssertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); + Data8 &= ~(UINT8)BIT6 ; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 + Status = AGESA_SUCCESS; + break; + case DeassertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); + Data8 |= BIT6 ; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 + Status = AGESA_SUCCESS; + break; + } + break; + case 6: + switch (ResetInfo->ResetControl) { + case AssertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); + Data8 &= ~(UINT8)BIT6 ; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 + Status = AGESA_SUCCESS; + break; + case DeassertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); + Data8 |= BIT6 ; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 + Status = AGESA_SUCCESS; + break; + } + break; + case 7: + switch (ResetInfo->ResetControl) { + case AssertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); + Data8 &= ~(UINT8)BIT6 ; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 + Status = AGESA_SUCCESS; + break; + case DeassertSlotReset: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); + Data8 |= BIT6 ; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 + Status = AGESA_SUCCESS; + break; + } + break; + } + return Status; } diff --git a/src/mainboard/amd/inagua/BiosCallOuts.h b/src/mainboard/amd/inagua/BiosCallOuts.h index f7124b9..e713ac3 100644 --- a/src/mainboard/amd/inagua/BiosCallOuts.h +++ b/src/mainboard/amd/inagua/BiosCallOuts.h @@ -28,15 +28,15 @@ #define BIOS_HEAP_SIZE 0x20000 /* 64MB */ typedef struct _BIOS_HEAP_MANAGER { - //UINT32 AvailableSize; - UINT32 StartOfAllocatedNodes; - UINT32 StartOfFreedNodes; + //UINT32 AvailableSize; + UINT32 StartOfAllocatedNodes; + UINT32 StartOfFreedNodes; } BIOS_HEAP_MANAGER; typedef struct _BIOS_BUFFER_NODE { - UINT32 BufferHandle; - UINT32 BufferSize; - UINT32 NextNodeOffset; + UINT32 BufferHandle; + UINT32 BufferSize; + UINT32 NextNodeOffset; } BIOS_BUFFER_NODE; /* * CALLOUTS diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig index b0c5f1a..a5920af 100644 --- a/src/mainboard/amd/inagua/Kconfig +++ b/src/mainboard/amd/inagua/Kconfig @@ -20,108 +20,108 @@ if BOARD_AMD_INAGUA config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select ARCH_X86 - select CPU_AMD_AGESA_FAMILY14 - select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX - select NORTHBRIDGE_AMD_AGESA_FAMILY14 - select SOUTHBRIDGE_AMD_CIMX_SB800 - select SUPERIO_SMSC_KBC1100 - select BOARD_HAS_FADT - select HAVE_BUS_CONFIG - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select HAVE_MAINBOARD_RESOURCES - select HAVE_HARD_RESET - select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select LIFT_BSP_APIC_ID - select SERIAL_CPU_INIT - select AMDMCT - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_2048 - select ENABLE_APIC_EXT_ID - select GFXUMA + def_bool y + select ARCH_X86 + select CPU_AMD_AGESA_FAMILY14 + select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX + select NORTHBRIDGE_AMD_AGESA_FAMILY14 + select SOUTHBRIDGE_AMD_CIMX_SB800 + select SUPERIO_SMSC_KBC1100 + select BOARD_HAS_FADT + select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_MAINBOARD_RESOURCES + select HAVE_HARD_RESET + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select LIFT_BSP_APIC_ID + select SERIAL_CPU_INIT + select AMDMCT + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_2048 + select ENABLE_APIC_EXT_ID + select GFXUMA config AMD_AGESA - bool - default y + bool + default y config MAINBOARD_DIR - string - default amd/inagua + string + default amd/inagua config APIC_ID_OFFSET - hex - default 0x0 + hex + default 0x0 config MAINBOARD_PART_NUMBER - string - default "Inagua" + string + default "Inagua" config HW_MEM_HOLE_SIZEK - hex - default 0x200000 + hex + default 0x200000 config MAX_CPUS - int - default 2 + int + default 2 config MAX_PHYSICAL_CPUS - int - default 1 + int + default 1 config HW_MEM_HOLE_SIZE_AUTO_INC - bool - default n + bool + default n config MEM_TRAIN_SEQ - int - default 2 + int + default 2 config IRQ_SLOT_COUNT - int - default 11 + int + default 11 config RAMTOP - hex - default 0x1000000 + hex + default 0x1000000 config HEAP_SIZE - hex - default 0xc0000 + hex + default 0xc0000 config STACK_SIZE - hex - default 0x10000 + hex + default 0x10000 config ACPI_SSDTX_NUM - int - default 0 + int + default 0 config RAMBASE - hex - default 0x200000 + hex + default 0x200000 config SIO_PORT - hex - default 0x2e + hex + default 0x2e config DRIVERS_PS2_KEYBOARD - bool - default y + bool + default y config WARNINGS_ARE_ERRORS - bool - default n + bool + default n config ONBOARD_VGA_IS_PRIMARY - bool - default y + bool + default y config VGA_BIOS - bool - default n + bool + default n #config VGA_BIOS_FILE # string "VGA BIOS path and filename" @@ -129,14 +129,13 @@ config VGA_BIOS # default "rom/video/OntarioGenericVBios.bin" config VGA_BIOS_ID - string "VGA device PCI IDs" - depends on VGA_BIOS - default "1002,9802" + string "VGA device PCI IDs" + depends on VGA_BIOS + default "1002,9802" config SB800_AHCI_ROM - bool - default n - + bool + default n endif # BOARD_AMD_INAGUA diff --git a/src/mainboard/amd/inagua/PlatformGnbPcie.c b/src/mainboard/amd/inagua/PlatformGnbPcie.c index f758006..539ca48 100644 --- a/src/mainboard/amd/inagua/PlatformGnbPcie.c +++ b/src/mainboard/amd/inagua/PlatformGnbPcie.c @@ -44,8 +44,8 @@ /*---------------------------------------------------------------------------------------*/ VOID OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ) + IN OUT AMD_EARLY_PARAMS *InitEarly + ) { AGESA_STATUS Status; VOID *BrazosPcieComplexListPtr; @@ -54,105 +54,105 @@ OemCustomizeInitEarly ( ALLOCATE_HEAP_PARAMS AllocHeapParams; -PCIe_PORT_DESCRIPTOR PortList [] = { - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) MXM - { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 5), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) - }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) PCIE LAN - { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) - }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) MINIPCIE SLOT1 - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) - }, - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) - { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) - } -}; - -PCIe_DDI_DESCRIPTOR DdiList [] = { - // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 to LVDS - { - 0, //Descriptor flags - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeLvds, Aux1, Hdp1) - }, - // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 to VGA - { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeAutoDetect, Aux2, Hdp2) - } -}; - -PCIe_COMPLEX_DESCRIPTOR Brazos = { - DESCRIPTOR_TERMINATE_LIST, - 0, - &PortList[0], - &DdiList[0] -}; - - // GNB PCIe topology Porting - - // - // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - // - AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 5 + - sizeof (PCIe_DDI_DESCRIPTOR)) * 2; - - AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); - if ( Status!= AGESA_SUCCESS) { - // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - ASSERT(FALSE); - return; - } - - BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; - - AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); - BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; - - AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5; - BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; - - LibAmdMemFill (BrazosPcieComplexListPtr, - 0, - sizeof (PCIe_COMPLEX_DESCRIPTOR), - &InitEarly->StdHeader); - - LibAmdMemFill (BrazosPciePortPtr, - 0, - sizeof (PCIe_PORT_DESCRIPTOR) * 5, - &InitEarly->StdHeader); - - LibAmdMemFill (BrazosPcieDdiPtr, - 0, - sizeof (PCIe_DDI_DESCRIPTOR) * 2, - &InitEarly->StdHeader); - - LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) *2, &InitEarly->StdHeader); - - - ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; - ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr; - - InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; - InitEarly->GnbConfig.PsppPolicy = 0; + PCIe_PORT_DESCRIPTOR PortList [] = { + // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) MXM + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 5), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) + }, + // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) PCIE LAN + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) + }, + // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) MINIPCIE SLOT1 + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) + }, + // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) + { + DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) + } + }; + + PCIe_DDI_DESCRIPTOR DdiList [] = { + // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 to LVDS + { + 0, //Descriptor flags + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeLvds, Aux1, Hdp1) + }, + // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 to VGA + { + DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeAutoDetect, Aux2, Hdp2) + } + }; + + PCIe_COMPLEX_DESCRIPTOR Brazos = { + DESCRIPTOR_TERMINATE_LIST, + 0, + &PortList[0], + &DdiList[0] + }; + + // GNB PCIe topology Porting + + // + // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + // + AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + + sizeof (PCIe_PORT_DESCRIPTOR) * 5 + + sizeof (PCIe_DDI_DESCRIPTOR)) * 2; + + AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); + if ( Status!= AGESA_SUCCESS) { + // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + ASSERT(FALSE); + return; + } + + BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); + BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5; + BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + LibAmdMemFill (BrazosPcieComplexListPtr, + 0, + sizeof (PCIe_COMPLEX_DESCRIPTOR), + &InitEarly->StdHeader); + + LibAmdMemFill (BrazosPciePortPtr, + 0, + sizeof (PCIe_PORT_DESCRIPTOR) * 5, + &InitEarly->StdHeader); + + LibAmdMemFill (BrazosPcieDdiPtr, + 0, + sizeof (PCIe_DDI_DESCRIPTOR) * 2, + &InitEarly->StdHeader); + + LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) *2, &InitEarly->StdHeader); + + + ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; + ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr; + + InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; + InitEarly->GnbConfig.PsppPolicy = 0; } diff --git a/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h b/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h index b51089f..6477892 100644 --- a/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h @@ -29,7 +29,7 @@ #define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 #define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port5 @@ -37,7 +37,7 @@ #define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 #define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port6 @@ -45,7 +45,7 @@ #define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 #define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port7 @@ -53,7 +53,7 @@ #define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 #define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port8 @@ -61,12 +61,9 @@ #define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 #define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ); +VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); #endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c index 8ed7d4f..8f47591 100644 --- a/src/mainboard/amd/inagua/acpi_tables.c +++ b/src/mainboard/amd/inagua/acpi_tables.c @@ -86,7 +86,7 @@ unsigned long acpi_fill_madt(unsigned long current) /* Write SB800 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); + CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); diff --git a/src/mainboard/amd/inagua/agesawrapper.c b/src/mainboard/amd/inagua/agesawrapper.c index fe2fe6b..113f962 100644 --- a/src/mainboard/amd/inagua/agesawrapper.c +++ b/src/mainboard/amd/inagua/agesawrapper.c @@ -78,8 +78,8 @@ VOID *AcpiAlib = NULL; */ UINT32 agesawrapper_amdinitcpuio ( - VOID - ) + VOID + ) { AGESA_STATUS Status; UINT64 MsrReg; @@ -127,8 +127,8 @@ agesawrapper_amdinitcpuio ( UINT32 agesawrapper_amdinitmmio ( - VOID - ) + VOID + ) { AGESA_STATUS Status; UINT64 MsrReg; @@ -141,9 +141,9 @@ agesawrapper_amdinitmmio ( UINT8 Index; /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. - */ + Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base + Address MSR register. + */ for (Index = 0; Index < 8; Index++) { BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index; @@ -157,8 +157,8 @@ agesawrapper_amdinitmmio ( LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); /* - Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. - */ + Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. + */ LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); MsrReg = MsrReg | 0x0000400000000000ull; LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); @@ -177,22 +177,22 @@ agesawrapper_amdinitmmio ( UINT32 agesawrapper_amdinitreset ( - VOID - ) + VOID + ) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; AMD_RESET_PARAMS AmdResetParams; LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); LibAmdMemFill (&AmdResetParams, - 0, - sizeof (AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); + 0, + sizeof (AMD_RESET_PARAMS), + &(AmdResetParams.StdHeader)); AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; AmdParamStruct.AllocationMethod = ByHost; @@ -209,21 +209,21 @@ agesawrapper_amdinitreset ( if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); AmdReleaseStruct (&AmdParamStruct); return (UINT32)status; - } +} UINT32 agesawrapper_amdinitearly ( - VOID - ) + VOID + ) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; AMD_EARLY_PARAMS *AmdEarlyParamsPtr; LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -245,8 +245,8 @@ agesawrapper_amdinitearly ( UINT32 agesawrapper_amdinitpost ( - VOID - ) + VOID + ) { AGESA_STATUS status; UINT16 i; @@ -255,9 +255,9 @@ agesawrapper_amdinitpost ( BIOS_HEAP_MANAGER *BiosManagerPtr; LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -287,8 +287,8 @@ agesawrapper_amdinitpost ( UINT32 agesawrapper_amdinitenv ( - VOID - ) + VOID + ) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; @@ -296,9 +296,9 @@ agesawrapper_amdinitenv ( UINT32 PciValue; LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; AmdParamStruct.AllocationMethod = PostMemDram; @@ -311,7 +311,7 @@ agesawrapper_amdinitenv ( if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); /* Initialize Subordinate Bus Number and Secondary Bus Number * In platform BIOS this address is allocated by PCI enumeration code - Modify D1F0x18 + Modify D1F0x18 */ PciAddress.Address.Bus = 0; PciAddress.Address.Device = 1; @@ -323,8 +323,8 @@ agesawrapper_amdinitenv ( LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); /* Initialize GMM Base Address for Legacy Bridge Mode - * Modify B1D5F0x18 - */ + * Modify B1D5F0x18 + */ PciAddress.Address.Bus = 1; PciAddress.Address.Device = 5; PciAddress.Address.Function = 0; @@ -335,16 +335,16 @@ agesawrapper_amdinitenv ( LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); /* Initialize FB Base Address for Legacy Bridge Mode - * Modify B1D5F0x10 - */ + * Modify B1D5F0x10 + */ PciAddress.Address.Register = 0x10; LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); PciValue |= 0x80000000; LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); /* Initialize GMM Base Address for Pcie Mode - * Modify B0D1F0x18 - */ + * Modify B0D1F0x18 + */ PciAddress.Address.Bus = 0; PciAddress.Address.Device = 1; PciAddress.Address.Function = 0; @@ -355,16 +355,16 @@ agesawrapper_amdinitenv ( LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); /* Initialize FB Base Address for Pcie Mode - * Modify B0D1F0x10 - */ + * Modify B0D1F0x10 + */ PciAddress.Address.Register = 0x10; LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); PciValue |= 0x80000000; LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); /* Initialize MMIO Base and Limit Address - * Modify B0D1F0x20 - */ + * Modify B0D1F0x20 + */ PciAddress.Address.Bus = 0; PciAddress.Address.Device = 1; PciAddress.Address.Function = 0; @@ -375,8 +375,8 @@ agesawrapper_amdinitenv ( LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); /* Initialize MMIO Prefetchable Memory Limit and Base - * Modify B0D1F0x24 - */ + * Modify B0D1F0x24 + */ PciAddress.Address.Register = 0x24; LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); PciValue |= 0x8FF18001; @@ -388,8 +388,8 @@ agesawrapper_amdinitenv ( VOID * agesawrapper_getlateinitptr ( - int pick - ) + int pick + ) { switch (pick) { case PICK_DMI: @@ -413,8 +413,8 @@ agesawrapper_getlateinitptr ( UINT32 agesawrapper_amdinitmid ( - VOID - ) + VOID + ) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; @@ -423,9 +423,9 @@ agesawrapper_amdinitmid ( agesawrapper_amdinitcpuio (); LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; AmdParamStruct.AllocationMethod = PostMemDram; @@ -445,17 +445,17 @@ agesawrapper_amdinitmid ( UINT32 agesawrapper_amdinitlate ( - VOID - ) + VOID + ) { AGESA_STATUS Status; AMD_INTERFACE_PARAMS AmdParamStruct; AMD_LATE_PARAMS * AmdLateParamsPtr; LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; AmdParamStruct.AllocationMethod = PostMemDram; @@ -484,10 +484,10 @@ agesawrapper_amdinitlate ( AcpiAlib = AmdLateParamsPtr->AcpiAlib; printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n" - " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n" - " Mce:%p\n Cmc:%p\n Alib:%p\n", - __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit, - AcpiWheaMce, AcpiWheaCmc, AcpiAlib); + " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n" + " Mce:%p\n Cmc:%p\n Alib:%p\n", + __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit, + AcpiWheaMce, AcpiWheaCmc, AcpiAlib); /* Don't release the structure until coreboot has copied the ACPI tables. * AmdReleaseStruct (&AmdLateParams); @@ -498,18 +498,18 @@ agesawrapper_amdinitlate ( UINT32 agesawrapper_amdlaterunaptask ( - UINT32 Func, - UINT32 Data, - VOID *ConfigPtr - ) + UINT32 Func, + UINT32 Data, + VOID *ConfigPtr + ) { AGESA_STATUS Status; AP_EXE_PARAMS ApExeParams; LibAmdMemFill (&ApExeParams, - 0, - sizeof (AP_EXE_PARAMS), - &(ApExeParams.StdHeader)); + 0, + sizeof (AP_EXE_PARAMS), + &(ApExeParams.StdHeader)); ApExeParams.StdHeader.AltImageBasePtr = 0; ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; @@ -529,16 +529,16 @@ agesawrapper_amdlaterunaptask ( UINT32 agesawrapper_amdreadeventlog ( - VOID - ) + VOID + ) { AGESA_STATUS Status; EVENT_PARAMS AmdEventParams; LibAmdMemFill (&AmdEventParams, - 0, - sizeof (EVENT_PARAMS), - &(AmdEventParams.StdHeader)); + 0, + sizeof (EVENT_PARAMS), + &(AmdEventParams.StdHeader)); AmdEventParams.StdHeader.AltImageBasePtr = 0; AmdEventParams.StdHeader.CalloutPtr = NULL; diff --git a/src/mainboard/amd/inagua/agesawrapper.h b/src/mainboard/amd/inagua/agesawrapper.h index f8d924e..3e819b7 100644 --- a/src/mainboard/amd/inagua/agesawrapper.h +++ b/src/mainboard/amd/inagua/agesawrapper.h @@ -39,13 +39,13 @@ #define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ - PICK_WHEA_MCE, /* WHEA MCE table */ - PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ + PICK_DMI, /* DMI Interface */ + PICK_PSTATE, /* Acpi Pstate SSDT Table */ + PICK_SRAT, /* SRAT Table */ + PICK_SLIT, /* SLIT Table */ + PICK_WHEA_MCE, /* WHEA MCE table */ + PICK_WHEA_CMC, /* WHEA CMV table */ + PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ }; /*---------------------------------------------------------------------------------------- @@ -54,8 +54,8 @@ enum { */ typedef struct { - UINT32 CalloutName; - AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr); + UINT32 CalloutName; + AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr); } BIOS_CALLOUT_STRUCT; /*---------------------------------------------------------------------------------------- diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c index 6506c2e..49eb7bf 100644 --- a/src/mainboard/amd/inagua/buildOpts.c +++ b/src/mainboard/amd/inagua/buildOpts.c @@ -89,12 +89,12 @@ #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE #define BLDOPT_REMOVE_ACPI_PSTATES FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE - #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE +#define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE +#define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE +#define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE +#define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE +#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE +#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE #define BLDOPT_REMOVE_SRAT FALSE #define BLDOPT_REMOVE_SLIT FALSE #define BLDOPT_REMOVE_WHEA FALSE @@ -329,65 +329,65 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = * use its default conservative settings. */ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { - // - // The following macros are supported (use comma to separate macros): - // - // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) - // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. - // AGESA will base on this value to disable unused MemClk to save power. - // Example: - // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: - // Bit AM3/S1g3 pin name - // 0 M[B,A]_CLK_H/L[0] - // 1 M[B,A]_CLK_H/L[1] - // 2 M[B,A]_CLK_H/L[2] - // 3 M[B,A]_CLK_H/L[3] - // 4 M[B,A]_CLK_H/L[4] - // 5 M[B,A]_CLK_H/L[5] - // 6 M[B,A]_CLK_H/L[6] - // 7 M[B,A]_CLK_H/L[7] - // And platform has the following routing: - // CS0 M[B,A]_CLK_H/L[4] - // CS1 M[B,A]_CLK_H/L[2] - // CS2 M[B,A]_CLK_H/L[3] - // CS3 M[B,A]_CLK_H/L[5] - // Then platform can specify the following macro: - // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) - // - // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) - // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. - // AGESA will base on this value to tristate unused CKE to save power. - // - // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) - // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. - // AGESA will base on this value to tristate unused ODT pins to save power. - // - // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) - // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. - // AGESA will base on this value to tristate unused Chip select to save power. - // - // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) - // Specifies the number of DIMM slots per channel. - // - // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) - // Specifies the number of Chip selects per channel. - // - // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) - // Specifies the number of channels per socket. - // - // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) - // Specifies DDR bus speed of channel ChannelID on socket SocketID. - // - // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) - // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) - // - // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - // Byte6Seed, Byte7Seed, ByteEccSeed) - // Specifies the write leveling seed for a channel of a socket. - // - NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), - NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), - PSO_END + // + // The following macros are supported (use comma to separate macros): + // + // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) + // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. + // AGESA will base on this value to disable unused MemClk to save power. + // Example: + // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: + // Bit AM3/S1g3 pin name + // 0 M[B,A]_CLK_H/L[0] + // 1 M[B,A]_CLK_H/L[1] + // 2 M[B,A]_CLK_H/L[2] + // 3 M[B,A]_CLK_H/L[3] + // 4 M[B,A]_CLK_H/L[4] + // 5 M[B,A]_CLK_H/L[5] + // 6 M[B,A]_CLK_H/L[6] + // 7 M[B,A]_CLK_H/L[7] + // And platform has the following routing: + // CS0 M[B,A]_CLK_H/L[4] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[3] + // CS3 M[B,A]_CLK_H/L[5] + // Then platform can specify the following macro: + // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) + // + // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) + // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. + // AGESA will base on this value to tristate unused CKE to save power. + // + // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) + // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. + // AGESA will base on this value to tristate unused ODT pins to save power. + // + // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) + // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. + // AGESA will base on this value to tristate unused Chip select to save power. + // + // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) + // Specifies the number of DIMM slots per channel. + // + // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) + // Specifies the number of Chip selects per channel. + // + // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) + // Specifies the number of channels per socket. + // + // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) + // Specifies DDR bus speed of channel ChannelID on socket SocketID. + // + // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) + // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) + // + // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Specifies the write leveling seed for a channel of a socket. + // + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), + NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), + PSO_END }; /* @@ -399,45 +399,45 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { //DA Customer table CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] = { - // Hardcoded Memory Training Values - - // The following macro should be used to override training values for your platform - // - // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20), - // - // NOTE: - // The following training hardcode values are example values that were taken from a tilapia motherboard - // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in - // the table and replace the byte lane values with your own. - // - // ------------------ BYTE LANES ---------------------- - // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC - // Write Data Timing - // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 - // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 - // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0 - // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1 - - // DQS Receiver Enable - // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 - // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1 - // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0 - // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1 - - // Write DQS Delays - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1 - - // Read DQS Delays - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0 - // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 - //-------------------------------------------------------------------------------------------------------------------------------------------------- - // TABLE END - NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table + // Hardcoded Memory Training Values + + // The following macro should be used to override training values for your platform + // + // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20), + // + // NOTE: + // The following training hardcode values are example values that were taken from a tilapia motherboard + // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in + // the table and replace the byte lane values with your own. + // + // ------------------ BYTE LANES ---------------------- + // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC + // Write Data Timing + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1 + + // DQS Receiver Enable + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1 + + // Write DQS Delays + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1 + + // Read DQS Delays + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 + //-------------------------------------------------------------------------------------------------------------------------------------------------- + // TABLE END + NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table }; CONST UINT8 SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABLE_ON[0]); diff --git a/src/mainboard/amd/inagua/devicetree.cb b/src/mainboard/amd/inagua/devicetree.cb index 60bb29b..100a5cc 100644 --- a/src/mainboard/amd/inagua/devicetree.cb +++ b/src/mainboard/amd/inagua/devicetree.cb @@ -17,56 +17,56 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # chip northbridge/amd/agesa/family14/root_complex - device lapic_cluster 0 on - chip cpu/amd/agesa/family14 - device lapic 0 on end - end - end - device pci_domain 0 on - subsystemid 0x1022 0x1510 inherit - chip northbridge/amd/agesa/family14 # CPU side of HT root complex -# device pci 18.0 on # northbridge - chip northbridge/amd/agesa/family14 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge, 9802 to 9806 - device pci 1.1 on end # Internal Multimedia - device pci 4.0 on end # PCIE P2P bridge MXM lane 0 - device pci 5.0 off end # PCIE P2P bridge MXM lane 1 - device pci 6.0 on end # PCIE P2P bridge LAN - device pci 7.0 on end # PCIE P2P bridge MINIPCIE SLOT1 - device pci 8.0 off end # NB/SB Link P2P bridge - end # agesa northbridge + device lapic_cluster 0 on + chip cpu/amd/agesa/family14 + device lapic 0 on end + end + end + device pci_domain 0 on + subsystemid 0x1022 0x1510 inherit + chip northbridge/amd/agesa/family14 # CPU side of HT root complex +# device pci 18.0 on # northbridge + chip northbridge/amd/agesa/family14 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge, 9802 to 9806 + device pci 1.1 on end # Internal Multimedia + device pci 4.0 on end # PCIE P2P bridge MXM lane 0 + device pci 5.0 off end # PCIE P2P bridge MXM lane 1 + device pci 6.0 on end # PCIE P2P bridge LAN + device pci 7.0 on end # PCIE P2P bridge MINIPCIE SLOT1 + device pci 8.0 off end # NB/SB Link P2P bridge + end # agesa northbridge - chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/smsc/kbc1100 - device pnp 2e.7 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - end # kbc1100 + chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.1 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.1 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/smsc/kbc1100 + device pnp 2e.7 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + end # kbc1100 end #LPC device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 on end # USB 2 + device pci 14.5 on end # USB 2 device pci 15.0 on end # PCIe PortA Express Card device pci 15.1 on end # PCIe PortB NEC USB3.0 device pci 15.2 on end # PCIe PortC MINIPCIE SLOT2 @@ -74,20 +74,20 @@ chip northbridge/amd/agesa/family14/root_complex device pci 16.0 on end # OHCI USB3 device pci 16.2 on end # EHCI USB3 register "gpp_configuration" = "4" #1:1:1:1 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE end #southbridge/amd/cimx/sb800 -# end # device pci 18.0 +# end # device pci 18.0 # These seem unnecessary - device pci 18.0 on end - #device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - device pci 18.6 on end - device pci 18.7 on end - end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex - end #pci_domain + device pci 18.0 on end + #device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + device pci 18.7 on end + end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex + end #pci_domain end #northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/amd/inagua/dimmSpd.c b/src/mainboard/amd/inagua/dimmSpd.c index 3719112..7a8e82a 100644 --- a/src/mainboard/amd/inagua/dimmSpd.c +++ b/src/mainboard/amd/inagua/dimmSpd.c @@ -26,19 +26,19 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA #define DIMENSION(array)(sizeof (array)/ sizeof (array [0])) /*#pragma optimize ("", off) // for source level debug -*--------------------------------------------------------------------------- -* -* SPD address table - porting required -*/ + *--------------------------------------------------------------------------- + * + * SPD address table - porting required + */ static const UINT8 spdAddressLookup [1] [2] [2] = // socket, channel, dimm - { - // socket 0 - { - {0xA0, 0xA2}, // channel 0 dimms - {0x00, 0x00}, // channel 1 dimms - }, - }; +{ + // socket 0 + { + {0xA0, 0xA2}, // channel 0 dimms + {0x00, 0x00}, // channel 1 dimms + }, +}; /*----------------------------------------------------------------------------- * @@ -47,30 +47,30 @@ static const UINT8 spdAddressLookup [1] [2] [2] = // socket, channel, dimm static int readSmbusByteData (int iobase, int address, char *buffer, int offset) { - unsigned int status; - UINT64 limit; + unsigned int status; + UINT64 limit; - address |= 1; // set read bit + address |= 1; // set read bit - __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 1, 0x1F); // clear error status - __outbyte (iobase + 3, offset); // offset in eeprom - __outbyte (iobase + 4, address); // slave address and read bit - __outbyte (iobase + 2, 0x48); // read byte command + __outbyte (iobase + 0, 0xFF); // clear error status + __outbyte (iobase + 1, 0x1F); // clear error status + __outbyte (iobase + 3, offset); // offset in eeprom + __outbyte (iobase + 4, address); // slave address and read bit + __outbyte (iobase + 2, 0x48); // read byte command - // time limit to avoid hanging for unexpected error status (should never happen) - limit = __rdtsc () + 2000000000 / 10; + // time limit to avoid hanging for unexpected error status (should never happen) + limit = __rdtsc () + 2000000000 / 10; for (;;) { - status = __inbyte (iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting - break; - } - - buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors - return status; + status = __inbyte (iobase); + if (__rdtsc () > limit) break; + if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((status & 1) == 1) continue; // HostBusy set, keep waiting + break; + } + + buffer [0] = __inbyte (iobase + 5); + if (status == 2) status = 0; // check for done with no errors + return status; } /*----------------------------------------------------------------------------- @@ -81,25 +81,25 @@ static int readSmbusByteData (int iobase, int address, char *buffer, int offset) static int readSmbusByte (int iobase, int address, char *buffer) { - unsigned int status; - UINT64 limit; + unsigned int status; + UINT64 limit; - __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 2, 0x44); // read command + __outbyte (iobase + 0, 0xFF); // clear error status + __outbyte (iobase + 2, 0x44); // read command - // time limit to avoid hanging for unexpected error status - limit = __rdtsc () + 2000000000 / 10; + // time limit to avoid hanging for unexpected error status + limit = __rdtsc () + 2000000000 / 10; for (;;) { - status = __inbyte (iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting - break; - } - - buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors - return status; + status = __inbyte (iobase); + if (__rdtsc () > limit) break; + if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((status & 1) == 1) continue; // HostBusy set, keep waiting + break; + } + + buffer [0] = __inbyte (iobase + 5); + if (status == 2) status = 0; // check for done with no errors + return status; } /*--------------------------------------------------------------------------- @@ -113,47 +113,47 @@ static int readSmbusByte (int iobase, int address, char *buffer) static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) { - int index, error; + int index, error; - /* read the first byte using offset zero */ - error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0); - if (error) return error; + /* read the first byte using offset zero */ + error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0); + if (error) return error; - /* read the remaining bytes using auto-increment for speed */ + /* read the remaining bytes using auto-increment for speed */ for (index = 1; index < count; index++) { - error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]); - if (error) return error; - } + error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]); + if (error) return error; + } - return 0; + return 0; } static void writePmReg (int reg, int data) - { - __outbyte (0xCD6, reg); - __outbyte (0xCD7, data); - } +{ + __outbyte (0xCD6, reg); + __outbyte (0xCD7, data); +} static void setupFch (int ioBase) { - writePmReg (0x2D, ioBase >> 8); - writePmReg (0x2C, ioBase | 1); - writePmReg (0x29, 0x80); - writePmReg (0x28, 0x61); - __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz + writePmReg (0x2D, ioBase >> 8); + writePmReg (0x2C, ioBase | 1); + writePmReg (0x29, 0x80); + writePmReg (0x28, 0x61); + __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz } AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info) { - int spdAddress, ioBase; + int spdAddress, ioBase; - if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; - if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR; - if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR; + if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; + if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR; + if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR; - spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; - if (spdAddress == 0) return AGESA_ERROR; + spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; + if (spdAddress == 0) return AGESA_ERROR; ioBase = SMBUS0_BASE_ADDRESS; - setupFch (ioBase); - return readspd (ioBase, spdAddress, (void *) info->Buffer, 128); + setupFch (ioBase); + return readspd (ioBase, spdAddress, (void *) info->Buffer, 128); } diff --git a/src/mainboard/amd/inagua/get_bus_conf.c b/src/mainboard/amd/inagua/get_bus_conf.c index 13d198a..229477d 100644 --- a/src/mainboard/amd/inagua/get_bus_conf.c +++ b/src/mainboard/amd/inagua/get_bus_conf.c @@ -31,19 +31,19 @@ /* Global variables for MB layouts and these will be shared by irqtable mptable -* and acpi_tables busnum is default. -*/ + * and acpi_tables busnum is default. + */ u8 bus_isa; u8 bus_sb800[3]; u32 apicid_sb800; /* -* Here you only need to set value in pci1234 for HT-IO that could be installed or not -* You may need to preset pci1234 for HTIO board, -* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail -*/ + * Here you only need to set value in pci1234 for HT-IO that could be installed or not + * You may need to preset pci1234 for HTIO board, + * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + */ u32 pci1234x[] = { - 0x0000ff0, + 0x0000ff0, }; u32 bus_type[256]; @@ -55,81 +55,81 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - u32 status; - - device_t dev; - int i, j; - - if (get_bus_conf_done == 1) - return; /* do it only once */ - - get_bus_conf_done = 1; - -/* - * This is the call to AmdInitLate. It is really in the wrong place, conceptually, - * but functionally within the coreboot model, this is the best place to make the - * call. The logically correct place to call AmdInitLate is after PCI scan is done, - * after the decision about S3 resume is made, and before the system tables are - * written into RAM. The routine that is responsible for writing the tables is - * "write_tables", called near the end of "hardwaremain". There is no platform - * specific entry point between the S3 resume decision point and the call to - * "write_tables", and the next platform specific entry points are the calls to - * the ACPI table write functions. The first of ose would seem to be the right - * place, but other table write functions, e.g. the PIRQ table write function, are - * called before the ACPI tables are written. This routine is called at the beginning - * of each of the write functions called prior to the ACPI write functions, so this - * becomes the best place for this call. - */ - status = agesawrapper_amdinitlate(); - if(status) { - printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); - } - - sbdn_sb800 = 0; - - for (i = 0; i < 3; i++) { - bus_sb800[i] = 0; - } - - for (i = 0; i < 256; i++) { - bus_type[i] = 0; /* default ISA bus. */ - } - - bus_type[0] = 1; /* pci */ - -// bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; - bus_sb800[0] = (pci1234x[0] >> 16) & 0xff; - - /* sb800 */ - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4)); - - if (dev) { - bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); - - bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; - for (j = bus_sb800[1]; j < bus_isa; j++) - bus_type[j] = 1; - } - - for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i)); - if (dev) { - bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; - } - } - - for (j = bus_sb800[2]; j < bus_isa; j++) - bus_type[j] = 1; - - /* I/O APICs: APIC ID Version State Address */ - bus_isa = 10; + u32 status; + + device_t dev; + int i, j; + + if (get_bus_conf_done == 1) + return; /* do it only once */ + + get_bus_conf_done = 1; + + /* + * This is the call to AmdInitLate. It is really in the wrong place, conceptually, + * but functionally within the coreboot model, this is the best place to make the + * call. The logically correct place to call AmdInitLate is after PCI scan is done, + * after the decision about S3 resume is made, and before the system tables are + * written into RAM. The routine that is responsible for writing the tables is + * "write_tables", called near the end of "hardwaremain". There is no platform + * specific entry point between the S3 resume decision point and the call to + * "write_tables", and the next platform specific entry points are the calls to + * the ACPI table write functions. The first of ose would seem to be the right + * place, but other table write functions, e.g. the PIRQ table write function, are + * called before the ACPI tables are written. This routine is called at the beginning + * of each of the write functions called prior to the ACPI write functions, so this + * becomes the best place for this call. + */ + status = agesawrapper_amdinitlate(); + if(status) { + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); + } + + sbdn_sb800 = 0; + + for (i = 0; i < 3; i++) { + bus_sb800[i] = 0; + } + + for (i = 0; i < 256; i++) { + bus_type[i] = 0; /* default ISA bus. */ + } + + bus_type[0] = 1; /* pci */ + + // bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; + bus_sb800[0] = (pci1234x[0] >> 16) & 0xff; + + /* sb800 */ + dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4)); + + if (dev) { + bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + for (j = bus_sb800[1]; j < bus_isa; j++) + bus_type[j] = 1; + } + + for (i = 0; i < 4; i++) { + dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i)); + if (dev) { + bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + } + } + + for (j = bus_sb800[2]; j < bus_isa; j++) + bus_type[j] = 1; + + /* I/O APICs: APIC ID Version State Address */ + bus_isa = 10; apicid_base = CONFIG_MAX_CPUS; apicid_sb800 = apicid_base; #if CONFIG_AMD_SB_CIMX - sb_Late_Post(); + sb_Late_Post(); #endif } diff --git a/src/mainboard/amd/inagua/irq_tables.c b/src/mainboard/amd/inagua/irq_tables.c index 28432dd..de25b48 100644 --- a/src/mainboard/amd/inagua/irq_tables.c +++ b/src/mainboard/amd/inagua/irq_tables.c @@ -27,9 +27,9 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) { pirq_info->bus = bus; pirq_info->devfn = devfn; diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c index 89a3c6b..17c985d 100644 --- a/src/mainboard/amd/inagua/mainboard.c +++ b/src/mainboard/amd/inagua/mainboard.c @@ -74,8 +74,8 @@ void set_pcie_dereset(void) uint64_t uma_memory_base, uma_memory_size; /************************************************* -* enable the dedicated function in INAGUA board. -*************************************************/ + * enable the dedicated function in INAGUA board. + *************************************************/ static void inagua_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); @@ -87,14 +87,14 @@ static void inagua_enable(device_t dev) /* TOP_MEM: the top of DRAM below 4G */ msr = rdmsr(TOP_MEM); printk - (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); + (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", + __func__, msr.lo, msr.hi); /* TOP_MEM2: the top of DRAM above 4G */ msr2 = rdmsr(TOP_MEM2); printk - (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); + (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", + __func__, msr2.lo, msr2.hi); /* refer to UMA Size Consideration in Family14h BKDG. */ sys_mem = msr.lo + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size, refer MemNGetUmaSizeON() @@ -102,16 +102,16 @@ static void inagua_enable(device_t dev) uma_memory_size = 0x18000000; /* >= 2G memory, 384M recommended UMA */ } else { - if (sys_mem >= 0x40000000) { - uma_memory_size = 0x10000000; /* >= 1G memory, 256M recommended UMA */ + if (sys_mem >= 0x40000000) { + uma_memory_size = 0x10000000; /* >= 1G memory, 256M recommended UMA */ } else { - uma_memory_size = 0x4000000; /* <1G memory, 64M recommended UMA */ - } + uma_memory_size = 0x4000000; /* <1G memory, 64M recommended UMA */ + } } uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", - __func__, uma_memory_size, uma_memory_base); + __func__, uma_memory_size, uma_memory_base); /* TODO: TOP_MEM2 */ #else @@ -127,16 +127,16 @@ int add_mainboard_resources(struct lb_memory *mem) { /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. - */ + */ #if (CONFIG_GFXUMA == 1) printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", - uma_memory_base, uma_memory_size); + uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, - uma_memory_size); + uma_memory_size); #endif return 0; } struct chip_operations mainboard_ops = { CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") - .enable_dev = inagua_enable, + .enable_dev = inagua_enable, }; diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c index 0a2096b..b339348 100644 --- a/src/mainboard/amd/inagua/mptable.c +++ b/src/mainboard/amd/inagua/mptable.c @@ -50,115 +50,115 @@ u8 intr_data[] = { static void *smp_write_config_table(void *v) { - struct mp_config_table *mc; - int bus_isa; + struct mp_config_table *mc; + int bus_isa; - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); + mptable_init(mc, LAPIC_ADDR); + memcpy(mc->mpc_oem, "AMD ", 8); smp_write_processors(mc); - get_bus_conf(); + get_bus_conf(); mptable_write_buses(mc, NULL, &bus_isa); - /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ - u32 dword; - u8 byte; + u32 dword; + u8 byte; - ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); - dword &= 0xFFFFFFF0; - smp_write_ioapic(mc, apicid_sb800, 0x21, dword); + ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); + dword &= 0xFFFFFFF0; + smp_write_ioapic(mc, apicid_sb800, 0x21, dword); - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } + for (byte = 0x0; byte < sizeof(intr_data); byte ++) { + outb(byte | 0x80, 0xC00); + outb(intr_data[byte], 0xC01); + } - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0); - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ #if CONFIG_GENERATE_ACPI_TABLES == 0 #define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) #else #define PCI_INT(bus, dev, fn, pin) #endif - /* APU Internal Graphic Device*/ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + /* APU Internal Graphic Device*/ + PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */ - PCI_INT(0x0, 0x14, 0x0, 0x10); + PCI_INT(0x0, 0x14, 0x0, 0x10); /* Southbridge HD Audio: */ PCI_INT(0x0, 0x14, 0x2, 0x12); PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */ - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - /* PCI_SLOT 0. */ - PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14); - PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15); - PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16); - PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15); - PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16); - PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17); - PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16); - PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17); - PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14); - PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15); - - PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12); - PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13); - PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14); + PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); + + /* sata */ + PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + + /* on board NIC & Slot PCIE. */ + + /* PCI slots */ + /* PCI_SLOT 0. */ + PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14); + PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15); + PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16); + PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17); + + /* PCI_SLOT 1. */ + PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15); + PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16); + PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17); + PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14); + + /* PCI_SLOT 2. */ + PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16); + PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17); + PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14); + PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15); + + PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12); + PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13); + PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14); /* PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); + PCI_INT(0x0, 0x15, 0x0, 0x10); /* PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); + PCI_INT(0x0, 0x15, 0x1, 0x11); /* PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); + PCI_INT(0x0, 0x15, 0x2, 0x12); /* PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); + PCI_INT(0x0, 0x15, 0x3, 0x13); - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ + /* There is no extension information... */ - /* Compute the checksums */ - return mptable_finalize(mc); + /* Compute the checksums */ + return mptable_finalize(mc); } unsigned long write_smp_table(unsigned long addr) { - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); } diff --git a/src/mainboard/amd/inagua/platform_cfg.h b/src/mainboard/amd/inagua/platform_cfg.h index 87b2893..2a3342c 100644 --- a/src/mainboard/amd/inagua/platform_cfg.h +++ b/src/mainboard/amd/inagua/platform_cfg.h @@ -38,13 +38,13 @@ */ #ifndef BIOS_SIZE #if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 - #define BIOS_SIZE BIOS_SIZE_1M +#define BIOS_SIZE BIOS_SIZE_1M #elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 - #define BIOS_SIZE BIOS_SIZE_2M +#define BIOS_SIZE BIOS_SIZE_2M #elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1 - #define BIOS_SIZE BIOS_SIZE_4M +#define BIOS_SIZE BIOS_SIZE_4M #elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1 - #define BIOS_SIZE BIOS_SIZE_8M +#define BIOS_SIZE BIOS_SIZE_8M #endif #endif

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New patch to review for coreboot: 5af98c9 Leave SSE and MMX instructions enabled in coreboot
by Stefan Reinauer 18 Jan '12

18 Jan '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/553 -gerrit commit 5af98c9e3b9c2dc27085247946a48346c33ea4cd Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Jan 18 23:28:52 2012 +0100 Leave SSE and MMX instructions enabled in coreboot In order to use SSE+MMX optimized payloads we don't want to disable SSE+MMX instructions in the CPU after romstage. Change-Id: I51aeb01f04492ad7bc8b1fe181a4ae17fe0ca61e Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/Makefile.inc | 7 ------ src/cpu/x86/mmx_disable.inc | 24 ----------------------- src/cpu/x86/sse_disable.inc | 44 ------------------------------------------- 3 files changed, 0 insertions(+), 75 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 54f0f82..cbe38dd 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -204,13 +204,6 @@ endif crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc -ifeq ($(CONFIG_SSE),y) -crt0s += $(src)/cpu/x86/sse_disable.inc -endif -ifeq ($(CONFIG_MMX),y) -crt0s += $(src)/cpu/x86/mmx_disable.inc -endif - ifeq ($(CONFIG_ROMCC),y) crt0s += $(src)/arch/x86/init/crt0_romcc_epilogue.inc endif diff --git a/src/cpu/x86/mmx_disable.inc b/src/cpu/x86/mmx_disable.inc deleted file mode 100644 index 1a4e70f..0000000 --- a/src/cpu/x86/mmx_disable.inc +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2002 Eric Biederman <ebiederm(a)xmission.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - - /* - * Execute the EMMS (Empty MMX Technology State) instruction. - */ - emms - diff --git a/src/cpu/x86/sse_disable.inc b/src/cpu/x86/sse_disable.inc deleted file mode 100644 index 37458c9..0000000 --- a/src/cpu/x86/sse_disable.inc +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2002 Eric Biederman <ebiederm(a)xmission.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - - /* - * Put the processor back into a reset state - * with respect to the XMM registers. - */ - xorps %xmm0, %xmm0 - xorps %xmm1, %xmm1 - xorps %xmm2, %xmm2 - xorps %xmm3, %xmm3 - xorps %xmm4, %xmm4 - xorps %xmm5, %xmm5 - xorps %xmm6, %xmm6 - xorps %xmm7, %xmm7 - - /* - * Disable SSE instructions. - * - * Clear CR4[9] (OSFXSR) and CR4[10] (OSXMMEXCPT) so that the - * processor can no longer execute SSE instructions, and unmasked - * SIMD floating point exceptions will generate an invalid opcode - * exception (#UD). - */ - movl %cr4, %eax - andl $~(3 << 9), %eax - movl %eax, %cr4 -

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New patch to review for coreboot: 7c77c17 Move SeaBIOS output out of coreboot source tree
by Stefan Reinauer 18 Jan '12

18 Jan '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/552 -gerrit commit 7c77c17c2998ba7b9e3ad4ae926a8030f50180ee Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Jan 18 23:25:16 2012 +0100 Move SeaBIOS output out of coreboot source tree Make sure SeaBIOS build files live under $(OUT) instead of in the source tree. Change-Id: I7d357773e32bc25ba7e7eae3fb6ddc31feb413ec Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- payloads/external/SeaBIOS/Makefile.inc | 30 +++++++++++++++--------------- src/arch/x86/Makefile.inc | 4 +++- 2 files changed, 18 insertions(+), 16 deletions(-) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 99d402c..5e34d6a 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -9,37 +9,37 @@ all: build seabios: echo " Cloning SeaBIOS from Git" - git clone git://git.seabios.org/seabios.git + cd $(OUT) && git clone git://git.seabios.org/seabios.git fetch: seabios - cd seabios; git show $(TAG-y) >/dev/null 2>&1 ; if [ $$? -ne 0 ]; \ + cd $(OUT)/seabios; git show $(TAG-y) >/dev/null 2>&1 ; if [ $$? -ne 0 ]; \ then echo " Fetching new commits from the SeaBIOS git repo"; git fetch; fi checkout: fetch echo " Checking out SeaBIOS revision $(TAG-y)" - cd seabios; git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y) + cd $(OUT)/seabios; git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y) config: checkout echo " CONFIG SeaBIOS $(TAG-y)" - $(MAKE) -C seabios defconfig - echo "CONFIG_COREBOOT=y" >> seabios/.config - echo "CONFIG_DEBUG_SERIAL=y" >> seabios/.config - echo "CONFIG_DEBUG_SERIAL_PORT=0x3f8" >> seabios/.config - echo "CONFIG_COREBOOT_FLASH=y" >> seabios/.config - echo "CONFIG_LZMA=y" >> seabios/.config - echo "CONFIG_FLASH_FLOPPY=y" >> seabios/.config - echo "CONFIG_VGAHOOKS=y" >> seabios/.config + $(MAKE) -C $(OUT)/seabios defconfig OUT=$(OUT)/seabios/out + echo "CONFIG_COREBOOT=y" >> $(OUT)/seabios/.config + echo "CONFIG_DEBUG_SERIAL=y" >> $(OUT)/seabios/.config + echo "CONFIG_DEBUG_SERIAL_PORT=0x3f8" >> $(OUT)/seabios/.config + echo "CONFIG_COREBOOT_FLASH=y" >> $(OUT)/seabios/.config + echo "CONFIG_LZMA=y" >> $(OUT)/seabios/.config + echo "CONFIG_FLASH_FLOPPY=y" >> $(OUT)/seabios/.config + echo "CONFIG_VGAHOOKS=y" >> $(OUT)/seabios/.config # This shows how to force a previously set .config option *off* - #echo "# CONFIG_SMBIOS is not set" >> seabios/.config + #echo "# CONFIG_SMBIOS is not set" >> $(OUT)/seabios/.config build: config echo " MAKE SeaBIOS $(TAG-y)" - $(MAKE) -C seabios + $(MAKE) -C $(OUT)/seabios OUT=$(OUT)/seabios/out clean: - test -d seabios && $(MAKE) -C seabios clean || exit 0 + test -d $(OUT)/seabios && $(MAKE) -C $(OUT)/seabios clean OUT=$(OUT)/seabios/out || exit 0 distclean: - rm -rf seabios + rm -rf $(OUT)/seabios .PHONY: checkout config build clean distclean clone fetch diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 54f0f82..3442b49 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -387,7 +387,9 @@ seabios: CC="$(CC)" LD="$(LD)" OBJDUMP="$(OBJDUMP)" \ OBJCOPY="$(OBJCOPY)" STRIP="$(STRIP)" \ CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \ - CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE) + CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE) \ + OUT=$(abspath $(obj))/ + filo: $(MAKE) -C payloads/external/FILO -f Makefile.inc \ HOSTCC="$(HOSTCC)" \

1 0

Patch merged into coreboot/master: 3e176ae Clean up AMD romstage.c serial output
by gerrit＠coreboot.org 18 Jan '12

18 Jan '12

the following patch was just integrated into master: commit 3e176aefd315f1ca0932c510241b0b7f599fa6e3 Author: Marc Jones <marcj303(a)gmail.com> Date: Tue Jan 17 16:51:24 2012 -0700 Clean up AMD romstage.c serial output This cleans up the strings in romstage.c, removing the ugly "got past". Also, cleaned up comments and some spacing. Change-Id: I0124df76eb442f8a0009a31a8632e4fd67ed7782 Signed-off-by: Marc Jones <marcj303(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Jan 18 21:10:23 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Wed Jan 18 22:55:58 2012, giving +2 See http://review.coreboot.org/539 for details. -gerrit

1 0

Patch merged into coreboot/master: 80f420e Add subsystem callbacks for VT8237x and VT890 family of chipsets
by gerrit＠coreboot.org 18 Jan '12

18 Jan '12

the following patch was just integrated into master: commit 80f420e5d626dc84c98196c2b9dd9d58cd3ad1d5 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Fri Apr 22 20:48:21 2011 +0200 Add subsystem callbacks for VT8237x and VT890 family of chipsets Change-Id: Id34615f0c229d276d72cdf984cf82ea8cc1a85bb Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Build-Tested: build bot (Jenkins) at Sat Jan 7 15:30:25 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Wed Jan 18 23:00:46 2012, giving +2 See http://review.coreboot.org/523 for details. -gerrit

1 0

Patch merged into coreboot/master: d579042 Remove duplicated line of code in AMD wrappers.
by gerrit＠coreboot.org 18 Jan '12

18 Jan '12

the following patch was just integrated into master: commit d579042843cb3faf2e240730a1f7ef9ecba9ff89 Author: Marc Jones <marcj303(a)gmail.com> Date: Tue Jan 17 17:34:03 2012 -0700 Remove duplicated line of code in AMD wrappers. This line was unnecessary and was duplicated on several mainboards. Change-Id: I438da05c770ded0bd32256f1c157cabcc383667a Signed-off-by: Marc Jones <marcj303(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Jan 18 20:47:42 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Wed Jan 18 22:58:40 2012, giving +2 See http://review.coreboot.org/541 for details. -gerrit

1 0

Patch merged into coreboot/master: 4a10baf Remove old AMD #define
by gerrit＠coreboot.org 18 Jan '12

18 Jan '12

the following patch was just integrated into master: commit 4a10bafe4a530f4ae3afc6ae5a1c692a702d9df6 Author: Marc Jones <marcj303(a)gmail.com> Date: Tue Jan 17 17:30:31 2012 -0700 Remove old AMD #define The #define REQUIRED_CALLOUTS is no longer used on these platforms. Change-Id: I536eb94119f1bc8f81e59ebefacdd4e04d0ed3ef Signed-off-by: Marc Jones <marcj303(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Jan 18 20:58:50 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Wed Jan 18 22:58:05 2012, giving +2 See http://review.coreboot.org/540 for details. -gerrit

1 0

Patch set updated for coreboot: 3e176ae Clean up AMD romstage.c serial output
by Marc Jones 18 Jan '12

18 Jan '12

Marc Jones (marcj303(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/539 -gerrit commit 3e176aefd315f1ca0932c510241b0b7f599fa6e3 Author: Marc Jones <marcj303(a)gmail.com> Date: Tue Jan 17 16:51:24 2012 -0700 Clean up AMD romstage.c serial output This cleans up the strings in romstage.c, removing the ugly "got past". Also, cleaned up comments and some spacing. Change-Id: I0124df76eb442f8a0009a31a8632e4fd67ed7782 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/mainboard/amd/inagua/romstage.c | 52 +++++++++++++----------- src/mainboard/amd/persimmon/romstage.c | 60 ++++++++++++++++----------- src/mainboard/amd/south_station/romstage.c | 56 +++++++++++++++----------- src/mainboard/amd/torpedo/get_bus_conf.c | 22 ++++------ src/mainboard/amd/torpedo/romstage.c | 60 ++++++++++++++------------- src/mainboard/amd/union_station/romstage.c | 54 +++++++++++++++---------- src/mainboard/asrock/e350m1/romstage.c | 60 +++++++++++++++------------ 7 files changed, 200 insertions(+), 164 deletions(-) diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index d5fa8c5..88c018e 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -63,47 +63,50 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x34); report_bist_failure(bist); - // Load MPB + /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); post_code(0x35); + printk(BIOS_DEBUG, "agesawrapper_amdinitmmio "); val = agesawrapper_amdinitmmio(); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); post_code(0x37); + printk(BIOS_DEBUG, "agesawrapper_amdinitreset "); val = agesawrapper_amdinitreset(); - if (val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", - val); - } - - post_code(0x38); - printk(BIOS_DEBUG, "Got past sb800_early_setup\n"); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); post_code(0x39); + printk(BIOS_DEBUG, "agesawrapper_amdinitearly "); val = agesawrapper_amdinitearly(); - if (val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", - val); - } - printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n"); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); post_code(0x40); + printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); val = agesawrapper_amdinitpost(); - if (val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", - val); - } - printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n"); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); post_code(0x41); + printk(BIOS_DEBUG, "agesawrapper_amdinitenv "); val = agesawrapper_amdinitenv(); - if (val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", - val); - } - printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n"); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); /* Initialize i8259 pic */ post_code(0x41); @@ -115,6 +118,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x50); copy_and_run(0); + printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - post_code(0x54); // Should never see this post code. + post_code(0x54); /* Should never see this post code. */ } diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index bf8535f..dfb1aca 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -9,12 +9,12 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <stdint.h> @@ -46,12 +46,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - // all cores: allow caching of flash chip code and data - // (there are no cache-as-ram reliability concerns with family 14h) + /* + * All cores: allow caching of flash chip code and data + * (there are no cache-as-ram reliability concerns with family 14h) + */ __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); - // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time + /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); if (!cpu_init_detectedx && boot_cpu()) { @@ -67,43 +69,50 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x34); report_bist_failure(bist); - // Load MPB + /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); post_code(0x35); + printk(BIOS_DEBUG, "agesawrapper_amdinitmmio "); val = agesawrapper_amdinitmmio(); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); post_code(0x37); + printk(BIOS_DEBUG, "agesawrapper_amdinitreset "); val = agesawrapper_amdinitreset(); - if(val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); - } - - post_code(0x38); - printk(BIOS_DEBUG, "Got past sb800_early_setup\n"); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); post_code(0x39); + printk(BIOS_DEBUG, "agesawrapper_amdinitearly "); val = agesawrapper_amdinitearly (); - if(val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); - } - printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n"); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); post_code(0x40); + printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); val = agesawrapper_amdinitpost (); - if(val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); - } - printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n"); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); post_code(0x41); + printk(BIOS_DEBUG, "agesawrapper_amdinitenv "); val = agesawrapper_amdinitenv (); - if(val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); - } - printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n"); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); /* Initialize i8259 pic */ post_code(0x41); @@ -115,6 +124,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x50); copy_and_run(0); + printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - post_code(0x54); // Should never see this post code. + post_code(0x54); /* Should never see this post code. */ } diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index 95f27bd..8ebe7a6 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -43,12 +43,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - // all cores: allow caching of flash chip code and data - // (there are no cache-as-ram reliability concerns with family 14h) + /* + * All cores: allow caching of flash chip code and data + * (there are no cache-as-ram reliability concerns with family 14h) + */ __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); - // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time + /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); if (!cpu_init_detectedx && boot_cpu()) { @@ -64,47 +66,55 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x34); report_bist_failure(bist); - // Load MPB + /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); post_code(0x35); + printk(BIOS_DEBUG, "agesawrapper_amdinitmmio "); val = agesawrapper_amdinitmmio(); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); post_code(0x37); + printk(BIOS_DEBUG, "agesawrapper_amdinitreset "); val = agesawrapper_amdinitreset(); - if(val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); - } - - post_code(0x38); - printk(BIOS_DEBUG, "Got past sb800_early_setup\n"); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); post_code(0x39); + printk(BIOS_DEBUG, "agesawrapper_amdinitearly "); val = agesawrapper_amdinitearly (); - if(val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); - } - printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n"); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); post_code(0x40); + printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); val = agesawrapper_amdinitpost (); - if(val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); - } - printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n"); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); post_code(0x41); + printk(BIOS_DEBUG, "agesawrapper_amdinitenv "); val = agesawrapper_amdinitenv (); - if(val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); - } - printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n"); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); post_code(0x50); copy_and_run(0); + printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - post_code(0x54); // Should never see this post code. + post_code(0x54); /* Should never see this post code. */ } diff --git a/src/mainboard/amd/torpedo/get_bus_conf.c b/src/mainboard/amd/torpedo/get_bus_conf.c index 7dbe9a5..13eadaa 100644 --- a/src/mainboard/amd/torpedo/get_bus_conf.c +++ b/src/mainboard/amd/torpedo/get_bus_conf.c @@ -54,7 +54,6 @@ u32 bus_type[256]; u32 sbdn_sb900; -//KZ [092110]extern void get_pci1234(void); static u32 get_bus_conf_done = 0; @@ -70,8 +69,7 @@ void get_bus_conf(void) get_bus_conf_done = 1; - printk(BIOS_DEBUG, - "Mainboard - Get_bus_conf.c - get_bus_conf - Start.\n"); + printk(BIOS_DEBUG, "Mainboard - %s - %s - Start.\n", __FILE__, __func__); /* * This is the call to AmdInitLate. It is really in the wrong place, conceptually, * but functionally within the coreboot model, this is the best place to make the @@ -87,12 +85,12 @@ void get_bus_conf(void) * of each of the write functions called prior to the ACPI write functions, so this * becomes the best place for this call. */ + printk(BIOS_DEBUG, "agesawrapper_amdinitlate "); status = agesawrapper_amdinitlate(); - if (status) { - printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", - status); - } - printk(BIOS_DEBUG, "Got past agesawrapper_amdinitlate\n"); + if (status) + printk(BIOS_DEBUG, "error level: %x \n", status); + else + printk(BIOS_DEBUG, "passed.\n"); sbdn_sb900 = 0; @@ -106,7 +104,6 @@ void get_bus_conf(void) bus_type[0] = 1; /* pci */ -// bus_sb900[0] = (sysconf.pci1234[0] >> 16) & 0xff; bus_sb900[0] = (pci1234x[0] >> 16) & 0xff; /* sb900 */ @@ -114,7 +111,6 @@ void get_bus_conf(void) if (dev) { bus_sb900[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; for (j = bus_sb900[1]; j < bus_isa; j++) @@ -122,8 +118,7 @@ void get_bus_conf(void) } for (i = 0; i < 4; i++) { - dev = - dev_find_slot(bus_sb900[0], + dev = dev_find_slot(bus_sb900[0], PCI_DEVFN(sbdn_sb900 + 0x14, i)); if (dev) { bus_sb900[2 + i] = @@ -139,6 +134,5 @@ void get_bus_conf(void) bus_isa = 10; sb_Late_Post(); - printk(BIOS_DEBUG, - "Mainboard - Get_bus_conf.c - get_bus_conf - End.\n"); + printk(BIOS_DEBUG, "Mainboard - %s - %s - End.\n", __FILE__, __func__); } diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index ea902d8..2e1d8fc 100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c @@ -45,12 +45,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; post_code(0x35); + printk(BIOS_DEBUG, "agesawrapper_amdinitmmio "); val = agesawrapper_amdinitmmio(); - if (val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitmmio failed: %x \n", - val); - } - printk(BIOS_DEBUG, "Got past agesawrapper_amdinitmmio\n"); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); @@ -77,54 +77,56 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); post_code(0x36); + printk(BIOS_DEBUG, "agesawrapper_amdinitreset "); val = agesawrapper_amdinitreset(); - if (val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", - val); - } - printk(BIOS_DEBUG, "Got past agesawrapper_amdinitreset\n"); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); post_code(0x37); + printk(BIOS_DEBUG, "agesawrapper_amdinitearly "); val = agesawrapper_amdinitearly(); - if (val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", - val); - } - printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n"); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); post_code(0x38); + printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); val = agesawrapper_amdinitpost(); - if (val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", - val); - } - printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n"); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); post_code(0x39); + printk(BIOS_DEBUG, "sb_before_pci_init "); sb_before_pci_init(); - printk(BIOS_DEBUG, "Got past sb_before_pci_init\n"); + printk(BIOS_DEBUG, "passed.\n"); post_code(0x40); + printk(BIOS_DEBUG, "agesawrapper_amdinitenv "); val = agesawrapper_amdinitenv(); - if (val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", - val); - } - printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n"); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); /* Initialize i8259 pic */ post_code(0x41); + printk(BIOS_DEBUG, "setup_i8259\n"); setup_i8259(); - printk(BIOS_DEBUG, "Got past setup_i8259\n"); /* Initialize i8254 timers */ post_code(0x42); + printk(BIOS_DEBUG, "setup_i8254\n"); setup_i8254(); - printk(BIOS_DEBUG, "Got past setup_i8254\n"); + post_code(0x43); copy_and_run(0); - printk(BIOS_DEBUG, "Got past copy_and_run\n"); + printk(BIOS_ERR, "Error: copy_and_run returned!\n"); post_code(0x44); // Should never see this post code. } diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index e7f05e8..26a05e8 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -43,8 +43,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - // all cores: allow caching of flash chip code and data - // (there are no cache-as-ram reliability concerns with family 14h) + /* + * All cores: allow caching of flash chip code and data + * (there are no cache-as-ram reliability concerns with family 14h) + */ __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); @@ -61,47 +63,55 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x34); report_bist_failure(bist); - // Load MPB + /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); post_code(0x35); + printk(BIOS_DEBUG, "agesawrapper_amdinitmmio "); val = agesawrapper_amdinitmmio(); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); post_code(0x37); + printk(BIOS_DEBUG, "agesawrapper_amdinitreset "); val = agesawrapper_amdinitreset(); - if(val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); - } - - post_code(0x38); - printk(BIOS_DEBUG, "Got past sb800_early_setup\n"); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); post_code(0x39); + printk(BIOS_DEBUG, "agesawrapper_amdinitearly "); val = agesawrapper_amdinitearly (); - if(val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); - } - printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n"); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); post_code(0x40); + printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); val = agesawrapper_amdinitpost (); - if(val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); - } - printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n"); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); post_code(0x41); + printk(BIOS_DEBUG, "agesawrapper_amdinitenv "); val = agesawrapper_amdinitenv (); - if(val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); - } - printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n"); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); post_code(0x50); copy_and_run(0); + printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - post_code(0x54); // Should never see this post code. + post_code(0x54); /* Should never see this post code. */ } diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 133aca7..8b46b19 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -47,12 +47,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; u8 reg8; - // all cores: allow caching of flash chip code and data - // (there are no cache-as-ram reliability concerns with family 14h) + /* + * All cores: allow caching of flash chip code and data + * (there are no cache-as-ram reliability concerns with family 14h) + */ __writemsr(0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); __writemsr(0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); - // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time + /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr(0xc0010062, 0); if (!cpu_init_detectedx && boot_cpu()) { @@ -68,47 +70,50 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x34); report_bist_failure(bist); - // Load MPB + /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); post_code(0x35); + printk(BIOS_DEBUG, "agesawrapper_amdinitmmio "); val = agesawrapper_amdinitmmio(); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); post_code(0x37); + printk(BIOS_DEBUG, "agesawrapper_amdinitreset "); val = agesawrapper_amdinitreset(); - if (val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", - val); - } - - post_code(0x38); - printk(BIOS_DEBUG, "Got past sb800_early_setup\n"); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); post_code(0x39); + printk(BIOS_DEBUG, "agesawrapper_amdinitearly "); val = agesawrapper_amdinitearly(); - if (val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", - val); - } - printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n"); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); post_code(0x40); + printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); val = agesawrapper_amdinitpost(); - if (val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", - val); - } - printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n"); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); post_code(0x41); + printk(BIOS_DEBUG, "agesawrapper_amdinitenv "); val = agesawrapper_amdinitenv(); - if (val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", - val); - } - printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n"); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); /* Initialize i8259 pic */ post_code(0x41); @@ -120,6 +125,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x50); copy_and_run(0); + printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - post_code(0x54); // Should never see this post code. + post_code(0x54); /* Should never see this post code. */ }

1 0

Patch set updated for coreboot: 4a10baf Remove old AMD #define
by Marc Jones 18 Jan '12

18 Jan '12

Marc Jones (marcj303(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/540 -gerrit commit 4a10bafe4a530f4ae3afc6ae5a1c692a702d9df6 Author: Marc Jones <marcj303(a)gmail.com> Date: Tue Jan 17 17:30:31 2012 -0700 Remove old AMD #define The #define REQUIRED_CALLOUTS is no longer used on these platforms. Change-Id: I536eb94119f1bc8f81e59ebefacdd4e04d0ed3ef Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/mainboard/amd/persimmon/BiosCallOuts.h | 1 - src/mainboard/amd/south_station/BiosCallOuts.h | 1 - src/mainboard/amd/union_station/BiosCallOuts.h | 1 - 3 files changed, 0 insertions(+), 3 deletions(-) diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.h b/src/mainboard/amd/persimmon/BiosCallOuts.h index e023e38..d9e4497 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.h +++ b/src/mainboard/amd/persimmon/BiosCallOuts.h @@ -23,7 +23,6 @@ #include "Porting.h" #include "AGESA.h" -#define REQUIRED_CALLOUTS 12 #define BIOS_HEAP_START_ADDRESS 0x00010000 #define BIOS_HEAP_SIZE 0x20000 /* 64MB */ diff --git a/src/mainboard/amd/south_station/BiosCallOuts.h b/src/mainboard/amd/south_station/BiosCallOuts.h index b187fa2..750b59d 100644 --- a/src/mainboard/amd/south_station/BiosCallOuts.h +++ b/src/mainboard/amd/south_station/BiosCallOuts.h @@ -23,7 +23,6 @@ #include "Porting.h" #include "AGESA.h" -#define REQUIRED_CALLOUTS 12 #define BIOS_HEAP_START_ADDRESS 0x00010000 #define BIOS_HEAP_SIZE 0x20000 /* 64MB */ diff --git a/src/mainboard/amd/union_station/BiosCallOuts.h b/src/mainboard/amd/union_station/BiosCallOuts.h index b187fa2..750b59d 100644 --- a/src/mainboard/amd/union_station/BiosCallOuts.h +++ b/src/mainboard/amd/union_station/BiosCallOuts.h @@ -23,7 +23,6 @@ #include "Porting.h" #include "AGESA.h" -#define REQUIRED_CALLOUTS 12 #define BIOS_HEAP_START_ADDRESS 0x00010000 #define BIOS_HEAP_SIZE 0x20000 /* 64MB */

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coreboot January 2012