coreboot January 2012

coreboot@coreboot.org

40 participants
302 discussions

Re: [coreboot] Lenovo T60 Type 8743-GZU - RAM Support? 3Gb or 4Gb
by Peter Stuge 17 Jan '12

17 Jan '12

Josh Stump wrote: > I have a Lenovo T60 Type 8743-GZU. From experience I know that with the > stock BIOS if I put in 4Gb of RAM I can only utilze 3Gb even with a 64bit > OS installed. Is this a limitation of the stock BIOS that coreboot can > overcome or is this simply a chipset limitation and even if I got coreboot > flashed I still would only have use of 4Gb of RAM. Does anyone know for > certain? It is a limitation of the factory BIOS. For comparison, on an X60 with 4GB of RAM with coreboot there is immediately 3.2GB available for OS use. This is with the standard resource allocator in coreboot, ie. without any intense optimizations. If you work on optimizing this, you may get even more usable RAM. The technical limit is that many of the hardware parts in the system require that they be memory mapped into the CPU bus, and that is only 32 bits, so some of the 4GB of RAM will be "covered" by these hardware memory regions, but with coreboot you have an opportunity to work on reducing this to the bare minimum. > what parts I might need to flash my rom over. You need the flashrom source, a small patch, and my bucts utility from http://git.stuge.se/?p=bucts.git Patch flashrom to use RES1 SPI identification and spi_chip_write1 for your flash chip, as well as change the flash chip model id to fit the RES1 command. then run flashrom -p internal:laptop=force_I_want_a_brick -r factory.bin # this step is IMPORTANT since the factory BIOS in your machine is # tied to your particular system board "planar in IBM FRU terms" with # a unique ID not present in factory BIOS updates then build coreboot.rom # note that you must include the correct VGA BIOS for your machine in # order to have any graphics working when you use coreboot then run dd if=coreboot.rom of=top64k.bin bs=1 \ skip=$[sizeof(coreboot.rom) - 0x10000] count=64k then run dd if=top64k of=coreboot.rom bs=1 \ seek=$[sizeof(coreboot.rom) - 0x20000] count=64k conv=notrunc then run bucts 1 then run flashrom -p internal:laptop=force_I_want_a_brick -w coreboot.rom # this will be slow, and shall generate an erase error at e.g. 0x1f0000 # when working with a 2 Mbyte flash chip. then power cycle, now starting with coreboot then undo the flashrom patch, so that you have a stock flashrom then run bucts 0 then run flashrom -p internal:laptop=force_I_want_a_brick -w coreboot.rom # his will successfully overwrite the entire flash chip, including # the last 64k that were write protected with the factory BIOS. Many thanks to Sven for figuring out this procedure! It has been successfully performed on at least two X60 machines with factory BIOS. ron minnich wrote: > It's almost certainly impossible to get coreboot going on your T60. I believe Sven's port is working! //Peter

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Re: [coreboot] Lenovo T60 Type 8743-GZU - RAM Support? 3Gb or 4Gb
by ron minnich 17 Jan '12

17 Jan '12

It's almost certainly impossible to get coreboot going on your T60. ron

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[RFC] Announce new posts in blogs.coreboot.org on list
by Paul Menzel 17 Jan '12

17 Jan '12

Dear coreboot folks, as hopefully everyone of you knows, coreboot has a blog [1]. Unfortunately not a lot of posts are written. So for people interested in coreboot and subscribed to the list but not using RSS/Atom feeds maybe an announcement could be sent to the list? (At least until ten blog posts per day are written.) If no subscriber objects during the next week, maybe Patrick could set up a hook in Wordpress? That would be great. Thanks, Paul [1] http://blogs.coreboot.org/

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New patch to review for coreboot: 7e6b6db Add coreboot version to id area
by Patrick Georgi 17 Jan '12

17 Jan '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/537 -gerrit commit 7e6b6db4ab80ffb8103c6a6ab32f3b648976b7fe Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Jan 17 13:13:59 2012 +0100 Add coreboot version to id area There was no good way to extract the build version from an image. This change will be mostly backward compatible: The only assumption that could break is that the board name string end directly before the 3 dwords that represent .id's "header". Change-Id: I325491a0c42911d9d6ecd59e21ee1b756c987693 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- src/arch/x86/Makefile.inc | 12 ++++++------ src/arch/x86/lib/id.inc | 3 +++ 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 7bba44e..54f0f82 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -321,15 +321,15 @@ $(obj)/bootblock/ldscript.ld: $$(bootblock_lds) $(obj)/ldoptions $(obj)/bootblock/bootblock.S: $$(bootblock_inc) @printf " GEN $(subst $(obj)/,,$(@))\n" mkdir -p $(obj)/bootblock - printf '$(foreach crt0,config.h $(bootblock_inc),#include "$(crt0)"\n)' > $@ + printf '$(foreach crt0,$(bootblock_inc),#include "$(crt0)"\n)' > $@ $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -I$(obj) -Wa,-acdlns -c -o $@ $< > $(dir $(a))/crt0.disasm -$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s: $(obj)/bootblock/bootblock.S +$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s: $(obj)/bootblock/bootblock.S $(obj)/config.h $(obj)/build.h @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/bootblock -include $(obj)/config.h -I. -I$(src) $< -o $@ + $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/bootblock -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) @printf " ROMCC $(subst $(obj)/,,$(@))\n" @@ -371,15 +371,15 @@ $(obj)/romstage/ldscript.ld: $$(ldscripts) $(obj)/ldoptions $(obj)/romstage/crt0.S: $$(crt0s) @printf " GEN $(subst $(obj)/,,$(@))\n" mkdir -p $(obj)/romstage - printf '$(foreach crt0,config.h $(crt0s),#include "$(crt0:$(obj)/%=%)"\n)' > $@ + printf '$(foreach crt0,$(crt0s),#include "$(crt0:$(obj)/%=%)"\n)' > $@ $(obj)/mainboard/$(MAINBOARDDIR)/crt0.romstage.o: $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -I$(obj) -Wa,-acdlns -c -o $@ $< > $(dir $(a))/crt0.disasm -$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(obj)/romstage/crt0.S +$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(obj)/romstage/crt0.S $(obj)/config.h $(obj)/build.h @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/romstage -include $(obj)/config.h -I. -I$(src) $< -o $@ + $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/romstage -include $(obj)/config.h -include $(obj)/build.h -I. -I$(src) $< -o $@ seabios: $(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc \ diff --git a/src/arch/x86/lib/id.inc b/src/arch/x86/lib/id.inc index 443dbad..f8aba0b 100644 --- a/src/arch/x86/lib/id.inc +++ b/src/arch/x86/lib/id.inc @@ -2,10 +2,13 @@ .globl __id_start __id_start: +ver: + .asciz COREBOOT_VERSION vendor: .asciz CONFIG_MAINBOARD_VENDOR part: .asciz CONFIG_MAINBOARD_PART_NUMBER +.long __id_end + CONFIG_ID_SECTION_OFFSET - ver /* Reverse offset to the vendor id */ .long __id_end + CONFIG_ID_SECTION_OFFSET - vendor /* Reverse offset to the vendor id */ .long __id_end + CONFIG_ID_SECTION_OFFSET - part /* Reverse offset to the part number */ .long CONFIG_ROM_SIZE /* Size of this romimage */

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Re: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization
by Marc Jones 16 Jan '12

16 Jan '12

On Mon, Jan 16, 2012 at 10:18 AM, Wolfgang Kamp - datakamp <wmkamp(a)datakamp.de> wrote: > Hello, > > > > I found a problem with the PCI enumeration of the PCIe Ports in the > CIMX/SB800 Southbridge for the INAGUA platform. > > The …/southbridge/amd/cimx/sb800/late.c routine calls the function > sb_Before_PCI_Init after > > case (0x16 >>3) | 2. This means when the PCI Express ports (0x15 <<3) | 0 > are probed in the routine ../devices/pci_device.c function > > pci_probe_dev they are not yet initialized. The probing fails and also > devices behind the bridge are not recognized. > > Behind the PCIe bridge I have an Intel 82574 LAN chip. > > But if I move the call to sb_Before_PCI_Init behind case (0x15 <<3) | 0 the > enumeration succeed but coreboot crashes later into nothing. The Sage > Debugger fails. > > I can’t imagine why. > > > > Marc have you any idea? This looks like a problem in the sb800 cimx wrapper logic. Cimx doesn't treat the devices separately. it lumps all the configuration and enables together, making the coreboot chipset device enable callback fail to enable the device, so it gets disabled. The sb900 wrapper appears to fix this issue with cimx setup in early init. You may want to try porting those changes to the sb800. I don't know why it fails later, but I assume it is due to the missing config since you moved the call earlier in the process. You could try calling it multiple times. I'm not sure how it handles that, though. Kerry, Do you have any comments? Marc -- http://se-eng.com

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Issue with CIMX/SB800 PCIe Port Initialization
by Wolfgang Kamp - datakamp 16 Jan '12

16 Jan '12

Hello, I found a problem with the PCI enumeration of the PCIe Ports in the CIMX/SB800 Southbridge for the INAGUA platform. The .../southbridge/amd/cimx/sb800/late.c routine calls the function sb_Before_PCI_Init after case (0x16 >>3) | 2. This means when the PCI Express ports (0x15 <<3) | 0 are probed in the routine ../devices/pci_device.c function pci_probe_dev they are not yet initialized. The probing fails and also devices behind the bridge are not recognized. Behind the PCIe bridge I have an Intel 82574 LAN chip. But if I move the call to sb_Before_PCI_Init behind case (0x15 <<3) | 0 the enumeration succeed but coreboot crashes later into nothing. The Sage Debugger fails. I can't imagine why. Marc have you any idea? Regards Wolfgang

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Trac reminder: list of new ticket(s)
by coreboot tracker 16 Jan '12

16 Jan '12

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Coreboot on P6X58D-E?
by Vincenzo Romano 16 Jan '12

16 Jan '12

Hi all. Is there anyone working on cioreboot for the ASUS P6X58D-E board? TIA.

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Patch set updated for coreboot: c2a8f4b APIC: Fixed reading MSR_FSB_FREQ register
by Vikram Narayanan 14 Jan '12

14 Jan '12

Vikram Narayanan (vikram186(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/507 -gerrit commit c2a8f4b71c767287ab34df8455fc5f3848dcf5c6 Author: Vikram Narayanan <vikram186(a)gmail.com> Date: Sat Jan 14 14:36:51 2012 +0530 APIC: Fixed reading MSR_FSB_FREQ register According to Intel's manual, bits 0:2 of MSR 0xCDh gives the FSB frequency. But the code had a right shift of 4 which will always give 267 MHz, as the valid bits are shifted to right. Change-Id: I6bf93bac1ee9123af78c003f5a0728f8f0801958 Signed-off-by: Vikram Narayanan <vikram186(a)gmail.com> --- src/cpu/x86/lapic/apic_timer.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 826f5b6..0b56fd5 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -28,6 +28,7 @@ */ #define FSB_CLOCK_STS 0xcd +#define FSB_FREQ_MASK 0x07 static u32 timer_fsb = 200; // default to 200MHz @@ -46,7 +47,7 @@ void init_timer(void) /* Set FSB frequency to a reasonable value */ fsb_clock_sts = rdmsr(FSB_CLOCK_STS); - switch ((fsb_clock_sts.lo >> 4) & 0x07) { + switch (fsb_clock_sts.lo & FSB_FREQ_MASK) { case 0: timer_fsb = 266; break; case 1: timer_fsb = 133; break; case 2: timer_fsb = 200; break;

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Patch set updated for coreboot: 419f496 APIC: Fixed reading MSR_FSB_FREQ register
by Vikram Narayanan 14 Jan '12

14 Jan '12

Vikram Narayanan (vikram186(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/507 -gerrit commit 419f496ece1a83a0317d1fa2ec9015a6d9d32a83 Author: Vikram Narayanan <vikram186(a)gmail.com> Date: Mon Dec 26 23:30:23 2011 +0530 APIC: Fixed reading MSR_FSB_FREQ register According to Intel's manual, bits 0:2 of MSR 0xCDh gives the FSB frequency. But the code had a right shift of 4 which will always give 267 MHz, as the valid bits are shifted to right. Also, fixed the indentations. Change-Id: I6bf93bac1ee9123af78c003f5a0728f8f0801958 Signed-off-by: Vikram Narayanan <vikram186(a)gmail.com> --- src/cpu/x86/lapic/apic_timer.c | 31 +++++++++++++++++++++---------- 1 files changed, 21 insertions(+), 10 deletions(-) diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 826f5b6..312951a 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -27,9 +27,10 @@ * memory init. */ -#define FSB_CLOCK_STS 0xcd +#define FSB_CLOCK_STS 0xCD +#define FSB_FREQ_MASK 0x07 -static u32 timer_fsb = 200; // default to 200MHz +static u32 timer_fsb = 200; // default to 200MHz void init_timer(void) { @@ -42,16 +43,26 @@ void init_timer(void) lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1); /* Set the initial counter to 0xffffffff */ - lapic_write(LAPIC_TMICT, 0xffffffff); + lapic_write(LAPIC_TMICT, ~0UL); /* Set FSB frequency to a reasonable value */ fsb_clock_sts = rdmsr(FSB_CLOCK_STS); - switch ((fsb_clock_sts.lo >> 4) & 0x07) { - case 0: timer_fsb = 266; break; - case 1: timer_fsb = 133; break; - case 2: timer_fsb = 200; break; - case 3: timer_fsb = 166; break; - case 5: timer_fsb = 100; break; + switch (fsb_clock_sts.lo & FSB_FREQ_MASK) { + case 0: + timer_fsb = 266; + break; + case 1: + timer_fsb = 133; + break; + case 2: + timer_fsb = 200; + break; + case 3: + timer_fsb = 166; + break; + case 5: + timer_fsb = 100; + break; } } @@ -63,5 +74,5 @@ void udelay(u32 usecs) start = lapic_read(LAPIC_TMCCT); do { value = lapic_read(LAPIC_TMCCT); - } while((start - value) < ticks); + } while ((start - value) < ticks); }

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coreboot January 2012