coreboot September 2011

coreboot@coreboot.org

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224 discussions

New patch to review for coreboot: b6a33d5 sb800: Add sata ahci/raid mode kconfig option
by Kerry Sheh 22 Sep '11

22 Sep '11

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/225 -gerrit commit b6a33d526298aca00643dab79c70631b76749434 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Thu Sep 22 18:52:30 2011 +0800 sb800: Add sata ahci/raid mode kconfig option If sb800 sata was configured as ahci or raid mode, locate the corresponding option rom at site-local directory by default. Change-Id: I87a7814930ce3a7c38cde1e235d151223eea2107 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/southbridge/amd/cimx/sb800/Kconfig | 59 ++++++++++++++++++++++++++++++++ 1 files changed, 59 insertions(+), 0 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 681c881..dc4dd7a 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -28,8 +28,67 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/amd/cimx/sb800/bootblock.c" +choice + prompt "SATA Mode" + default SB800_SATA_IDE + help + Select the mode in which SATA should be driven. NATIVE AHCI, or RAID. + The default is NATIVE. + +config SB800_SATA_IDE + bool "NATIVE" + +config SB800_SATA_AHCI + bool "AHCI" + +config SB800_SATA_RAID + bool "RAID" +endchoice + +config SB800_SATA_MODE + hex + depends on (SB800_SATA_IDE || SB800_SATA_RAID || SB800_SATA_AHCI) + default "0x0" if SB800_SATA_IDE + default "0x1" if SB800_SATA_RAID + default "0x2" if SB800_SATA_AHCI + config SB_SUPERIO_HWM bool default n + +if SB800_SATA_AHCI +config AHCI_ROM_ID + string "AHCI device PCI IDs" + default "1002,4391" + +config AHCI_ROM_FILE + string "AHCI ROM path and filename" + default "site-local/sb800/ahci.bin" +endif + +if SB800_SATA_RAID +config RAID_ROM_ID + string "RAID device PCI IDs" + default "1002,4393" + help + 1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode + +config RAID_ROM_FILE + string "RAID ROM path and filename" + default "site-local/sb800/raid.bin" + +config RAID_MISC_ROM + bool + default y + help + SB800 Promisc RAID Option ROM misc binary + +config RAID_MISC_ROM_FILE + string "RAID Misc ROM path and filename" + default "site-local/sb800/misc.bin" + depends on RAID_MISC_ROM + +endif + endif #SOUTHBRIDGE_AMD_CIMX_SB800

1 0

I want to know if my laptop supports coreboot
by Pedro Armando Ojeda May 22 Sep '11

22 Sep '11

I send you the information requested in the wiki of coreboot.

1 0

Patch merged into coreboot/master: 5dc9abd Use ACPI text fields consistently with all other boards
by gerrit＠coreboot.org 20 Sep '11

20 Sep '11

the following patch was just integrated into master: commit 5dc9abd86cda91a06039fd642dc91f62b74555a7 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Sep 20 22:36:32 2011 +0200 Use ACPI text fields consistently with all other boards LXBIOS and LXB-DSDT are not used in other parts of the tree. Make names consistent across the tree. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: I91caeac09fd2401a36e53bd061d249b236a48e43 See http://review.coreboot.org/224 for details. -gerrit

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Patch set updated for coreboot: 5dc9abd Use ACPI text fields consistently with all other boards
by Stefan Reinauer 20 Sep '11

20 Sep '11

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/224 -gerrit commit 5dc9abd86cda91a06039fd642dc91f62b74555a7 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Sep 20 22:36:32 2011 +0200 Use ACPI text fields consistently with all other boards LXBIOS and LXB-DSDT are not used in other parts of the tree. Make names consistent across the tree. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: I91caeac09fd2401a36e53bd061d249b236a48e43 --- src/mainboard/asus/a8v-e_deluxe/dsdt.asl | 2 +- src/mainboard/asus/a8v-e_se/dsdt.asl | 2 +- src/mainboard/asus/m2v-mx_se/dsdt.asl | 2 +- src/mainboard/getac/p470/fadt.c | 6 +- src/mainboard/gigabyte/m57sli/dsdt.asl | 2 +- src/mainboard/ibase/mb899/fadt.c | 6 +- src/mainboard/intel/d945gclf/fadt.c | 6 +- src/mainboard/intel/eagleheights/fadt.c | 6 +- src/mainboard/iwave/iWRainbowG6/fadt.c | 6 +- src/mainboard/kontron/986lcd-m/fadt.c | 6 +- src/mainboard/lenovo/t60/fadt.c | 6 +- src/mainboard/lenovo/x60/fadt.c | 6 +- src/mainboard/msi/ms9652_fam10/dsdt.asl | 2 +- src/mainboard/roda/rk886ex/fadt.c | 6 +- src/mainboard/via/epia-m/dsdt.asl | 2 +- src/mainboard/via/epia-m/dsdt.c | 142 ------------------------------ src/mainboard/via/epia-m700/fadt.c | 6 +- src/mainboard/via/vt8454c/fadt.c | 6 +- src/southbridge/intel/i82371eb/fadt.c | 6 +- src/southbridge/nvidia/ck804/fadt.c | 6 +- src/southbridge/nvidia/mcp55/fadt.c | 6 +- src/southbridge/via/vt8237r/fadt.c | 6 +- 22 files changed, 51 insertions(+), 193 deletions(-) diff --git a/src/mainboard/asus/a8v-e_deluxe/dsdt.asl b/src/mainboard/asus/a8v-e_deluxe/dsdt.asl index 55226db..6a46102 100644 --- a/src/mainboard/asus/a8v-e_deluxe/dsdt.asl +++ b/src/mainboard/asus/a8v-e_deluxe/dsdt.asl @@ -22,7 +22,7 @@ * ISA portions taken from QEMU acpi-dsdt.dsl. */ -DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) +DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) { /* Define the main processor.*/ Scope (\_PR) diff --git a/src/mainboard/asus/a8v-e_se/dsdt.asl b/src/mainboard/asus/a8v-e_se/dsdt.asl index 55226db..6a46102 100644 --- a/src/mainboard/asus/a8v-e_se/dsdt.asl +++ b/src/mainboard/asus/a8v-e_se/dsdt.asl @@ -22,7 +22,7 @@ * ISA portions taken from QEMU acpi-dsdt.dsl. */ -DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) +DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) { /* Define the main processor.*/ Scope (\_PR) diff --git a/src/mainboard/asus/m2v-mx_se/dsdt.asl b/src/mainboard/asus/m2v-mx_se/dsdt.asl index 1f5027c..5777bd9 100644 --- a/src/mainboard/asus/m2v-mx_se/dsdt.asl +++ b/src/mainboard/asus/m2v-mx_se/dsdt.asl @@ -22,7 +22,7 @@ * ISA portions taken from QEMU acpi-dsdt.dsl. */ -DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) +DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) { #include "northbridge/amd/amdk8/util.asl" diff --git a/src/mainboard/getac/p470/fadt.c b/src/mainboard/getac/p470/fadt.c index 7c9b113..98d7f41 100644 --- a/src/mainboard/getac/p470/fadt.c +++ b/src/mainboard/getac/p470/fadt.c @@ -38,9 +38,9 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); header->revision = 3; - memcpy(header->oem_id, "CORE ", 6); - memcpy(header->oem_table_id, "COREBOOT", 8); - memcpy(header->asl_compiler_id, "CORE", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 1; fadt->firmware_ctrl = (unsigned long) facs; diff --git a/src/mainboard/gigabyte/m57sli/dsdt.asl b/src/mainboard/gigabyte/m57sli/dsdt.asl index 44e9e6b..6a6e2e4 100644 --- a/src/mainboard/gigabyte/m57sli/dsdt.asl +++ b/src/mainboard/gigabyte/m57sli/dsdt.asl @@ -23,7 +23,7 @@ * ISA portions taken from QEMU acpi-dsdt.dsl. */ -DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) +DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) { #include "northbridge/amd/amdk8/util.asl" diff --git a/src/mainboard/ibase/mb899/fadt.c b/src/mainboard/ibase/mb899/fadt.c index 44d4c9b..b55f628 100644 --- a/src/mainboard/ibase/mb899/fadt.c +++ b/src/mainboard/ibase/mb899/fadt.c @@ -31,9 +31,9 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); header->revision = 3; - memcpy(header->oem_id, "CORE ", 6); - memcpy(header->oem_table_id, "COREBOOT", 8); - memcpy(header->asl_compiler_id, "CORE", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 1; fadt->firmware_ctrl = (unsigned long) facs; diff --git a/src/mainboard/intel/d945gclf/fadt.c b/src/mainboard/intel/d945gclf/fadt.c index 1a66eef..bf379cb 100644 --- a/src/mainboard/intel/d945gclf/fadt.c +++ b/src/mainboard/intel/d945gclf/fadt.c @@ -31,9 +31,9 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); header->revision = 3; - memcpy(header->oem_id, "CORE ", 6); - memcpy(header->oem_table_id, "COREBOOT", 8); - memcpy(header->asl_compiler_id, "CORE", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 1; fadt->firmware_ctrl = (unsigned long) facs; diff --git a/src/mainboard/intel/eagleheights/fadt.c b/src/mainboard/intel/eagleheights/fadt.c index 992c318..40be3ea 100644 --- a/src/mainboard/intel/eagleheights/fadt.c +++ b/src/mainboard/intel/eagleheights/fadt.c @@ -58,9 +58,9 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) memcpy(header->signature, "FACP", 4); header->length = 244; header->revision = 3; - memcpy(header->oem_id, "CORE ", 6); - memcpy(header->oem_table_id, "COREBOOT", 8); - memcpy(header->asl_compiler_id, "CORE", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 0; fadt->firmware_ctrl = (unsigned long) facs; diff --git a/src/mainboard/iwave/iWRainbowG6/fadt.c b/src/mainboard/iwave/iWRainbowG6/fadt.c index bc4a0d4..8111672 100644 --- a/src/mainboard/iwave/iWRainbowG6/fadt.c +++ b/src/mainboard/iwave/iWRainbowG6/fadt.c @@ -32,9 +32,9 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); header->revision = 3; - memcpy(header->oem_id, "CORE ", 6); - memcpy(header->oem_table_id, "COREBOOT", 8); - memcpy(header->asl_compiler_id, "CORE", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 1; fadt->firmware_ctrl = (unsigned long)facs; diff --git a/src/mainboard/kontron/986lcd-m/fadt.c b/src/mainboard/kontron/986lcd-m/fadt.c index f945d3f..c7227bf 100644 --- a/src/mainboard/kontron/986lcd-m/fadt.c +++ b/src/mainboard/kontron/986lcd-m/fadt.c @@ -31,9 +31,9 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); header->revision = 3; - memcpy(header->oem_id, "CORE ", 6); - memcpy(header->oem_table_id, "COREBOOT", 8); - memcpy(header->asl_compiler_id, "CORE", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 1; fadt->firmware_ctrl = (unsigned long) facs; diff --git a/src/mainboard/lenovo/t60/fadt.c b/src/mainboard/lenovo/t60/fadt.c index 9f73f9c..3a984b1 100644 --- a/src/mainboard/lenovo/t60/fadt.c +++ b/src/mainboard/lenovo/t60/fadt.c @@ -38,9 +38,9 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); header->revision = 3; - memcpy(header->oem_id, "CORE ", 6); - memcpy(header->oem_table_id, "COREBOOT", 8); - memcpy(header->asl_compiler_id, "CORE", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 0; fadt->firmware_ctrl = (unsigned long) facs; diff --git a/src/mainboard/lenovo/x60/fadt.c b/src/mainboard/lenovo/x60/fadt.c index 9f73f9c..3a984b1 100644 --- a/src/mainboard/lenovo/x60/fadt.c +++ b/src/mainboard/lenovo/x60/fadt.c @@ -38,9 +38,9 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); header->revision = 3; - memcpy(header->oem_id, "CORE ", 6); - memcpy(header->oem_table_id, "COREBOOT", 8); - memcpy(header->asl_compiler_id, "CORE", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 0; fadt->firmware_ctrl = (unsigned long) facs; diff --git a/src/mainboard/msi/ms9652_fam10/dsdt.asl b/src/mainboard/msi/ms9652_fam10/dsdt.asl index c0ed969..fe34112 100644 --- a/src/mainboard/msi/ms9652_fam10/dsdt.asl +++ b/src/mainboard/msi/ms9652_fam10/dsdt.asl @@ -21,7 +21,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) +DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) { #include "../../../../src/northbridge/amd/amdk8/util.asl" diff --git a/src/mainboard/roda/rk886ex/fadt.c b/src/mainboard/roda/rk886ex/fadt.c index b07856a..07b50d8 100644 --- a/src/mainboard/roda/rk886ex/fadt.c +++ b/src/mainboard/roda/rk886ex/fadt.c @@ -33,9 +33,9 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); header->revision = 3; - memcpy(header->oem_id, "CORE ", 6); - memcpy(header->oem_table_id, "COREBOOT", 8); - memcpy(header->asl_compiler_id, "CORE", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 0; fadt->firmware_ctrl = (unsigned long) facs; diff --git a/src/mainboard/via/epia-m/dsdt.asl b/src/mainboard/via/epia-m/dsdt.asl index cbc8d24..edc38bf 100644 --- a/src/mainboard/via/epia-m/dsdt.asl +++ b/src/mainboard/via/epia-m/dsdt.asl @@ -5,7 +5,7 @@ * */ -DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) +DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) { /* * Define the main processor diff --git a/src/mainboard/via/epia-m/dsdt.c b/src/mainboard/via/epia-m/dsdt.c deleted file mode 100644 index ca40651..0000000 --- a/src/mainboard/via/epia-m/dsdt.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * - * Intel ACPI Component Architecture - * ASL Optimizing Compiler version 20060127 [Apr 23 2006] - * Copyright (C) 2000 - 2006 Intel Corporation - * Supports ACPI Specification Revision 3.0a - * - * Compilation of "dsdt.asl" - Wed Sep 6 11:36:08 2006 - * - * C source code output - * - */ -unsigned char AmlCode[] = -{ - 0x44,0x53,0x44,0x54,0xF0,0x03,0x00,0x00, /* 00000000 "DSDT...." */ - 0x01,0x03,0x4C,0x58,0x42,0x49,0x4F,0x53, /* 00000008 "..LXBIOS" */ - 0x4C,0x58,0x42,0x2D,0x44,0x53,0x44,0x54, /* 00000010 "LXB-DSDT" */ - 0x01,0x00,0x00,0x00,0x49,0x4E,0x54,0x4C, /* 00000018 "....INTL" */ - 0x27,0x01,0x06,0x20,0x10,0x12,0x5F,0x50, /* 00000020 "'.. .._P" */ - 0x52,0x5F,0x5B,0x83,0x0B,0x43,0x50,0x55, /* 00000028 "R_[..CPU" */ - 0x30,0x00,0x10,0x04,0x00,0x00,0x06,0x08, /* 00000030 "0......." */ - 0x5F,0x53,0x30,0x5F,0x12,0x06,0x04,0x00, /* 00000038 "_S0_...." */ - 0x00,0x00,0x00,0x08,0x5F,0x53,0x35,0x5F, /* 00000040 "...._S5_" */ - 0x12,0x08,0x04,0x0A,0x02,0x0A,0x02,0x00, /* 00000048 "........" */ - 0x00,0x10,0x4E,0x39,0x5F,0x53,0x42,0x5F, /* 00000050 "..N9_SB_" */ - 0x5B,0x82,0x44,0x06,0x4C,0x4E,0x4B,0x41, /* 00000058 "[.D.LNKA" */ - 0x08,0x5F,0x48,0x49,0x44,0x0C,0x41,0xD0, /* 00000060 "._HID.A." */ - 0x0C,0x0F,0x08,0x5F,0x55,0x49,0x44,0x01, /* 00000068 "..._UID." */ - 0x14,0x09,0x5F,0x53,0x54,0x41,0x00,0xA4, /* 00000070 ".._STA.." */ - 0x0A,0x0B,0x14,0x1A,0x5F,0x43,0x52,0x53, /* 00000078 "...._CRS" */ - 0x00,0x08,0x42,0x55,0x46,0x46,0x11,0x09, /* 00000080 "..BUFF.." */ - 0x0A,0x06,0x23,0x20,0x00,0x18,0x79,0x00, /* 00000088 "..# ..y." */ - 0xA4,0x42,0x55,0x46,0x46,0x14,0x1A,0x5F, /* 00000090 ".BUFF.._" */ - 0x50,0x52,0x53,0x00,0x08,0x42,0x55,0x46, /* 00000098 "PRS..BUF" */ - 0x46,0x11,0x09,0x0A,0x06,0x23,0x20,0x06, /* 000000A0 "F....# ." */ - 0x18,0x79,0x00,0xA4,0x42,0x55,0x46,0x46, /* 000000A8 ".y..BUFF" */ - 0x14,0x06,0x5F,0x53,0x52,0x53,0x01,0x14, /* 000000B0 ".._SRS.." */ - 0x06,0x5F,0x44,0x49,0x53,0x00,0x5B,0x82, /* 000000B8 "._DIS.[." */ - 0x45,0x06,0x4C,0x4E,0x4B,0x42,0x08,0x5F, /* 000000C0 "E.LNKB._" */ - 0x48,0x49,0x44,0x0C,0x41,0xD0,0x0C,0x0F, /* 000000C8 "HID.A..." */ - 0x08,0x5F,0x55,0x49,0x44,0x0A,0x02,0x14, /* 000000D0 "._UID..." */ - 0x09,0x5F,0x53,0x54,0x41,0x00,0xA4,0x0A, /* 000000D8 "._STA..." */ - 0x0B,0x14,0x1A,0x5F,0x43,0x52,0x53,0x00, /* 000000E0 "..._CRS." */ - 0x08,0x42,0x55,0x46,0x46,0x11,0x09,0x0A, /* 000000E8 ".BUFF..." */ - 0x06,0x23,0x00,0x02,0x18,0x79,0x00,0xA4, /* 000000F0 ".#...y.." */ - 0x42,0x55,0x46,0x46,0x14,0x1A,0x5F,0x50, /* 000000F8 "BUFF.._P" */ - 0x52,0x53,0x00,0x08,0x42,0x55,0x46,0x46, /* 00000100 "RS..BUFF" */ - 0x11,0x09,0x0A,0x06,0x23,0x20,0x06,0x18, /* 00000108 "....# .." */ - 0x79,0x00,0xA4,0x42,0x55,0x46,0x46,0x14, /* 00000110 "y..BUFF." */ - 0x06,0x5F,0x53,0x52,0x53,0x01,0x14,0x06, /* 00000118 "._SRS..." */ - 0x5F,0x44,0x49,0x53,0x00,0x5B,0x82,0x45, /* 00000120 "_DIS.[.E" */ - 0x06,0x4C,0x4E,0x4B,0x43,0x08,0x5F,0x48, /* 00000128 ".LNKC._H" */ - 0x49,0x44,0x0C,0x41,0xD0,0x0C,0x0F,0x08, /* 00000130 "ID.A...." */ - 0x5F,0x55,0x49,0x44,0x0A,0x03,0x14,0x09, /* 00000138 "_UID...." */ - 0x5F,0x53,0x54,0x41,0x00,0xA4,0x0A,0x0B, /* 00000140 "_STA...." */ - 0x14,0x1A,0x5F,0x43,0x52,0x53,0x00,0x08, /* 00000148 ".._CRS.." */ - 0x42,0x55,0x46,0x46,0x11,0x09,0x0A,0x06, /* 00000150 "BUFF...." */ - 0x23,0x00,0x02,0x18,0x79,0x00,0xA4,0x42, /* 00000158 "#...y..B" */ - 0x55,0x46,0x46,0x14,0x1A,0x5F,0x50,0x52, /* 00000160 "UFF.._PR" */ - 0x53,0x00,0x08,0x42,0x55,0x46,0x46,0x11, /* 00000168 "S..BUFF." */ - 0x09,0x0A,0x06,0x23,0x20,0x06,0x18,0x79, /* 00000170 "...# ..y" */ - 0x00,0xA4,0x42,0x55,0x46,0x46,0x14,0x06, /* 00000178 "..BUFF.." */ - 0x5F,0x53,0x52,0x53,0x01,0x14,0x06,0x5F, /* 00000180 "_SRS..._" */ - 0x44,0x49,0x53,0x00,0x5B,0x82,0x45,0x06, /* 00000188 "DIS.[.E." */ - 0x4C,0x4E,0x4B,0x44,0x08,0x5F,0x48,0x49, /* 00000190 "LNKD._HI" */ - 0x44,0x0C,0x41,0xD0,0x0C,0x0F,0x08,0x5F, /* 00000198 "D.A...._" */ - 0x55,0x49,0x44,0x0A,0x04,0x14,0x09,0x5F, /* 000001A0 "UID...._" */ - 0x53,0x54,0x41,0x00,0xA4,0x0A,0x0B,0x14, /* 000001A8 "STA....." */ - 0x1A,0x5F,0x43,0x52,0x53,0x00,0x08,0x42, /* 000001B0 "._CRS..B" */ - 0x55,0x46,0x46,0x11,0x09,0x0A,0x06,0x23, /* 000001B8 "UFF....#" */ - 0x20,0x00,0x18,0x79,0x00,0xA4,0x42,0x55, /* 000001C0 " ..y..BU" */ - 0x46,0x46,0x14,0x1A,0x5F,0x50,0x52,0x53, /* 000001C8 "FF.._PRS" */ - 0x00,0x08,0x42,0x55,0x46,0x46,0x11,0x09, /* 000001D0 "..BUFF.." */ - 0x0A,0x06,0x23,0x20,0x06,0x18,0x79,0x00, /* 000001D8 "..# ..y." */ - 0xA4,0x42,0x55,0x46,0x46,0x14,0x06,0x5F, /* 000001E0 ".BUFF.._" */ - 0x53,0x52,0x53,0x01,0x14,0x06,0x5F,0x44, /* 000001E8 "SRS..._D" */ - 0x49,0x53,0x00,0x5B,0x82,0x4B,0x1F,0x50, /* 000001F0 "IS.[.K.P" */ - 0x43,0x49,0x30,0x08,0x5F,0x48,0x49,0x44, /* 000001F8 "CI0._HID" */ - 0x0C,0x41,0xD0,0x0A,0x03,0x08,0x5F,0x41, /* 00000200 ".A...._A" */ - 0x44,0x52,0x00,0x08,0x5F,0x55,0x49,0x44, /* 00000208 "DR.._UID" */ - 0x00,0x08,0x5F,0x42,0x42,0x4E,0x00,0x08, /* 00000210 ".._BBN.." */ - 0x5F,0x50,0x52,0x54,0x12,0x43,0x1D,0x20, /* 00000218 "_PRT.C. " */ - 0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x0A,0x00, /* 00000220 "........" */ - 0x00,0x4C,0x4E,0x4B,0x41,0x00,0x12,0x0D, /* 00000228 ".LNKA..." */ - 0x04,0x0C,0xFF,0xFF,0x0A,0x00,0x01,0x4C, /* 00000230 ".......L" */ - 0x4E,0x4B,0x42,0x00,0x12,0x0E,0x04,0x0C, /* 00000238 "NKB....." */ - 0xFF,0xFF,0x0A,0x00,0x0A,0x02,0x4C,0x4E, /* 00000240 "......LN" */ - 0x4B,0x43,0x00,0x12,0x0E,0x04,0x0C,0xFF, /* 00000248 "KC......" */ - 0xFF,0x0A,0x00,0x0A,0x03,0x4C,0x4E,0x4B, /* 00000250 ".....LNK" */ - 0x44,0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF, /* 00000258 "D......." */ - 0x0D,0x00,0x00,0x4C,0x4E,0x4B,0x42,0x00, /* 00000260 "...LNKB." */ - 0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x0D,0x00, /* 00000268 "........" */ - 0x01,0x4C,0x4E,0x4B,0x43,0x00,0x12,0x0E, /* 00000270 ".LNKC..." */ - 0x04,0x0C,0xFF,0xFF,0x0D,0x00,0x0A,0x02, /* 00000278 "........" */ - 0x4C,0x4E,0x4B,0x44,0x00,0x12,0x0E,0x04, /* 00000280 "LNKD...." */ - 0x0C,0xFF,0xFF,0x0D,0x00,0x0A,0x03,0x4C, /* 00000288 ".......L" */ - 0x4E,0x4B,0x41,0x00,0x12,0x0D,0x04,0x0C, /* 00000290 "NKA....." */ - 0xFF,0xFF,0x10,0x00,0x00,0x4C,0x4E,0x4B, /* 00000298 ".....LNK" */ - 0x41,0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF, /* 000002A0 "A......." */ - 0x10,0x00,0x01,0x4C,0x4E,0x4B,0x42,0x00, /* 000002A8 "...LNKB." */ - 0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x10,0x00, /* 000002B0 "........" */ - 0x0A,0x02,0x4C,0x4E,0x4B,0x43,0x00,0x12, /* 000002B8 "..LNKC.." */ - 0x0E,0x04,0x0C,0xFF,0xFF,0x10,0x00,0x0A, /* 000002C0 "........" */ - 0x03,0x4C,0x4E,0x4B,0x44,0x00,0x12,0x0D, /* 000002C8 ".LNKD..." */ - 0x04,0x0C,0xFF,0xFF,0x11,0x00,0x00,0x4C, /* 000002D0 ".......L" */ - 0x4E,0x4B,0x41,0x00,0x12,0x0D,0x04,0x0C, /* 000002D8 "NKA....." */ - 0xFF,0xFF,0x11,0x00,0x01,0x4C,0x4E,0x4B, /* 000002E0 ".....LNK" */ - 0x42,0x00,0x12,0x0E,0x04,0x0C,0xFF,0xFF, /* 000002E8 "B......." */ - 0x11,0x00,0x0A,0x02,0x4C,0x4E,0x4B,0x43, /* 000002F0 "....LNKC" */ - 0x00,0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x11, /* 000002F8 "........" */ - 0x00,0x0A,0x03,0x4C,0x4E,0x4B,0x44,0x00, /* 00000300 "...LNKD." */ - 0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x12,0x00, /* 00000308 "........" */ - 0x00,0x4C,0x4E,0x4B,0x41,0x00,0x12,0x0D, /* 00000310 ".LNKA..." */ - 0x04,0x0C,0xFF,0xFF,0x12,0x00,0x01,0x4C, /* 00000318 ".......L" */ - 0x4E,0x4B,0x42,0x00,0x12,0x0E,0x04,0x0C, /* 00000320 "NKB....." */ - 0xFF,0xFF,0x12,0x00,0x0A,0x02,0x4C,0x4E, /* 00000328 "......LN" */ - 0x4B,0x43,0x00,0x12,0x0E,0x04,0x0C,0xFF, /* 00000330 "KC......" */ - 0xFF,0x12,0x00,0x0A,0x03,0x4C,0x4E,0x4B, /* 00000338 ".....LNK" */ - 0x44,0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF, /* 00000340 "D......." */ - 0x13,0x00,0x00,0x4C,0x4E,0x4B,0x41,0x00, /* 00000348 "...LNKA." */ - 0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x13,0x00, /* 00000350 "........" */ - 0x01,0x4C,0x4E,0x4B,0x42,0x00,0x12,0x0E, /* 00000358 ".LNKB..." */ - 0x04,0x0C,0xFF,0xFF,0x13,0x00,0x0A,0x02, /* 00000360 "........" */ - 0x4C,0x4E,0x4B,0x43,0x00,0x12,0x0E,0x04, /* 00000368 "LNKC...." */ - 0x0C,0xFF,0xFF,0x13,0x00,0x0A,0x03,0x4C, /* 00000370 ".......L" */ - 0x4E,0x4B,0x44,0x00,0x12,0x0D,0x04,0x0C, /* 00000378 "NKD....." */ - 0xFF,0xFF,0x14,0x00,0x00,0x4C,0x4E,0x4B, /* 00000380 ".....LNK" */ - 0x42,0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF, /* 00000388 "B......." */ - 0x14,0x00,0x01,0x4C,0x4E,0x4B,0x43,0x00, /* 00000390 "...LNKC." */ - 0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x14,0x00, /* 00000398 "........" */ - 0x0A,0x02,0x4C,0x4E,0x4B,0x44,0x00,0x12, /* 000003A0 "..LNKD.." */ - 0x0E,0x04,0x0C,0xFF,0xFF,0x14,0x00,0x0A, /* 000003A8 "........" */ - 0x03,0x4C,0x4E,0x4B,0x41,0x00,0x12,0x0D, /* 000003B0 ".LNKA..." */ - 0x04,0x0C,0xFF,0xFF,0x01,0x00,0x00,0x4C, /* 000003B8 ".......L" */ - 0x4E,0x4B,0x41,0x00,0x12,0x0D,0x04,0x0C, /* 000003C0 "NKA....." */ - 0xFF,0xFF,0x01,0x00,0x01,0x4C,0x4E,0x4B, /* 000003C8 ".....LNK" */ - 0x42,0x00,0x12,0x0E,0x04,0x0C,0xFF,0xFF, /* 000003D0 "B......." */ - 0x01,0x00,0x0A,0x02,0x4C,0x4E,0x4B,0x43, /* 000003D8 "....LNKC" */ - 0x00,0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x01, /* 000003E0 "........" */ - 0x00,0x0A,0x03,0x4C,0x4E,0x4B,0x44,0x00, /* 000003E8 "...LNKD." */ - -}; diff --git a/src/mainboard/via/epia-m700/fadt.c b/src/mainboard/via/epia-m700/fadt.c index 7ba1040..7a1d944 100644 --- a/src/mainboard/via/epia-m700/fadt.c +++ b/src/mainboard/via/epia-m700/fadt.c @@ -31,9 +31,9 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) memcpy(header->signature, "FACP", 4); header->length = 244; header->revision = 3; - memcpy(header->oem_id, "VX800 ", 6); - memcpy(header->oem_table_id, "LNXBACPI", 8); - memcpy(header->asl_compiler_id, "LXB", 8); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 0; fadt->firmware_ctrl = (u32)facs; diff --git a/src/mainboard/via/vt8454c/fadt.c b/src/mainboard/via/vt8454c/fadt.c index 0b720b5..a420010 100644 --- a/src/mainboard/via/vt8454c/fadt.c +++ b/src/mainboard/via/vt8454c/fadt.c @@ -30,9 +30,9 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) memcpy(header->signature, "FACP", 4); header->length = 244; header->revision = 3; - memcpy(header->oem_id, "CX700 ", 6); - memcpy(header->oem_table_id, "COREBOOT", 8); - memcpy(header->asl_compiler_id, "CORE", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 0; fadt->firmware_ctrl = (unsigned long) facs; diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index 5891440..ea6baef 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -45,9 +45,9 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) memcpy(header->signature, "FACP", 4); header->length = 244; header->revision = 1; - memcpy(header->oem_id, "CORE ", 6); - memcpy(header->oem_table_id, "COREBOOT", 8); - memcpy(header->asl_compiler_id, "CORE", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 42; fadt->firmware_ctrl = (u32)facs; diff --git a/src/southbridge/nvidia/ck804/fadt.c b/src/southbridge/nvidia/ck804/fadt.c index a315a32..3a0e926 100644 --- a/src/southbridge/nvidia/ck804/fadt.c +++ b/src/southbridge/nvidia/ck804/fadt.c @@ -25,9 +25,9 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) header->length = 0x74; header->revision = 1; #endif - memcpy(header->oem_id, "CORE ", 6); - memcpy(header->oem_table_id, "CB-FADT ", 8); - memcpy(header->asl_compiler_id, "IASL", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 0; fadt->firmware_ctrl = (u32)facs; diff --git a/src/southbridge/nvidia/mcp55/fadt.c b/src/southbridge/nvidia/mcp55/fadt.c index 753a663..e69172a 100644 --- a/src/southbridge/nvidia/mcp55/fadt.c +++ b/src/southbridge/nvidia/mcp55/fadt.c @@ -44,9 +44,9 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); header->revision = 1; - memcpy(header->oem_id, "GBT", 6); - memcpy(header->oem_table_id, "COREBOOT ", 8); - memcpy(header->asl_compiler_id, "CORE", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 42; printk(BIOS_INFO, "ACPI: pm_base: %u...\n", pm_base); diff --git a/src/southbridge/via/vt8237r/fadt.c b/src/southbridge/via/vt8237r/fadt.c index 6976f4d..dcb6689 100644 --- a/src/southbridge/via/vt8237r/fadt.c +++ b/src/southbridge/via/vt8237r/fadt.c @@ -46,9 +46,9 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) memcpy(header->signature, "FACP", 4); header->length = 244; header->revision = 4; - memcpy(header->oem_id, "COREBO", 6); - memcpy(header->oem_table_id, "COREBOOT", 8); - memcpy(header->asl_compiler_id, "CORE", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 42; fadt->firmware_ctrl = (u32)facs;

1 0

New patch to review for coreboot: cab7f66 Use ACPI text fields consistently with all other boards
by Stefan Reinauer 20 Sep '11

20 Sep '11

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/224 -gerrit commit cab7f6622f9d73aa3cb37e03d6cf9b39df5b56d7 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Sep 20 22:36:32 2011 +0200 Use ACPI text fields consistently with all other boards LXBIOS and LXB-DSDT are not used in other parts of the tree. Make names consistent across the tree. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: I91caeac09fd2401a36e53bd061d249b236a48e43 --- src/mainboard/asus/a8v-e_deluxe/dsdt.asl | 2 +- src/mainboard/asus/a8v-e_se/dsdt.asl | 2 +- src/mainboard/asus/m2v-mx_se/dsdt.asl | 2 +- src/mainboard/getac/p470/fadt.c | 6 +- src/mainboard/gigabyte/m57sli/dsdt.asl | 2 +- src/mainboard/ibase/mb899/fadt.c | 6 +- src/mainboard/intel/d945gclf/fadt.c | 6 +- src/mainboard/intel/eagleheights/fadt.c | 6 +- src/mainboard/iwave/iWRainbowG6/fadt.c | 6 +- src/mainboard/kontron/986lcd-m/fadt.c | 6 +- src/mainboard/lenovo/t60/fadt.c | 6 +- src/mainboard/lenovo/x60/fadt.c | 6 +- src/mainboard/msi/ms9652_fam10/dsdt.asl | 2 +- src/mainboard/roda/rk886ex/fadt.c | 6 +- src/mainboard/via/epia-m/dsdt.asl | 2 +- src/mainboard/via/epia-m/dsdt.c | 142 ------------------------------ src/mainboard/via/epia-m700/fadt.c | 6 +- src/mainboard/via/vt8454c/fadt.c | 6 +- src/southbridge/intel/i82371eb/fadt.c | 6 +- src/southbridge/nvidia/ck804/fadt.c | 6 +- src/southbridge/nvidia/mcp55/fadt.c | 6 +- src/southbridge/via/vt8237r/fadt.c | 6 +- 22 files changed, 51 insertions(+), 193 deletions(-) diff --git a/src/mainboard/asus/a8v-e_deluxe/dsdt.asl b/src/mainboard/asus/a8v-e_deluxe/dsdt.asl index 55226db..6a46102 100644 --- a/src/mainboard/asus/a8v-e_deluxe/dsdt.asl +++ b/src/mainboard/asus/a8v-e_deluxe/dsdt.asl @@ -22,7 +22,7 @@ * ISA portions taken from QEMU acpi-dsdt.dsl. */ -DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) +DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) { /* Define the main processor.*/ Scope (\_PR) diff --git a/src/mainboard/asus/a8v-e_se/dsdt.asl b/src/mainboard/asus/a8v-e_se/dsdt.asl index 55226db..6a46102 100644 --- a/src/mainboard/asus/a8v-e_se/dsdt.asl +++ b/src/mainboard/asus/a8v-e_se/dsdt.asl @@ -22,7 +22,7 @@ * ISA portions taken from QEMU acpi-dsdt.dsl. */ -DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) +DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) { /* Define the main processor.*/ Scope (\_PR) diff --git a/src/mainboard/asus/m2v-mx_se/dsdt.asl b/src/mainboard/asus/m2v-mx_se/dsdt.asl index 1f5027c..5777bd9 100644 --- a/src/mainboard/asus/m2v-mx_se/dsdt.asl +++ b/src/mainboard/asus/m2v-mx_se/dsdt.asl @@ -22,7 +22,7 @@ * ISA portions taken from QEMU acpi-dsdt.dsl. */ -DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) +DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) { #include "northbridge/amd/amdk8/util.asl" diff --git a/src/mainboard/getac/p470/fadt.c b/src/mainboard/getac/p470/fadt.c index 7c9b113..cb65c53 100644 --- a/src/mainboard/getac/p470/fadt.c +++ b/src/mainboard/getac/p470/fadt.c @@ -38,9 +38,9 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); header->revision = 3; - memcpy(header->oem_id, "CORE ", 6); - memcpy(header->oem_table_id, "COREBOOT", 8); - memcpy(header->asl_compiler_id, "CORE", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, OEM_TABLE_ID, 8); + memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 1; fadt->firmware_ctrl = (unsigned long) facs; diff --git a/src/mainboard/gigabyte/m57sli/dsdt.asl b/src/mainboard/gigabyte/m57sli/dsdt.asl index 44e9e6b..6a6e2e4 100644 --- a/src/mainboard/gigabyte/m57sli/dsdt.asl +++ b/src/mainboard/gigabyte/m57sli/dsdt.asl @@ -23,7 +23,7 @@ * ISA portions taken from QEMU acpi-dsdt.dsl. */ -DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) +DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) { #include "northbridge/amd/amdk8/util.asl" diff --git a/src/mainboard/ibase/mb899/fadt.c b/src/mainboard/ibase/mb899/fadt.c index 44d4c9b..2396224 100644 --- a/src/mainboard/ibase/mb899/fadt.c +++ b/src/mainboard/ibase/mb899/fadt.c @@ -31,9 +31,9 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); header->revision = 3; - memcpy(header->oem_id, "CORE ", 6); - memcpy(header->oem_table_id, "COREBOOT", 8); - memcpy(header->asl_compiler_id, "CORE", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, OEM_TABLE_ID, 8); + memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 1; fadt->firmware_ctrl = (unsigned long) facs; diff --git a/src/mainboard/intel/d945gclf/fadt.c b/src/mainboard/intel/d945gclf/fadt.c index 1a66eef..9328823 100644 --- a/src/mainboard/intel/d945gclf/fadt.c +++ b/src/mainboard/intel/d945gclf/fadt.c @@ -31,9 +31,9 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); header->revision = 3; - memcpy(header->oem_id, "CORE ", 6); - memcpy(header->oem_table_id, "COREBOOT", 8); - memcpy(header->asl_compiler_id, "CORE", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, OEM_TABLE_ID, 8); + memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 1; fadt->firmware_ctrl = (unsigned long) facs; diff --git a/src/mainboard/intel/eagleheights/fadt.c b/src/mainboard/intel/eagleheights/fadt.c index 992c318..7c7cfe0 100644 --- a/src/mainboard/intel/eagleheights/fadt.c +++ b/src/mainboard/intel/eagleheights/fadt.c @@ -58,9 +58,9 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) memcpy(header->signature, "FACP", 4); header->length = 244; header->revision = 3; - memcpy(header->oem_id, "CORE ", 6); - memcpy(header->oem_table_id, "COREBOOT", 8); - memcpy(header->asl_compiler_id, "CORE", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, OEM_TABLE_ID, 8); + memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 0; fadt->firmware_ctrl = (unsigned long) facs; diff --git a/src/mainboard/iwave/iWRainbowG6/fadt.c b/src/mainboard/iwave/iWRainbowG6/fadt.c index bc4a0d4..cb68d32 100644 --- a/src/mainboard/iwave/iWRainbowG6/fadt.c +++ b/src/mainboard/iwave/iWRainbowG6/fadt.c @@ -32,9 +32,9 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); header->revision = 3; - memcpy(header->oem_id, "CORE ", 6); - memcpy(header->oem_table_id, "COREBOOT", 8); - memcpy(header->asl_compiler_id, "CORE", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, OEM_TABLE_ID, 8); + memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 1; fadt->firmware_ctrl = (unsigned long)facs; diff --git a/src/mainboard/kontron/986lcd-m/fadt.c b/src/mainboard/kontron/986lcd-m/fadt.c index f945d3f..9a2bbaf 100644 --- a/src/mainboard/kontron/986lcd-m/fadt.c +++ b/src/mainboard/kontron/986lcd-m/fadt.c @@ -31,9 +31,9 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); header->revision = 3; - memcpy(header->oem_id, "CORE ", 6); - memcpy(header->oem_table_id, "COREBOOT", 8); - memcpy(header->asl_compiler_id, "CORE", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, OEM_TABLE_ID, 8); + memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 1; fadt->firmware_ctrl = (unsigned long) facs; diff --git a/src/mainboard/lenovo/t60/fadt.c b/src/mainboard/lenovo/t60/fadt.c index 9f73f9c..2f7301a 100644 --- a/src/mainboard/lenovo/t60/fadt.c +++ b/src/mainboard/lenovo/t60/fadt.c @@ -38,9 +38,9 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); header->revision = 3; - memcpy(header->oem_id, "CORE ", 6); - memcpy(header->oem_table_id, "COREBOOT", 8); - memcpy(header->asl_compiler_id, "CORE", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, OEM_TABLE_ID, 8); + memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 0; fadt->firmware_ctrl = (unsigned long) facs; diff --git a/src/mainboard/lenovo/x60/fadt.c b/src/mainboard/lenovo/x60/fadt.c index 9f73f9c..2f7301a 100644 --- a/src/mainboard/lenovo/x60/fadt.c +++ b/src/mainboard/lenovo/x60/fadt.c @@ -38,9 +38,9 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); header->revision = 3; - memcpy(header->oem_id, "CORE ", 6); - memcpy(header->oem_table_id, "COREBOOT", 8); - memcpy(header->asl_compiler_id, "CORE", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, OEM_TABLE_ID, 8); + memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 0; fadt->firmware_ctrl = (unsigned long) facs; diff --git a/src/mainboard/msi/ms9652_fam10/dsdt.asl b/src/mainboard/msi/ms9652_fam10/dsdt.asl index c0ed969..fe34112 100644 --- a/src/mainboard/msi/ms9652_fam10/dsdt.asl +++ b/src/mainboard/msi/ms9652_fam10/dsdt.asl @@ -21,7 +21,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) +DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) { #include "../../../../src/northbridge/amd/amdk8/util.asl" diff --git a/src/mainboard/roda/rk886ex/fadt.c b/src/mainboard/roda/rk886ex/fadt.c index b07856a..e76f361 100644 --- a/src/mainboard/roda/rk886ex/fadt.c +++ b/src/mainboard/roda/rk886ex/fadt.c @@ -33,9 +33,9 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); header->revision = 3; - memcpy(header->oem_id, "CORE ", 6); - memcpy(header->oem_table_id, "COREBOOT", 8); - memcpy(header->asl_compiler_id, "CORE", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, OEM_TABLE_ID, 8); + memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 0; fadt->firmware_ctrl = (unsigned long) facs; diff --git a/src/mainboard/via/epia-m/dsdt.asl b/src/mainboard/via/epia-m/dsdt.asl index cbc8d24..edc38bf 100644 --- a/src/mainboard/via/epia-m/dsdt.asl +++ b/src/mainboard/via/epia-m/dsdt.asl @@ -5,7 +5,7 @@ * */ -DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) +DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) { /* * Define the main processor diff --git a/src/mainboard/via/epia-m/dsdt.c b/src/mainboard/via/epia-m/dsdt.c deleted file mode 100644 index ca40651..0000000 --- a/src/mainboard/via/epia-m/dsdt.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * - * Intel ACPI Component Architecture - * ASL Optimizing Compiler version 20060127 [Apr 23 2006] - * Copyright (C) 2000 - 2006 Intel Corporation - * Supports ACPI Specification Revision 3.0a - * - * Compilation of "dsdt.asl" - Wed Sep 6 11:36:08 2006 - * - * C source code output - * - */ -unsigned char AmlCode[] = -{ - 0x44,0x53,0x44,0x54,0xF0,0x03,0x00,0x00, /* 00000000 "DSDT...." */ - 0x01,0x03,0x4C,0x58,0x42,0x49,0x4F,0x53, /* 00000008 "..LXBIOS" */ - 0x4C,0x58,0x42,0x2D,0x44,0x53,0x44,0x54, /* 00000010 "LXB-DSDT" */ - 0x01,0x00,0x00,0x00,0x49,0x4E,0x54,0x4C, /* 00000018 "....INTL" */ - 0x27,0x01,0x06,0x20,0x10,0x12,0x5F,0x50, /* 00000020 "'.. .._P" */ - 0x52,0x5F,0x5B,0x83,0x0B,0x43,0x50,0x55, /* 00000028 "R_[..CPU" */ - 0x30,0x00,0x10,0x04,0x00,0x00,0x06,0x08, /* 00000030 "0......." */ - 0x5F,0x53,0x30,0x5F,0x12,0x06,0x04,0x00, /* 00000038 "_S0_...." */ - 0x00,0x00,0x00,0x08,0x5F,0x53,0x35,0x5F, /* 00000040 "...._S5_" */ - 0x12,0x08,0x04,0x0A,0x02,0x0A,0x02,0x00, /* 00000048 "........" */ - 0x00,0x10,0x4E,0x39,0x5F,0x53,0x42,0x5F, /* 00000050 "..N9_SB_" */ - 0x5B,0x82,0x44,0x06,0x4C,0x4E,0x4B,0x41, /* 00000058 "[.D.LNKA" */ - 0x08,0x5F,0x48,0x49,0x44,0x0C,0x41,0xD0, /* 00000060 "._HID.A." */ - 0x0C,0x0F,0x08,0x5F,0x55,0x49,0x44,0x01, /* 00000068 "..._UID." */ - 0x14,0x09,0x5F,0x53,0x54,0x41,0x00,0xA4, /* 00000070 ".._STA.." */ - 0x0A,0x0B,0x14,0x1A,0x5F,0x43,0x52,0x53, /* 00000078 "...._CRS" */ - 0x00,0x08,0x42,0x55,0x46,0x46,0x11,0x09, /* 00000080 "..BUFF.." */ - 0x0A,0x06,0x23,0x20,0x00,0x18,0x79,0x00, /* 00000088 "..# ..y." */ - 0xA4,0x42,0x55,0x46,0x46,0x14,0x1A,0x5F, /* 00000090 ".BUFF.._" */ - 0x50,0x52,0x53,0x00,0x08,0x42,0x55,0x46, /* 00000098 "PRS..BUF" */ - 0x46,0x11,0x09,0x0A,0x06,0x23,0x20,0x06, /* 000000A0 "F....# ." */ - 0x18,0x79,0x00,0xA4,0x42,0x55,0x46,0x46, /* 000000A8 ".y..BUFF" */ - 0x14,0x06,0x5F,0x53,0x52,0x53,0x01,0x14, /* 000000B0 ".._SRS.." */ - 0x06,0x5F,0x44,0x49,0x53,0x00,0x5B,0x82, /* 000000B8 "._DIS.[." */ - 0x45,0x06,0x4C,0x4E,0x4B,0x42,0x08,0x5F, /* 000000C0 "E.LNKB._" */ - 0x48,0x49,0x44,0x0C,0x41,0xD0,0x0C,0x0F, /* 000000C8 "HID.A..." */ - 0x08,0x5F,0x55,0x49,0x44,0x0A,0x02,0x14, /* 000000D0 "._UID..." */ - 0x09,0x5F,0x53,0x54,0x41,0x00,0xA4,0x0A, /* 000000D8 "._STA..." */ - 0x0B,0x14,0x1A,0x5F,0x43,0x52,0x53,0x00, /* 000000E0 "..._CRS." */ - 0x08,0x42,0x55,0x46,0x46,0x11,0x09,0x0A, /* 000000E8 ".BUFF..." */ - 0x06,0x23,0x00,0x02,0x18,0x79,0x00,0xA4, /* 000000F0 ".#...y.." */ - 0x42,0x55,0x46,0x46,0x14,0x1A,0x5F,0x50, /* 000000F8 "BUFF.._P" */ - 0x52,0x53,0x00,0x08,0x42,0x55,0x46,0x46, /* 00000100 "RS..BUFF" */ - 0x11,0x09,0x0A,0x06,0x23,0x20,0x06,0x18, /* 00000108 "....# .." */ - 0x79,0x00,0xA4,0x42,0x55,0x46,0x46,0x14, /* 00000110 "y..BUFF." */ - 0x06,0x5F,0x53,0x52,0x53,0x01,0x14,0x06, /* 00000118 "._SRS..." */ - 0x5F,0x44,0x49,0x53,0x00,0x5B,0x82,0x45, /* 00000120 "_DIS.[.E" */ - 0x06,0x4C,0x4E,0x4B,0x43,0x08,0x5F,0x48, /* 00000128 ".LNKC._H" */ - 0x49,0x44,0x0C,0x41,0xD0,0x0C,0x0F,0x08, /* 00000130 "ID.A...." */ - 0x5F,0x55,0x49,0x44,0x0A,0x03,0x14,0x09, /* 00000138 "_UID...." */ - 0x5F,0x53,0x54,0x41,0x00,0xA4,0x0A,0x0B, /* 00000140 "_STA...." */ - 0x14,0x1A,0x5F,0x43,0x52,0x53,0x00,0x08, /* 00000148 ".._CRS.." */ - 0x42,0x55,0x46,0x46,0x11,0x09,0x0A,0x06, /* 00000150 "BUFF...." */ - 0x23,0x00,0x02,0x18,0x79,0x00,0xA4,0x42, /* 00000158 "#...y..B" */ - 0x55,0x46,0x46,0x14,0x1A,0x5F,0x50,0x52, /* 00000160 "UFF.._PR" */ - 0x53,0x00,0x08,0x42,0x55,0x46,0x46,0x11, /* 00000168 "S..BUFF." */ - 0x09,0x0A,0x06,0x23,0x20,0x06,0x18,0x79, /* 00000170 "...# ..y" */ - 0x00,0xA4,0x42,0x55,0x46,0x46,0x14,0x06, /* 00000178 "..BUFF.." */ - 0x5F,0x53,0x52,0x53,0x01,0x14,0x06,0x5F, /* 00000180 "_SRS..._" */ - 0x44,0x49,0x53,0x00,0x5B,0x82,0x45,0x06, /* 00000188 "DIS.[.E." */ - 0x4C,0x4E,0x4B,0x44,0x08,0x5F,0x48,0x49, /* 00000190 "LNKD._HI" */ - 0x44,0x0C,0x41,0xD0,0x0C,0x0F,0x08,0x5F, /* 00000198 "D.A...._" */ - 0x55,0x49,0x44,0x0A,0x04,0x14,0x09,0x5F, /* 000001A0 "UID...._" */ - 0x53,0x54,0x41,0x00,0xA4,0x0A,0x0B,0x14, /* 000001A8 "STA....." */ - 0x1A,0x5F,0x43,0x52,0x53,0x00,0x08,0x42, /* 000001B0 "._CRS..B" */ - 0x55,0x46,0x46,0x11,0x09,0x0A,0x06,0x23, /* 000001B8 "UFF....#" */ - 0x20,0x00,0x18,0x79,0x00,0xA4,0x42,0x55, /* 000001C0 " ..y..BU" */ - 0x46,0x46,0x14,0x1A,0x5F,0x50,0x52,0x53, /* 000001C8 "FF.._PRS" */ - 0x00,0x08,0x42,0x55,0x46,0x46,0x11,0x09, /* 000001D0 "..BUFF.." */ - 0x0A,0x06,0x23,0x20,0x06,0x18,0x79,0x00, /* 000001D8 "..# ..y." */ - 0xA4,0x42,0x55,0x46,0x46,0x14,0x06,0x5F, /* 000001E0 ".BUFF.._" */ - 0x53,0x52,0x53,0x01,0x14,0x06,0x5F,0x44, /* 000001E8 "SRS..._D" */ - 0x49,0x53,0x00,0x5B,0x82,0x4B,0x1F,0x50, /* 000001F0 "IS.[.K.P" */ - 0x43,0x49,0x30,0x08,0x5F,0x48,0x49,0x44, /* 000001F8 "CI0._HID" */ - 0x0C,0x41,0xD0,0x0A,0x03,0x08,0x5F,0x41, /* 00000200 ".A...._A" */ - 0x44,0x52,0x00,0x08,0x5F,0x55,0x49,0x44, /* 00000208 "DR.._UID" */ - 0x00,0x08,0x5F,0x42,0x42,0x4E,0x00,0x08, /* 00000210 ".._BBN.." */ - 0x5F,0x50,0x52,0x54,0x12,0x43,0x1D,0x20, /* 00000218 "_PRT.C. " */ - 0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x0A,0x00, /* 00000220 "........" */ - 0x00,0x4C,0x4E,0x4B,0x41,0x00,0x12,0x0D, /* 00000228 ".LNKA..." */ - 0x04,0x0C,0xFF,0xFF,0x0A,0x00,0x01,0x4C, /* 00000230 ".......L" */ - 0x4E,0x4B,0x42,0x00,0x12,0x0E,0x04,0x0C, /* 00000238 "NKB....." */ - 0xFF,0xFF,0x0A,0x00,0x0A,0x02,0x4C,0x4E, /* 00000240 "......LN" */ - 0x4B,0x43,0x00,0x12,0x0E,0x04,0x0C,0xFF, /* 00000248 "KC......" */ - 0xFF,0x0A,0x00,0x0A,0x03,0x4C,0x4E,0x4B, /* 00000250 ".....LNK" */ - 0x44,0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF, /* 00000258 "D......." */ - 0x0D,0x00,0x00,0x4C,0x4E,0x4B,0x42,0x00, /* 00000260 "...LNKB." */ - 0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x0D,0x00, /* 00000268 "........" */ - 0x01,0x4C,0x4E,0x4B,0x43,0x00,0x12,0x0E, /* 00000270 ".LNKC..." */ - 0x04,0x0C,0xFF,0xFF,0x0D,0x00,0x0A,0x02, /* 00000278 "........" */ - 0x4C,0x4E,0x4B,0x44,0x00,0x12,0x0E,0x04, /* 00000280 "LNKD...." */ - 0x0C,0xFF,0xFF,0x0D,0x00,0x0A,0x03,0x4C, /* 00000288 ".......L" */ - 0x4E,0x4B,0x41,0x00,0x12,0x0D,0x04,0x0C, /* 00000290 "NKA....." */ - 0xFF,0xFF,0x10,0x00,0x00,0x4C,0x4E,0x4B, /* 00000298 ".....LNK" */ - 0x41,0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF, /* 000002A0 "A......." */ - 0x10,0x00,0x01,0x4C,0x4E,0x4B,0x42,0x00, /* 000002A8 "...LNKB." */ - 0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x10,0x00, /* 000002B0 "........" */ - 0x0A,0x02,0x4C,0x4E,0x4B,0x43,0x00,0x12, /* 000002B8 "..LNKC.." */ - 0x0E,0x04,0x0C,0xFF,0xFF,0x10,0x00,0x0A, /* 000002C0 "........" */ - 0x03,0x4C,0x4E,0x4B,0x44,0x00,0x12,0x0D, /* 000002C8 ".LNKD..." */ - 0x04,0x0C,0xFF,0xFF,0x11,0x00,0x00,0x4C, /* 000002D0 ".......L" */ - 0x4E,0x4B,0x41,0x00,0x12,0x0D,0x04,0x0C, /* 000002D8 "NKA....." */ - 0xFF,0xFF,0x11,0x00,0x01,0x4C,0x4E,0x4B, /* 000002E0 ".....LNK" */ - 0x42,0x00,0x12,0x0E,0x04,0x0C,0xFF,0xFF, /* 000002E8 "B......." */ - 0x11,0x00,0x0A,0x02,0x4C,0x4E,0x4B,0x43, /* 000002F0 "....LNKC" */ - 0x00,0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x11, /* 000002F8 "........" */ - 0x00,0x0A,0x03,0x4C,0x4E,0x4B,0x44,0x00, /* 00000300 "...LNKD." */ - 0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x12,0x00, /* 00000308 "........" */ - 0x00,0x4C,0x4E,0x4B,0x41,0x00,0x12,0x0D, /* 00000310 ".LNKA..." */ - 0x04,0x0C,0xFF,0xFF,0x12,0x00,0x01,0x4C, /* 00000318 ".......L" */ - 0x4E,0x4B,0x42,0x00,0x12,0x0E,0x04,0x0C, /* 00000320 "NKB....." */ - 0xFF,0xFF,0x12,0x00,0x0A,0x02,0x4C,0x4E, /* 00000328 "......LN" */ - 0x4B,0x43,0x00,0x12,0x0E,0x04,0x0C,0xFF, /* 00000330 "KC......" */ - 0xFF,0x12,0x00,0x0A,0x03,0x4C,0x4E,0x4B, /* 00000338 ".....LNK" */ - 0x44,0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF, /* 00000340 "D......." */ - 0x13,0x00,0x00,0x4C,0x4E,0x4B,0x41,0x00, /* 00000348 "...LNKA." */ - 0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x13,0x00, /* 00000350 "........" */ - 0x01,0x4C,0x4E,0x4B,0x42,0x00,0x12,0x0E, /* 00000358 ".LNKB..." */ - 0x04,0x0C,0xFF,0xFF,0x13,0x00,0x0A,0x02, /* 00000360 "........" */ - 0x4C,0x4E,0x4B,0x43,0x00,0x12,0x0E,0x04, /* 00000368 "LNKC...." */ - 0x0C,0xFF,0xFF,0x13,0x00,0x0A,0x03,0x4C, /* 00000370 ".......L" */ - 0x4E,0x4B,0x44,0x00,0x12,0x0D,0x04,0x0C, /* 00000378 "NKD....." */ - 0xFF,0xFF,0x14,0x00,0x00,0x4C,0x4E,0x4B, /* 00000380 ".....LNK" */ - 0x42,0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF, /* 00000388 "B......." */ - 0x14,0x00,0x01,0x4C,0x4E,0x4B,0x43,0x00, /* 00000390 "...LNKC." */ - 0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x14,0x00, /* 00000398 "........" */ - 0x0A,0x02,0x4C,0x4E,0x4B,0x44,0x00,0x12, /* 000003A0 "..LNKD.." */ - 0x0E,0x04,0x0C,0xFF,0xFF,0x14,0x00,0x0A, /* 000003A8 "........" */ - 0x03,0x4C,0x4E,0x4B,0x41,0x00,0x12,0x0D, /* 000003B0 ".LNKA..." */ - 0x04,0x0C,0xFF,0xFF,0x01,0x00,0x00,0x4C, /* 000003B8 ".......L" */ - 0x4E,0x4B,0x41,0x00,0x12,0x0D,0x04,0x0C, /* 000003C0 "NKA....." */ - 0xFF,0xFF,0x01,0x00,0x01,0x4C,0x4E,0x4B, /* 000003C8 ".....LNK" */ - 0x42,0x00,0x12,0x0E,0x04,0x0C,0xFF,0xFF, /* 000003D0 "B......." */ - 0x01,0x00,0x0A,0x02,0x4C,0x4E,0x4B,0x43, /* 000003D8 "....LNKC" */ - 0x00,0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x01, /* 000003E0 "........" */ - 0x00,0x0A,0x03,0x4C,0x4E,0x4B,0x44,0x00, /* 000003E8 "...LNKD." */ - -}; diff --git a/src/mainboard/via/epia-m700/fadt.c b/src/mainboard/via/epia-m700/fadt.c index 7ba1040..04f4097 100644 --- a/src/mainboard/via/epia-m700/fadt.c +++ b/src/mainboard/via/epia-m700/fadt.c @@ -31,9 +31,9 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) memcpy(header->signature, "FACP", 4); header->length = 244; header->revision = 3; - memcpy(header->oem_id, "VX800 ", 6); - memcpy(header->oem_table_id, "LNXBACPI", 8); - memcpy(header->asl_compiler_id, "LXB", 8); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, OEM_TABLE_ID, 8); + memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 0; fadt->firmware_ctrl = (u32)facs; diff --git a/src/mainboard/via/vt8454c/fadt.c b/src/mainboard/via/vt8454c/fadt.c index 0b720b5..5c15c01 100644 --- a/src/mainboard/via/vt8454c/fadt.c +++ b/src/mainboard/via/vt8454c/fadt.c @@ -30,9 +30,9 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) memcpy(header->signature, "FACP", 4); header->length = 244; header->revision = 3; - memcpy(header->oem_id, "CX700 ", 6); - memcpy(header->oem_table_id, "COREBOOT", 8); - memcpy(header->asl_compiler_id, "CORE", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, OEM_TABLE_ID, 8); + memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 0; fadt->firmware_ctrl = (unsigned long) facs; diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index 5891440..f46fb35 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -45,9 +45,9 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) memcpy(header->signature, "FACP", 4); header->length = 244; header->revision = 1; - memcpy(header->oem_id, "CORE ", 6); - memcpy(header->oem_table_id, "COREBOOT", 8); - memcpy(header->asl_compiler_id, "CORE", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, OEM_TABLE_ID, 8); + memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 42; fadt->firmware_ctrl = (u32)facs; diff --git a/src/southbridge/nvidia/ck804/fadt.c b/src/southbridge/nvidia/ck804/fadt.c index a315a32..6212e39 100644 --- a/src/southbridge/nvidia/ck804/fadt.c +++ b/src/southbridge/nvidia/ck804/fadt.c @@ -25,9 +25,9 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) header->length = 0x74; header->revision = 1; #endif - memcpy(header->oem_id, "CORE ", 6); - memcpy(header->oem_table_id, "CB-FADT ", 8); - memcpy(header->asl_compiler_id, "IASL", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, OEM_TABLE_ID, 8); + memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 0; fadt->firmware_ctrl = (u32)facs; diff --git a/src/southbridge/nvidia/mcp55/fadt.c b/src/southbridge/nvidia/mcp55/fadt.c index 753a663..b429a29 100644 --- a/src/southbridge/nvidia/mcp55/fadt.c +++ b/src/southbridge/nvidia/mcp55/fadt.c @@ -44,9 +44,9 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); header->revision = 1; - memcpy(header->oem_id, "GBT", 6); - memcpy(header->oem_table_id, "COREBOOT ", 8); - memcpy(header->asl_compiler_id, "CORE", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, OEM_TABLE_ID, 8); + memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 42; printk(BIOS_INFO, "ACPI: pm_base: %u...\n", pm_base); diff --git a/src/southbridge/via/vt8237r/fadt.c b/src/southbridge/via/vt8237r/fadt.c index 6976f4d..4b983dd 100644 --- a/src/southbridge/via/vt8237r/fadt.c +++ b/src/southbridge/via/vt8237r/fadt.c @@ -46,9 +46,9 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) memcpy(header->signature, "FACP", 4); header->length = 244; header->revision = 4; - memcpy(header->oem_id, "COREBO", 6); - memcpy(header->oem_table_id, "COREBOOT", 8); - memcpy(header->asl_compiler_id, "CORE", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, OEM_TABLE_ID, 8); + memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 42; fadt->firmware_ctrl = (u32)facs;

1 0

880G Device ID
by QingPei Wang 20 Sep '11

20 Sep '11

hi all, since AMD 880G have a Device ID 0x9715 which still not be supported by coreboot at this moment. i am trying to add this, but the AMD 880 RPR[1] does not include 880G(0x9715). and coreboot named the 880D/880C as 785D/785C etc. So i want to know if i should name 880G as 785G or let it just "880G". [1]http://support.amd.com/us/Embedded_TechDocs/46141.pdf Best wishes QingPei Wang Phone: 86+018930528086

1 0

Patch set updated for coreboot: 94e9f37 w83627hf: ASL include containing virtual device tree of the SuperIO
by Christoph Grenz 19 Sep '11

19 Sep '11

Christoph Grenz (christophg+cb(a)grenz-bonn.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/223 -gerrit commit 94e9f377664dbb9b49aa80ff47aa7ae3b7d78c34 Author: Christoph Grenz <christophg+cb(a)grenz-bonn.de> Date: Sun Sep 18 22:53:18 2011 +0200 w83627hf: ASL include containing virtual device tree of the SuperIO Add a ACPI Source Language snippet to superio/w83627hf which maps the SuperIO and most of the logical devices to PnP devices, exposing configuration options and chip power management to the OS. Written using the Winbond W83627HF/F datasheet. Change-Id: I1108d29b341ef78fe7f1e574f98b680aada39daf Signed-off-by: Christoph Grenz <christophg+cb(a)grenz-bonn.de> --- src/superio/winbond/w83627hf/devtree.asl | 1514 ++++++++++++++++++++++++++++++ 1 files changed, 1514 insertions(+), 0 deletions(-) diff --git a/src/superio/winbond/w83627hf/devtree.asl b/src/superio/winbond/w83627hf/devtree.asl new file mode 100644 index 0000000..fa78845 --- /dev/null +++ b/src/superio/winbond/w83627hf/devtree.asl @@ -0,0 +1,1514 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Christoph Grenz <christophg+cb(a)grenz-bonn.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * include this file into a mainboard's DSDT and it will expose the W83627HF + * SuperIO and its functionality in the _SB device tree. + * + * Devices are marked as nonexistant if they got 0x00000000 as I/O base address + * (compatibility with legacy bios, which disables logical devices that way) + * + * It allows the change of IO ports, IRQs and DMA settings on most logical + * devices, disabling and reenabling logical devices and controlling power + * saving mode on logical devices or the whole chip. + * + * Notes: + * - ECP mode of parallel port not implemented, DMA settings of parallel port + * will be reset on DSDT init + * - Hardware monitor is only shown as "Motherboard Resource", shows no real + * functionality + * + * Controllable through preprocessor macros: + * NO_W83627HF_FDC: don't expose the floppy disk controller + * NO_W83627HF_FDC_ENUM: don't try to enumerate the connected floppy drives + * NO_W83627HF_PPORT: don't expose the parallel port + * NO_W83627HF_UARTA: don't expose the first serial port + * NO_W83627HF_UARTB: don't expose the second serial port (already hidden + * if UARTB is configured as IRDA port by firmware) + * NO_W83627HF_IRDA: don't expose the IRDA port (already hidden if UARTB is + * configured as serial port by firmware) + * NO_W83627HF_CIR: don't expose the Consumer Infrared functionality + * NO_W83627HF_KBC: don't expose the keyboard controller + * NO_W83627HF_PS2M: don't expose the PS/2 mouse functionality of the + * keyboard controller + * NO_W83627HF_GAME: don't expose the game port + * NO_W83627HF_MIDI: don't expose the MIDI port + * NO_W83627HF_HWMON: don't expose the hardware monitor as + * PnP "Motherboard Ressource" + * + * Datasheet: "W83627HF/F WINBOND I/O" rev. 6.0 + * http://www.itox.com/pages/support/wdt/W83627HF.pdf + */ + +Scope (\_SB) +{ + + Device(SIO) { + Name (_HID, EisaId("PNP0A05")) + Name (_STR, Unicode("Winbond W83627HF SuperIO")) + Name (_UID, "w83627hf") + + /* Mutex for accesses to the configuration ports (prolog and epilog commands are used, so synchronization is useful) */ + Mutex(CRMX, 1) + + /* SuperIO configuration ports */ + OperationRegion (CREG, SystemIO, 0x2E, 0x02) + Field (CREG, ByteAcc, NoLock, Preserve) + { + ADDR, 8, + DATA, 8 + } + IndexField (CREG, DATA, ByteAcc, NoLock, Preserve) + { + Offset (0x02), + RST, 1, /* Soft reset */ + , 7, + Offset (0x07), + LDN, 8, /* Logical device selector */ + Offset (0x20), + DID, 8, /* Device ID */ + DREV, 8, /* Device Revision */ + POWC, 8, + FDPW, 1, /* FDC Power Down */ + , 2, + PRPW, 1, /* PRT Power Down */ + UAPW, 1, /* UART A Power Down */ + UBPW, 1, /* UART B Power Down */ + HWPW, 1, /* HWM Power Down */ + , 1, + IPD, 1, /* Immediate Chip Power Down */ + , 7, + PNPS, 1, /* PnP Address Select Register Default Value Mode */ + , 1, + KBCR, 1, /* KBC enabled after system reset (read-only) */ + , 3, + CLKS, 1, /* Clock select */ + AQ16, 1, /* 16bit Address Qualification */ + FDCT, 1, /* Tristate FDC (?) */ + , 2, + PRTT, 1, /* Tristate parallel port (?) */ + URAT, 1, /* Tristate UART A (?) */ + URBT, 1, /* Tristate UART B (?) */ + , 2, + URAI, 1, /* UART A Legacy IRQ Select Disable */ + URBI, 1, /* UART B Legacy IRQ Select Disable */ + PRTI, 1, /* Parallel Port Legacy IRQ/DRQ Select Disable */ + FDCI, 1, /* FDC Legacy IRQ/DRQ Select Disable */ + , 1, + LCKC, 1, /* Lock Configuration Registers */ + Offset (0x29), + IO3S, 8, /* GPIO3 pin selection register */ + ACTR, 1, /* Logical device activation */ + ACT1, 1, /* Logical part activation 1 (mostly unused) */ + ACT2, 1, /* Logical part activation 2 (mostly unused) */ + , 5, + Offset (0x60), + IO1H, 8, /* First I/O port base - high byte */ + IO1L, 8, /* First I/O port base - low byte */ + IO2H, 8, /* Second I/O port base - high byte */ + IO2L, 8, /* Second I/O port base - low byte */ + Offset (0x70), + IRQ0, 8, /* First IRQ */ + Offset (0x72), + IRQ1, 8, /* First IRQ */ + Offset (0x74), + DMA0, 8, /* DMA */ + Offset (0xE0), + /* CRE0-CRE4: function logical device dependant, seems to be reserved for ACPI settings */ + CRE0, 8, + CRE1, 8, + CRE2, 8, + CRE3, 8, + CRE4, 8, + Offset (0xF0), + /* OPT1-OPTA aka CRF0-CRF9: function logical device dependant */ + OPT1, 8, + OPT2, 8, + OPT3, 8, + OPT4, 8, + OPT5, 8, + OPT6, 8, + OPT7, 8, + OPT8, 8, + OPT9, 8, + OPTA, 8 + } + + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x002E, 0x002E, 0x02, 0x01) /* Announce the used I/O ports to the OS */ + IO (Decode16, 0x004E, 0x004E, 0x01, 0x01) /* this port is used in some configurations, so announce it to be sure */ + }) + + /* Enter configuration mode (and aquire mutex) + Method must be run before accesssing the configuration region. + */ + Method (ENCM) + { + Acquire (CRMX, 0xFFFF) + Store (0x87, ADDR) + Store (0x87, ADDR) + } + + /* Exit configuration mode (and release mutex) + Method must be run after accessing the configuration region. + */ + Method (EXCM) + { + Release (CRMX) + Store (0xAA, ADDR) + } + + /* PM: indicate IPD (Immediate Power Down) bit state as D0/D2 */ + Method (_PSC) { + ENCM () + Store (IPD, Local0) + EXCM () + If (Local0) { Return (2) } + Else { Return (0) } + } + + /* PM: Switch to D0 by setting IPD low */ + Method (_PS0) { + ENCM () + Store (Zero, IPD) + EXCM () + } + + /* PM: Switch to D2 by setting IPD high */ + Method (_PS2) { + ENCM () + Store (One, IPD) + EXCM () + } + + #ifndef NO_W83627HF_FDC + /* =================== Floppy Disk Controller ================ */ + Device (FDC0) { + Name (_HID, EisaId ("PNP0700")) + Name (_STR, Unicode ("W83627HF Floppy Disk Controller")) + Name (_UID, "w83627hf-fdc") + + #ifndef NO_W83627HF_FDC_ENUM + /* Initialization method: Should be run once on boot + If FDC is active, enumerate all connected devices */ + Method (_INI) { + ENCM () + Store (0x00, LDN) + Store (ACTR, Local0) + Store (IO1H, Local1) + Store (IO1L, Local2) + EXCM () + ShiftLeft(Local1, 8, Local1) + Or(Local1, Local2, Local1) + If (Local0) { + /* Try probing drives and save result in _FDE */ + PROB(Local1) + } + } + #endif + + Method (_STA) + { + Store (0x00, Local0) + ENCM () + Store (0x00, LDN) + If (ACTR) { + Store (0x0F, Local0) + } + ElseIf (LOr (IO1H, IO1L)) + { + Store (0x0D, Local0) + } + EXCM () + Return (Local0) + } + + Method (_PSC) { + Store(^^_PSC (), Local0) + If (Local0) { Return (Local0) } + ENCM () + Store (FDPW, Local0) + EXCM () + If (Local0) { Return (1) } + Else { Return (0) } + } + Method (_PS0) { + ENCM () + Store (Zero, FDPW) + EXCM () + } + Method (_PS1) { + ENCM () + Store (One, FDPW) + EXCM () + } + Name (_PR0, Package () { ^^ }) + + Method (_DIS) + { + ENCM () + Store (0x00, LDN) + Store (Zero, ACTR) + EXCM () + } + + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x06, IO0) + IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + ENCM () + Store (0x00, LDN) + Store(IO1H, Local0) + Store(IO1L, Local1) + EXCM () + ShiftLeft(Local1, 8, Local1) + Or (Local1, Local0, Local0) + + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) + + Return (CRS) + } + + Name (_PRS, ResourceTemplate () + { + StartDependentFnNoPri () + { + IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) + IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + } + EndDependentFn () + }) + + #ifndef NO_W83627HF_FDC_ENUM + Name(_FDE, Buffer(){0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}) + #endif + + Method (PROB, 1) { + #ifndef NO_W83627HF_FDC_ENUM + /* Try probing drives and save result in _FDE + Probing is done through selecting and activating a drive + and reading 0x03F7 aka the "shared IDE and floppy register" + as any value there besides zero seems to indicate a + connected drive. + */ + OperationRegion (FIO1, SystemIO, Arg0, 0x06) + Field (FIO1, ByteAcc, NoLock, Preserve) + { + Offset(0x02), + SELE, 2, + RSTL, 1, + IDMA, 1, + ACT1, 1, + ACT2, 1, + ACT3, 1, + ACT4, 1, + Offset(0x04), + BSY1, 1, + BSY2, 1, + BSY3, 1, + BSY4, 1, + BUSY, 1, + NDMA, 1, + IODI, 1, + RDY, 1, + DATA, 8, + } + OperationRegion (FIO2, SystemIO, 0x3F7, 0x01) + + CreateByteField (_FDE, 3, FD1) + CreateByteField (_FDE, 7, FD2) + CreateByteField (_FDE, 11, FD3) + CreateByteField (_FDE, 15, FD4) + + Store(One, ACT1) + Store(0, SELE) + Sleep(0x64) + If (FIO2) { Store (One, FD1) } + + Store(Zero, ACT1) + Store(One, ACT2) + Store(1, SELE) + Sleep(0x64) + If (FIO2) { Store (One, FD2) } + + Store(Zero, ACT2) + Store(One, ACT3) + Store(2, SELE) + Sleep(0x64) + If (FIO2) { Store (One, FD3) } + + Store(Zero, ACT3) + Store(One, ACT4) + Store(3, SELE) + Sleep(0x64) + If (FIO2) { Store (One, FD4) } + Store(Zero, ACT4) + Store(Zero, SELE) + #endif + } + + + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IO (Decode16, 0, 0, 1, 6, IO0) + IO (Decode16, 0, 0, 1, 1, IO1) + IRQNoFlags (IRQ0) {} + DMA (Compatibility, NotBusMaster, Transfer8, DMA0) {} + }) + CreateWordField (Arg0, IO0._MIN, IOA0) + CreateWordField (Arg0, IO1._MIN, IOA1) + CreateByteField (Arg0, IRQ0._INT, IRQL) + CreateByteField (Arg0, DMA0._DMA, DMCH) + + Divide(IOA0, 256, Local0, Local1) + ShiftRight(Local1, 8, Local1) + + ENCM () + Store (0, LDN) + Store (Local1, IO1H) + Store (Local0, IO1L) + Store (One, ACTR) + EXCM () + + /* Try probing drives and save result in _FDE */ + PROB(IOA0) + } + } + #endif + + #ifndef NO_W83627HF_PPORT + /* ======================== Parallel Port ======================== */ + /* Currently no ECP support */ + Device (PAR0) { + Name (_HID, EisaId ("PNP0400")) + Name (_DDN, "LPT1") + Name (_UID, "w83627hf-pport") + + Method (MODE, 1) { + And(Arg0, 0x07, Local0) + ENCM () + Store (0x01, LDN) + And(OPT1, 0x3, Local1) + Or(Local1, Local0, OPT1) + EXCM() + } + + Method (_INI) + { + /* Deactivate DMA, even if set by BIOS. We don't announce it + through _CRS and it's only useful in ECP mode which we + don't support at the moment. */ + ENCM () + Store (0x01, LDN) + Store (0x04, DMA0) + EXCM () + } + + Method (_STA) + { + Store (0x00, Local0) + ENCM () + Store (0x01, LDN) + And(OPT1, 0x3, Local1) + If (ACTR) { + If (LNotEqual(Local1, 2)) { + Store (0x0D, Local0) + } Else { + Store (0x0D, Local0) + } + } + ElseIf (LOr (IO1H, IO1L)) + { + Store (0x0D, Local0) + } + EXCM () + Return (Local0) + } + + Method (_PSC) { + Store(^^_PSC (), Local0) + If (Local0) { Return (Local0) } + ENCM () + Store (PRPW, Local0) + EXCM () + If (Local0) { Return (1) } + Else { Return (0) } + } + Method (_PS0) { + ENCM () + Store (Zero, PRPW) + EXCM () + } + Method (_PS1) { + ENCM () + Store (One, PRPW) + EXCM () + } + Name (_PR0, Package () { ^^ }) + + Method (_DIS) { + ENCM () + Store (0x01, LDN) + Store (Zero, ACTR) + EXCM () + } + + Method (_CRS) + { + Name (CRS, ResourceTemplate () + { + IO (Decode16, 0x0000, 0x0000, 0x04, 0x08, IO0) + IRQNoFlags (IRQX) {} + }) + CreateWordField (CRS, IO0._MIN, IOP0) + CreateWordField (CRS, IO0._MAX, IOR0) + CreateByteField (CRS, IO0._ALN, IOAL) + CreateByteField (CRS, IO0._LEN, IOLE) + CreateWordField (CRS, IRQX._INT, IRQW) + + ENCM () + Store (0x01, LDN) + Store (IO1L, Local0) + Store (IO1H, Local1) + Store (OPT1, Local2) + Store (IRQ0, Local5) + EXCM () + ShiftLeft(Local1, 8, Local1) + Or (Local1, Local0, Local1) + + And(Local2, 0x3, Local3) + And(Local2, 0x4, Local4) + If (Local4) { + Store(0x04, IOAL) + } + + Store(Local1, IOP0) + Store(Local1, IOR0) + + If (LEqual (Local0, 0xBC)) + { + Store (0x04, IOLE) + } + Else + { + Store (0x08, IOLE) + } + + Store (One, Local0) + ShiftLeft (Local0, Local5, IRQW) + + Return (CRS) + } + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,1) + { + IO (Decode16, 0x0378, 0x0378, 0x04, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (0,1) + { + IO (Decode16, 0x0278, 0x0278, 0x04, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (0,1) + { + IO (Decode16, 0x03BC, 0x03BC, 0x04, 0x04) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (0,0) + { + IO (Decode16, 0x0378, 0x0378, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (0,0) + { + IO (Decode16, 0x0278, 0x0278, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (2,0) + { + IO (Decode16, 0x0100, 0x0FFC, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (2,1) + { + IO (Decode16, 0x0100, 0x0FFC, 0x04, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + EndDependentFn () + }) + + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IO (Decode16, 0, 0, 4, 4, IO0) + IRQNoFlags (IRQX) {} + }) + CreateWordField (Arg0, IO0._MIN, IOA0) + CreateWordField (Arg0, IO0._MIN, IOA1) + CreateByteField (Arg0, IO0._ALN, IOAL) + CreateByteField (Arg0, IO0._LEN, IOLE) + CreateWordField (Arg0, IRQX._INT, IRQL) + + If (LEqual(IOAL, 4)) { + Store(0x0, Local2) + } else { + Store(0x1, Local2) + } + + Divide(IOA0, 256, Local0, Local1) + ShiftRight(Local1, 8, Local1) + + ENCM () + Store (0x01, LDN) + Store (Local1, IO1H) + Store (Local0, IO1L) + /*Mode*/ + Store (OPT1, Local3) + And (Local3, 0xF8, Local3) + Or (Local2, Local3, OPT1) + /*DMA off*/ + Store (0x04, DMA0) + /*IRQ*/ + FindSetLeftBit (IRQL, Local3) + Subtract (Local3, 0x01, Local3) + Store (Local3, IRQ0) + /*Activate*/ + Store (One, ACTR) + EXCM () + } + } + #endif + + #ifndef NO_W83627HF_UARTA + /* =========================== UART A ============================ */ + Device (SER0) { + Name (_HID, EisaId ("PNP0501")) + Name (_UID, "w83627hf-uarta") + Name (_DDN, "COM1") + + Method (_STA) + { + Store (0x00, Local0) + ENCM () + Store (0x02, LDN) + If (ACTR) { + Store (0x0F, Local0) + } + ElseIf (LOr (IO1H, IO1L)) + { + Store (0x0D, Local0) + } + EXCM () + Return (Local0) + } + + Method (_PSC) { + Store(^^_PSC (), Local0) + If (Local0) { Return (Local0) } + ENCM () + Store (UAPW, Local0) + EXCM () + If (Local0) { Return (1) } + Else { Return (0) } + } + Method (_PS0) { + ENCM () + Store (Zero, UAPW) + EXCM () + } + Method (_PS1) { + ENCM () + Store (One, UAPW) + EXCM () + } + Name (_PR0, Package () { ^^ }) + + Method (_DIS) + { + ENCM () + Store (0x02, LDN) + Store (Zero, ACTR) + EXCM () + } + + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x08, IO0) + IRQNoFlags (IRQX) {6} + }) + ENCM () + Store (0x02, LDN) + Store(IO1H, Local1) + Store(IO1L, Local0) + Store(IRQ0, Local2) + EXCM () + ShiftLeft(Local1, 8, Local1) + Or (Local1, Local0, Local0) + + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) + + CreateWordField (CRS, IRQX._INT, IRQW) + Store (One, Local3) + ShiftLeft (Local3, Local2, IRQW) + + Return (CRS) + } + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,0) { + IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (0,0) { + IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (1,0) { + IO (Decode16, 0x03E8, 0x03E8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (1,0) { + IO (Decode16, 0x02E8, 0x02E8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (2,0) { + IO (Decode16, 0x0100, 0x0FF8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + EndDependentFn() + }) + + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IO (Decode16, 0, 0, 1, 6, IO0) + IRQNoFlags (IRQX) {} + }) + CreateWordField (Arg0, IO0._MIN, IOA0) + CreateByteField (Arg0, IRQX._INT, IRQL) + + Divide(IOA0, 256, Local0, Local1) + ShiftRight(Local1, 8, Local1) + + FindSetLeftBit (IRQL, Local3) + Subtract (Local3, 0x01, Local3) + + ENCM () + Store (2, LDN) + Store (Local1, IO1H) + Store (Local0, IO1L) + Store (Local3, IRQ0) + Store (One, ACTR) + EXCM () + } + } + #endif + + #ifndef NO_W83627HF_UARTB + /* =========================== UART B ============================ */ + Device (SER1) { + Name (_HID, EisaId ("PNP0501")) + Name (_UID, "w83627hf-uartb") + Name (_DDN, "COM2") + + Method (_STA) + { + Store (0x00, Local0) + ENCM () + Store (0x03, LDN) + If (LNot(And(OPT2, 0x30))) + { + If (ACTR) { + Store (0x0F, Local0) + } + ElseIf (LOr (IO1H, IO1L)) + { + Store (0x0D, Local0) + } + } + EXCM () + Return (Local0) + } + + Method (_PSC) { + Store(^^_PSC (), Local0) + If (Local0) { Return (Local0) } + ENCM () + Store (UBPW, Local0) + EXCM () + If (Local0) { Return (1) } + Else { Return (0) } + } + Method (_PS0) { + ENCM () + Store (Zero, UBPW) + EXCM () + } + Method (_PS1) { + ENCM () + Store (One, UBPW) + EXCM () + } + Name (_PR0, Package () { ^^ }) + + Method (_DIS) + { + ENCM () + Store (0x03, LDN) + Store (Zero, ACTR) + EXCM () + } + + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x08, IO0) + IRQNoFlags (IRQX) {6} + }) + ENCM () + Store (0x03, LDN) + Store(IO1H, Local1) + Store(IO1L, Local0) + Store(IRQ0, Local2) + EXCM () + ShiftLeft(Local1, 8, Local1) + Or (Local1, Local0, Local0) + + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) + + CreateWordField (CRS, IRQX._INT, IRQW) + Store (One, Local3) + ShiftLeft (Local3, Local2, IRQW) + + Return (CRS) + } + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,0) { + IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (0,0) { + IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (1,0) { + IO (Decode16, 0x03E8, 0x03E8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (1,0) { + IO (Decode16, 0x02E8, 0x02E8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (2,0) { + IO (Decode16, 0x0100, 0x0FF8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + EndDependentFn() + }) + + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IO (Decode16, 0, 0, 1, 8, IO0) + IRQNoFlags (IRQX) {} + }) + CreateWordField (Arg0, IO0._MIN, IOA0) + CreateByteField (Arg0, IRQX._INT, IRQL) + + Divide(IOA0, 256, Local0, Local1) + ShiftRight(Local1, 8, Local1) + + FindSetLeftBit (IRQL, Local3) + Subtract (Local3, 0x01, Local3) + + ENCM () + Store (3, LDN) + Store (Local1, IO1H) + Store (Local0, IO1L) + Store (Local3, IRQ0) + Store (One, ACTR) + EXCM () + } + } + #endif + + #ifndef NO_W83627HF_IRDA + /* ======================== UART B (IRDA) ======================== */ + Device (IRDA) { + Name (_HID, EisaId ("PNP0510")) + Name (_UID, "w83627hf-irda") + Name (_STR, Unicode("IrDA Port")) + + Method (_STA) + { + Store (0x00, Local0) + ENCM () + Store (0x03, LDN) + If (And(OPT2, 0x30)) + { + If (ACTR) { + Store (0x0F, Local0) + } + ElseIf (LOr (IO1H, IO1L)) + { + Store (0x0D, Local0) + } + } + EXCM () + Return (Local0) + } + + Method (_PSC) { + Store(^^_PSC (), Local0) + If (Local0) { Return (Local0) } + ENCM () + Store (UBPW, Local0) + EXCM () + If (Local0) { Return (1) } + Else { Return (0) } + } + Method (_PS0) { + ENCM () + Store (Zero, UBPW) + EXCM () + } + Method (_PS1) { + ENCM () + Store (One, UBPW) + EXCM () + } + Name (_PR0, Package () { ^^ }) + + Method (_DIS) + { + ENCM () + Store (0x03, LDN) + Store (Zero, ACTR) + EXCM () + } + + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x08, IO0) + IRQNoFlags (IRQX) {6} + }) + ENCM () + Store (0x03, LDN) + Store(IO1H, Local1) + Store(IO1L, Local0) + Store(IRQ0, Local2) + EXCM () + ShiftLeft(Local1, 8, Local1) + Or (Local1, Local0, Local0) + + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) + + CreateWordField (CRS, IRQX._INT, IRQW) + Store (One, Local3) + ShiftLeft (Local3, Local2, IRQW) + + Return (CRS) + } + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,0) { + IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (1,0) { + IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (0,0) { + IO (Decode16, 0x03E8, 0x03E8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (0,0) { + IO (Decode16, 0x02E8, 0x02E8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (2,0) { + IO (Decode16, 0x0100, 0x0FF8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + EndDependentFn() + }) + + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IO (Decode16, 0, 0, 1, 8, IO0) + IRQNoFlags (IRQX) {} + }) + CreateWordField (Arg0, IO0._MIN, IOA0) + CreateByteField (Arg0, IRQX._INT, IRQL) + + Divide(IOA0, 256, Local0, Local1) + ShiftRight(Local1, 8, Local1) + + FindSetLeftBit (IRQL, Local3) + Subtract (Local3, 0x01, Local3) + + ENCM () + Store (3, LDN) + Store (Local1, IO1H) + Store (Local0, IO1L) + Store (Local3, IRQ0) + Store (One, ACTR) + EXCM () + } + } + #endif + + #ifndef NO_W83627HF_CIR + /* ========================= Consumer IR ========================= */ + Device (CIR0) { + Name (_HID, EisaId ("WEC1022")) /* Should be the correct one */ + Name (_UID, "w83627hf-cir") + Name (_STR, Unicode("Winbond Consumer Infrared Transceiver")) + + Method (_STA) + { + Store (0x00, Local0) + ENCM () + Store (0x06, LDN) + If (ACTR) { + Store (0x0F, Local0) + } + ElseIf (LOr (IO1H, IO1L)) + { + Store (0x0D, Local0) + } + EXCM () + Return (Local0) + } + + Method (_DIS) + { + ENCM () + Store (0x06, LDN) + Store (Zero, ACTR) + EXCM () + } + + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x08, IO0) + IRQNoFlags (IRQX) {6} + }) + ENCM () + Store (0x03, LDN) + Store(IO1H, Local1) + Store(IO1L, Local0) + Store(IRQ0, Local2) + EXCM () + ShiftLeft(Local1, 8, Local1) + Or (Local1, Local0, Local0) + + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) + + CreateWordField (CRS, IRQX._INT, IRQW) + Store (One, Local3) + ShiftLeft (Local3, Local2, IRQW) + + Return (CRS) + } + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,0) { + IO (Decode16, 0x0100, 0x0FF8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + EndDependentFn() + }) + + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IO (Decode16, 0, 0, 1, 8, IO0) + IRQNoFlags (IRQX) {} + }) + CreateWordField (Arg0, IO0._MIN, IOA0) + CreateByteField (Arg0, IRQX._INT, IRQL) + + Divide(IOA0, 256, Local0, Local1) + ShiftRight(Local1, 8, Local1) + + FindSetLeftBit (IRQL, Local3) + Subtract (Local3, 0x01, Local3) + + ENCM () + Store (6, LDN) + Store (Local1, IO1H) + Store (Local0, IO1L) + Store (Local3, IRQ0) + Store (One, ACTR) + EXCM () + } + } + #endif + + #ifndef NO_W83627HF_KBC + /* ===================== Keyboard Controller ===================== */ + Device (KBD0) { + Name (_HID, EisaId ("PNP0303")) + Name (_CID, 0x0B03D041) + Name (_UID, "w83627hf-kbc") + + Method (_STA) + { + Store (0x00, Local0) + ENCM () + Store (0x05, LDN) + If (ACTR) { + Store (0x0F, Local0) + } + ElseIf (Lor(LOr (IO1H, IO1L), LOr (IO2H, IO2L))) + { + Store (0x0D, Local0) + } + EXCM () + Return (Local0) + } + + Method (_DIS) + { + ENCM () + Store (0x05, LDN) + Store (Zero, ACTR) + EXCM () + Notify(PS2M, 1) + } + + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO0) + IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO1) + IRQNoFlags (IRQX) {} + }) + ENCM () + Store (0x05, LDN) + Store(IO1H, Local0) + Store(IO1L, Local1) + Store(IO2H, Local2) + Store(IO2L, Local3) + Store(IRQ0, Local4) + EXCM () + ShiftLeft(Local0, 8, Local0) + Or (Local1, Local0, Local0) + + ShiftLeft(Local2, 8, Local2) + Or (Local1, Local0, Local0) + + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) + + CreateWordField (CRS, IO1._MIN, I1MI) + Store (Local2, I1MI) + CreateWordField (CRS, IO1._MAX, I1MA) + Store (Local2, I1MA) + + CreateWordField (CRS, IRQX._INT, IRQW) + Store (One, Local5) + ShiftLeft (Local5, Local4, IRQW) + + Return (CRS) + } + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,0) { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + } + EndDependentFn() + }) + + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IO (Decode16, 0, 0, 1, 1, IO0) + IO (Decode16, 0, 0, 1, 1, IO1) + IRQNoFlags (IRQX) {} + }) + CreateWordField (Arg0, IO0._MIN, IOA0) + CreateWordField (Arg0, IO1._MIN, IOA1) + CreateByteField (Arg0, IRQX._INT, IRQL) + + Divide(IOA0, 256, Local0, Local1) + ShiftRight(Local1, 8, Local1) + + Divide(IOA1, 256, Local2, Local3) + ShiftRight(Local1, 8, Local1) + + FindSetLeftBit (IRQL, Local4) + Subtract (Local4, 0x01, Local4) + + ENCM () + Store (5, LDN) + Store (Local1, IO1H) + Store (Local0, IO1L) + Store (Local3, IO2H) + Store (Local2, IO2L) + Store (Local3, IRQ0) + Store (One, ACTR) + EXCM () + } + } + #ifndef NO_W83627HF_PS2M + Device (PS2M) { + Name (_HID, EisaId ("PNP0F13")) + Name (_UID, "w83627hf-ps2m") + + Method (_STA) + { + Store (0x00, Local0) + ENCM () + Store (0x05, LDN) + If (LAnd(ACTR, IRQ1) ) { + Store (0x0F, Local0) + } + ElseIf (Lor(LOr (IO1H, IO1L), LOr (IO2H, IO2L))) + { + Store (0x0D, Local0) + } + EXCM () + Return (Local0) + } + + Method (_DIS) + { + ENCM () + Store (0x05, LDN) + Store (Zero, IRQ1) + EXCM () + } + + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IRQNoFlags (IRQX) {} + IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO0) + IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO1) + }) + ENCM () + Store (0x05, LDN) + Store(IO1H, Local0) + Store(IO1L, Local1) + Store(IO2H, Local2) + Store(IO2L, Local3) + Store(IRQ1, Local4) + EXCM () + ShiftLeft(Local0, 8, Local0) + Or (Local1, Local0, Local0) + + ShiftLeft(Local2, 8, Local2) + Or (Local1, Local0, Local0) + + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) + + CreateWordField (CRS, IO1._MIN, I1MI) + Store (Local2, I1MI) + CreateWordField (CRS, IO1._MAX, I1MA) + Store (Local2, I1MA) + + CreateWordField (CRS, IRQX._INT, IRQW) + Store (One, Local5) + ShiftLeft (Local5, Local4, IRQW) + + Return (CRS) + } + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,0) { + IRQNoFlags () {12} + } + StartDependentFn (2,0) { + IRQNoFlags () {1,3,4,5,6,7,9,10,11,12} + } + EndDependentFn() + }) + + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IRQNoFlags (IRQX) {} + }) + CreateByteField (Arg0, IRQX._INT, IRQL) + + FindSetLeftBit (IRQL, Local0) + Subtract (Local0, 0x01, Local0) + + ENCM () + Store (5, LDN) + Store (Local0, IRQ1) + /* Only activates if KBD is active */ + Store (One, ACTR) + EXCM () + } + } + #endif + #endif + + #ifndef NO_W83627HF_GAME + /* ========================== Game Port ========================== */ + Device (GAME) { + Name (_HID, EisaId ("PNPB02F")) + Name (_STR, Unicode ("Joystick/Game Port")) + Name (_UID, "w83627hf-game") + + Method (_STA) { + ENCM () + Store(0, Local0) + Store (0x07, LDN) + If (LOr(IO1L, IO1H)) { + If (LOr(ACTR, ACT1)) { + Store (0x0F, Local0) + } + Else { + Store (0x0D, Local0) + } + } + EXCM () + Return (Local0) + } + + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO0) + IRQNoFlags (IRQX) {} + }) + ENCM () + Store (0x07, LDN) + Store(IO1H, Local0) + Store(IO1L, Local1) + Store(IRQ0, Local2) + EXCM () + ShiftLeft(Local0, 8, Local0) + Or (Local1, Local0, Local0) + + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) + + If (Local2) { + CreateWordField (CRS, IRQX._INT, IRQW) + Store (One, Local3) + ShiftLeft (Local3, Local2, IRQW) + } + + Return (CRS) + } + + } + #endif + + #ifndef NO_W83627HF_MIDI + /* ========================== MIDI Port ========================== */ + Device (MIDI) { + Name (_HID, EisaId ("PNPB006")) + Name (_STR, Unicode ("MPU-401 Compatible MIDI Port")) + Name (_UID, "w83627hf-midi") + + Method (_STA) { + ENCM () + Store(0, Local0) + Store (0x07, LDN) + If (LOr(IO2L, IO2H)) { + If (LOr(ACTR, ACT2)) { + Store (0x0F, Local0) + } + Else { + Store (0x0D, Local0) + } + } + EXCM () + Return (Local0) + } + + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x02, 0x02, IO0) + IRQNoFlags (IRQX) {} + }) + ENCM () + Store (0x07, LDN) + Store(IO2H, Local0) + Store(IO2L, Local1) + Store(IRQ1, Local2) + EXCM () + ShiftLeft(Local0, 8, Local0) + Or (Local1, Local0, Local0) + + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) + + If (Local2) { + CreateWordField (CRS, IRQX._INT, IRQW) + Store (One, Local3) + ShiftLeft (Local3, Local2, IRQW) + } + + Return (CRS) + } + + } + #endif + + /* ==== Suspend LED control if it is connected to the SuperIO ==== */ + Method (SLED, 1) { + ENCM () + Store (9, LDN) + Store(OPT4, Local0) + And(Local0, 63, Local0) + Or(Local0, ShiftLeft(And(Arg0, 0x03), 6), OPT4) + EXCM () + } + + /* ===== Power LED control if it is connected to the SuperIO ===== */ + Method (PLED, 1) { + ENCM () + Store (8, LDN) + Store(OPT4, Local0) + And(Local0, 63, Local0) + Or(Local0, ShiftLeft(And(Arg0, 0x03), 6), OPT4) + EXCM () + } + + #ifndef NO_W83627HF_HWMON + /* ====================== Hardware Monitor ======================= */ + Device (HMON) { + Name (_HID, EisaId ("PNP0C02")) // TODO: find better matching ID + Name (_STR, Unicode("W83627 Hardware Monitor")) + Name (_UID, "w83627hf-hwmon") + + Method (_STA) + { + Store (0x00, Local0) + ENCM () + Store (0x0B, LDN) + If (ACTR) { + Store (0x0F, Local0) + } + ElseIf (LOr (IO1H, IO1L)) + { + Store (0x0D, Local0) + } + EXCM () + Return (Local0) + } + + Method (_PSC) { + Store(^^_PSC (), Local0) + If (Local0) { Return (Local0) } + ENCM () + Store (HWPW, Local0) + EXCM () + If (Local0) { Return (1) } + Else { Return (0) } + } + Method (_PS0) { + ENCM () + Store (Zero, HWPW) + EXCM () + } + Method (_PS1) { + ENCM () + Store (One, HWPW) + EXCM () + } + Name (_PR0, Package () { ^^ }) + + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x08, 0x02, IO0) + IRQNoFlags (IRQX) {} + }) + ENCM () + Store (0x0B, LDN) + Store(IO1H, Local0) + Store(IO1L, Local1) + Store(IRQ1, Local2) + EXCM () + ShiftLeft(Local0, 8, Local0) + Or (Local1, Local0, Local0) + + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) + + If (Local2) { + CreateWordField (CRS, IRQX._INT, IRQW) + Store (One, Local3) + ShiftLeft (Local3, Local2, IRQW) + } + Return (CRS) + } + } + #endif + } +} \ No newline at end of file

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Patch set updated for coreboot: 6803e54 amdk8: ASL include for K8 temperature sensor support in ACPI
by Christoph Grenz 19 Sep '11

19 Sep '11

Christoph Grenz (christophg+cb(a)grenz-bonn.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/222 -gerrit commit 6803e546d97b07d01845e3be2708e99d09591378 Author: Christoph Grenz <christophg+cb(a)grenz-bonn.de> Date: Sun Sep 18 23:20:55 2011 +0200 amdk8: ASL include for K8 temperature sensor support in ACPI Add a ACPI Source Language snippet which if included as shown in the comments in the file, exposes the 4 possible temperature sensors in the CPU as ACPI thermal zones. Change-Id: I94dd773108e348a0fdb9d2f8d6cfe415d5fa0339 Signed-off-by: Christoph Grenz <christophg+cb(a)grenz-bonn.de> --- src/northbridge/amd/amdk8/thermal_mixin.asl | 289 +++++++++++++++++++++++++++ 1 files changed, 289 insertions(+), 0 deletions(-) diff --git a/src/northbridge/amd/amdk8/thermal_mixin.asl b/src/northbridge/amd/amdk8/thermal_mixin.asl new file mode 100644 index 0000000..2cb3813 --- /dev/null +++ b/src/northbridge/amd/amdk8/thermal_mixin.asl @@ -0,0 +1,289 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Christoph Grenz <christophg+cb(a)grenz-bonn.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * include this file into a mainboards DSDT inside the PCI device + * "K8 Miscellaneous Control" and it will expose the temperature + * sensors of the processor as thermal zones. + * + * If, for example, the K8 Misc. Control device is on 0:18.3, include the + * following inside the PCI0 device: + * + * Device(K8MC) { + * Name (_ADR, 0x00180003) + * #include northbridge/amd/amdk8/thermal_mixin.asl + * } + * + * Note: as only the current temperature and the trip temperature for + * "Software Thermal Control" are available in the PCI registers, but the + * linux driver for thermal zones needs a critical temperature value, a + * reasonable critical temperature is calculated by simply adding 6°C to + * the trip temperature. + * + * The used registers are documented in the "BIOS and Kernel Developer's + * Guide for AMD NPT Family 0Fh Processors" + * http://support.amd.com/us/Processor_TechDocs/32559.pdf + * + */ + +#ifndef K8TEMP_CRITICAL_ADD +# define K8TEMP_CRITICAL_ADD 6 +#endif + +OperationRegion(K8TR, PCI_Config, 0xE4, 0x4) +Field(K8TR, DWordAcc, NoLock, Preserve) { + , 1, + THTP, 1, /* Temperature sensor trip occured */ + CORE, 1, /* Select Core */ + TTS0, 1, /* Temperature sensor trip on CPU1 (or single core CPU0) */ + TTS1, 1, /* Temperature sensor trip on CPU0 */ + TTEN, 1, /* Temperature sensor trip enabled */ + PLAC, 1, /* Select Sensor */ + , 1, + DOFF, 6, /* Diode offset (signed 6bit-Integer) in °C */ + TFRC, 2, /* Temperature fractions */ + TVAL, 8, /* Temperature value in °C biased by -49 */ + TJOF, 5, + , 2, + SWTT, 1, /* Induce a thermtrip event (for diagnostic purposes) */ +} + +OperationRegion(K8ST, PCI_Config, 0x70, 0x1) +Field(K8ST, ByteAcc, NoLock, Preserve) { + TMAX, 5, /* Maximum temperature for software thermal control, in °C, biased by 52 */ +} + +/* Calculates temperature in tenths Kelvin from given TVAL and TFRC values */ +Method(K8PT, 2) { + Divide(Multiply(Arg1, 5), 2, , Local0) + Return (Add(Multiply(Add(Arg0, 224),10), Local0)) +} + +/* Calculates the diode offset from a DOFF value */ +Method(K8PO, 1) { + If (And(Arg0, 0x20)) + { + Return (Multiply(Subtract(Xor(Arg0, 0x3F), 1), 10)) + } + Else { + Return (Multiply(Arg0, 10)) + } +} + +ThermalZone (K8T0) { + Name(_HID, EisaId("PNP0C11")) + Name(_UID, "k8-0") + Name(_STR, Unicode("K8 compatible CPU Core 1 Thermal Sensor 1")) + + Method(_STA) { + Store(CORE, Local0) + Store(PLAC, Local1) + + Store(Zero, CORE) + Store(Zero, PLAC) + If (LOr(PLAC, CORE)) { + Store(Local0, CORE) + Store(Local1, PLAC) + Return (0x00) + } + + If (LOr(LNot(TVAL), LEqual(TVAL, 0xFF))) { + Return (0x00) + } + + Store(Local0, CORE) + Store(Local1, PLAC) + Return (0x0F) + } + + Method(_TMP) { + Store(CORE, Local0) + Store(PLAC, Local1) + + Store(Zero, CORE) + Store(Zero, PLAC) + + Store (K8PT(TVAL, TFRC), Local2) + Add (K8PO(DOFF), Local2, Local2) + Store(Local0, CORE) + Store(Local1, PLAC) + + Return (Local2) + } + + Method(_CRT) { + Add(TMAX, 325, Local0) + Add(Local0, K8TEMP_CRITICAL_ADD, Local0) + Return (Multiply(Local0, 10)) + } +} + +ThermalZone (K8T1) { + Name(_HID, EisaId("PNP0C11")) + Name(_UID, "k8-1") + Name(_STR, Unicode("K8 compatible CPU Core 1 Thermal Sensor 2")) + + Name(_TZD, Package () {\_PR.CPU0}) + + Method(_STA) { + Store(CORE, Local0) + Store(PLAC, Local1) + + Store(Zero, CORE) + Store(Zero, PLAC) + If (LOr(PLAC, CORE)) { + Store(Local0, CORE) + Store(Local1, PLAC) + Return (0x00) + } + + Store(One, PLAC) + If (LOr(LNot(TVAL), LEqual(TVAL, 0xFF))) { + Return (0x00) + } + + Store(Local0, CORE) + Store(Local1, PLAC) + Return (0x0F) + } + + Method(_TMP) { + Store(CORE, Local0) + Store(PLAC, Local1) + + Store(Zero, CORE) + Store(One, PLAC) + + Store (K8PT(TVAL, TFRC), Local2) + Add (K8PO(DOFF), Local2, Local2) + Store(Local0, CORE) + Store(Local1, PLAC) + + Return (Local2) + } + + Method(_CRT) { + Add(TMAX, 325, Local0) + Add(Local0, K8TEMP_CRITICAL_ADD, Local0) + Return (Multiply(Local0, 10)) + } +} + +ThermalZone (K8T2) { + Name(_HID, EisaId("PNP0C11")) + Name(_UID, "k8-2") + Name(_STR, Unicode("K8 compatible CPU Core 2 Thermal Sensor 1")) + + Name(_TZD, Package () {\_PR.CPU0}) + + Method(_STA) { + Store(CORE, Local0) + Store(PLAC, Local1) + + Store(Zero, CORE) + Store(Zero, PLAC) + If (LOr(PLAC, CORE)) { + Store(Local0, CORE) + Store(Local1, PLAC) + Return (0x00) + } + + Store(One, CORE) + If (LOr(LNot(TVAL), LEqual(TVAL, 0xFF))) { + Return (0x00) + } + + Store(Local0, CORE) + Store(Local1, PLAC) + Return (0x0F) + } + + Method(_TMP) { + Store(CORE, Local0) + Store(PLAC, Local1) + + Store(One, CORE) + Store(Zero, PLAC) + + Store (K8PT(TVAL, TFRC), Local2) + Add (K8PO(DOFF), Local2, Local2) + Store(Local0, CORE) + Store(Local1, PLAC) + + Return (Local2) + } + + Method(_CRT) { + Add(TMAX, 325, Local0) + Add(Local0, K8TEMP_CRITICAL_ADD, Local0) + Return (Multiply(Local0, 10)) + } +} + +ThermalZone (K8T3) { + Name(_HID, EisaId("PNP0C11")) + Name(_UID, "k8-3") + Name(_STR, Unicode("K8 compatible CPU Core 2 Thermal Sensor 2")) + + Name(_TZD, Package () {\_PR.CPU0}) + + Method(_STA) { + Store(CORE, Local0) + Store(PLAC, Local1) + + Store(Zero, CORE) + Store(Zero, PLAC) + If (LOr(PLAC, CORE)) { + Store(Local0, CORE) + Store(Local1, PLAC) + Return (0x00) + } + + Store(One, CORE) + Store(One, PLAC) + If (LOr(LNot(TVAL), LEqual(TVAL, 0xFF))) { + Return (0x00) + } + + Store(Local0, CORE) + Store(Local1, PLAC) + Return (0x0F) + } + + Method(_TMP) { + Store(CORE, Local0) + Store(PLAC, Local1) + + Store(One, CORE) + Store(One, PLAC) + + Store (K8PT(TVAL, TFRC), Local2) + Add (K8PO(DOFF), Local2, Local2) + Store(Local0, CORE) + Store(Local1, PLAC) + + Return (Local2) + } + + Method(_CRT) { + Add(TMAX, 325, Local0) + Add(Local0, K8TEMP_CRITICAL_ADD, Local0) + Return (Multiply(Local0, 10)) + } +} \ No newline at end of file

1 0

Trac reminder: list of new ticket(s)
by coreboot tracker 19 Sep '11

19 Sep '11

1 0

Patch set updated for coreboot: 151c09c amdk8: ASL include for K8 temperature sensor support in ACPI
by Christoph Grenz 18 Sep '11

18 Sep '11

Christoph Grenz (christophg+cb(a)grenz-bonn.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/222 -gerrit commit 151c09c12aa15bcb260b741e6578377f28febfd6 Author: Christoph Grenz <christophg+cb(a)grenz-bonn.de> Date: Sun Sep 18 23:20:55 2011 +0200 amdk8: ASL include for K8 temperature sensor support in ACPI Add a ACPI Source Language snippet which if included as shown in the comments in the file, exposes the 4 possible temperature sensors in the CPU as ACPI thermal zones. . Rebased to remove dependencies. Change-Id: I94dd773108e348a0fdb9d2f8d6cfe415d5fa0339 Signed-off-by: Christoph Grenz <christophg+cb(a)grenz-bonn.de> --- src/northbridge/amd/amdk8/thermal_mixin.asl | 282 +++++++++++++++++++++++++++ 1 files changed, 282 insertions(+), 0 deletions(-) diff --git a/src/northbridge/amd/amdk8/thermal_mixin.asl b/src/northbridge/amd/amdk8/thermal_mixin.asl new file mode 100644 index 0000000..3424cb5 --- /dev/null +++ b/src/northbridge/amd/amdk8/thermal_mixin.asl @@ -0,0 +1,282 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Christoph Grenz <christophg+cb(a)grenz-bonn.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * include this file into a mainboards DSDT inside the PCI device + * "K8 Miscellaneous Control" and it will expose the temperature + * sensors of the processor as thermal zones. + * + * If, for example, the K8 Misc. Control device is on 0:18.3, include the + * following inside the PCI0 device: + * + * Device(K8MC) { + * Name (_ADR, 0x00180003) + * #include northbridge/amd/amdk8/thermal_mixin.asl + * } + * + * Note: as only the current temperature and the trip temperature for + * "Software Thermal Control" are available in the PCI registers, but the + * linux driver for thermal zones needs a critical temperature value, a + * reasonable critical temperature is calculated by simply adding 6°C to + * the trip temperature. + */ + +#ifndef K8TEMP_CRITICAL_ADD +# define K8TEMP_CRITICAL_ADD 6 +#endif + +OperationRegion(K8TR, PCI_Config, 0xE4, 0x4) +Field(K8TR, DWordAcc, NoLock, Preserve) { + , 1, + THTP, 1, /* Temperature sensor trip occured */ + CORE, 1, /* Select Core */ + TTS0, 1, /* Temperature sensor trip on CPU1 (or single core CPU0) */ + TTS1, 1, /* Temperature sensor trip on CPU0 */ + TTEN, 1, /* Temperature sensor trip enabled */ + PLAC, 1, /* Select Sensor */ + , 1, + DOFF, 6, /* Diode offset (signed 6bit-Integer) in °C */ + TFRC, 2, /* Temperature fractions */ + TVAL, 8, /* Temperature value in °C biased by -49 */ + TJOF, 5, + , 2, + SWTT, 1, /* Induce a thermtrip event (for diagnostic purposes) */ +} + +OperationRegion(K8ST, PCI_Config, 0x70, 0x1) +Field(K8ST, ByteAcc, NoLock, Preserve) { + TMAX, 5, /* Maximum temperature for software thermal control, in °C, biased by 52 */ +} + +Method(K8PT, 2) { + Divide(Multiply(Arg1, 5), 2, , Local0) + Return (Add(Multiply(Add(Arg0, 224),10), Local0)) +} + +Method(K8PO, 1) { + If (And(Arg0, 0x20)) + { + Return (Multiply(Subtract(Xor(Arg0, 0x3F), 1), 10)) + } + Else { + Return (Multiply(Arg0, 10)) + } +} + +ThermalZone (K8T0) { + Name(_HID, EisaId("PNP0C11")) + Name(_UID, "k8-0") + Name(_STR, Unicode("K8 compatible CPU Core 1 Thermal Sensor 1")) + + Method(_STA) { + Store(CORE, Local0) + Store(PLAC, Local1) + + Store(Zero, CORE) + Store(Zero, PLAC) + If (LOr(PLAC, CORE)) { + Store(Local0, CORE) + Store(Local1, PLAC) + Return (0x00) + } + + If (LOr(LNot(TVAL), LEqual(TVAL, 0xFF))) { + Return (0x00) + } + + Store(Local0, CORE) + Store(Local1, PLAC) + Return (0x0F) + } + + Method(_TMP) { + Store(CORE, Local0) + Store(PLAC, Local1) + + Store(Zero, CORE) + Store(Zero, PLAC) + + Store (K8PT(TVAL, TFRC), Local2) + Add (K8PO(DOFF), Local2, Local2) + Store(Local0, CORE) + Store(Local1, PLAC) + + Return (Local2) + } + + Method(_CRT) { + Add(TMAX, 325, Local0) + Add(Local0, K8TEMP_CRITICAL_ADD, Local0) + Return (Multiply(Local0, 10)) + } +} + +ThermalZone (K8T1) { + Name(_HID, EisaId("PNP0C11")) + Name(_UID, "k8-1") + Name(_STR, Unicode("K8 compatible CPU Core 1 Thermal Sensor 2")) + + Name(_TZD, Package () {\_PR.CPU0}) + + Method(_STA) { + Store(CORE, Local0) + Store(PLAC, Local1) + + Store(Zero, CORE) + Store(Zero, PLAC) + If (LOr(PLAC, CORE)) { + Store(Local0, CORE) + Store(Local1, PLAC) + Return (0x00) + } + + Store(One, PLAC) + If (LOr(LNot(TVAL), LEqual(TVAL, 0xFF))) { + Return (0x00) + } + + Store(Local0, CORE) + Store(Local1, PLAC) + Return (0x0F) + } + + Method(_TMP) { + Store(CORE, Local0) + Store(PLAC, Local1) + + Store(Zero, CORE) + Store(One, PLAC) + + Store (K8PT(TVAL, TFRC), Local2) + Add (K8PO(DOFF), Local2, Local2) + Store(Local0, CORE) + Store(Local1, PLAC) + + Return (Local2) + } + + Method(_CRT) { + Add(TMAX, 325, Local0) + Add(Local0, K8TEMP_CRITICAL_ADD, Local0) + Return (Multiply(Local0, 10)) + } +} + +ThermalZone (K8T2) { + Name(_HID, EisaId("PNP0C11")) + Name(_UID, "k8-2") + Name(_STR, Unicode("K8 compatible CPU Core 2 Thermal Sensor 1")) + + Name(_TZD, Package () {\_PR.CPU0}) + + Method(_STA) { + Store(CORE, Local0) + Store(PLAC, Local1) + + Store(Zero, CORE) + Store(Zero, PLAC) + If (LOr(PLAC, CORE)) { + Store(Local0, CORE) + Store(Local1, PLAC) + Return (0x00) + } + + Store(One, CORE) + If (LOr(LNot(TVAL), LEqual(TVAL, 0xFF))) { + Return (0x00) + } + + Store(Local0, CORE) + Store(Local1, PLAC) + Return (0x0F) + } + + Method(_TMP) { + Store(CORE, Local0) + Store(PLAC, Local1) + + Store(One, CORE) + Store(Zero, PLAC) + + Store (K8PT(TVAL, TFRC), Local2) + Add (K8PO(DOFF), Local2, Local2) + Store(Local0, CORE) + Store(Local1, PLAC) + + Return (Local2) + } + + Method(_CRT) { + Add(TMAX, 325, Local0) + Add(Local0, K8TEMP_CRITICAL_ADD, Local0) + Return (Multiply(Local0, 10)) + } +} + +ThermalZone (K8T3) { + Name(_HID, EisaId("PNP0C11")) + Name(_UID, "k8-3") + Name(_STR, Unicode("K8 compatible CPU Core 2 Thermal Sensor 2")) + + Name(_TZD, Package () {\_PR.CPU0}) + + Method(_STA) { + Store(CORE, Local0) + Store(PLAC, Local1) + + Store(Zero, CORE) + Store(Zero, PLAC) + If (LOr(PLAC, CORE)) { + Store(Local0, CORE) + Store(Local1, PLAC) + Return (0x00) + } + + Store(One, CORE) + Store(One, PLAC) + If (LOr(LNot(TVAL), LEqual(TVAL, 0xFF))) { + Return (0x00) + } + + Store(Local0, CORE) + Store(Local1, PLAC) + Return (0x0F) + } + + Method(_TMP) { + Store(CORE, Local0) + Store(PLAC, Local1) + + Store(One, CORE) + Store(One, PLAC) + + Store (K8PT(TVAL, TFRC), Local2) + Add (K8PO(DOFF), Local2, Local2) + Store(Local0, CORE) + Store(Local1, PLAC) + + Return (Local2) + } + + Method(_CRT) { + Add(TMAX, 325, Local0) + Add(Local0, K8TEMP_CRITICAL_ADD, Local0) + Return (Multiply(Local0, 10)) + } +} \ No newline at end of file

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coreboot September 2011