coreboot September 2011

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by marjolein kooistra 22 Sep '11

22 Sep '11

marjolein

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New patch to review for coreboot: 0bb7b21 sb800 raid/ahci site-local Makefile
by Kerry Sheh 22 Sep '11

22 Sep '11

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/234 -gerrit commit 0bb7b21eb22937b05f4dfa716092fb6251b8c5ec Author: Kerry Sheh <shekairui(a)gmail.com> Date: Thu Sep 22 19:01:46 2011 +0800 sb800 raid/ahci site-local Makefile Site-local Makefile to add raid/ahci option rom enable RAID0, RAID1, RAID10 and RAID5 feature with Promise Option ROM. test on amd/persimmon and avalue/eax-785e mainboard. Change-Id: Ia124fa8a132f7cb16d8d7864f7fcda6433f447f0 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- site-local/Makefile.inc | 33 +++++++++++++++++++++++++++++++++ 1 files changed, 33 insertions(+), 0 deletions(-) diff --git a/site-local/Makefile.inc b/site-local/Makefile.inc new file mode 100644 index 0000000..324357f --- /dev/null +++ b/site-local/Makefile.inc @@ -0,0 +1,33 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +stripped_ahci_rom_id = $(call strip_quotes,$(CONFIG_AHCI_ROM_ID)) +cbfs-files-$(CONFIG_SB800_SATA_AHCI) += pci$(stripped_ahci_rom_id).rom +pci$(stripped_ahci_rom_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_ROM_FILE)) +pci$(stripped_ahci_rom_id).rom-type := optionrom + +stripped_raid_rom_id = $(call strip_quotes,$(CONFIG_RAID_ROM_ID)) +cbfs-files-$(CONFIG_SB800_SATA_RAID) += pci$(stripped_raid_rom_id).rom +pci$(stripped_raid_rom_id).rom-file := $(call strip_quotes,$(CONFIG_RAID_ROM_FILE)) +pci$(stripped_raid_rom_id).rom-type := optionrom + +cbfs-files-$(CONFIG_RAID_MISC_ROM) += raid/misc.bin +raid/misc.bin-file := $(call strip_quotes,$(CONFIG_RAID_MISC_ROM_FILE)) +raid/misc.bin-type := raw +

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New patch to review for coreboot: 314d2ba avalue/eax-785e: Get SATA Mode from Kconfig option
by Kerry Sheh 22 Sep '11

22 Sep '11

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/233 -gerrit commit 314d2ba1720e3f350e40cf4ef420ad1070b7b6bb Author: Kerry Sheh <shekairui(a)gmail.com> Date: Thu Sep 22 18:56:48 2011 +0800 avalue/eax-785e: Get SATA Mode from Kconfig option Change-Id: I67aab3ba7de85337e2cf83b6d1be63cb04bf0fcd Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/mainboard/avalue/eax-785e/platform_cfg.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mainboard/avalue/eax-785e/platform_cfg.h b/src/mainboard/avalue/eax-785e/platform_cfg.h index 24dcae0..e503585 100644 --- a/src/mainboard/avalue/eax-785e/platform_cfg.h +++ b/src/mainboard/avalue/eax-785e/platform_cfg.h @@ -103,7 +103,7 @@ * @breif INCHIP Sata Controller Mode * NOTE: DO NOT ALLOW SATA & IDE use same mode */ -#define SATA_MODE NATIVE_IDE_MODE +#define SATA_MODE CONFIG_SB800_SATA_MODE /** * @breif INCHIP Sata IDE Controller Mode

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New patch to review for coreboot: 90cc2db sb800: Add Kconfig option ENABLE_IDE_COMBINED_MODE
by Kerry Sheh 22 Sep '11

22 Sep '11

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/231 -gerrit commit 90cc2db57549d588e96b2d5490451bb0b51b13e5 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Thu Sep 22 18:56:46 2011 +0800 sb800: Add Kconfig option ENABLE_IDE_COMBINED_MODE Add this option to enable/disable SATA IDE Combined Mode feature Change-Id: I1ab8acd27947a71baf954f44d0741f81f48e5541 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/southbridge/amd/cimx/sb800/Kconfig | 16 ++++++++++++++++ src/southbridge/amd/cimx/sb800/cfg.c | 2 +- 2 files changed, 17 insertions(+), 1 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index dc4dd7a..1370e7e 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -28,6 +28,22 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/amd/cimx/sb800/bootblock.c" +config ENABLE_IDE_COMBINED_MODE + bool "Enable SATA IDE combined mode" + default n + help + If Combined Mode is enabled. IDE controller is exposed and + SATA controller has control over Port0 through Port3, + IDE controller has control over Port4 and Port5. + + If Combined Mode is disabled, IDE controller is hidden and + SATA controller has full control of all 6 Ports when operating in non-IDE mode. + +config IDE_COMBINED_MODE + hex + default "0x0" if ENABLE_IDE_COMBINED_MODE + default "0x1" if !ENABLE_IDE_COMBINED_MODE + choice prompt "SATA Mode" default SB800_SATA_IDE diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index a7801a8..a34dd14 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -84,7 +84,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config) sb_config->SATAMODE.SataMode.SataController = SATA_CONTROLLER; sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary. //TODO: set to secondary not take effect. - sb_config->SATAMODE.SataMode.SataIdeCombinedMode = 0; //IDE controlor exposed and combined mode enabled + sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CONFIG_IDE_COMBINED_MODE; sb_config->SATAMODE.SataMode.SATARefClkSel = SATA_CLOCK_SOURCE; /* Azalia HDA */

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New patch to review for coreboot: ebf8e44 persimmon: Add usb3 dev in devicetree
by Kerry Sheh 22 Sep '11

22 Sep '11

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/232 -gerrit commit ebf8e4438b1343816cf4e6b27a891c1ef25476cc Author: Kerry Sheh <shekairui(a)gmail.com> Date: Thu Sep 22 18:56:47 2011 +0800 persimmon: Add usb3 dev in devicetree Change-Id: If060ccb43df7fbe88bafc61e9e600a9120575437 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/mainboard/amd/persimmon/devicetree.cb | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb index 7da2169..fe87bca 100644 --- a/src/mainboard/amd/persimmon/devicetree.cb +++ b/src/mainboard/amd/persimmon/devicetree.cb @@ -87,6 +87,8 @@ chip northbridge/amd/agesa/family14/root_complex device pci 15.1 off end # PCIe PortB device pci 15.2 off end # PCIe PortC device pci 15.3 off end # PCIe PortD + device pci 16.0 off end # OHCI-USB3 + device pci 16.2 off end # UHCI-USB3 register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE end #southbridge/amd/cimx/sb800

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New patch to review for coreboot: 649b026 sb800: sata combine mode configure fix
by Kerry Sheh 22 Sep '11

22 Sep '11

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/229 -gerrit commit 649b0261522df56f279db86a5a3fce3524277fe6 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Thu Sep 22 18:56:45 2011 +0800 sb800: sata combine mode configure fix Using micro CIMX_OPTION_ENABLED/CIMX_OPTION_DISABLED to configure SataIdeCombinedMode is wrong. sbPowerOnInit() use SataIdeCombinedMode to determine whether hide the IDE controller 0: IDE controller is exposed and Combined Mode is enabled. SATA controller has control over Port0 through Port3, IDE controller has control over Port4 and Port5 1: IDE controller is hidden and Combined Mode is disabled, SATA controller has full control of all 6 Ports when operating in non-IDE mode Change-Id: I32e7101737f1dbfff49daa58670e6820b476b250 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/vendorcode/amd/cimx/sb800/SATA.c | 4 ++-- src/vendorcode/amd/cimx/sb800/SBTYPE.h | 10 ++++++++++ 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/src/vendorcode/amd/cimx/sb800/SATA.c b/src/vendorcode/amd/cimx/sb800/SATA.c index 1c0e7e6..b7bbacd 100644 --- a/src/vendorcode/amd/cimx/sb800/SATA.c +++ b/src/vendorcode/amd/cimx/sb800/SATA.c @@ -470,7 +470,7 @@ sataInitAfterPciEnum ( if (((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE)) { // RIAD or AHCI - if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == CIMX_OPTION_DISABLED) { + if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == SATA_IDE_COMBINE_DISABLE) { RWMEM ((ddBar5 + SB_SATA_BAR5_REG00), AccWidthUint8 | S3_SAVE, ~(BIT2 + BIT1 + BIT0), BIT2 + BIT0); RWMEM ((ddBar5 + SB_SATA_BAR5_REG0C), AccWidthUint8 | S3_SAVE, 0xC0, 0x3F); // RPR 8.10 Disabling CCC (Command Completion Coalescing) support. @@ -631,7 +631,7 @@ sataInitLatePost ( //Enable write access to pci header, pm capabilities RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0); -// if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == CIMX_OPTION_DISABLED) { +// if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == SATA_IDE_COMBINE_DISABLE) { RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 1), AccWidthUint8 | S3_SAVE, ~BIT7, BIT7); // } sataBar5setting (pConfig, &ddBar5); diff --git a/src/vendorcode/amd/cimx/sb800/SBTYPE.h b/src/vendorcode/amd/cimx/sb800/SBTYPE.h index b8278cf..f8e825e 100644 --- a/src/vendorcode/amd/cimx/sb800/SBTYPE.h +++ b/src/vendorcode/amd/cimx/sb800/SBTYPE.h @@ -1106,6 +1106,16 @@ typedef unsigned int CIM_STATUS; */ #define CIMX_OPTION_ENABLED 1 +/** + * SATA_IDE_COMBINE_ENABLE -Define Enable Combined Mode + */ +#define SATA_IDE_COMBINE_ENABLE 0 + +/** + * SATA_IDE_COMBINE_DISABLE -Define Disable Combined Mode + */ +#define SATA_IDE_COMBINE_DISABLE 1 + // mov al, code // out 80h, al // jmp $

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New patch to review for coreboot: ec5e844 sb800: Update entry point of sb_Before_Pci_Init
by Kerry Sheh 22 Sep '11

22 Sep '11

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/230 -gerrit commit ec5e844c1d1c88cfcf000a33beee644301a05179 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Thu Sep 22 18:56:46 2011 +0800 sb800: Update entry point of sb_Before_Pci_Init Formally sb800 cimx entry sb_Before_Pci_Init was called in the device 16.2 enable_dev() function. If the devicetree don't have this device, then sb_Before_Pci_Init will not get called. Change-Id: I76ebad842e90b0f740abbec031165d7c39a80abf Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/northbridge/amd/agesa/family10/northbridge.c | 6 ++++++ src/northbridge/amd/agesa/family14/northbridge.c | 3 +++ src/northbridge/amd/amdfam10/northbridge.c | 3 +++ src/southbridge/amd/cimx/sb800/late.c | 3 --- 4 files changed, 12 insertions(+), 3 deletions(-) diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index b3e4c63..b347469 100755 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -38,6 +38,9 @@ #include <Porting.h> #include <AGESA.h> #include <Options.h> +#if CONFIG_AMD_SB_CIMX +#include <sb_cimx.h> +#endif #include "root_complex/chip.h" #include "northbridge.h" #include "amdfam10.h" @@ -775,6 +778,9 @@ static void amdfam10_domain_read_resources(device_t dev) { unsigned reg; +#if CONFIG_AMD_SB_CIMX + sb_Before_Pci_Init(); +#endif /* Find the already assigned resource pairs */ get_fx_devs(); for (reg = 0x80; reg <= 0xd8; reg+= 0x08) { diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index b2ca256..712145b 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -488,6 +488,9 @@ static void domain_read_resources(device_t dev) unsigned reg; printk(BIOS_DEBUG, "\nFam14h - domain_read_resources.\n"); +#if CONFIG_AMD_SB_CIMX + sb_Before_Pci_Init(); +#endif /* Find the already assigned resource pairs */ get_fx_devs(); diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 89bd673..33843b8 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -634,6 +634,9 @@ static void amdfam10_domain_read_resources(device_t dev) { unsigned reg; +#if CONFIG_AMD_SB_CIMX + sb_Before_Pci_Init(); +#endif /* Find the already assigned resource pairs */ get_fx_devs(); for(reg = 0x80; reg <= 0xd8; reg+= 0x08) { diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index eb78546..74f952a 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -413,9 +413,6 @@ static void sb800_enable(device_t dev) break; case (0x16 << 3) | 2: /* 0:16:2 EHCI-USB3 */ sb_config->USBMODE.UsbMode.Ehci3 = dev->enabled; - - /* the last sb800 device */ - sb_Before_Pci_Init(); break; default:

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New patch to review for coreboot: 9876acc persimmon: sb800 sata mode configure update
by Kerry Sheh 22 Sep '11

22 Sep '11

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/227 -gerrit commit 9876acc20e1b8d88ce6b766dc10200a265a67cc1 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Thu Sep 22 18:52:36 2011 +0800 persimmon: sb800 sata mode configure update persimmon configure sb800 sata mode according to the southbridge kconfig selection. Change-Id: I44a9c36ca68b4a0e1086f04c4338d3a5f536fdca Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/mainboard/amd/persimmon/platform_cfg.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h index 5e3c3f4..e4fedd9 100644 --- a/src/mainboard/amd/persimmon/platform_cfg.h +++ b/src/mainboard/amd/persimmon/platform_cfg.h @@ -103,7 +103,7 @@ * @breif INCHIP Sata Controller Mode * NOTE: DO NOT ALLOW SATA & IDE use same mode */ -#define SATA_MODE AHCI_MODE +#define SATA_MODE CONFIG_SB800_SATA_MODE /** * @breif INCHIP Sata IDE Controller Mode

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New patch to review for coreboot: 684b764 sb800: IDE configure fix
by Kerry Sheh 22 Sep '11

22 Sep '11

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/228 -gerrit commit 684b764eac0dba6de7cf86510e02ddf5b671679a Author: Kerry Sheh <shekairui(a)gmail.com> Date: Thu Sep 22 18:56:42 2011 +0800 sb800: IDE configure fix Using micro CIMX_OPTION_ENABLED/CIMX_OPTION_DISABLED to configure SataIdeCombinedMode is wrong. This code need to be removed. Change-Id: I8664a104bd0432b8dfbdaa9a1464c25e9f8ac963 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/southbridge/amd/cimx/sb800/late.c | 5 ----- 1 files changed, 0 insertions(+), 5 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index b581212..eb78546 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -343,11 +343,6 @@ static void sb800_enable(device_t dev) break; case (0x14 << 3) | 1: /* 0:14:1 IDE */ - if (dev->enabled) { - sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CIMX_OPTION_ENABLED; - } else { - sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CIMX_OPTION_DISABLED; - } break; case (0x14 << 3) | 2: /* 0:14:2 HDA */

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New patch to review for coreboot: b6a33d5 sb800: Add sata ahci/raid mode kconfig option
by Kerry Sheh 22 Sep '11

22 Sep '11

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/225 -gerrit commit b6a33d526298aca00643dab79c70631b76749434 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Thu Sep 22 18:52:30 2011 +0800 sb800: Add sata ahci/raid mode kconfig option If sb800 sata was configured as ahci or raid mode, locate the corresponding option rom at site-local directory by default. Change-Id: I87a7814930ce3a7c38cde1e235d151223eea2107 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/southbridge/amd/cimx/sb800/Kconfig | 59 ++++++++++++++++++++++++++++++++ 1 files changed, 59 insertions(+), 0 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 681c881..dc4dd7a 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -28,8 +28,67 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/amd/cimx/sb800/bootblock.c" +choice + prompt "SATA Mode" + default SB800_SATA_IDE + help + Select the mode in which SATA should be driven. NATIVE AHCI, or RAID. + The default is NATIVE. + +config SB800_SATA_IDE + bool "NATIVE" + +config SB800_SATA_AHCI + bool "AHCI" + +config SB800_SATA_RAID + bool "RAID" +endchoice + +config SB800_SATA_MODE + hex + depends on (SB800_SATA_IDE || SB800_SATA_RAID || SB800_SATA_AHCI) + default "0x0" if SB800_SATA_IDE + default "0x1" if SB800_SATA_RAID + default "0x2" if SB800_SATA_AHCI + config SB_SUPERIO_HWM bool default n + +if SB800_SATA_AHCI +config AHCI_ROM_ID + string "AHCI device PCI IDs" + default "1002,4391" + +config AHCI_ROM_FILE + string "AHCI ROM path and filename" + default "site-local/sb800/ahci.bin" +endif + +if SB800_SATA_RAID +config RAID_ROM_ID + string "RAID device PCI IDs" + default "1002,4393" + help + 1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode + +config RAID_ROM_FILE + string "RAID ROM path and filename" + default "site-local/sb800/raid.bin" + +config RAID_MISC_ROM + bool + default y + help + SB800 Promisc RAID Option ROM misc binary + +config RAID_MISC_ROM_FILE + string "RAID Misc ROM path and filename" + default "site-local/sb800/misc.bin" + depends on RAID_MISC_ROM + +endif + endif #SOUTHBRIDGE_AMD_CIMX_SB800

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coreboot September 2011