coreboot September 2011

coreboot@coreboot.org

40 participants
224 discussions

New patch to review: f787a41 Adjust some code/comment of sb700 sata init
by Patrick Georgi 03 Sep '11

03 Sep '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/186 -gerrit commit f787a41e3ae338b7d337236b69761dddde2340fe Author: Wang Qing Pei <wangqingpei(a)gmail.com> Date: Tue Nov 9 09:17:07 2010 +0100 Adjust some code/comment of sb700 sata init The inline comment of sata_init function seems not placed correctly. Rearrange it. Change-Id: I63480da60e51cdc68e64c302ad2d8a6197e288f6 Signed-off-by: Wang Qing Pei <wangqingpei(a)gmail.com> Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/southbridge/amd/sb700/sata.c | 9 ++++----- 1 files changed, 4 insertions(+), 5 deletions(-) diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c index 411baf5..58b72ad 100755 --- a/src/southbridge/amd/sb700/sata.c +++ b/src/southbridge/amd/sb700/sata.c @@ -91,14 +91,13 @@ static void sata_init(struct device *dev) device_t sm_dev; /* SATA SMBus Disable */ - /* sm_dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - /* Disable SATA SMBUS */ - byte = pci_read_config8(sm_dev, 0xad); - byte |= (1 << 1); - /* Enable SATA and power saving */ + byte = pci_read_config8(sm_dev, 0xad); + /* Disable SATA SMBUS */ byte |= (1 << 0); + /* Enable SATA and power saving */ + byte |= (1 << 1); byte |= (1 << 5); pci_write_config8(sm_dev, 0xad, byte);

1 0

New patch to review: 4f27a0a inteltool: added more device IDs
by Patrick Georgi 03 Sep '11

03 Sep '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/185 -gerrit commit 4f27a0a423753b7b5d6d088c6a2411a6ecc7dad2 Author: Ruud Schramp <schramp(a)holmes.nl> Date: Mon Apr 4 07:53:19 2011 +0200 inteltool: added more device IDs Change-Id: I6f2272ae4071025e671638e83bade6a96aac658b Signed-off-by: Ruud Schramp <schramp(a)holmes.nl> Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/inteltool/inteltool.c | 2 ++ util/inteltool/inteltool.h | 2 ++ util/inteltool/memory.c | 2 ++ util/inteltool/pcie.c | 6 ++++++ 4 files changed, 12 insertions(+), 0 deletions(-) diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index a416106..93169d3 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -80,6 +80,8 @@ static const struct { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH0, "ICH0" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "82371AB/EB/MB" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X44, "82X38/X48" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_32X0, "3200/3210" }, }; #ifndef __DARWIN__ diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index ca8066f..24846c8 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -78,6 +78,8 @@ #define PCI_DEVICE_ID_INTEL_82Q35 0x29b0 #define PCI_DEVICE_ID_INTEL_82G33 0x29c0 #define PCI_DEVICE_ID_INTEL_82Q33 0x29d0 +#define PCI_DEVICE_ID_INTEL_X44 0x29e0 +#define PCI_DEVICE_ID_INTEL_32X0 0x29F0 #define PCI_DEVICE_ID_INTEL_GS45 0x2a40 #define PCI_DEVICE_ID_INTEL_X58 0x3405 #define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100 diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index 256204c..9230419 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -109,6 +109,8 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc) printf("This northbridge does not have MCHBAR.\n"); return 1; case PCI_DEVICE_ID_INTEL_GS45: + case PCI_DEVICE_ID_INTEL_X44: + case PCI_DEVICE_ID_INTEL_32X0: mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; break; diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index 1ca57b6..4913150 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -45,6 +45,8 @@ int print_epbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_82Q35: case PCI_DEVICE_ID_INTEL_82G33: case PCI_DEVICE_ID_INTEL_82Q33: + case PCI_DEVICE_ID_INTEL_X44: + case PCI_DEVICE_ID_INTEL_32X0: case PCI_DEVICE_ID_INTEL_GS45: case PCI_DEVICE_ID_INTEL_ATOM_DXXX: case PCI_DEVICE_ID_INTEL_ATOM_NXXX: @@ -104,6 +106,8 @@ int print_dmibar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_82Q35: case PCI_DEVICE_ID_INTEL_82G33: case PCI_DEVICE_ID_INTEL_82Q33: + case PCI_DEVICE_ID_INTEL_X44: + case PCI_DEVICE_ID_INTEL_32X0: case PCI_DEVICE_ID_INTEL_GS45: case PCI_DEVICE_ID_INTEL_ATOM_DXXX: case PCI_DEVICE_ID_INTEL_ATOM_NXXX: @@ -167,6 +171,8 @@ int print_pciexbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_82Q35: case PCI_DEVICE_ID_INTEL_82G33: case PCI_DEVICE_ID_INTEL_82Q33: + case PCI_DEVICE_ID_INTEL_X44: + case PCI_DEVICE_ID_INTEL_32X0: case PCI_DEVICE_ID_INTEL_GS45: case PCI_DEVICE_ID_INTEL_ATOM_DXXX: case PCI_DEVICE_ID_INTEL_ATOM_NXXX:

1 0

New patch to review: b8fe009 Report GSE chipset and warn if the code has been compiled for the wrong chipset.
by Patrick Georgi 03 Sep '11

03 Sep '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/184 -gerrit commit b8fe009787a26f079b236a26ebc0c6e676c0c884 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Apr 1 22:33:25 2011 +0200 Report GSE chipset and warn if the code has been compiled for the wrong chipset. It would be nicer to unify the code so that it does all detection at runtime instead of compile time (but that would also significantly increase code size) so if someone else wants to give it a shot... Change-Id: Idc67bdf7a6ff2b78dc8fc67a0da5ae7a4c0a3bf0 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/northbridge/intel/i945/early_init.c | 8 +++++++- 1 files changed, 7 insertions(+), 1 deletions(-) diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 21efc37..197c58f 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -42,7 +42,7 @@ static void i945m_detect_chipset(void) printk(BIOS_INFO, "Mobile Intel(R) 82945GM/GME Express"); break; case 2: - printk(BIOS_INFO, "Mobile Intel(R) 82945GMS/GU Express"); + printk(BIOS_INFO, "Mobile Intel(R) 82945GMS/GU/GSE Express"); break; case 3: printk(BIOS_INFO, "Mobile Intel(R) 82945PM Express"); @@ -91,6 +91,9 @@ static void i945m_detect_chipset(void) printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */ } printk(BIOS_DEBUG, "\n"); +#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GC) + printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); +#endif } static void i945_detect_chipset(void) @@ -137,6 +140,9 @@ static void i945_detect_chipset(void) printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */ } printk(BIOS_DEBUG, "\n"); +#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM) + printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); +#endif } static void i945_setup_bars(void)

1 0

New patch to review: 66367fa Replace while with do; while to avoid repetition
by Patrick Georgi 03 Sep '11

03 Sep '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/183 -gerrit commit 66367fa77ecc1501bdb2b081370268442e45408d Author: Noe Rubinstein <nrubinstein(a)proformatique.com> Date: Thu May 5 15:44:40 2011 +0200 Replace while with do; while to avoid repetition Cosmetic only; replaces some 'while' loops with 'do; while' loops to avoid repetition. Replacement performed by the Ruby expression: t.gsub!(/^(\s*)([^\n\{]+)\n\1(while[^\n\{;]+)\n\s*\2/, "\\1do \\2\n\\1\\3;") Change-Id: Ie0a4fa622df881edeaab08f59bb888a903b864fd Signed-off-by: Noe Rubinstein <nrubinstein(a)proformatique.com> Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/northbridge/intel/e7520/raminit.c | 55 +++++++++-------------- src/northbridge/intel/e7525/raminit.c | 55 +++++++++-------------- src/northbridge/intel/i3100/raminit.c | 55 +++++++++-------------- src/northbridge/intel/i3100/raminit_ep80579.c | 60 ++++++++++--------------- 4 files changed, 90 insertions(+), 135 deletions(-) diff --git a/src/northbridge/intel/e7520/raminit.c b/src/northbridge/intel/e7520/raminit.c index 7a0661c..e9a60f1 100644 --- a/src/northbridge/intel/e7520/raminit.c +++ b/src/northbridge/intel/e7520/raminit.c @@ -1128,9 +1128,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) write32(BAR+0x100, (0x83000000 | (i<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } @@ -1139,9 +1138,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs++) { write32(BAR + DCALCSR, (0x83000000 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* Precharg all banks */ @@ -1152,9 +1150,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) else /* DDR1 */ write32(BAR+DCALADDR, 0x00000000); write32(BAR+DCALCSR, (0x83000002 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* EMRS dll's enabled */ @@ -1166,9 +1163,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) else /* DDR1 */ write32(BAR+DCALADDR, 0x00000001); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* MRS reset dll's */ do_delay(); @@ -1187,9 +1183,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs++) { write32(BAR+DCALADDR, mode_reg); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* Precharg all banks */ @@ -1202,25 +1197,22 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) else /* DDR1 */ write32(BAR+DCALADDR, 0x00000000); write32(BAR+DCALCSR, (0x83000002 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* Do 2 refreshes */ do_delay(); for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } do_delay(); for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } do_delay(); /* for good luck do 6 more */ @@ -1253,9 +1245,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs++) { write32(BAR+DCALADDR, (mode_reg & ~(1<<24))); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* Do only if DDR2 EMRS dll's enabled */ @@ -1264,9 +1255,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs++) { write32(BAR+DCALADDR, (0x0b940001)); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } } @@ -1310,9 +1300,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x830831d8 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* Bring memory subsystem on line */ diff --git a/src/northbridge/intel/e7525/raminit.c b/src/northbridge/intel/e7525/raminit.c index 495a142..e341596 100644 --- a/src/northbridge/intel/e7525/raminit.c +++ b/src/northbridge/intel/e7525/raminit.c @@ -1104,9 +1104,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) write32(BAR+0x100, (0x83000000 | (i<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } @@ -1115,9 +1114,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs++) { write32(BAR + DCALCSR, (0x83000000 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* Precharg all banks */ @@ -1128,9 +1126,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) else /* DDR1 */ write32(BAR+DCALADDR, 0x00000000); write32(BAR+DCALCSR, (0x83000002 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* EMRS dll's enabled */ @@ -1142,9 +1139,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) else /* DDR1 */ write32(BAR+DCALADDR, 0x00000001); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* MRS reset dll's */ do_delay(); @@ -1163,9 +1159,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs++) { write32(BAR+DCALADDR, mode_reg); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* Precharg all banks */ @@ -1178,25 +1173,22 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) else /* DDR1 */ write32(BAR+DCALADDR, 0x00000000); write32(BAR+DCALCSR, (0x83000002 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* Do 2 refreshes */ do_delay(); for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } do_delay(); for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } do_delay(); /* for good luck do 6 more */ @@ -1229,9 +1221,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs++) { write32(BAR+DCALADDR, (mode_reg & ~(1<<24))); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* Do only if DDR2 EMRS dll's enabled */ @@ -1240,9 +1231,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs++) { write32(BAR+DCALADDR, (0x0b940001)); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } } @@ -1283,9 +1273,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x830831d8 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* Bring memory subsystem on line */ diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c index 86e610f..ced3de1 100644 --- a/src/northbridge/intel/i3100/raminit.c +++ b/src/northbridge/intel/i3100/raminit.c @@ -1020,9 +1020,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) write32(MCBAR+DCALCSR, (0x01000000 | (i<<20))); write32(MCBAR+DCALCSR, (0x81000000 | (i<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } /* Apply NOP */ @@ -1030,9 +1029,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs+=2) { write32(MCBAR + DCALCSR, (0x81000000 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } /* Precharg all banks */ @@ -1040,9 +1038,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs+=2) { write32(MCBAR+DCALADDR, 0x04000000); write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } /* EMRS dll's enabled */ @@ -1051,9 +1048,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* fixme hard code AL additive latency */ write32(MCBAR+DCALADDR, 0x0b940001); write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } /* MRS reset dll's */ do_delay(); @@ -1064,9 +1060,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs+=2) { write32(MCBAR+DCALADDR, mode_reg); write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } /* Precharg all banks */ @@ -1076,25 +1071,22 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs+=2) { write32(MCBAR+DCALADDR, 0x04000000); write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } /* Do 2 refreshes */ do_delay(); for(cs=0;cs<8;cs+=2) { write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } do_delay(); for(cs=0;cs<8;cs+=2) { write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } do_delay(); /* for good luck do 6 more */ @@ -1127,9 +1119,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs+=2) { write32(MCBAR+DCALADDR, (mode_reg & ~(1<<24))); write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } /* Do only if DDR2 EMRS dll's enabled */ @@ -1137,9 +1128,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs+=2) { write32(MCBAR+DCALADDR, (0x0b940001)); write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } do_delay(); @@ -1173,9 +1163,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs+=2) { write32(MCBAR+DCALCSR, (0x810831d8 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } /* Bring memory subsystem on line */ diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c index 8967594..de3ffce 100644 --- a/src/northbridge/intel/i3100/raminit_ep80579.c +++ b/src/northbridge/intel/i3100/raminit_ep80579.c @@ -534,9 +534,8 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) write32(BAR+DCALADDR, 0x0b840001); write32(BAR+DCALCSR, 0x80000003 | ((i+1)<<21)); - data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while (data32 & 0x80000000); } } @@ -603,9 +602,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) udelay(16); write32(BAR+DCALCSR, (0x00000000 | ((cs+1)<<21))); write32(BAR+DCALCSR, (0x80000000 | ((cs+1)<<21))); - data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while (data32 & 0x80000000); } /* Apply NOP */ @@ -615,9 +613,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) print_debug_hex8(cs); print_debug("\n"); write32(BAR + DCALCSR, (0x80000000 | ((cs+1)<<21))); - data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while (data32 & 0x80000000); } /* Precharge all banks */ @@ -628,9 +625,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) print_debug("\n"); write32(BAR+DCALADDR, 0x04000000); write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21))); - data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while (data32 & 0x80000000); } /* EMRS: Enable DLLs, set OCD calibration mode to default */ @@ -641,9 +637,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) print_debug("\n"); write32(BAR+DCALADDR, 0x0b840001); write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21))); - data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while (data32 & 0x80000000); } /* MRS: Reset DLLs */ udelay(16); @@ -653,9 +648,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) print_debug("\n"); write32(BAR+DCALADDR, mode_reg); write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21))); - data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while (data32 & 0x80000000); } /* Precharge all banks */ @@ -666,9 +660,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) print_debug("\n"); write32(BAR+DCALADDR, 0x04000000); write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21))); - data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while (data32 & 0x80000000); } /* Do 2 refreshes */ @@ -679,9 +672,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) print_debug_hex8(cs); print_debug("\n"); write32(BAR+DCALCSR, (0x80000001 | ((cs+1)<<21))); - data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while (data32 & 0x80000000); } } @@ -693,9 +685,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) print_debug("\n"); write32(BAR+DCALADDR, (mode_reg & ~(1<<24))); write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21))); - data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while (data32 & 0x80000000); } /* EMRS: Enable DLLs */ @@ -706,9 +697,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) print_debug("\n"); write32(BAR+DCALADDR, 0x0b840001); write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21))); - data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while (data32 & 0x80000000); } udelay(16); @@ -729,9 +719,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) print_debug_hex8(cs); print_debug("\n"); write32(BAR+DCALCSR, (0x8000000c | ((cs+1)<<21))); - data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while (data32 & 0x80000000); } dump_dcal_regs(); @@ -756,9 +745,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) print_debug_hex8(cs); print_debug("\n"); write32(BAR+MBCSR, 0xa00000f0 | ((cs+1)<<20) | (0<<16)); - data32 = read32(BAR+MBCSR); - while (data32 & 0x80000000) - data32 = read32(BAR+MBCSR); + do data32 = read32(BAR+MBCSR); + while (data32 & 0x80000000); if (data32 & 0x40000000) print_debug("failed!\n"); }

1 0

Patch set updated: 79c690a Simplify kconfig handling some more
by Patrick Georgi 03 Sep '11

03 Sep '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/180 -gerrit commit 79c690a5e0b60f318837f152df0f7baf412f2149 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Sep 3 13:29:27 2011 +0200 Simplify kconfig handling some more Inspired by http://patchwork.coreboot.org/patch/1757/, this simplifies the build some more. Also fixes menuconfig if the compiler is picky about file naming order. Change-Id: I6d5b56a041bab1d844f4dd6ef00965736f9eb5b8 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/kconfig/Makefile | 97 ++++++++++--------------------------------------- 1 files changed, 20 insertions(+), 77 deletions(-) diff --git a/util/kconfig/Makefile b/util/kconfig/Makefile index 64a340c..70c3870 100644 --- a/util/kconfig/Makefile +++ b/util/kconfig/Makefile @@ -18,94 +18,42 @@ LIB_CONFIG := $(src)/lib.config HAVE_FILO_CONFIG := $(wildcard $(FILO_CONFIG)) HAVE_LIB_CONFIG := $(wildcard $(LIB_CONFIG)) -# We don't know how to cope with FILO config being present and -# libpayload config not. -$(if $(and $(HAVE_FILO_CONFIG),$(filter 0,$(words $(LIB_CONFIG)))), \ - FATAL:=1, \ - FATAL:=0) - -LIBPAYLOAD_CONFIG_PRE := echo "Libpayload config for FILO." \ - $(if $(HAVE_FILO_CONFIG),; mv $(FILO_CONFIG) $(FILO_CONFIG).temp) \ - $(if $(HAVE_LIB_CONFIG),; mv $(LIB_CONFIG) $(FILO_CONFIG)) - -LIBPAYLOAD_CONFIG_POST := mv $(FILO_CONFIG) $(LIB_CONFIG) \ - ; echo "Libpayload config done." \ - $(if $(HAVE_FILO_CONFIG),; mv $(FILO_CONFIG).temp $(FILO_CONFIG)) - -ifeq ($(FATAL),1) -xconfig gconfig menuconfig config oldconfig silentoldconfig: - echo "Lost libpayload config file." - rm -f $(FILO_CONFIG) -else -xconfig: prepare $(objk)/qconf - $(LIBPAYLOAD_CONFIG_PRE) - $(objk)/qconf $(LIBCONFIG_PATH)/Config.in - $(LIBPAYLOAD_CONFIG_POST) +libpayload_config_%: + echo "Libpayload config for FILO." + $(MAKE) -C $(LIBCONFIG_PATH) KCONFIG_CONFIG=$(LIB_CONFIG) $(patsubst libpayload_config_%,%,$@) + echo "Libpayload config done." + +xconfig: prepare $(objk)/qconf libpayload_config_xconfig $(objk)/qconf $(Kconfig) -gconfig: prepare $(objk)/gconf - $(LIBPAYLOAD_CONFIG_PRE) - $(objk)/gconf $(LIBCONFIG_PATH)/Config.in - $(LIBPAYLOAD_CONFIG_POST) +gconfig: prepare $(objk)/gconf libpayload_config_gconfig $(objk)/gconf $(Kconfig) -menuconfig: prepare $(objk)/mconf - $(LIBPAYLOAD_CONFIG_PRE) - $(objk)/mconf $(LIBCONFIG_PATH)/Config.in - $(LIBPAYLOAD_CONFIG_POST) +menuconfig: prepare $(objk)/mconf libpayload_config_menuconfig $(objk)/mconf $(Kconfig) -config: prepare $(objk)/conf - $(LIBPAYLOAD_CONFIG_PRE) - $(objk)/conf $(LIBCONFIG_PATH)/Config.in - $(LIBPAYLOAD_CONFIG_POST) +config: prepare $(objk)/conf libpayload_config_config $(objk)/conf $(Kconfig) -oldconfig: prepare $(objk)/conf - $(LIBPAYLOAD_CONFIG_PRE) - $(objk)/conf -o $(LIBCONFIG_PATH)/Config.in - $(LIBPAYLOAD_CONFIG_POST) +oldconfig: prepare $(objk)/conf libpayload_config_oldconfig $(objk)/conf -o $(Kconfig) -silentoldconfig: prepare $(objk)/conf - $(LIBPAYLOAD_CONFIG_PRE) - $(objk)/conf -s $(LIBCONFIG_PATH)/Config.in - $(LIBPAYLOAD_CONFIG_POST) +silentoldconfig: prepare $(objk)/conf libpayload_config_silentoldconfig $(objk)/conf -s $(Kconfig) -randconfig: prepare $(objk)/conf - $(LIBPAYLOAD_CONFIG_PRE) - $(objk)/conf -r $(LIBCONFIG_PATH)/Config.in - $(LIBPAYLOAD_CONFIG_POST) +randconfig: prepare $(objk)/conf libpayload_config_randconfig $(objk)/conf -r $(Kconfig) -allyesconfig: prepare $(objk)/conf - $(LIBPAYLOAD_CONFIG_PRE) - $(objk)/conf -y $(LIBCONFIG_PATH)/Config.in - $(LIBPAYLOAD_CONFIG_POST) +allyesconfig: prepare $(objk)/conf libpayload_config_allyesconfig $(objk)/conf -y $(Kconfig) -allnoconfig: prepare $(objk)/conf - $(LIBPAYLOAD_CONFIG_PRE) - $(objk)/conf -n $(LIBCONFIG_PATH)/Config.in - $(LIBPAYLOAD_CONFIG_POST) +allnoconfig: prepare $(objk)/conf libpayload_config_allnoconfig $(objk)/conf -n $(Kconfig) -allmodconfig: prepare $(objk)/conf - $(LIBPAYLOAD_CONFIG_PRE) - $(objk)/conf -m $(LIBCONFIG_PATH)/Config.in - $(LIBPAYLOAD_CONFIG_POST) +allmodconfig: prepare $(objk)/conf libpayload_config_allmodconfig $(objk)/conf -m $(Kconfig) -defconfig: prepare $(objk)/conf - $(LIBPAYLOAD_CONFIG_PRE) -ifeq ($(KBUILD_DEFCONFIG),) - $(objk)/conf -D $(LIBCONFIG_PATH)/configs/defconfig $(LIBCONFIG_PATH)/Config.in -else - @echo "*** Default configuration is based on '$(KBUILD_DEFCONFIG)'" - $(objk)/conf -D $(LIBCONFIG_PATH)/$(KBUILD_DEFCONFIG) $(LIBCONFIG_PATH)/Config.in -endif - $(LIBPAYLOAD_CONFIG_POST) +defconfig: prepare $(objk)/conf libpayload_config_defconfig ifeq ($(KBUILD_DEFCONFIG),) $(objk)/conf -d $(Kconfig) else @@ -113,14 +61,9 @@ else $(objk)/conf -D $(KBUILD_DEFCONFIG) $(Kconfig) endif -%_defconfig: prepare $(objk)/conf - $(LIBPAYLOAD_CONFIG_PRE) - $(objk)/conf -D $(LIBCONFIG_PATH)/configs/$@ $(LIBCONFIG_PATH)/Config.in - $(LIBPAYLOAD_CONFIG_POST) +%_defconfig: prepare $(objk)/conf libpayload_config_%_defconfig $(objk)/conf -D configs/$@ $(Kconfig) -endif # "FATAL" - # Help text used by make help help: @echo ' config - Update current config utilising a line-oriented program' @@ -341,11 +284,11 @@ endif $(objk)/qconf: $(patsubst %,$(objk)/%,$(qconf-cxxobjs)) \ $(patsubst %,$(objk)/%,$(qconf-objs)) - $(HOSTCXX) $(HOSTCXXFLAGS) $(HOSTLOADLIBES_qconf) -o $@ $^ + $(HOSTCXX) $(HOSTCXXFLAGS) -o $@ $^ $(HOSTLOADLIBES_qconf) $(objk)/gconf: $(patsubst %,$(objk)/%,$(gconf-objs)) - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLOADLIBES_gconf) -o $@ $^ + $(HOSTCC) $(HOSTCFLAGS) -o $@ $^ $(HOSTLOADLIBES_gconf) $(objk)/mconf: $(patsubst %,$(objk)/%,$(mconf-objs)) - $(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) $(HOST_LOADLIBES) -o $@ $^ + $(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -o $@ $^ $(HOST_LOADLIBES) $(objk)/conf: $(patsubst %,$(objk)/%,$(conf-objs)) $(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -o $@ $^

1 0

New patch to review: a81e32c Trivial compilation fix
by Patrick Georgi 03 Sep '11

03 Sep '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/181 -gerrit commit a81e32cd0ea95aeea75b894b00f0924f7d635216 Author: Aurélien <footplus(a)gmail.com> Date: Thu Sep 9 18:39:10 2010 +0200 Trivial compilation fix Change-Id: I9e1ef711b62a42b1ddbd620d09a9c19a6e1ff0db Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- main/grub/completions.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/main/grub/completions.c b/main/grub/completions.c index 6588301..c54a558 100644 --- a/main/grub/completions.c +++ b/main/grub/completions.c @@ -23,6 +23,7 @@ #include <config.h> #include <grub/shared.h> #define current_slice 0 +#define IS_PC_SLICE_TYPE_BSD(type) 0 static int do_completion; static int unique;

1 0

New patch to review: e869861 Utility for generating an Artecboot image
by Patrick Georgi 03 Sep '11

03 Sep '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/182 -gerrit commit e8698619be9024fef2babeaccebd7a7a65ce3f2f Author: Nathan Williams <nathan(a)traverse.com.au> Date: Mon Apr 4 01:36:13 2011 +0200 Utility for generating an Artecboot image This program outputs a binary file with artecboot header and Linux kernel that can be used with the FILO Artecboot loader. Change-Id: I855845fffae57472d027e20a8db25b19f106a488 Signed-off-by: Nathan Williams <nathan(a)traverse.com.au> Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/artecimage.c | 200 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 200 insertions(+), 0 deletions(-) diff --git a/util/artecimage.c b/util/artecimage.c new file mode 100644 index 0000000..ee282cc --- /dev/null +++ b/util/artecimage.c @@ -0,0 +1,200 @@ +#include <stdio.h> +#include <string.h> +#include <unistd.h> + +#define PROG_NAME "artecimage" +#define VERSION "1.1" + +#define BUFSIZE 512 + +// Artecboot header, gives information to loader + +#define ARTECBOOT_HEADER_MAGIC 0x10ADFACE +#define CURRENT_VERSION 0x0102 + +#define OS_UNKNOWN 0x00 +#define OS_LINUX 0x01 +#define OS_WINCE 0x02 + +#define FLAG_INITRD 0x0001 // if set, the loader will provide initrd to kernel +#define FLAG_FILESYSTEM 0x0002 // if set, the loader will use specified file names +#define FLAG_CMDLINE 0x0004 // if set, the loader will pass the new command line + +#define ABOOT_FILE_KERNEL "/kernel" +#define ABOOT_FILE_INITRD "/initrd" +#define ABOOT_FILE_HEADER "/header" + +#define DEV_SECTOR_SIZE 512 +#define DEV_SECTOR_BITS 9 + +typedef struct __attribute__ ((packed)) +{ + unsigned long magicHeader; + unsigned short bootVersion; + unsigned short headerSize; // also kernel image start + unsigned long imageSize; // NB! since 1.02 is the total image/partition size + unsigned long bitFlags; + unsigned short osType; + char cmdLine[256]; + unsigned long kernelStart; // used with Artecboot VFS / NULLFS + unsigned long kernelSize; // used with Artecboot VFS / NULLFS + unsigned long initrdStart; // used with Artecboot VFS / NULLFS + unsigned long initrdSize; // used with Artecboot VFS / NULLFS + char kernelFile[100]; // valid only with FLAG_FILESYSTEM + char initrdFile[100]; // valid only with FLAG_FILESYSTEM + +} ARTECBOOT_HEADER; + +void usage(void); + +int main(int argc, char **argv){ + ARTECBOOT_HEADER bootHdr; + FILE *BINFILE = 0; + FILE *KERNFILE = 0; + FILE *INITRDFILE = 0; + char buf[BUFSIZE]; + int c; + int i; + int verbose = 0; + + /* clear header */ + memset(&bootHdr, 0, sizeof(ARTECBOOT_HEADER)); + + while ((c = getopt(argc, argv, "c:hi:k:o:v")) != -1) { + switch(c) { + case 'c': + if (strlen(optarg) < sizeof(bootHdr.cmdLine)) { + strcpy(bootHdr.cmdLine, optarg); + bootHdr.bitFlags |= FLAG_CMDLINE; + } else { + usage(); + printf("\nCommand line exceeds %d char limit\n", (sizeof(bootHdr.cmdLine) - 1)); + return 1; + } + break; + case 'h': + usage(); + return 0; + break; + case 'i': + INITRDFILE = fopen(optarg,"r"); + if(INITRDFILE == NULL){ + usage(); + printf("\nError: Failed to open file '%s'\n\n", optarg); + return 1; + } + break; + case 'k': + KERNFILE = fopen(optarg,"r"); + if(KERNFILE == NULL){ + usage(); + printf("\nError: Failed to open file '%s'\n\n", optarg); + return 1; + } + break; + case 'o': + BINFILE = fopen(optarg,"w"); + if(BINFILE == NULL){ + usage(); + printf("\nError: Failed to open file '%s'\n\n", optarg); + return 1; + } + break; + case 'v': + verbose = 1; + break; + } + } + if(!BINFILE){ + usage(); + printf("\nError: No output file specified\n\n"); + return 1; + } + + if(!KERNFILE){ + usage(); + printf("\nError: No kernel image specified\n\n"); + return 1; + } + + bootHdr.magicHeader = ARTECBOOT_HEADER_MAGIC; + bootHdr.bootVersion = CURRENT_VERSION; + bootHdr.headerSize = sizeof(ARTECBOOT_HEADER); + + /* Get kernel image size */ + fseek(KERNFILE, 0L, SEEK_END); + bootHdr.imageSize = ftell(KERNFILE); + + bootHdr.kernelSize = bootHdr.imageSize; + bootHdr.kernelStart = DEV_SECTOR_SIZE; + + bootHdr.osType = OS_LINUX; + + if(INITRDFILE){ + /* Get initrd image size */ + fseek(INITRDFILE, 0L, SEEK_END); + bootHdr.initrdSize = ftell(INITRDFILE); + + /* Set INITRD flag */ + bootHdr.bitFlags |= FLAG_INITRD; + + /* Calculate start address (512 boundary) */ + bootHdr.initrdStart = (bootHdr.kernelStart + bootHdr.imageSize); + bootHdr.initrdStart = (bootHdr.initrdStart >> DEV_SECTOR_BITS) + 1; + bootHdr.initrdStart <<= DEV_SECTOR_BITS; + } + + fwrite(&bootHdr, 1, sizeof(ARTECBOOT_HEADER), BINFILE); + fseek(BINFILE, bootHdr.kernelStart, SEEK_SET); + + /* Copy kernel into output file */ + fseek(KERNFILE, 0, SEEK_SET); + while((i = fread(&buf, 1, BUFSIZE, KERNFILE)) != 0){ + fwrite(&buf, 1, i, BINFILE); + } + fclose(KERNFILE); + + if(INITRDFILE){ + fseek(BINFILE, bootHdr.initrdStart, SEEK_SET); + + /* Copy initrd into output file */ + fseek(INITRDFILE, 0, SEEK_SET); + while((i = fread(&buf, 1, BUFSIZE, INITRDFILE)) != 0){ + fwrite(&buf, 1, i, BINFILE); + } + fclose(INITRDFILE); + } + + fclose(BINFILE); + + if(verbose){ + printf("magicHeader: 0x%04lx\n", bootHdr.magicHeader); + printf("bootVersion: 0x%04x\n", bootHdr.bootVersion); + printf("headerSize: 0x%08x\n", bootHdr.headerSize); + printf("imageSize: 0x%08lx\n", bootHdr.imageSize); + printf("bitFlags: 0x%08lx\n", bootHdr.bitFlags); + printf("osType: 0x%04x\n", bootHdr.osType); + printf("cmdLine: %s\n", bootHdr.cmdLine); + printf("kernelStart: 0x%08lx\n", bootHdr.kernelStart); + printf("kernelSize: 0x%08lx\n", bootHdr.imageSize); + printf("initrdStart: 0x%08lx\n", bootHdr.initrdStart); + printf("initrdSize: 0x%08lx\n", bootHdr.initrdSize); + printf("kernelFile: %s\n", bootHdr.kernelFile); + printf("initrdFile: %s\n", bootHdr.initrdFile); + } + return 0; +} + +void usage(void) { + printf(PROG_NAME " v" VERSION "\n" + "Usage: " PROG_NAME " [-hv] [-c cmdline] [-i initrd] -k kernel -o outfile\n\n" + "Options:\n" + " -c cmdline Kernel command line (max 255 chars).\n" + " -h Display this help.\n" + " -i initrd initrd filename.\n" + " -k kernel Linux kernel filename.\n" + " -o outfile Write image to outfile.\n" + " -v Verbose.\n" + ); + return; +}

1 0

New patch to review: 1874079 Simplify kconfig handling some more
by Patrick Georgi 03 Sep '11

03 Sep '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/180 -gerrit commit 1874079af233466bf6988ac32748195028072dd2 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Sep 3 13:29:27 2011 +0200 Simplify kconfig handling some more Inspired by http://patchwork.coreboot.org/patch/1757/, this simplifies the build some more. Also fixes menuconfig if the compiler is picky about file naming order. Change-Id: I6d5b56a041bab1d844f4dd6ef00965736f9eb5b8 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/kconfig/Makefile | 91 +++++++++++-------------------------------------- 1 files changed, 20 insertions(+), 71 deletions(-) diff --git a/util/kconfig/Makefile b/util/kconfig/Makefile index 64a340c..17d7f46 100644 --- a/util/kconfig/Makefile +++ b/util/kconfig/Makefile @@ -24,88 +24,42 @@ $(if $(and $(HAVE_FILO_CONFIG),$(filter 0,$(words $(LIB_CONFIG)))), \ FATAL:=1, \ FATAL:=0) -LIBPAYLOAD_CONFIG_PRE := echo "Libpayload config for FILO." \ - $(if $(HAVE_FILO_CONFIG),; mv $(FILO_CONFIG) $(FILO_CONFIG).temp) \ - $(if $(HAVE_LIB_CONFIG),; mv $(LIB_CONFIG) $(FILO_CONFIG)) - -LIBPAYLOAD_CONFIG_POST := mv $(FILO_CONFIG) $(LIB_CONFIG) \ - ; echo "Libpayload config done." \ - $(if $(HAVE_FILO_CONFIG),; mv $(FILO_CONFIG).temp $(FILO_CONFIG)) - -ifeq ($(FATAL),1) -xconfig gconfig menuconfig config oldconfig silentoldconfig: - echo "Lost libpayload config file." - rm -f $(FILO_CONFIG) -else -xconfig: prepare $(objk)/qconf - $(LIBPAYLOAD_CONFIG_PRE) - $(objk)/qconf $(LIBCONFIG_PATH)/Config.in - $(LIBPAYLOAD_CONFIG_POST) +libpayload_config_%: + echo "Libpayload config for FILO." + $(MAKE) -C $(LIBCONFIG_PATH) KCONFIG_CONFIG=$(LIB_CONFIG) $(patsubst libpayload_config_%,%,$@) + echo "Libpayload config done." + +xconfig: prepare $(objk)/qconf libpayload_config_xconfig $(objk)/qconf $(Kconfig) -gconfig: prepare $(objk)/gconf - $(LIBPAYLOAD_CONFIG_PRE) - $(objk)/gconf $(LIBCONFIG_PATH)/Config.in - $(LIBPAYLOAD_CONFIG_POST) +gconfig: prepare $(objk)/gconf libpayload_config_gconfig $(objk)/gconf $(Kconfig) -menuconfig: prepare $(objk)/mconf - $(LIBPAYLOAD_CONFIG_PRE) - $(objk)/mconf $(LIBCONFIG_PATH)/Config.in - $(LIBPAYLOAD_CONFIG_POST) +menuconfig: prepare $(objk)/mconf libpayload_config_menuconfig $(objk)/mconf $(Kconfig) -config: prepare $(objk)/conf - $(LIBPAYLOAD_CONFIG_PRE) - $(objk)/conf $(LIBCONFIG_PATH)/Config.in - $(LIBPAYLOAD_CONFIG_POST) +config: prepare $(objk)/conf libpayload_config_config $(objk)/conf $(Kconfig) -oldconfig: prepare $(objk)/conf - $(LIBPAYLOAD_CONFIG_PRE) - $(objk)/conf -o $(LIBCONFIG_PATH)/Config.in - $(LIBPAYLOAD_CONFIG_POST) +oldconfig: prepare $(objk)/conf libpayload_config_oldconfig $(objk)/conf -o $(Kconfig) -silentoldconfig: prepare $(objk)/conf - $(LIBPAYLOAD_CONFIG_PRE) - $(objk)/conf -s $(LIBCONFIG_PATH)/Config.in - $(LIBPAYLOAD_CONFIG_POST) +silentoldconfig: prepare $(objk)/conf libpayload_config_silentoldconfig $(objk)/conf -s $(Kconfig) -randconfig: prepare $(objk)/conf - $(LIBPAYLOAD_CONFIG_PRE) - $(objk)/conf -r $(LIBCONFIG_PATH)/Config.in - $(LIBPAYLOAD_CONFIG_POST) +randconfig: prepare $(objk)/conf libpayload_config_randconfig $(objk)/conf -r $(Kconfig) -allyesconfig: prepare $(objk)/conf - $(LIBPAYLOAD_CONFIG_PRE) - $(objk)/conf -y $(LIBCONFIG_PATH)/Config.in - $(LIBPAYLOAD_CONFIG_POST) +allyesconfig: prepare $(objk)/conf libpayload_config_allyesconfig $(objk)/conf -y $(Kconfig) -allnoconfig: prepare $(objk)/conf - $(LIBPAYLOAD_CONFIG_PRE) - $(objk)/conf -n $(LIBCONFIG_PATH)/Config.in - $(LIBPAYLOAD_CONFIG_POST) +allnoconfig: prepare $(objk)/conf libpayload_config_allnoconfig $(objk)/conf -n $(Kconfig) -allmodconfig: prepare $(objk)/conf - $(LIBPAYLOAD_CONFIG_PRE) - $(objk)/conf -m $(LIBCONFIG_PATH)/Config.in - $(LIBPAYLOAD_CONFIG_POST) +allmodconfig: prepare $(objk)/conf libpayload_config_allmodconfig $(objk)/conf -m $(Kconfig) -defconfig: prepare $(objk)/conf - $(LIBPAYLOAD_CONFIG_PRE) -ifeq ($(KBUILD_DEFCONFIG),) - $(objk)/conf -D $(LIBCONFIG_PATH)/configs/defconfig $(LIBCONFIG_PATH)/Config.in -else - @echo "*** Default configuration is based on '$(KBUILD_DEFCONFIG)'" - $(objk)/conf -D $(LIBCONFIG_PATH)/$(KBUILD_DEFCONFIG) $(LIBCONFIG_PATH)/Config.in -endif - $(LIBPAYLOAD_CONFIG_POST) +defconfig: prepare $(objk)/conf libpayload_config_defconfig ifeq ($(KBUILD_DEFCONFIG),) $(objk)/conf -d $(Kconfig) else @@ -113,14 +67,9 @@ else $(objk)/conf -D $(KBUILD_DEFCONFIG) $(Kconfig) endif -%_defconfig: prepare $(objk)/conf - $(LIBPAYLOAD_CONFIG_PRE) - $(objk)/conf -D $(LIBCONFIG_PATH)/configs/$@ $(LIBCONFIG_PATH)/Config.in - $(LIBPAYLOAD_CONFIG_POST) +%_defconfig: prepare $(objk)/conf libpayload_config_%_defconfig $(objk)/conf -D configs/$@ $(Kconfig) -endif # "FATAL" - # Help text used by make help help: @echo ' config - Update current config utilising a line-oriented program' @@ -341,11 +290,11 @@ endif $(objk)/qconf: $(patsubst %,$(objk)/%,$(qconf-cxxobjs)) \ $(patsubst %,$(objk)/%,$(qconf-objs)) - $(HOSTCXX) $(HOSTCXXFLAGS) $(HOSTLOADLIBES_qconf) -o $@ $^ + $(HOSTCXX) $(HOSTCXXFLAGS) -o $@ $^ $(HOSTLOADLIBES_qconf) $(objk)/gconf: $(patsubst %,$(objk)/%,$(gconf-objs)) - $(HOSTCC) $(HOSTCFLAGS) $(HOSTLOADLIBES_gconf) -o $@ $^ + $(HOSTCC) $(HOSTCFLAGS) -o $@ $^ $(HOSTLOADLIBES_gconf) $(objk)/mconf: $(patsubst %,$(objk)/%,$(mconf-objs)) - $(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) $(HOST_LOADLIBES) -o $@ $^ + $(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -o $@ $^ $(HOST_LOADLIBES) $(objk)/conf: $(patsubst %,$(objk)/%,$(conf-objs)) $(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -o $@ $^

1 0

Patch set updated: 7700f5d Add support utils for tracing
by Rudolf Marek 03 Sep '11

03 Sep '11

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/179 -gerrit commit 7700f5df07fd80c65eced4deb7d0c6051fd9f2b6 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Fri Sep 2 23:34:15 2011 +0200 Add support utils for tracing Following patch adds a userspace util genprof which is able to convert the console printed traces to gmon.out file used by gprof & friends. The log2dress will replace the adresses in logfile with a line numbers. Change-Id: I9f716f3ff2522a24fbc844a1dd5e32ef49b540c5 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- util/genprof/Makefile | 12 +++++ util/genprof/README | 31 ++++++++++++++ util/genprof/genprof.c | 108 ++++++++++++++++++++++++++++++++++++++++++++++++ util/genprof/log2dress | 20 +++++++++ 4 files changed, 171 insertions(+), 0 deletions(-) diff --git a/util/genprof/Makefile b/util/genprof/Makefile new file mode 100644 index 0000000..2ec77c9 --- /dev/null +++ b/util/genprof/Makefile @@ -0,0 +1,12 @@ +CC=gcc +CFLAGS=-O2 -Wall + +all: genprof + +genprof: genprof.o + $(CC) $(CFLAGS) -o genprof $^ + +clean: + rm -f genprof *.o *~ + +distclean: clean diff --git a/util/genprof/README b/util/genprof/README new file mode 100644 index 0000000..3483a2b --- /dev/null +++ b/util/genprof/README @@ -0,0 +1,31 @@ +Function tracing +---------------- + +Enable CONFIG_TRACE in debug menu. Run the compiled image on target. You will get +a log with a lot of lines like: + +... +~0x001072e8(0x00100099) +~0x00108bc0(0x0010730a) +... + +First address is address of function which was just entered, the second address +is address of functions which call that. + +You can use the log2dress to dress the log again: + +... +src/arch/x86/lib/c_start.S:85 calls /home/ruik/coreboot/src/boot/selfboot.c:367 +/home/ruik/coreboot/src/boot/selfboot.c:370 calls /home/ruik/coreboot/src/devices/device.c:325 +... + +Alternatively, you can use genprof to generate a gmon.out file, which can be used +by gprof to show the call traces. You will need to install uthash library to compile +that. + +Great use is: + +make +./genprof /tmp/yourlog ; gprof ../../build/coreboot_ram | ./gprof2dot.py -e0 -n0 | dot -Tpng -o output.png + +Which generates a PNG with a call graph. diff --git a/util/genprof/genprof.c b/util/genprof/genprof.c new file mode 100644 index 0000000..9fc39da --- /dev/null +++ b/util/genprof/genprof.c @@ -0,0 +1,108 @@ +#include <stdio.h> +#include <uthash.h> +#include <sys/gmon_out.h> +#include <stdlib.h> + +#define GMON_SEC "seconds s" +uint32_t mineip = 0xffffffff; +uint32_t maxeip = 0; + +/* a hash structure to hold the arc */ +struct arec { + uint32_t eip; + uint32_t from; + uint32_t count; + UT_hash_handle hh; +}; + +struct arec *arc = NULL; + +void note_arc(uint32_t eip, uint32_t from) +{ + struct arec *s; + + HASH_FIND_INT(arc, &eip, s); + if (s == NULL) { + s = malloc(sizeof(struct arec)); + s->eip = eip; + s->from = from; + s->count = 1; + if (eip > maxeip) + maxeip = eip; + if (eip < mineip) + maxeip = eip; + + HASH_ADD_INT(arc, eip, s); + } else { + s->count++; + } +} + +int main(int argc, char* argv[]) +{ + FILE *f, *fo; + struct arec *s; + uint32_t eip, from, tmp; + uint8_t tag; + uint16_t hit; + + if ( argc < 2 ) + { + fprintf(stderr, "Please specify the coreboot trace log as parameter\n"); + return 1; + } + + f = fopen(argv[1], "r"); + fo = fopen("gmon.out", "w+"); + + if ((f == NULL) || (fo == NULL)) { + fprintf(stderr, "Unable to manipulate with the input file\n"); + return 1; + } + + while (!feof(f)) { + if (fscanf(f, "~%x(%x)%*[^\n]\n", &eip, &from) == 2) { + note_arc(eip, from); + } else if (fscanf(f, "%*c~%x(%x)%*[^\n]\n", &eip, &from) == 2) { + note_arc(eip, from); + } else { + /* just drop a line */ + tmp = fscanf(f, "%*[^\n]\n"); + } + } + + /* write gprof header */ + fwrite(GMON_MAGIC, 1, sizeof(GMON_MAGIC) - 1, fo); + tmp = GMON_VERSION; + fwrite(&tmp, 1, sizeof(tmp), fo); + tmp = 0; + fwrite(&tmp, 1, sizeof(tmp), fo); + fwrite(&tmp, 1, sizeof(tmp), fo); + fwrite(&tmp, 1, sizeof(tmp), fo); + /* write fake histogram */ + tag = GMON_TAG_TIME_HIST; + fwrite(&tag, 1, sizeof(tag), fo); + fwrite(&mineip, 1, sizeof(mineip), fo); + fwrite(&maxeip, 1, sizeof(maxeip), fo); + /* size of histogram */ + tmp = 1; + fwrite(&tmp, 1, sizeof(tmp), fo); + /* prof rate */ + tmp = 1000; + fwrite(&tmp, 1, sizeof(tmp), fo); + fwrite(GMON_SEC, 1, sizeof(GMON_SEC) - 1, fo); + hit = 1; + fwrite(&hit, 1, sizeof(hit), fo); + + /* write call graph data */ + tag = GMON_TAG_CG_ARC; + for (s = arc; s != NULL; s = s->hh.next) { + fwrite(&tag, 1, sizeof(tag), fo); + fwrite(&s->from, 1, sizeof(s->from), fo); + fwrite(&s->eip, 1, sizeof(s->eip), fo); + fwrite(&s->count, 1, sizeof(s->count), fo); + } + + fclose(fo); + return 0; +} diff --git a/util/genprof/log2dress b/util/genprof/log2dress new file mode 100755 index 0000000..429f846 --- /dev/null +++ b/util/genprof/log2dress @@ -0,0 +1,20 @@ +#!/bin/bash +#Parse a log and get back the function names and line numbers +#Provide a log file as first argument + +#Please rewrite to something more saner ! + +cat $1 | while read line ; do +A=`echo $line | cut -c 1` + +if [ "$A" = '~' ] ; then +FROM=`echo $line | tr \~ $ | tr $ $ | awk -F\( '{print $3}'` +TO=`echo $line | tr \~ \( | tr $ \(|awk -F\( '{print $2}'` +addr2line -e ../../build/coreboot_ram.debug "$FROM" | tr -d "\n" +echo -n " calls " +addr2line -e ../../build/coreboot_ram.debug "$TO" +else +echo "$line" +fi + +done

1 0

Patch set updated: 5ef3380 Add support for the tracing infastructure in coreboot.
by Rudolf Marek 03 Sep '11

03 Sep '11

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/178 -gerrit commit 5ef3380428f35b9196ecfe7f52281bb26080c364 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Fri Sep 2 23:23:41 2011 +0200 Add support for the tracing infastructure in coreboot. The compiler is forced to emmit special functions on every entry/exit of the function. Add a compile time option to support it. Function entries will be printed in the console. The CONFIG_TRACE has more documentation. Patch for userspace tools will follow. Change-Id: I2cbeb3f104892b034c8756f86ed05bf71187c3f3 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- Makefile.inc | 4 +++ src/Kconfig | 9 ++++++++ src/console/printk.c | 3 ++ src/console/vsprintf.c | 3 ++ src/include/trace.h | 54 ++++++++++++++++++++++++++++++++++++++++++++++++ src/lib/Makefile.inc | 1 + src/lib/trace.c | 39 ++++++++++++++++++++++++++++++++++ src/lib/uart8250.c | 4 +++ 8 files changed, 117 insertions(+), 0 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 37e4fb6..167ab5b 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -51,6 +51,10 @@ classes-y := ramstage romstage driver smm romstage-c-ccopts:=-D__PRE_RAM__ romstage-S-ccopts:=-D__PRE_RAM__ +ifeq ($(CONFIG_TRACE),y) +ramstage-c-ccopts:= -finstrument-functions +endif + smm-c-ccopts:=-D__SMM__ smm-S-ccopts:=-D__SMM__ diff --git a/src/Kconfig b/src/Kconfig index f96c903..e9ceed5 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -845,6 +845,15 @@ config LLSHELL Put llshell() in your (romstage) code to start the shell. See src/arch/x86/llshell/llshell.inc for details. +config TRACE + bool "Trace function calls" + default n + help + If enabled, every function will print information to console once + the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd) + the 0xaaaabbbb is the actual function and 0xccccdddd is EIP + of calling function. Please note some printk releated functions + are omitted from trace to have good looking console dumps. endmenu config LIFT_BSP_APIC_ID diff --git a/src/console/printk.c b/src/console/printk.c index 488d4e5..7549088 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -8,6 +8,7 @@ #include <smp/spinlock.h> #include <console/vtxprintf.h> #include <console/console.h> +#include <trace.h> int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; int default_console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; @@ -23,6 +24,7 @@ int do_printk(int msg_level, const char *fmt, ...) return 0; } + DISABLE_TRACE; spin_lock(&console_lock); va_start(args, fmt); @@ -32,6 +34,7 @@ int do_printk(int msg_level, const char *fmt, ...) console_tx_flush(); spin_unlock(&console_lock); + ENABLE_TRACE; return i; } diff --git a/src/console/vsprintf.c b/src/console/vsprintf.c index 4a74523..435401b 100644 --- a/src/console/vsprintf.c +++ b/src/console/vsprintf.c @@ -22,6 +22,7 @@ #include <string.h> #include <smp/spinlock.h> #include <console/vtxprintf.h> +#include <trace.h> DECLARE_SPIN_LOCK(vsprintf_lock) @@ -37,6 +38,7 @@ static int vsprintf(char *buf, const char *fmt, va_list args) { int i; + DISABLE_TRACE; spin_lock(&vsprintf_lock); str_buf = buf; @@ -44,6 +46,7 @@ static int vsprintf(char *buf, const char *fmt, va_list args) *str_buf = '\0'; spin_unlock(&vsprintf_lock); + ENABLE_TRACE; return i; } diff --git a/src/include/trace.h b/src/include/trace.h new file mode 100644 index 0000000..ff5b6c2 --- /dev/null +++ b/src/include/trace.h @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __TRACE_H +#define __TRACE_H + + +#ifdef __PRE_RAM__ + +#define DISABLE_TRACE +#define ENABLE_TRACE +#define DISABLE_TRACE_ON_FUNCTION + +#else /* !__PRE_RAM__ */ + +#if CONFIG_TRACE + +void __cyg_profile_func_enter( void *, void * ) + __attribute__ ((no_instrument_function)); + +void __cyg_profile_func_exit( void *, void * ) + __attribute__ ((no_instrument_function)); + +extern volatile int trace_dis; + +#define DISABLE_TRACE do { trace_dis = 1; } while (0); +#define ENABLE_TRACE do { trace_dis = 0; } while (0); +#define DISABLE_TRACE_ON_FUNCTION __attribute__ ((no_instrument_function)); + +#else /* !CONFIG_TRACE */ + +#define DISABLE_TRACE +#define ENABLE_TRACE +#define DISABLE_TRACE_ON_FUNCTION + +#endif +#endif +#endif diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 54935ca..b207ffe 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -33,6 +33,7 @@ ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c ramstage-$(CONFIG_USBDEBUG) += usbdebug.c ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c +ramstage-$(CONFIG_TRACE) += trace.c driver-$(CONFIG_CONSOLE_NE2K) += ne2k.c diff --git a/src/lib/trace.c b/src/lib/trace.c new file mode 100644 index 0000000..8736c82 --- /dev/null +++ b/src/lib/trace.c @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <console/console.h> +#include <trace.h> + +int volatile trace_dis = 0; + +void __cyg_profile_func_enter( void *func, void *callsite) +{ + + if (trace_dis) + return; + + DISABLE_TRACE + printk(BIOS_INFO, "~0x%08x(0x%08x)\n", (uint32_t) func, (uint32_t) callsite); + ENABLE_TRACE +} + +void __cyg_profile_func_exit( void *func, void *callsite ) +{ +} diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c index e7ddd0b..b224671 100644 --- a/src/lib/uart8250.c +++ b/src/lib/uart8250.c @@ -21,6 +21,8 @@ #include <arch/io.h> #include <uart8250.h> #include <pc80/mc146818rtc.h> +#include <trace.h> + #if CONFIG_USE_OPTION_TABLE #include "option_table.h" #endif @@ -69,6 +71,7 @@ unsigned char uart8250_rx_byte(unsigned base_port) void uart8250_init(unsigned base_port, unsigned divisor) { + DISABLE_TRACE; /* Disable interrupts */ outb(0x0, base_port + UART_IER); /* Enable FIFOs */ @@ -86,6 +89,7 @@ void uart8250_init(unsigned base_port, unsigned divisor) /* Set to 3 for 8N1 */ outb(CONFIG_TTYS0_LCS, base_port + UART_LCR); + ENABLE_TRACE; } void uart_init(void)

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot September 2011