coreboot September 2011

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Patch set updated: d40a6ca Use ACPI table area to store cbmem_toc pointer needed for resume
by Patrick Georgi 04 Sep '11

04 Sep '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/189 -gerrit commit d40a6caa2a5ab1df3bdb3f5a12f848289afd063d Author: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Date: Mon Dec 13 22:42:48 2010 +0100 Use ACPI table area to store cbmem_toc pointer needed for resume This adds a cbmem_toc_ptr_t structure, which is written just below the FADT, so we can find it using the FADP information. The actual writing is only implemented for the Intel 82371EB southbridge. Also adds code to acpi.c resume codepath to use this pointer when the chipset has not overridden the weak get_cbmem_toc() function. Effectively the latter part affects all boards that already implement ACPI S2 or S3 resume, but shouldn't change behaviour since none of them generate the structure: asus/m2v asus/m4a785-m asus/m2v-mx_se gigabyte/ma78gm gigabyte/ma785gmt jetway/pa78vm5 iwill/dk8_htx asrock/939a785gmh amd/dbm690t amd/mahogany amd/tilapia_fam10 amd/pistachio amd/serengeti_cheetah_fam10 amd/serengeti_cheetah amd/mahogany_fam10 kontron/kt690 iei/kino-780am2-fam10 technexion/tim5690 technexion/tim8690 Change-Id: I9a0eca24d595b9d01d1ba7c81cc7fa0f05ae9229 Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/arch/x86/boot/acpi.c | 12 ++++++++++++ src/include/cbmem.h | 7 +++++++ src/lib/cbmem.c | 5 ++++- src/southbridge/intel/i82371eb/acpi_tables.c | 14 ++++++++++++-- 4 files changed, 35 insertions(+), 3 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index f1be034..abafb04 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -517,6 +517,7 @@ void *acpi_find_wakeup_vector(void) acpi_rsdt_t *rsdt; acpi_facs_t *facs; acpi_fadt_t *fadt; + cbmem_toc_ptr_t *cbmem_tocp; void *wake_vec; int i; @@ -537,11 +538,22 @@ void *acpi_find_wakeup_vector(void) return NULL; printk(BIOS_DEBUG, "RSDP found at %p\n", rsdp); + cbmem_tocp = (cbmem_toc_ptr_t *)(rsdp->rsdt_address - sizeof(cbmem_toc_ptr_t)); rsdt = (acpi_rsdt_t *) rsdp->rsdt_address; end = (char *)rsdt + rsdt->header.length; printk(BIOS_DEBUG, "RSDT found at %p ends at %p\n", rsdt, end); + if (get_cbmem_toc() == 0) { + if (cbmem_tocp->sig != CBMEM_TOC_PTR_SIG) { + printk(BIOS_DEBUG, "cbmem toc pointer not found at %p (sig %08x sz %lu)\n", cbmem_tocp, cbmem_tocp->sig, sizeof(cbmem_toc_ptr_t)); + return NULL; + } + set_cbmem_toc(cbmem_tocp->ptr); + } else { + printk(BIOS_DEBUG, "cbmem toc is at %p\n", get_cbmem_toc()); + } + for (i = 0; ((char *)&rsdt->entry[i]) < end; i++) { fadt = (acpi_fadt_t *)rsdt->entry[i]; if (strncmp((char *)fadt, "FACP", 4) == 0) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 7c5ec07..6bafa1e 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -41,6 +41,13 @@ extern uint64_t high_tables_base, high_tables_size; #define CBMEM_ID_SMBIOS 0x534d4254 #define CBMEM_ID_NONE 0x00000000 +#define CBMEM_TOC_PTR_SIG 0x43425443 + +typedef struct cbmem_toc_ptr { + u32 sig; + void *ptr; +} __attribute__((packed)) cbmem_toc_ptr_t; + void cbmem_initialize(void); void cbmem_init(u64 baseaddr, u64 size); diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 202f521..516f557 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -39,6 +39,9 @@ struct cbmem_entry { #ifndef __PRE_RAM__ static struct cbmem_entry *bss_cbmem_toc; +/* chipset can override get/set_cbmem_toc to store the cbmem_toc address + * in nvram if available */ + struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) { return bss_cbmem_toc; @@ -46,7 +49,7 @@ struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) void __attribute__((weak)) set_cbmem_toc(struct cbmem_entry * x) { - /* do nothing, this should be called by chipset to save TOC in NVRAM */ + bss_cbmem_toc = x; } #else diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c index 2173a3d..1291c2d 100644 --- a/src/southbridge/intel/i82371eb/acpi_tables.c +++ b/src/southbridge/intel/i82371eb/acpi_tables.c @@ -26,6 +26,7 @@ #include <arch/smp/mpspec.h> #include <device/device.h> #include <device/pci_ids.h> +#include <cbmem.h> #include "i82371eb.h" extern const unsigned char AmlCode[]; @@ -104,6 +105,7 @@ unsigned long __attribute__((weak)) acpi_fill_ssdt_generator(unsigned long curre unsigned long __attribute__((weak)) write_acpi_tables(unsigned long start) { unsigned long current; + cbmem_toc_ptr_t *cbmem_tocp; acpi_rsdp_t *rsdp; acpi_rsdt_t *rsdt; acpi_fadt_t *fadt; @@ -113,20 +115,28 @@ unsigned long __attribute__((weak)) write_acpi_tables(unsigned long start) acpi_header_t *dsdt; /* Align ACPI tables to 16 byte. */ - start = (start + 0x0f) & -0x10; - current = start; + current = ALIGN(start, 16); printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); /* We need at least an RSDP and an RSDT table. */ rsdp = (acpi_rsdp_t *) current; current += sizeof(acpi_rsdp_t); + + /* put cbmem toc ptr structure directly below rsdt */ + printk(BIOS_INFO, "ACPI: Writing cbmem_toc pointer at %lx...\n", current); + cbmem_tocp = (cbmem_toc_ptr_t *) current; + current += sizeof(cbmem_toc_ptr_t); + rsdt = (acpi_rsdt_t *) current; current += sizeof(acpi_rsdt_t); /* Clear all table memory. */ memset((void *) start, 0, current - start); + cbmem_tocp->sig = CBMEM_TOC_PTR_SIG; + cbmem_tocp->ptr = get_cbmem_toc(); + acpi_write_rsdp(rsdp, rsdt, NULL); acpi_write_rsdt(rsdt);

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New patch to review: aa0e057 Use ACPI table area to store cbmem_toc pointer needed for resume
by Patrick Georgi 04 Sep '11

04 Sep '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/189 -gerrit commit aa0e057d044217988052c580cc3c156e05296d48 Author: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Date: Mon Dec 13 22:42:48 2010 +0100 Use ACPI table area to store cbmem_toc pointer needed for resume This adds a cbmem_toc_ptr_t structure, which is written just below the FADT, so we can find it using the FADP information. The actual writing is only implemented for the Intel 82371EB southbridge. Also adds code to acpi.c resume codepath to use this pointer when the chipset has not overridden the weak get_cbmem_toc() function. Effectively the latter part affects all boards that already implement ACPI S2 or S3 resume, but shouldn't change behaviour since none of them generate the structure: asus/m2v asus/m4a785-m asus/m2v-mx_se gigabyte/ma78gm gigabyte/ma785gmt jetway/pa78vm5 iwill/dk8_htx asrock/939a785gmh amd/dbm690t amd/mahogany amd/tilapia_fam10 amd/pistachio amd/serengeti_cheetah_fam10 amd/serengeti_cheetah amd/mahogany_fam10 kontron/kt690 iei/kino-780am2-fam10 technexion/tim5690 technexion/tim8690 Change-Id: I9a0eca24d595b9d01d1ba7c81cc7fa0f05ae9229 Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/arch/x86/boot/acpi.c | 12 ++++++++++++ src/include/cbmem.h | 7 +++++++ src/lib/cbmem.c | 5 ++++- src/southbridge/intel/i82371eb/acpi_tables.c | 14 ++++++++++++-- 4 files changed, 35 insertions(+), 3 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index f1be034..8baeaa4 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -517,6 +517,7 @@ void *acpi_find_wakeup_vector(void) acpi_rsdt_t *rsdt; acpi_facs_t *facs; acpi_fadt_t *fadt; + cbmem_toc_ptr_t *cbmem_tocp; void *wake_vec; int i; @@ -537,11 +538,22 @@ void *acpi_find_wakeup_vector(void) return NULL; printk(BIOS_DEBUG, "RSDP found at %p\n", rsdp); + cbmem_tocp = (cbmem_toc_ptr_t *)(rsdp->rsdt_address - sizeof(cbmem_toc_ptr_t)); rsdt = (acpi_rsdt_t *) rsdp->rsdt_address; end = (char *)rsdt + rsdt->header.length; printk(BIOS_DEBUG, "RSDT found at %p ends at %p\n", rsdt, end); + if (get_cbmem_toc() == 0) { + if (cbmem_tocp->sig != CBMEM_TOC_PTR_SIG) { + printk(BIOS_DEBUG, "cbmem toc pointer not found at %p (sig %08x sz %d)\n", cbmem_tocp, cbmem_tocp->sig, sizeof(cbmem_toc_ptr_t)); + return NULL; + } + set_cbmem_toc(cbmem_tocp->ptr); + } else { + printk(BIOS_DEBUG, "cbmem toc is at %p\n", get_cbmem_toc()); + } + for (i = 0; ((char *)&rsdt->entry[i]) < end; i++) { fadt = (acpi_fadt_t *)rsdt->entry[i]; if (strncmp((char *)fadt, "FACP", 4) == 0) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 7c5ec07..6bafa1e 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -41,6 +41,13 @@ extern uint64_t high_tables_base, high_tables_size; #define CBMEM_ID_SMBIOS 0x534d4254 #define CBMEM_ID_NONE 0x00000000 +#define CBMEM_TOC_PTR_SIG 0x43425443 + +typedef struct cbmem_toc_ptr { + u32 sig; + void *ptr; +} __attribute__((packed)) cbmem_toc_ptr_t; + void cbmem_initialize(void); void cbmem_init(u64 baseaddr, u64 size); diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 202f521..516f557 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -39,6 +39,9 @@ struct cbmem_entry { #ifndef __PRE_RAM__ static struct cbmem_entry *bss_cbmem_toc; +/* chipset can override get/set_cbmem_toc to store the cbmem_toc address + * in nvram if available */ + struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) { return bss_cbmem_toc; @@ -46,7 +49,7 @@ struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) void __attribute__((weak)) set_cbmem_toc(struct cbmem_entry * x) { - /* do nothing, this should be called by chipset to save TOC in NVRAM */ + bss_cbmem_toc = x; } #else diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c index 2173a3d..1291c2d 100644 --- a/src/southbridge/intel/i82371eb/acpi_tables.c +++ b/src/southbridge/intel/i82371eb/acpi_tables.c @@ -26,6 +26,7 @@ #include <arch/smp/mpspec.h> #include <device/device.h> #include <device/pci_ids.h> +#include <cbmem.h> #include "i82371eb.h" extern const unsigned char AmlCode[]; @@ -104,6 +105,7 @@ unsigned long __attribute__((weak)) acpi_fill_ssdt_generator(unsigned long curre unsigned long __attribute__((weak)) write_acpi_tables(unsigned long start) { unsigned long current; + cbmem_toc_ptr_t *cbmem_tocp; acpi_rsdp_t *rsdp; acpi_rsdt_t *rsdt; acpi_fadt_t *fadt; @@ -113,20 +115,28 @@ unsigned long __attribute__((weak)) write_acpi_tables(unsigned long start) acpi_header_t *dsdt; /* Align ACPI tables to 16 byte. */ - start = (start + 0x0f) & -0x10; - current = start; + current = ALIGN(start, 16); printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); /* We need at least an RSDP and an RSDT table. */ rsdp = (acpi_rsdp_t *) current; current += sizeof(acpi_rsdp_t); + + /* put cbmem toc ptr structure directly below rsdt */ + printk(BIOS_INFO, "ACPI: Writing cbmem_toc pointer at %lx...\n", current); + cbmem_tocp = (cbmem_toc_ptr_t *) current; + current += sizeof(cbmem_toc_ptr_t); + rsdt = (acpi_rsdt_t *) current; current += sizeof(acpi_rsdt_t); /* Clear all table memory. */ memset((void *) start, 0, current - start); + cbmem_tocp->sig = CBMEM_TOC_PTR_SIG; + cbmem_tocp->ptr = get_cbmem_toc(); + acpi_write_rsdp(rsdp, rsdt, NULL); acpi_write_rsdt(rsdt);

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New patch to review: 0e277fb Add acpi_get_sleep_type() to i82371eb and P2B _PTS/_WAK methods
by Patrick Georgi 04 Sep '11

04 Sep '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/188 -gerrit commit 0e277fb131ed9eee75c1b1c6641b2ac7c2635165 Author: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Date: Mon Dec 13 22:39:46 2010 +0100 Add acpi_get_sleep_type() to i82371eb and P2B _PTS/_WAK methods Build fix for src/arch/i386/boot/acpi.c if !CONFIG_SMP Also check for acpi_slp_type 2 in acpi_is_wakeup, since S2 uses the same acpi wakeup vector as S3. Add _PTS/_WAK methods to turn off/on the CPU/case fans and blink the power LED while sleeping. acpi_get_sleep_type() is in a seperate file i82371eb_wakeup.c because it is used in both romstage and ramstage after patch 3/3, whereas i82371eb_early_pm.c is used only in romstage. I used the name acpi_get_sleep_type instead of acpi_is_wakeup_early because I think acpi_is_wakeup_early is a bit misleading as a name since it doesn't return a boolean value. Other chipsets so far only ever set acpi_slp_type to 0 and 3, so the added check for acpi_slp_type == 2 (resume from S2) should not change behaviour of other boards: northbridge/intel/i945/northbridge.c:256:extern u8 acpi_slp_type; northbridge/intel/i945/northbridge.c:263: acpi_slp_type=0; northbridge/intel/i945/northbridge.c:267: acpi_slp_type=3; northbridge/intel/i945/northbridge.c:271: acpi_slp_type=0; southbridge/intel/i82801gx/i82801gx_lpc.c:171:extern u8 acpi_slp_type; southbridge/via/vt8237r/vt8237r_lpc.c:149:extern u8 acpi_slp_type; southbridge/via/vt8237r/vt8237r_lpc.c:238: acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; southbridge/via/vt8237r/vt8237r_lpc.c:239: printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type); Change-Id: I13feff0b8f49aa988e5467cdbef02981f0a6be8a Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/arch/x86/boot/acpi.c | 7 +++- src/lib/cbmem.c | 4 +- src/mainboard/asus/p2b/dsdt.asl | 56 ++++++++++++++++++------- src/southbridge/intel/i82371eb/Kconfig | 1 + src/southbridge/intel/i82371eb/Makefile.inc | 1 + src/southbridge/intel/i82371eb/smbus.c | 13 +++++- src/southbridge/intel/i82371eb/wakeup.c | 59 +++++++++++++++++++++++++++ 7 files changed, 122 insertions(+), 19 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index caf860e..f1be034 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -481,7 +481,8 @@ u8 acpi_slp_type = 0; static int acpi_is_wakeup(void) { - return (acpi_slp_type == 3); + /* Both resume from S2 and resume from S3 restart at CPU reset */ + return (acpi_slp_type == 3 || acpi_slp_type == 2); } static acpi_rsdp_t *valid_rsdp(acpi_rsdp_t *rsdp) @@ -567,9 +568,11 @@ void *acpi_find_wakeup_vector(void) return wake_vec; } +#if CONFIG_SMP extern char *lowmem_backup; extern char *lowmem_backup_ptr; extern int lowmem_backup_size; +#endif #define WAKEUP_BASE 0x600 @@ -588,12 +591,14 @@ void acpi_jump_to_wakeup(void *vector) return; } +#if CONFIG_SMP // FIXME: This should go into the ACPI backup memory, too. No pork saussages. /* * Just restore the SMP trampoline and continue with wakeup on * assembly level. */ memcpy(lowmem_backup_ptr, lowmem_backup, lowmem_backup_size); +#endif /* Copy wakeup trampoline in place. */ memcpy((void *)WAKEUP_BASE, &__wakeup, (size_t)&__wakeup_size); diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index eecefcd..202f521 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -191,8 +191,10 @@ extern u8 acpi_slp_type; void cbmem_initialize(void) { #if CONFIG_HAVE_ACPI_RESUME - if (acpi_slp_type == 3) { + printk(BIOS_DEBUG, "%s: acpi_slp_type=%d\n", __func__, acpi_slp_type); + if (acpi_slp_type == 3 || acpi_slp_type == 2) { if (!cbmem_reinit(high_tables_base)) { + printk(BIOS_DEBUG, "cbmem_reinit failed\n"); /* Something went wrong, our high memory area got wiped */ acpi_slp_type = 0; cbmem_init(high_tables_base, high_tables_size); diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index 5e6411c..c5befa0 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -21,27 +21,51 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1) { - /* For now only define 2 power states: - * - S0 which is fully on - * - S5 which is soft off - * Any others would involve declaring the wake up methods. - */ - - /* intel i82371eb (piix4e) datasheet, section 7.2.3, page 142 */ /* - 000b / 0x0: soft off/suspend to disk (soff/std) s5 - 001b / 0x1: suspend to ram (str) s3 - 010b / 0x2: powered on suspend, context lost (poscl) s1 - 011b / 0x3: powered on suspend, cpu context lost (posccl) s2 - 100b / 0x4: powered on suspend, context maintained (pos) s4 - 101b / 0x5: working (clock control) s0 - 110b / 0x6: reserved - 111b / 0x7: reserved - */ + * Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142 + * + * 0: soft off/suspend to disk S5 + * 1: suspend to ram S3 + * 2: powered on suspend, context lost S2 + * Note: 'context lost' means the CPU restarts at the reset + * vector + * 3: powered on suspend, CPU context lost S1 + * Note: Looks like 'CPU context lost' does _not_ mean the + * CPU restarts at the reset vector. Most likely only + * caches are lost, so both 0x3 and 0x4 map to acpi S1 + * 4: powered on suspend, context maintained S1 + * 5: working (clock control) S0 + * 6: reserved + * 7: reserved + */ Name (\_S0, Package () { 0x05, 0x05, 0x00, 0x00 }) Name (\_S1, Package () { 0x03, 0x03, 0x00, 0x00 }) Name (\_S5, Package () { 0x00, 0x00, 0x00, 0x00 }) + OperationRegion (SIO1, SystemIO, Add(DEFAULT_PMBASE, GPO0), 2) + Field (SIO1, ByteAcc, NoLock, Preserve) + { + FANP, 1, /* CPU/case fan power */ + Offset (0x01), + PLED, 1, + } + + Method (\_PTS, 1, NotSerialized) + { + /* Disable fan, blink power led */ + Store (Zero, FANP) + Store (Zero, PLED) + } + + Method (\_WAK, 1, NotSerialized) + { + /* Re-enable fan, stop power led blinking */ + Store (One, FANP) + Store (One, PLED) + /* wake OK */ + Return(Package(0x02){0x00, 0x00}) + } + /* Root of the bus hierarchy */ Scope (\_SB) { diff --git a/src/southbridge/intel/i82371eb/Kconfig b/src/southbridge/intel/i82371eb/Kconfig index 9b037fe..3b56796 100644 --- a/src/southbridge/intel/i82371eb/Kconfig +++ b/src/southbridge/intel/i82371eb/Kconfig @@ -1,6 +1,7 @@ config SOUTHBRIDGE_INTEL_I82371EB bool select TINY_BOOTBLOCK + select HAVE_ACPI_RESUME if HAVE_ACPI_TABLES config BOOTBLOCK_SOUTHBRIDGE_INIT string diff --git a/src/southbridge/intel/i82371eb/Makefile.inc b/src/southbridge/intel/i82371eb/Makefile.inc index 940a17d..9e2c3eb 100644 --- a/src/southbridge/intel/i82371eb/Makefile.inc +++ b/src/southbridge/intel/i82371eb/Makefile.inc @@ -26,6 +26,7 @@ driver-y += smbus.c driver-y += reset.c driver-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c driver-$(CONFIG_GENERATE_ACPI_TABLES) += acpi_tables.c +driver-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.c romstage-y += early_pm.c romstage-y += early_smbus.c diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c index b1a51c6..65af02a 100644 --- a/src/southbridge/intel/i82371eb/smbus.c +++ b/src/southbridge/intel/i82371eb/smbus.c @@ -31,6 +31,11 @@ #include "i82371eb.h" #include "smbus.h" +#if CONFIG_HAVE_ACPI_RESUME == 1 +extern u8 acpi_slp_type; +int acpi_get_sleep_type(void); +#endif + static void pwrmgt_enable(struct device *dev) { struct southbridge_intel_i82371eb_config *sb = dev->chip_info; @@ -87,7 +92,13 @@ static void pwrmgt_enable(struct device *dev) outw(0xffff, DEFAULT_PMBASE + GLBSTS); outl(0xffffffff, DEFAULT_PMBASE + DEVSTS); - /* set pmcntrl default */ +#if CONFIG_HAVE_ACPI_RESUME == 1 + /* this reads PMCNTRL, so we have to call it before writing the + * default value */ + acpi_slp_type = acpi_get_sleep_type(); +#endif + + /* set PMCNTRL default */ outw(SUS_TYP_S0|SCI_EN, DEFAULT_PMBASE + PMCNTRL); } diff --git a/src/southbridge/intel/i82371eb/wakeup.c b/src/southbridge/intel/i82371eb/wakeup.c new file mode 100644 index 0000000..f018ad9 --- /dev/null +++ b/src/southbridge/intel/i82371eb/wakeup.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/io.h> +#include <console/console.h> +#include "i82371eb.h" + +int acpi_get_sleep_type(void); + +/* + * Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142 + * + * 0: soft off/suspend to disk S5 + * 1: suspend to ram S3 + * 2: powered on suspend, context lost S2 + * Note: 'context lost' means the CPU restarts at the reset + * vector + * 3: powered on suspend, CPU context lost S1 + * Note: Looks like 'CPU context lost' does _not_ mean the + * CPU restarts at the reset vector. Most likely only + * caches are lost, so both 0x3 and 0x4 map to acpi S1 + * 4: powered on suspend, context maintained S1 + * 5: working (clock control) S0 + * 6: reserved + * 7: reserved + */ +static const u8 acpi_sus_to_slp_typ[8] = { + 5, 3, 2, 1, 1, 0, 0, 0 +}; + +int acpi_get_sleep_type(void) +{ + u16 reg, result; + + reg = inw(DEFAULT_PMBASE + PMCNTRL); + result = acpi_sus_to_slp_typ[(reg >> 10) & 7]; + + printk(BIOS_DEBUG, "Wakeup from ACPI sleep type S%d (PMCNTRL=%04x)\n", result, reg); + + return result; +}

1 0

question
by Lyubomir Minchev 04 Sep '11

04 Sep '11

Hi All, I have Laptop HP Pavilion dv4 with Chipset Intel 82801 I (ICH9) Shall it be compatible with coreboot ? some cut : ---------------------------------------------------------------------------------------------------------------------------- [0000:00]-+-00.0 Intel Corporation Mobile 4 Series Chipset Memory Controller Hub [8086:2a40] +-01.0-[01]----00.0 nVidia Corporation G98 [GeForce 9200M GS] [10de:06e8] +-1a.0 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #4 [8086:2937] +-1a.1 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #5 [8086:2938] +-1a.7 Intel Corporation 82801I (ICH9 Family) USB2 EHCI Controller #2 [8086:293c] +-1b.0 Intel Corporation 82801I (ICH9 Family) HD Audio Controller [8086:293e] +-1c.0-[02]-- +-1c.1-[03]-- +-1c.2-[04]----00.0 Intel Corporation PRO/Wireless 5100 AGN [Shiloh] Network Connection [8086:4237] +-1c.3-[05]----00.0 Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller [10ec:8168] +-1c.4-[06]--+-00.0 JMicron Technology Corp. SD/MMC Host Controller [197b:2382] | +-00.2 JMicron Technology Corp. Standard SD Host Controller [197b:2381] | +-00.3 JMicron Technology Corp. MS Host Controller [197b:2383] | \-00.4 JMicron Technology Corp. xD Host Controller [197b:2384] +-1c.5-[07-09]-- +-1d.0 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #1 [8086:2934] +-1d.1 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #2 [8086:2935] +-1d.2 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #3 [8086:2936] +-1d.3 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #6 [8086:2939] +-1d.7 Intel Corporation 82801I (ICH9 Family) USB2 EHCI Controller #1 [8086:293a] +-1e.0-[0a]-- +-1f.0 Intel Corporation ICH9M LPC Interface Controller [8086:2919] +-1f.2 Intel Corporation ICH9M/M-E SATA AHCI Controller [8086:2929] \-1f.3 Intel Corporation 82801I (ICH9 Family) SMBus Controller [8086:2930] ----------------------------------------------------------------------------------------------------------------------------Regards, Lyubomir Minchev

1 0

AMD Hudson FCH datasheet
by Darmawan Salihun 04 Sep '11

04 Sep '11

Hi everyone, I'm looking for AMD Hudson datasheet. I've looked at the links in the Coreboot datasheet section but only AMD Family 14h links exists. Has the Hudson FCH datasheet made public? Thanks, Darmawan -- -------------------------------------------------------------------- -= Human knowledge belongs to the world =-

1 0

Patch merged into master: f787a41 Adjust some code/comment of sb700 sata init
by gerrit＠coreboot.org 04 Sep '11

04 Sep '11

the following patch was just integrated into master: commit f787a41e3ae338b7d337236b69761dddde2340fe Author: Wang Qing Pei <wangqingpei(a)gmail.com> Date: Tue Nov 9 09:17:07 2010 +0100 Adjust some code/comment of sb700 sata init The inline comment of sata_init function seems not placed correctly. Rearrange it. Change-Id: I63480da60e51cdc68e64c302ad2d8a6197e288f6 Signed-off-by: Wang Qing Pei <wangqingpei(a)gmail.com> Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/186 for details. -gerrit

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Patch merged into master: 7b67759 Disable dev3 on ma78gm-us2h
by gerrit＠coreboot.org 04 Sep '11

04 Sep '11

the following patch was just integrated into master: commit 7b67759c7f1711e7e7305440bfd476f4f12486bd Author: Wang Qing Pei <wangqingpei(a)gmail.com> Date: Tue Nov 9 09:09:47 2010 +0100 Disable dev3 on ma78gm-us2h Disable bus 0 dev 3 PCI bridge, ma78gm-us2h does not have this slot. Change-Id: Ia355ee385fd0f37793b4bdf1815c033670823eaa Signed-off-by: Wang Qing Pei <wangqingpei(a)gmail.com> Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/187 for details. -gerrit

1 0

Patch merged into master: e869861 Utility for generating an Artecboot image
by gerrit＠coreboot.org 04 Sep '11

04 Sep '11

the following patch was just integrated into master: commit e8698619be9024fef2babeaccebd7a7a65ce3f2f Author: Nathan Williams <nathan(a)traverse.com.au> Date: Mon Apr 4 01:36:13 2011 +0200 Utility for generating an Artecboot image This program outputs a binary file with artecboot header and Linux kernel that can be used with the FILO Artecboot loader. Change-Id: I855845fffae57472d027e20a8db25b19f106a488 Signed-off-by: Nathan Williams <nathan(a)traverse.com.au> Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/182 for details. -gerrit

1 0

Patch set updated: 56440ee mkelfImage: Use -fno-stack-protector if supported by gcc
by Raymond Danks 04 Sep '11

04 Sep '11

Raymond Danks (raymonddanks(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/112 -gerrit commit 56440ee651a1508722d3256003fe66d126b0f8e5 Author: Raymond Danks <raymonddanks(a)gmail.com> Date: Sat Sep 3 21:45:38 2011 -0600 mkelfImage: Use -fno-stack-protector if supported by gcc Gcc 4.1 comes with an SSP https://wiki.ubuntu.com/GccSsp This is disabled to work around '__stack_chk_fail' symbol not found failures http://www.coreboot.org/FAQ/Obsolete#How_do_I_fix_stack_chk_fail_errors.3F The presence of -fno-stack-protector is tested for automatically by configure. Change-Id: I28ef158829f5935f985cfd5a5440733685cf479a Reported-by: Raymond Danks <raymonddanks(a)gmail.com> Signed-off-by: Raymond Danks <raymonddanks(a)gmail.com> --- util/mkelfImage/configure | 38 +++++++++++++++++++++++++++++++++++++- util/mkelfImage/configure.ac | 21 +++++++++++++++++++++ 2 files changed, 58 insertions(+), 1 deletions(-) diff --git a/util/mkelfImage/configure b/util/mkelfImage/configure index b3021de..150e5c8 100755 --- a/util/mkelfImage/configure +++ b/util/mkelfImage/configure @@ -690,6 +690,7 @@ IA64_LD IA64_AS IA64_OBJCOPY HOST_CC +libc_cv_fno_stack_protector HOST_CFLAGS I386_CFLAGS I386_ASFLAGS @@ -4963,6 +4964,40 @@ IA64_LDFLAGS='-static --warn-multiple-gp --warn-common' +{ echo "$as_me:$LINENO: checking for -fno-stack-protector" >&5 +echo $ECHO_N "checking for -fno-stack-protector... $ECHO_C" >&6; } +if test "${libc_cv_fno_stack_protector+set}" = set; then + echo $ECHO_N "(cached) $ECHO_C" >&6 +else + +cat > conftest.c <<EOF +int foo; +main () { return 0;} +EOF +if { ac_try='$I386_CC -fno-stack-protector + -o conftest conftest.c 1>&5' + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 + (eval $ac_try) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; } +then + libc_cv_fno_stack_protector=yes +else + libc_cv_fno_stack_protector=no +fi +rm -f conftest* +fi +{ echo "$as_me:$LINENO: result: $libc_cv_fno_stack_protector" >&5 +echo "${ECHO_T}$libc_cv_fno_stack_protector" >&6; } +if test $libc_cv_fno_stack_protector = yes; then + I386_CFLAGS="$I386_CFLAGS -fno-stack-protector" + IA64_CFLAGS="$IA64_CFLAGS -fno-stack-protector" + +fi + + + @@ -5689,6 +5724,7 @@ IA64_LD!$IA64_LD$ac_delim IA64_AS!$IA64_AS$ac_delim IA64_OBJCOPY!$IA64_OBJCOPY$ac_delim HOST_CC!$HOST_CC$ac_delim +libc_cv_fno_stack_protector!$libc_cv_fno_stack_protector$ac_delim HOST_CFLAGS!$HOST_CFLAGS$ac_delim I386_CFLAGS!$I386_CFLAGS$ac_delim I386_ASFLAGS!$I386_ASFLAGS$ac_delim @@ -5700,7 +5736,7 @@ LIBOBJS!$LIBOBJS$ac_delim LTLIBOBJS!$LTLIBOBJS$ac_delim _ACEOF - if test `sed -n "s/.*$ac_delim\$/X/p" conf$$subs.sed | grep -c X` = 86; then + if test `sed -n "s/.*$ac_delim\$/X/p" conf$$subs.sed | grep -c X` = 87; then break elif $ac_last_try; then { { echo "$as_me:$LINENO: error: could not make $CONFIG_STATUS" >&5 diff --git a/util/mkelfImage/configure.ac b/util/mkelfImage/configure.ac index 7aebd36..a7fc37e 100644 --- a/util/mkelfImage/configure.ac +++ b/util/mkelfImage/configure.ac @@ -186,6 +186,27 @@ IA64_ASFLAGS='-mconstant-gp -mauto-pic' IA64_LDFLAGS='-static --warn-multiple-gp --warn-common' AC_SUBST([HOST_CC]) + +AC_CACHE_CHECK(for -fno-stack-protector, libc_cv_fno_stack_protector, [ +cat > conftest.c <<EOF +int foo; +main () { return 0;} +EOF +if AC_TRY_COMMAND([$I386_CC -fno-stack-protector + -o conftest conftest.c 1>&AS_MESSAGE_LOG_FD]) +then + libc_cv_fno_stack_protector=yes +else + libc_cv_fno_stack_protector=no +fi +rm -f conftest*]) +if test $libc_cv_fno_stack_protector = yes; then + I386_CFLAGS="$I386_CFLAGS -fno-stack-protector" + IA64_CFLAGS="$IA64_CFLAGS -fno-stack-protector" + +fi +AC_SUBST(libc_cv_fno_stack_protector) + AC_SUBST([HOST_CFLAGS]) AC_SUBST([I386_CC])

1 0

New patch to review: 7b67759 Disable dev3 on ma78gm-us2h
by Patrick Georgi 03 Sep '11

03 Sep '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/187 -gerrit commit 7b67759c7f1711e7e7305440bfd476f4f12486bd Author: Wang Qing Pei <wangqingpei(a)gmail.com> Date: Tue Nov 9 09:09:47 2010 +0100 Disable dev3 on ma78gm-us2h Disable bus 0 dev 3 PCI bridge, ma78gm-us2h does not have this slot. Change-Id: Ia355ee385fd0f37793b4bdf1815c033670823eaa Signed-off-by: Wang Qing Pei <wangqingpei(a)gmail.com> Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/mainboard/gigabyte/ma78gm/devicetree.cb | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mainboard/gigabyte/ma78gm/devicetree.cb b/src/mainboard/gigabyte/ma78gm/devicetree.cb index 1aa859f..2fb4824 100644 --- a/src/mainboard/gigabyte/ma78gm/devicetree.cb +++ b/src/mainboard/gigabyte/ma78gm/devicetree.cb @@ -13,7 +13,7 @@ chip northbridge/amd/amdfam10/root_complex device pci 0.0 on end # HT 0x9600 device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 on end # PCIE P2P bridge 0x960b + device pci 3.0 off end # PCIE P2P bridge 0x960b device pci 4.0 on end # PCIE P2P bridge 0x9604 device pci 5.0 off end # PCIE P2P bridge 0x9605 device pci 6.0 off end # PCIE P2P bridge 0x9606

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coreboot September 2011