coreboot August 2011

coreboot@coreboot.org

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217 discussions

[RFC] tracing execution flow
by Rudolf Marek 02 Sep '11

02 Sep '11

Hi, Sorry about the email quality I'm too tired to re-check it again. I had an idea to hijack the gprof for fun. I compiled the coreboot with -pg option (and enabled stack frames) resulting that each called function has a "mcount" funtion called in prolog for gprof. However we do not use libc and gprof but we can use this for: 1) to show where whole execution flow goes 2) real time tracing (if console is RAM) 3) stack size checking So far I have a proof of concept which is attached. It adds for ramstage -pg option and then implements the mcount function which looks into the frame pointer and prints to serial console who is it and who is the caller. This function then calls C function gprof which just print stack size and that information Also, I protect the recursive usage of mcount during the gprof call via in_pg. Which is also triggered to remove sprintf and printf bits from logs. It produces something like this: Stage: loading fallback/coreboot_ram @ 0x100000 (606208 bytes), entry @ 0x100000 Stage: done loading. Jumping to image. ~0x00107139(0x00100099)1638316 ~0x00108599(0x00107146)1638304 ~0x00107da5(0x0010714b)1638296 ~0x001070fe(0x00107dbe)1638288 ~0x00108599(0x00107157)1638304 ~0x00107d3c(0x00107186)1638264 coreboot-4.0-1681-gd6a736e-dirty Mon Aug 29 22:56:18 CEST 2011 booting... ~0x00108599(0x00107190)1638304 ~0x0011157d(0x001071a1)1638320 ~0x00109a7a(0x001071a6)1638304 ~0x00107d3c(0x00109a86)1638264 Enumerating buses... No timing info so far. I annotate this log with a help of gdb and script tp: Check fallback/romstage Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (606208 bytes), entry @ 0x100000 Stage: done loading. Jumping to image. ~0x00107139(0x00100099)1638316~0x107139 is in hardwaremain (src/boot /hardwaremain.c:57). FROM 0x100099 is at src/arch/x86/lib/c_start.S:85. ~0x00108599(0x00107146)1638304~0x108599 is in post_code (src/arch/x86/include/arch/io.h:46). FROM 0x107146 is in hardwaremain (src/boot/hardwaremain.c:63). ~0x00107da5(0x0010714b)1638296~0x107da5 is in console_init (src/console/console.c:42). FROM 0x10714b is in hardwaremain (src/boot/hardwaremain.c:65). ~0x001070fe(0x00107dbe)1638288~0x1070fe is in uart_init (src/arch/x86/include/arch/io.h:46). FROM 0x107dbe is in console_init (src/console/console.c:44). ~0x00108599(0x00107157)1638304~0x108599 is in post_code (src/arch/x86/include/arch/io.h:46). FROM 0x107157 is in hardwaremain (src/boot/hardwaremain.c:67). ~0x00107d3c(0x00107186)1638264~0x107d3c is in do_printk (src/console/printk.c:25). FROM 0x107186 is in hardwaremain (src/boot/hardwaremain.c:71). coreboot-4.0-1681-gd6a736e-dirty Mon Aug 29 22:56:18 CEST 2011 booting... Or some nice bits: Adding high table area ~0x0010dc84(0x0010e23d)463340~0x10dc84 is in lb_add_memory_range (src/arch/x86/boot/coreboot_table.c:417). FROM 0x10e23d is in write_coreboot_table (src/arch/x86/boot/coreboot_table.c:495). ~0x00113a60(0x0010dd65)463304~0x113a60 is in memmove (src/lib/memmove.c:3). FROM 0x10dd65 is in lb_add_memory_range (src/arch/x86/boot/coreboot_table.c:383). ~0x00113a60(0x0010dd65)463304~0x113a60 is in memmove (src/lib/memmove.c:3). FROM 0x10dd65 is in lb_add_memory_range (src/arch/x86/boot/coreboot_table.c:383). ~0x0010d96a(0x0010dea1)463296~0x10d96a is in lb_memory_range (src/arch/x86/boot/coreboot_table.c:252). FROM 0x10dea1 is in lb_add_memory_range (src/arch/x86/boot/coreboot_table.c:420). ~0x0010d9fa(0x0010e23d)463324~0x10d9fa is in lb_cleanup_memory_ranges (src/arch/x86/boot/coreboot_table.c:317). FROM 0x10e23d is in write_coreboot_table (src/arch/x86/boot/coreboot_table.c P#1 freq 1000 [MHz] voltage 1100 [mV] TDP 21000 [mW] ~0x00110384(0x00116dcd)463164~0x110384 is in acpigen_write_processor (src/arch/x86/boot/acpigen.c:259). FROM 0x116dcd is in amd_model_fxx_generate_powernow (src/cpu/amd/model_fxx/powernow_a cpi.c:44). ~0x0010fd74(0x001103ab)463148~0x10fd74 is in acpigen_write_len_f (src/arch/x86/boot/acpigen.c:40). FROM 0x1103ab is in acpigen_write_processor (src/arch/x86/boot/acpigen.c:271). ~0x0010853f(0x001103c4)463128~0x10853f is in sprintf (src/console/vsprintf.c:58). FROM 0x1103c4 is in acpigen_write_processor (src/arch/x86/boot/acpigen.c:272). ~0x0010fe6b(0x001103cc)463100~0x10fe6b is in acpigen_emit_namestring (src/arch/x86/boot/acpigen.c:203). FROM 0x1103cc is in acpigen_write_processor (src/arch/x86/boot/acpigen.c:70). ~0x0010fb66(0x0010ff03)463048~0x10fb66 is in acpigen_emit_simple_namestring (src/arch/x86/boot/acpigen.c:156). FROM 0x10ff03 is in acpigen_emit_namestring (src/arch/x86/boot/acpigen.c:174). ~0x0010fb66(0x0010ff14)463048~0x10fb66 is in acpigen_emit_simple_namestring (src/arch/x86/boot/acpigen.c:156). FROM 0x10ff14 is in acpigen_emit_namestring (src/arch/x86/boot/acpigen.c:234). ~0x0010fbcf(0x00116dd8)463236~0x10fbcf is in acpigen_write_empty_PCT (src/arch/x86/boot/acpigen.c:283). FROM 0x116dd8 is in amd_model_fxx_generate_powernow (src/cpu/amd/model_fxx/powernow_a It looks like a fun, especially if one can image that the log is printed to raw memory and TSC info is used. The whole log is on assembler.cz/alog.txt.gz which answeres a questions about execution flows ;) I bit changed the annotate script at the end, because it took ages to execute ;) Good method is to just grep all lines with the info to one file, sort -u ask for the rest and just grep in the results for matching lines and intermix with original log. Instead of doing 30000 lines it did only few hundreds. If there is someone with more time it would be great to integrate this somehow. Thanks Rudolf

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Dose coreboot support TPM(trusted platform module) ?
by Cui Lei 31 Aug '11

31 Aug '11

Hi all, I know TPM was supported by FreeBIOS and the FreeBIOS was turned into linuxBIOS , now linuxBIOS is called coreboot. But it seems that coreboot now does not provide the TPM support, may be I lost in the source code.So,dose corebootV4 support TPM(trusted platform module) ? BRs, Rock.

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CPU Multiplier in coreboot
by Oliver Schinagl 30 Aug '11

30 Aug '11

Hi list, I was just researching the available options to coreboot/seabios and noticed that it might not be possible to change CPU multiplier/memory timings. I know coreboot obtains the timings from the SPD but what if one would want to change these when using coreboot? With the traditional bios, that always has been one of the 'normal' features. How is this handled in coreboot? oliver

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New patch to review: ca06106 Crank up CPU speed on Intel Core and Core2 CPUs
by Patrick Georgi 30 Aug '11

30 Aug '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/176 -gerrit commit ca06106e0e8de1777aa311c4ea1c1fd45f7eee38 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Aug 9 08:52:14 2011 +0200 Crank up CPU speed on Intel Core and Core2 CPUs The CPUs start on their slowest speed, and were left that way by coreboot. This change will speed up coreboot a bit, as well as systems that don't change the clock for whatever reason. Change-Id: Ia6225eea97299a473cf50eccc6c5e7de830b1ddc Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- src/cpu/intel/model_6ex/model_6ex_init.c | 14 ++++++++++++++ src/cpu/intel/model_6fx/model_6fx_init.c | 14 ++++++++++++++ 2 files changed, 28 insertions(+), 0 deletions(-) diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index eee651a..abd9cf4 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -30,6 +30,7 @@ #include <cpu/intel/microcode.h> #include <cpu/intel/hyperthreading.h> #include <cpu/intel/speedstep.h> +#include <cpu/intel/acpi.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> #include <usbdebug.h> @@ -129,6 +130,19 @@ static void configure_misc(void) msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ wrmsr(IA32_MISC_ENABLE, msr); + + // set maximum CPU speed + msr = rdmsr(IA32_PERF_STS); + int busratio_max=(msr.hi >> (40-32)) & 0x1f; + + msr = rdmsr(IA32_PLATFORM_ID); + int vid_max=msr.lo & 0x3f; + + msr.lo &= ~0xffff; + msr.lo |= busratio_max << 8; + msr.lo |= vid_max; + + wrmsr(IA32_PERF_CTL, msr); } #define PIC_SENS_CFG 0x1aa diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index a3939c9..5cb1cae 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -29,6 +29,7 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> +#include <cpu/intel/acpi.h> #include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -156,6 +157,19 @@ static void configure_misc(void) msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ wrmsr(IA32_MISC_ENABLE, msr); + + // set maximum CPU speed + msr = rdmsr(IA32_PERF_STS); + int busratio_max=(msr.hi >> (40-32)) & 0x1f; + + msr = rdmsr(IA32_PLATFORM_ID); + int vid_max=msr.lo & 0x3f; + + msr.lo &= ~0xffff; + msr.lo |= busratio_max << 8; + msr.lo |= vid_max; + + wrmsr(IA32_PERF_CTL, msr); } #define PIC_SENS_CFG 0x1aa

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Patch merged into master: bbacccf buildgcc: Do not download GDB source code if run with --skip-gdb
by gerrit＠coreboot.org 29 Aug '11

29 Aug '11

the following patch was just integrated into master: commit bbacccfb9a990f10bbf86601bca4a564cdf2f2b0 Author: Peter Stuge <peter(a)stuge.se> Date: Sun Aug 28 11:04:23 2011 +0200 buildgcc: Do not download GDB source code if run with --skip-gdb Change-Id: Ida3680418fdd3136752d51cc19f3e14111c12131 Signed-off-by: Peter Stuge <peter(a)stuge.se> See http://review.coreboot.org/175 for details. -gerrit

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3.0T harddisk support?
by KelvinKLi＠viatech.com.cn 29 Aug '11

29 Aug '11

Hi All, Could coreboot can support 3.0T harddisk or GPT partition? Best Regards, Kelvin K. Li 李凯 --------------------------------------------------------------- Software Team, VIA Technologies, Inc. 4F, VIA Tower, 1 Zhongguancun East Road, Haidian District, Beijing, 100084 Tel: 86-10-59852288 ext.3620 mailto: kelvinkli(a)viatech.com.cn

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Trac reminder: list of new ticket(s)
by coreboot tracker 29 Aug '11

29 Aug '11

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New patch to review: bbacccf buildgcc: Do not download GDB source code if run with --skip-gdb
by Peter Stuge 28 Aug '11

28 Aug '11

Peter Stuge (peter(a)stuge.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/175 -gerrit commit bbacccfb9a990f10bbf86601bca4a564cdf2f2b0 Author: Peter Stuge <peter(a)stuge.se> Date: Sun Aug 28 11:04:23 2011 +0200 buildgcc: Do not download GDB source code if run with --skip-gdb Change-Id: Ida3680418fdd3136752d51cc19f3e14111c12131 Signed-off-by: Peter Stuge <peter(a)stuge.se> --- util/crossgcc/buildgcc | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 5591810..937fb75 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -189,6 +189,7 @@ done GDB_PACKAGE="GDB" if [ $SKIPGDB -eq 1 ]; then printf "Will skip GDB ... ${green}ok${NC}\n" + GDB_ARCHIVE="" GDB_PACKAGE="" fi

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Patch merged into master: abea90d Add a few more patterns to .gitignore
by gerrit＠coreboot.org 27 Aug '11

27 Aug '11

the following patch was just integrated into master: commit abea90d19c4b6a1120566fc8470fcfd6e8835eab Author: Sven Schnelle <svens(a)stackframe.org> Date: Fri Aug 26 21:48:32 2011 +0200 Add a few more patterns to .gitignore Change-Id: If7c1c6d9a96dd788bacee72b6e18a435069cad6e Signed-off-by: Sven Schnelle <svens(a)stackframe.org> See http://review.coreboot.org/172 for details. -gerrit

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Patch merged into master: a04bb6f Add dirty flag to git describe
by gerrit＠coreboot.org 27 Aug '11

27 Aug '11

the following patch was just integrated into master: commit a04bb6f22eec2673f61fc98c03c224a5f5985b13 Author: Sven Schnelle <svens(a)stackframe.org> Date: Fri Aug 26 21:57:53 2011 +0200 Add dirty flag to git describe git describe knows --dirty, which adds -dirty to the verion number if the tree contains uncommited changes. We should add this flag to make it obvious that the COREBOOT_VERSION might be misleading. This is especially important as this version number is now used in the SMBIOS data structures. Change-Id: If4c608c7455e1bbf0cc530c6299fa00eb0fe4d58 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> See http://review.coreboot.org/173 for details. -gerrit

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coreboot August 2011