coreboot August 2011

coreboot@coreboot.org

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217 discussions

#169: ASUS P4PE-X/SE.
by coreboot 01 Nov '11

01 Nov '11

#169: ASUS P4PE-X/SE. --------------------------------+-------------------------------------- Reporter: anonymous | Owner: stepan@… Type: defect | Status: new Priority: major | Milestone: Component: coreboot | Keywords: ASUS P4PE-X/SE. Dependencies: ASUS P4PE-X/SE. | Patch Status: there is no patch --------------------------------+-------------------------------------- ASUS P4PE-X/SE. -- Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/169> coreboot <http://www.coreboot.org/>

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#179: Coreboot on GigaByte GA-8IEXP ver. 1.2
by coreboot 01 Nov '11

01 Nov '11

#179: Coreboot on GigaByte GA-8IEXP ver. 1.2 ------------------------------+---------------------------------- Reporter: BlackSheep0@… | Owner: stepan@… Type: enhancement | Status: new Priority: minor | Milestone: Going mainstream Component: coreboot | Keywords: Dependencies: | Patch Status: there is no patch ------------------------------+---------------------------------- Hi, I know the main goal is to bring coreboot on most systems and I don't need to open an extra Call for that :) But I have not the programming skills to do that by myself... If someone can do that for me, I can do a lot of testing because this Mainboard has a Dual BIOS and I can quick switch between Normal BIOS and Coreboot and of course recover if something dosn't work correct ;-) Thanks and Regards -- Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/179> coreboot <http://www.coreboot.org/>

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#177: Not compiling coreBoot
by coreboot 01 Nov '11

01 Nov '11

#177: Not compiling coreBoot -----------------------------+---------------------------------- Reporter: darkshvein@… | Owner: stepan@… Type: defect | Status: new Priority: major | Milestone: Component: coreboot | Keywords: compile error Dependencies: | Patch Status: there is no patch -----------------------------+---------------------------------- Вылетает с такой ошибкой CC lib/cbfs.ramstage.o cc1: warnings being treated as errors src/southbridge/amd/rs780/rs780.c: In function ‘rs780_enable’: src/southbridge/amd/rs780/rs780.c:193:8: error: ‘pcie_mmio_save$lo’ may be used uninitialized in this function src/southbridge/amd/rs780/rs780.c:193:8: error: ‘pcie_mmio_save$hi’ may be used uninitialized in this function make: *** [build/southbridge/amd/rs780/rs780.driver.o] Ошибка 1 I tried also CC=gcc-4.4 and 4.3 и 4.5 .config: http://pastebin.com/iLVM9u80 OS ubuntu 11.04, last updates. -- Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/177> coreboot <http://www.coreboot.org/>

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#178: linux kernel hang while boot from SATA SSD on EPIA CN
by coreboot 01 Nov '11

01 Nov '11

#178: linux kernel hang while boot from SATA SSD on EPIA CN -------------------------------+---------------------------------- Reporter: ryzhovsergey@… | Owner: stepan@… Type: defect | Status: new Priority: major | Milestone: Component: coreboot | Keywords: SATA SSD EPIA CN Dependencies: | Patch Status: there is no patch -------------------------------+---------------------------------- I use seabios as payload. After grub2 continue booting process, linux kernel cannot boot from SATA SSD (OCZ Vertex Turbo 32Gb)on EPIA CN Errors with IRQ I try 2.6.33 and 2.6.38 kernels, but with original BIOS all works. -- Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/178> coreboot <http://www.coreboot.org/>

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#162: Move SYSTEM_TYPE to Kconfig
by coreboot 01 Nov '11

01 Nov '11

#162: Move SYSTEM_TYPE to Kconfig ----------------------------+----------------------------------------------- Reporter: oxygene | Owner: oxygene Type: enhancement | Status: new Priority: minor | Milestone: Component: coreboot | Keywords: Dependencies: | Patchstatus: there is no patch ----------------------------+----------------------------------------------- SYSTEM_TYPE is used to tell coreboot if the board is "server", "desktop" or "laptop". It's only used for AMD for now, but could also be used elsewhere to tweak configuration (and there's a flag in some table, maybe ACPI, that tells the OS about the system type, too). It's defined for some boards, there's a default defined somewhere in the code, that looks a lot like a good match for Kconfig. -- Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/162> coreboot <http://www.coreboot.org/>

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Re: [coreboot] DL145 G1 with dual dualcore CPU using coreboot ?
by Oskar Enoksson 28 Sep '11

28 Sep '11

Oskar Enoksson wrote: > Myles Watson wrote: > >>> I think Myles was right, there is a i2c mux in this server that somehow >>> multiplexes DIMM devices on the i2c bus. I was able to guess which i2c >>> ports contain the DIMM info, and which port is the mux, then added the >>> mux to devicetree.cb and the DIMM ports under it. Now I'm able to use >>> memory from both CPU's, at least for the combination of DIMM's I have >>> (2x2x1GB and 2x2x512MB). >>> >>> >> I'm glad it worked out! >> >> >>> So I'm basically able to use these servers now. I would love to have >>> ACPI and Cool'nQuiet of course, perhaps I'll try to do that later. >>> >>> Thanks very much for all help! If you want me to commit the new >>> mainboard to your svn repository let me know. >>> >>> >> Yes, please. If you'll send your latest patch with a Signed-off-by: line, >> I'll take it from there. >> >> Thanks, >> Myles >> >> > I hope this file is the way you want it. I did "svn cp > src/mainboard/tyan/s2881 src/mainboard/hp/dl145_g1" and then modified > the files, then "svn diff src/mainboard" so I assume you should do the > same svn cp operation, then apply my patch, then commit to retain the > original files' history. > I have fixed several problems and now it boots reliably for both and older dual Opteron 248 server and an upgraded dual Opteron 280 server. memtest86+ doesn't work, but according to another mailinglist thread memtest cannot handle tables in high memory, so that seems to be a memtest issue. Attached is a cleaned-up patch. Thanks to Myles and others for excellent help and support. I hope someone finds the result useful.

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Re: [coreboot] Porting Asus A8V-VM: Problem with initializing the SuperIO
by Rudolf Marek 18 Sep '11

18 Sep '11

Hi, Try changing ROMSTRAP if the M2V-MX SE works than it might be this. Go to the src/southbridge/via/romstrap.inc and change the romstrap to use the K8T890 instead of K8M890. I think both differs only in one byte 0xaa versus 0xff In other words check if with changed ROMSIP something changes. I guess this is the only remaining difference between the SerialICE and coreboot. Let me know if this works for you. Thanks Rudolf

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I865 memory controller status
by James Wall 09 Sep '11

09 Sep '11

Hello all, What is the status of the i865 memory controller? I have a board that all the other chips are supported but the memory controller is a big question mark.

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E350M1 does not POST
by perh52＠runbox.com 08 Sep '11

08 Sep '11

>>> Hi, >>> >>>> Upon booting, I get this: >>> >>> [...] >>> >>> you could try commit 0df0e14fb, that may or may not work, the commit after >>> that broke fusion boards completely, apparently. >>> >>> Florian >>> >> Thank you! I can confirm that 0df0e14fb works properly. >> -Marshall > >Frank, > >It looks like we have a regression. Is there some dependency on the >other patches that have not yet been committed? > >Marc Unfortunately git bisect is no help here because the commit which caused the regression was a huge one. It's important that large patches are broken down into a set of small comprehensible patches, each with an explanatory commit message. <<quote from git-bisect-lk2009.html documentation>> ... sometimes "interesting" changes of behavior in the software are introduced in some commits. In fact people are specially interested in commits that introduce a "bad" behavior, called a bug or a regression. They are interested in these commits because a commit (hopefully) contains a very small set of source code changes. And it's much easier to understand and properly fix a problem when you only need to check a very small set of changes, than when you don't know where look in the first place. So to help people find commits that introduce a "bad" behavior, the "git bisect" set of commands was invented. ...

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Re: [coreboot] POST code error "EE"
by Abhinav Hardikar 05 Sep '11

05 Sep '11

ok. I did as you said. Created the irq_tables.c file and added it. I even created some more files. ./src/mainboard/jetway/ | -> j7bxan | ->chip.h ->devicetree.cb ->irq_tables.c ->Kconfig ->mainboard.c ->romstage.c I did the changes in the respective Kconfig files too. I know I could have made some patches too but I don't know how to make them. :P But the keyb and all other Input devices are not working. I checked the IRQ tables of my mobo and they seem to be fine. Once the PC boot into the Linux Kernel on the HDD the Keyb starts working. Without the Keyb I can't boot into windows(dual boot). I have attached the mobo manual also. It has the memory, I/O maps and IRQ tables. And yes It is using the correct SuperIO Winbond W3977TF. Although on the Mobo it is EF, technically it should work since the vendor BIOS was using TF driver. Thanx for all the help Abhinav

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coreboot August 2011