coreboot August 2011

coreboot@coreboot.org

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217 discussions

Patch set updated: ea7a21e AMD F14 southbridge update
by perh52＠runbox.com 07 Aug '11

07 Aug '11

Looking at src/southbridge/amd/cimx/sb800/late.c static void usb_init(struct device *dev) { + printk(BIOS_DEBUG, "SB800 - Late.c - usb_init - Start.\n"); usbInitAfterPciInit(sb_config); commonInitLateBoot(sb_config); + printk(BIOS_DEBUG, "SB800 - Late.c - usb_init - End.\n"); } it is not correct to call usbInitAfterPciInit like this because usb_init is called for every usb device, and usbInitAfterPciInit (re)initializes all the usb devices each time. This problem predates the patch of course but while changing late.c let us get it right. On a different part of the patch relating to src/southbridge/amd/cimx/sb800/cfg.c there is + sb_config->PORTCONFIG[0].PortCfg.PortPresent = CIMX_OPTION_ENABLED; + sb_config->PORTCONFIG[1].PortCfg.PortPresent = CIMX_OPTION_ENABLED; + sb_config->PORTCONFIG[2].PortCfg.PortPresent = CIMX_OPTION_ENABLED; + sb_config->PORTCONFIG[3].PortCfg.PortPresent = CIMX_OPTION_ENABLED; Not sure why you want to set these, but all enabled is not always correct, and they get reset in PreInitGppLink according to PortMask[lane_config]. Perhaps move the PortMask logic into cfg.h/cfg.c ? The sb900 cfg.c is much more complete than sb800. Leaving many values undefined in sb_config seems like a bad idea. I found I needed to set SataPortPower. + sb_config->SataPortPower = 0; // 0=all enabled. Disable ports by setting bits 5:0. + sb_config->SataPortMode = 0; // 0=all Gen3 (6Gb/s) -- 12 bits which select Gen1/2 and these need to be set correctly depending on the SB8xx version. + sb_config->NbSbGen2 = NBSB_GEN2; + sb_config->GppGen2 = GPP_GEN2;

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Patch set updated: ea7a21e AMD F14 southbridge update
by perh52＠runbox.com 07 Aug '11

07 Aug '11

The proposed get_sb800_revision is incomplete. We know that at least SB810, SB820M and SB850 exist, and that production ASIC revisions are A12, A13 (and perhaps later). Since Frank is at AMD I guess he can obtain the full set easily. The SB8xx device in the Asrock E350M1 has rev_id = 0x42 and so is _not_ covered by the proposed patch. I guess it is an SB850 A12 or A13, but I have not removed the heatsink to check. +/* RPR 2.28 Get SB ASIC Revision.*/ +static u8 get_sb800_revision(void) +{ .... .... + rev_id = pci_read_config8(dev, 0x08); + + if (rev_id == 0x40) { + rev = REV_SB800_A11; + } else if (rev_id == 0x41) { + rev = REV_SB800_A12; + } else { + die("It is not SB800 or SB810\r\n"); + } + + return rev; +} Slightly OT, but still on the subject of device identification: The following code in vendorcode/amd/cimx/sb800/SBPOR.c incorrectly turns off NbSbGen2 for the Asrock E350M1. I don't know why it was put in or if it is correct for some other hardware. dbEfuse = MINOR_ID_EFUSE_LOC; getEfuseStatus (&dbEfuse); if ( dbEfuse == M1_MINOR_ID ) { // Limit ALink speed to 2.5G if Hudson-M1 cimNbSbGen2 = 0; } So it would be nice to have a complete routine for identifying the SB8xx versions accurately.

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Patch set updated: e42cf6b Update to Asrock E350m1 for AMD F14 C0
by perh52＠runbox.com 07 Aug '11

07 Aug '11

Assuming the patch in the ML is the one under discussion (gerrit is 100% broken here), that patch didn't produce a usable SSDT for me. I used the patch below to make agesawrapper_amdinitlate work. The resulting SSDT has a different cpu scope so change CPU0/1 to C000/1 in dsdt.aml. I also changed acpi_tables to do the substitution of TOM1 in dsdt rather than ssdt. The HeapStatus line fixes a problem which shows up in an Alib routine called from GnbInitAtLate. Signed-off-by: Per Hansen <perh52(a)runbox.com> diff --git a/src/mainboard/asrock/e350m1/agesawrapper.c b/src/mainboard/asrock/e350m1/agesawrapper.c index 9178a18..3beea4b 100644 --- a/src/mainboard/asrock/e350m1/agesawrapper.c +++ b/src/mainboard/asrock/e350m1/agesawrapper.c @@ -36,6 +36,8 @@ #include "amdlib.h" #include "PlatformGnbPcieComplex.h" #include "Filecode.h" +#include "heapManager.h" +#include "CreateStruct.h" #define FILECODE UNASSIGNED_FILE_FILECODE @@ -436,42 +438,51 @@ agesawrapper_amdinitlate ( VOID ) { + printk(BIOS_DEBUG,"agesawrapper_amdinitlate: START\n"); AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdParamStruct = {0}; - AMD_LATE_PARAMS *AmdLateParams; + + AMD_LATE_PARAMS AmdLateParams; + + LibAmdMemFill (&AmdLateParams, + 0, + sizeof (AMD_LATE_PARAMS), + &(AmdLateParams.StdHeader)); - return 0; // this causes bad ACPI SSDT, need to debug + AMD_CONFIG_PARAMS StdHeader; + StdHeader.AltImageBasePtr = 0; + StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + StdHeader.Func = 0; + StdHeader.ImageBasePtr = 0; + StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + Status = AmdInitLateInitializer (&StdHeader, &AmdLateParams); + ASSERT(Status == AGESA_SUCCESS); - AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdCreateStruct (&AmdParamStruct); - AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; - Status = AmdInitLate (AmdLateParams); + Status = AmdInitLate (&AmdLateParams); if (Status != AGESA_SUCCESS) { agesawrapper_amdreadeventlog(); ASSERT(Status == AGESA_SUCCESS); } - DmiTable = AmdLateParams->DmiTable; - AcpiPstate = AmdLateParams->AcpiPState; - AcpiSrat = AmdLateParams->AcpiSrat; - AcpiSlit = AmdLateParams->AcpiSlit; - - AcpiWheaMce = AmdLateParams->AcpiWheaMce; - AcpiWheaCmc = AmdLateParams->AcpiWheaCmc; - AcpiAlib = AmdLateParams->AcpiAlib; + DmiTable = AmdLateParams.DmiTable; + AcpiPstate = AmdLateParams.AcpiPState; + AcpiSrat = AmdLateParams.AcpiSrat; + AcpiSlit = AmdLateParams.AcpiSlit; - AmdReleaseStruct (&AmdParamStruct); + AcpiWheaMce = AmdLateParams.AcpiWheaMce; + AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; + AcpiAlib = AmdLateParams.AcpiAlib; + + printk(BIOS_DEBUG,"agesawrapper_amdinitlate: END\n"); return (UINT32)Status; }

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Reference stub for CB signature detection?
by Philip Prindeville 07 Aug '11

07 Aug '11

I'm writing a Linux platform driver for a couple of Geode based boards, and was thinking that it would be nice if there was a canonical/prototypical stub routine that came with coreboot that detected the signature on a target system. That is, I could paste this code into a platform driver (for instance) in Linux that would locate the mainboard vendor and model, and I could use that to confirm that I'm running on the correct target and not a mismatched kernel configuration. I looked at flashrom's coreboot_init() and find_lb_table() and it looks like something could be cobbled from there. Can someone please piece that together? Thanks, -Philip

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Patch set updated: e42cf6b Update to Asrock E350m1 for AMD F14 C0
by Frank Vibrans III 07 Aug '11

07 Aug '11

Frank Vibrans III (frank.vibrans(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/139 -gerrit commit e42cf6b20097d3370cab840bc3223f690cde9747 Author: efdesign98 <efdesign98(a)gmail.com> Date: Thu Aug 4 22:09:53 2011 -0600 Update to Asrock E350m1 for AMD F14 C0 This updates the E350m1 mainboard code to support the C0 revision of the AMD F14 cpu. Change-Id: I19942c7d3ecd229a13ef0a69fa7e5b1ea0b909bf Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com> Signed-off-by: efdesign98 <efdesign98(a)gmail.com> --- src/mainboard/asrock/e350m1/agesawrapper.c | 35 ++++++++++++++------------- 1 files changed, 18 insertions(+), 17 deletions(-) diff --git a/src/mainboard/asrock/e350m1/agesawrapper.c b/src/mainboard/asrock/e350m1/agesawrapper.c index e98d874..919789f 100644 --- a/src/mainboard/asrock/e350m1/agesawrapper.c +++ b/src/mainboard/asrock/e350m1/agesawrapper.c @@ -437,32 +437,33 @@ agesawrapper_amdinitlate ( ) { AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdParamStruct = {0}; - AMD_LATE_PARAMS *AmdLateParams; + AMD_LATE_PARAMS AmdLateParams; - return 0; // this causes bad ACPI SSDT, need to debug + LibAmdMemFill (&AmdLateParams, + 0, + sizeof (AMD_LATE_PARAMS), + &(AmdLateParams.StdHeader)); - AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdCreateStruct (&AmdParamStruct); - AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; - Status = AmdInitLate (AmdLateParams); + AmdLateParams.StdHeader.AltImageBasePtr = 0; + AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdLateParams.StdHeader.Func = 0; + AmdLateParams.StdHeader.ImageBasePtr = 0; + + Status = AmdInitLate (&AmdLateParams); if (Status != AGESA_SUCCESS) { agesawrapper_amdreadeventlog(); ASSERT(Status == AGESA_SUCCESS); } - DmiTable = AmdLateParams->DmiTable; - AcpiPstate = AmdLateParams->AcpiPState; - AcpiSrat = AmdLateParams->AcpiSrat; - AcpiSlit = AmdLateParams->AcpiSlit; + DmiTable = AmdLateParams.DmiTable; + AcpiPstate = AmdLateParams.AcpiPState; + AcpiSrat = AmdLateParams.AcpiSrat; + AcpiSlit = AmdLateParams.AcpiSlit; - AcpiWheaMce = AmdLateParams->AcpiWheaMce; - AcpiWheaCmc = AmdLateParams->AcpiWheaCmc; - AcpiAlib = AmdLateParams->AcpiAlib; + AcpiWheaMce = AmdLateParams.AcpiWheaMce; + AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; + AcpiAlib = AmdLateParams.AcpiAlib; - AmdReleaseStruct (&AmdParamStruct); return (UINT32)Status; }

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Re: [coreboot] 200 euros for altering the font in BIOS
by Peter Stuge 07 Aug '11

07 Aug '11

Hi Meeku, dove - railing wrote: > I am prepared to offer 200 euros to any software engineer/s who > is/are able to alter the BIOS fonts to a font that I prefer. First, coreboot is not a BIOS modding forum. There are at least a few actual BIOS modding forums, where you would be swamped with responses from people who are both capable and incapable of doing whatever you ask for, while the coreboot mailing list is simply not the good place to ask. Second, the system BIOS is not involved in initializing graphics at all, and has nothing to do with fonts. The font you see in text mode is either stored in mask memory in the graphics chip, or it is part of the VGA BIOS; the isolated option ROM that knows how to initialize graphics. Third, to achieve what you want it may not even be neccessary to modify any firmware. Some operating systems natively support changing the VGA text mode font. In other operating systems there are already various font editors and other font utilities available, which will allow you to very easily change the font at run time. //Peter

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Patch merged into master: 1e41ce0 ms7135: add ACPI support
by gerrit＠coreboot.org 06 Aug '11

06 Aug '11

the following patch was just integrated into master: commit 1e41ce0a914eeab5cc746c4f1250ba49ef3e10da Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Fri Aug 5 14:43:08 2011 -0500 ms7135: add ACPI support Change-Id: I64a74d3dc0ea2d006ed4b25657d531fb243c2993 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> See http://review.coreboot.org/140 for details. -gerrit

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Patch merged into master: 1f5fb9e Update AMD F14 Agesa to support Rev C0 cpus
by gerrit＠coreboot.org 06 Aug '11

06 Aug '11

the following patch was just integrated into master: commit 1f5fb9ee4e1776c963e2221af37ac3e0d2e7c03b Author: efdesign98 <efdesign98(a)gmail.com> Date: Thu Aug 4 12:09:17 2011 -0600 Update AMD F14 Agesa to support Rev C0 cpus This change updates the AMD Agesa code to support the Family 14 rev C0 cpus. It also fixes (again) a ton of warnings, although not all of them are gone. The warning fixes affect code in the Family 12 tree as well, so there are some small changes therein. This code has been tested on a Persimmon and passes Abuild. This is the first (and largest) of a number of commits to complete the upgrade. Change-Id: Id28d9bf7931f8baa2a602f6bb096a5a465ccd20d Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com> Signed-off-by: efdesign98 <efdesign98(a)gmail.com> See http://review.coreboot.org/131 for details. -gerrit

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Testing PCI Option/Expansion ROM in SeaBIOS
by Darmawan Salihun 06 Aug '11

06 Aug '11

Hi Guys, Does enabling CONFIG_PCI_ROM_RUN in SeaBIOS is enough to test a PCI expansion ROM ? I have a PCI Expansion ROM to test with SeaBIOS (running in QEMU). TIA, Darmawan -- -------------------------------------------------------------------- -= Human knowledge belongs to the world =-

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Re: [coreboot] 200 euros for altering the font in BIOS
by Niklas Cholmkvist 05 Aug '11

05 Aug '11

Hi there, I would advise just choosing someone among the people posting to the list or checking the work they do(porting motherboards) in the svn(or whatever system they are using) and email someone specific asking if they would like to spend some time on the project which you explain to them, and how much they would like to be paid, if they would like to be paid and if regardless of if they are being paid or not if they are willing to do it. Sorry if my post sounds confusing. Kind regards, -- Niklas Cholmkvist Public GPG/PGP key block ID: 1024D/C09E670B Fingerprint: 8487 ECE3 8ED9 870B BB56 95E7 9AD2 946A C09E 670B Key download: https://sites.google.com/site/towardsfloss/main-page/NiklasCholmkvist.asc [Please, do not send my key to any keyserver]

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coreboot August 2011