coreboot August 2011

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New patch to review: f2e37b8 Add iasl to buldgcc and rev the version.
by Marc Jones 09 Aug '11

09 Aug '11

Marc Jones (marcj303(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/147 -gerrit commit f2e37b80a556336edad95724b2d62e4024d5b678 Author: Marc Jones <marcj303(a)gmail.com> Date: Mon Aug 8 16:07:50 2011 -0600 Add iasl to buldgcc and rev the version. Change-Id: If9144cdf088f16bc3974a1784a442a1fd12ac75b Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- Makefile.inc | 2 +- util/crossgcc/buildgcc | 34 +++++++++++++++++++++++++++++----- util/xcompile/xcompile | 11 ++++++++++- 3 files changed, 40 insertions(+), 7 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 65550e6..89467db 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -64,7 +64,7 @@ define ramstage-objs_asl_template $(obj)/$(1).ramstage.o: src/$(1).asl $(obj)/config.h @printf " IASL $$(subst $(top)/,,$$(@))\n" $(CC) -x assembler-with-cpp -E -MMD -MT $$(@) -D__ACPI__ -P -include $(abspath $(obj)/config.h) -I$(src) -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $$(basename $$(a)).asl - cd $$(dir $$@); iasl -p $$(notdir $$@) -tc $$(notdir $$(basename $$(a))).asl + cd $$(dir $$@); $(IASL) -p $$(notdir $$@) -tc $$(notdir $$(basename $$(a))).asl mv $$(basename $$(a)).hex $$(basename $$(a)).c $(CC) $$(CFLAGS) $$(if $$(subst dsdt,,$$(basename $$(notdir $(1)))), -DAmlCode=AmlCode_$$(basename $$(notdir $(1)))) -c -o $$@ $$(basename $$(a)).c # keep %.o: %.c rule from catching the temporary .c file after a make clean diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 83b7cdf..e97a651 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -4,6 +4,8 @@ # written by Patrick Georgi <patrick.georgi(a)coresystems.de> and # Stefan Reinauer <stefan.reinauer(a)coresystems.de> # +# Copyright (C) 2011 by Sage Electronic Engineering +# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. @@ -18,8 +20,8 @@ # Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA # -CROSSGCC_DATE="December 16th, 2010" -CROSSGCC_VERSION="1.03" +CROSSGCC_DATE="August 8th, 2011" +CROSSGCC_VERSION="1.04" # default settings TARGETDIR=`pwd`/xgcc @@ -37,6 +39,7 @@ GDB_VERSION=7.2 W32API_VERSION=3.17-2 W32API_VERSION_SHORT=3.17 MINGWRT_VERSION=3.18 +IASL_VERSION=20110623 # archive locations GMP_ARCHIVE="ftp://ftp.gmplib.org/pub/gmp-${GMP_VERSION}/gmp-${GMP_VERSION}.tar.bz2" @@ -48,6 +51,7 @@ BINUTILS_ARCHIVE="http://ftp.gnu.org/gnu/binutils/binutils-${BINUTILS_VERSION}.t GDB_ARCHIVE="http://ftp.gnu.org/gnu/gdb/gdb-${GDB_VERSION}.tar.bz2" W32API_ARCHIVE="http://downloads.sourceforge.net/project/mingw/MinGW/BaseSystem/RuntimeLibr…" MINGWRT_ARCHIVE="http://downloads.sourceforge.net/project/mingw/MinGW/BaseSystem/RuntimeLibr…" +IASL_ARCHIVE="http://www.acpica.org/download/acpica-unix-${IASL_VERSION}.tar.gz" GMP_DIR="gmp-${GMP_VERSION}" MPFR_DIR="mpfr-${MPFR_VERSION}" @@ -58,6 +62,7 @@ BINUTILS_DIR="binutils-${BINUTILS_VERSION}" GDB_DIR="gdb-${GDB_VERSION}" W32API_DIR="w32api-${W32API_VERSION}-mingw32" MINGWRT_DIR="mingwrt-${MINGWRT_VERSION}-mingw32" +IASL_DIR="acpica-unix-${IASL_VERSION}" SAVETEMPS=0 SKIPGDB=0 @@ -96,7 +101,7 @@ MAKE=`searchgnu make` || exit $? cleanup() { printf "Cleaning up temporary files... " - rm -rf build-* combined gcc-* gmp-* mpfr-* mpc-* libelf-* binutils-* gdb-* w32api-* mingwrt-* + rm -rf build-* combined gcc-* gmp-* mpfr-* mpc-* libelf-* binutils-* gdb-* w32api-* mingwrt-* acpica-* printf "${green}ok${NC}\n" } @@ -127,6 +132,7 @@ myversion() cat << EOF Copyright (C) 2008-2010 by coresystems GmbH +Copyright (C) 2011 by Sage Electronic Engineering This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -217,7 +223,7 @@ fi printf "Downloading tar balls ... \n" mkdir -p tarballs -for ARCHIVE in $GMP_ARCHIVE $MPFR_ARCHIVE $MPC_ARCHIVE $LIBELF_ARCHIVE $GCC_ARCHIVE $BINUTILS_ARCHIVE $GDB_ARCHIVE $MINGW_ARCHIVES; do +for ARCHIVE in $GMP_ARCHIVE $MPFR_ARCHIVE $MPC_ARCHIVE $LIBELF_ARCHIVE $GCC_ARCHIVE $BINUTILS_ARCHIVE $GDB_ARCHIVE $MINGW_ARCHIVES $IASL_ARCHIVE; do FILE=`basename $ARCHIVE` printf " * $FILE " test -f tarballs/$FILE && printf "(cached)" || ( @@ -238,7 +244,7 @@ if [ "$TARGETARCH" = "i386-mingw32" ]; then fi printf "Unpacking and patching ... \n" -for PACKAGE in GMP MPFR MPC LIBELF GCC BINUTILS $GDB_PACKAGE $MINGW_PACKAGES; do +for PACKAGE in GMP MPFR MPC LIBELF GCC BINUTILS $GDB_PACKAGE $MINGW_PACKAGES IASL; do archive=$PACKAGE"_ARCHIVE" archive=${!archive} dir=$PACKAGE"_DIR" @@ -447,6 +453,23 @@ test -r build-gdb/.failed && printf "${RED}failed${NC}\n" || printf "${green}ok$ test -r build-gdb/.failed && exit 1 fi +if [ -f $IASL_DIR/compiler/.success ]; then + printf "Skipping IASL as it is already built\n" +else +printf "Building IASL ${IASL_VERSION} ... " +( + cd $IASL_DIR/compiler + export PATH=$PATH:$DESTDIR$TARGETDIR/bin + rm -f .failed + CFLAGS="$HOSTCFLAGS" + $MAKE || touch .failed + cp --remove-destination iasl* $DESTDIR$TARGETDIR/bin || touch .failed + if [ ! -f .failed ]; then touch .success; fi +) &> $IASL_DIR/compiler/crossgcc-build.log +test -r $IASL_DIR/compiler/.failed && printf "${RED}failed${NC}\n" || printf "${green}ok${NC}\n" +test -r $IASL_DIR/compiler.failed && exit 1 +fi + if [ $SAVETEMPS -eq 0 ]; then printf "Cleaning up... " rm -rf ${GMP_DIR} build-gmp @@ -456,6 +479,7 @@ if [ $SAVETEMPS -eq 0 ]; then rm -rf ${BINUTILS_DIR} build-binutils rm -rf ${GCC_DIR} build-gcc rm -rf ${GDB_DIR} build-gdb + rm -rf ${IASL_DIR} printf "${green}ok${NC}\n" else printf "Leaving temporary files around... ${green}ok${NC}\n" diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 19103c7..fd4dbeb 100644 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -35,13 +35,14 @@ for make in make gmake gnumake; do done GCCPREFIX=invalid +XGCCPATH="`pwd`/util/crossgcc/xgcc/bin/" TMPFILE=`mktemp /tmp/temp.XXXX 2>/dev/null || echo /tmp/temp.78gOIUGz` touch $TMPFILE # This should be a loop over all supported architectures TARCH=i386 TWIDTH=32 -for gccprefixes in `pwd`/util/crossgcc/xgcc/bin/${TARCH}-elf- ${TARCH}-elf- ""; do +for gccprefixes in ${XGCCPATH}${TARCH}-elf- ${TARCH}-elf- ""; do if ! which ${gccprefixes}as 2>/dev/null >/dev/null; then continue fi @@ -85,6 +86,12 @@ else HOSTCC=cc fi +if [ "`${XGCCPATH}/iasl 2>/dev/null | grep -c ACPI`" -gt 0 ]; then + IASL=${XGCCPATH}iasl +else + IASL=iasl +fi + cat << EOF # elf${TWIDTH}-${TARCH} toolchain AS:=${GCCPREFIX}as ${ASFLAGS} @@ -96,6 +103,8 @@ NM:=${GCCPREFIX}nm OBJCOPY:=${GCCPREFIX}objcopy OBJDUMP:=${GCCPREFIX}objdump +IASL:=${IASL} + # native toolchain HOSTCC:=${HOSTCC} EOF

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Patch merged into master: 36161df Do not compile nuvoton superio for all board
by gerrit＠coreboot.org 09 Aug '11

09 Aug '11

the following patch was just integrated into master: commit 36161df7a4fb2733be2659fa2a395cccc27907ba Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Wed Aug 3 09:14:59 2011 -0500 Do not compile nuvoton superio for all board The nuvoton WPCM450 code is compiled for all boards regardless of whether or not they use it. Compile it only for boards needing it. Change-Id: Iaf4cf2c479eb3238863f0771be799f02a8cc3421 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/129 for details. -gerrit

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Patch merged into master: 3431fbd AMD Family 14 Agesa warning fix
by gerrit＠coreboot.org 09 Aug '11

09 Aug '11

the following patch was just integrated into master: commit 3431fbd1d653a36055bf9e73dcb1d917a7720dab Author: efdesign98 <efdesign98(a)gmail.com> Date: Thu Aug 4 15:07:45 2011 -0600 AMD Family 14 Agesa warning fix This change fixes one Agesa warning. Originally this commit included some changes that I later deemed unnecessary. Change-Id: I31ad13bb92509228b89921561c340c95e5136370 Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com> Signed-off-by: efdesign98 <efdesign98(a)gmail.com> See http://review.coreboot.org/132 for details. -gerrit

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Re: [coreboot] ASROCK e350m1 ASSERTION FAIL on CPU capability detection / No serial
by Vibrans, Frank 09 Aug '11

09 Aug '11

Hi Andrew, The assert failed because the structure involved didn’t pick up its default value out of PlatformInstall.h which is included in buildOpts.c. I’m suspicious of the hard path to the Family14 code in the Makefile.inc, but I don’t know that that is the definitive failure. You might also try uncommenting line 196 in you r buildOpts.c file since that is the particular option that is not getting set. That should get you going. FrankV From: Andrew Bolster [mailto:me@andrewbolster.info] Sent: Tuesday, August 09, 2011 4:03 AM To: coreboot(a)coreboot.org Cc: Vibrans, Frank Subject: ASROCK e350m1 ASSERTION FAIL on CPU capability detection / No serial Morning all; Quick bug report on the 'latest' master (commit ebbfbd59115c1a8ccf380041aecd6e903dcf925a) Build's fine but on boot: BSP Family_Model: 00500f10 cpu_init_detectedx = 00000000 Got past sb800_early_setup BSP Family_Model: 00500f10 cpu_init_detectedx = 00000001 Got past sb800_early_setup ASSERTION FAILED: file 'src/vendorcode/amd/agesa/f14/Proc/CPU/Table.c', line 1388 Also, as florz already mentioned, applying the relevant patch (http://review.coreboot.org/#change,139), the serial port is dead. Regards Andrew Bolster [http://andrewbolster.info/icons/feed.png]<http://andrewbolster.info/blog/?utm_source=correspondence&utm_medium=email&…>[http://andrewbolster.info/icons/linkedin.png]<http://www.linkedin.com/in/andrewbolster>[http://andrewbolster.info/icons/facebook.png]<http://facebook.com/andrew.bolster>[http://andrewbolster.info/icons/twitter.png]<http://twitter.com/bolster> No trees were killed to send this message, but a large number of electrons were terribly inconvenienced.I enjoy the massacre of ads. This sentence will slaughter ads without a messy bloodbath.

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ASROCK e350m1 ASSERTION FAIL on CPU capability detection / No serial
by Andrew Bolster 09 Aug '11

09 Aug '11

Morning all; Quick bug report on the 'latest' master (commit ebbfbd59115c1a8ccf380041aecd6e903dcf925a) Build's fine but on boot: BSP Family_Model: 00500f10 cpu_init_detectedx = 00000000 Got past sb800_early_setup BSP Family_Model: 00500f10 cpu_init_detectedx = 00000001 Got past sb800_early_setup ASSERTION FAILED: file 'src/vendorcode/amd/agesa/f14/Proc/CPU/Table.c', line 1388 Also, as florz already mentioned, applying the relevant patch ( http://review.coreboot.org/#change,139), the serial port is dead. Regards Andrew Bolster <http://andrewbolster.info/blog/?utm_source=correspondence&utm_medium=email&…><http://www.linkedin.com/in/andrewbolster><http://facebook.com/andrew.bolster><http://twitter.com/bolster> No trees were killed to send this message, but a large number of electrons were terribly inconvenienced.I enjoy the massacre of ads. This sentence will slaughter ads without a messy bloodbath.

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New patch to review: efa4eab smbus: Example of how to use generic smbus code
by Alexandru Gagniuc 09 Aug '11

09 Aug '11

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/144 -gerrit commit efa4eabbf4a197726d351685d48b61edfa202f06 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Tue Aug 9 02:00:43 2011 -0500 smbus: Example of how to use generic smbus code NOTFORMERGE Change-Id: If5ad8cd0942ac02d358a0139967e7d85d395660f Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/northbridge/via/vx900/Kconfig | 23 ++++ src/northbridge/via/vx900/Makefile.inc | 33 +++++ src/northbridge/via/vx900/early_smbus.c | 194 +++++++++++++++++++++++++++++++ src/northbridge/via/vx900/early_vx900.h | 31 +++++ src/northbridge/via/vx900/romstrap.inc | 50 ++++++++ src/northbridge/via/vx900/romstrap.lds | 27 +++++ src/northbridge/via/vx900/vx900.h | 26 ++++ 7 files changed, 384 insertions(+), 0 deletions(-) diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig new file mode 100644 index 0000000..60e7993 --- /dev/null +++ b/src/northbridge/via/vx900/Kconfig @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see <http://www.gnu.org/licenses/>. +## + +config NORTHBRIDGE_VIA_VX900 + bool + select HAVE_DEBUG_RAM_SETUP + select HAVE_DEBUG_SMBUS \ No newline at end of file diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc new file mode 100644 index 0000000..5450b1d --- /dev/null +++ b/src/northbridge/via/vx900/Makefile.inc @@ -0,0 +1,33 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see <http://www.gnu.org/licenses/>. +## + +romstage-y += early_smbus.c +romstage-y += raminit_ddr3.c +romstage-y += ./../../../devices/dram/dram_util.c +romstage-y += ./../../../devices/smbus/early_smbus.c + +# Drivers for these devices already exist with the vx800 +# Use those instead of duplicating code + +driver-y += ./../vx800/northbridge.c +driver-y += ./../vx800/vga.c +driver-y += ./../vx800/lpc.c + +chipset_bootblock_inc += $(src)/northbridge/via/vx900/romstrap.inc +chipset_bootblock_lds += $(src)/northbridge/via/vx900/romstrap.lds \ No newline at end of file diff --git a/src/northbridge/via/vx900/early_smbus.c b/src/northbridge/via/vx900/early_smbus.c new file mode 100644 index 0000000..707bd10 --- /dev/null +++ b/src/northbridge/via/vx900/early_smbus.c @@ -0,0 +1,194 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <device/pci_ids.h> +#include "early_vx900.h" + +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <console/console.h> +#include <devices/dram/dram.h> + +#define SMBUS_IO_BASE 0x500 +#include <devices/smbus/smbus.h> + +__attribute__((unused)) +static void smbus_delays(int delays) +{ + while(delays--) __smbus_delay(); +} + + +/** + * Read a byte from the SMBus. + * + * @param dimm The address location of the DIMM on the SMBus. + * @param offset The offset the data is located at. + */ +u8 __smbus_read_byte(u8 dimm, u8 offset, u16 __smbus_io_base) +{ + u8 val; + + /* Initialize SMBUS sequence */ + smbus_reset(); + /* Clear host data port. */ + outb(0x00, SMBHSTDAT0); + + smbus_wait_until_ready(); + smbus_delays(50); + + /* Actual addr to reg format. */ + dimm = (dimm << 1); + dimm |= 1; /* read command */ + outb(dimm, SMBXMITADD); + outb(offset, SMBHSTCMD); + /* Start transaction, byte data read. */ + outb(0x48, SMBHSTCTL); + smbus_wait_until_ready(); + + val = inb(SMBHSTDAT0); + return val; +} + +void enable_smbus(void) +{ + device_t dev; + u8 reg8; + u16 __smbus_io_base = SMBUS_IO_BASE; + + /* Locate the Power Management control */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VX900_LPC), 0); + + if (dev == PCI_DEV_INVALID) { + die("Power Managment Controller not found\n"); + } + + /* + * To use SMBus to manage devices on the system board, it is a must to + * enable SMBus function by setting + * PMU_RXD2[0] (SMBus Controller Enable) to 1. + * And set PMU_RXD0 and PMU_RXD1 (SMBus I/O Base) to an appropriate + * I/O port address, so that all registers in SMBus I/O port can be + * accessed. + */ + + reg8 = pci_read_config8(dev, 0xd2); + /* Enable SMBus controller */ + reg8 |= 1; + /* Set SMBUS clock from 128k source */ + reg8 |= 1<<2; + pci_write_config8(dev, 0xd2, reg8); + + reg8 = pci_read_config8(dev, 0x94); + /* SMBUS clock from divider of 14.318 MHz */ + reg8 &= ~(1<<7); + pci_write_config8(dev, 0x94, reg8); + + /* Set SMBus IO base */ + pci_write_config16(dev, 0xd0, SMBUS_IO_BASE); + + /* + * Initialize the SMBus sequence: + */ + /* Clear SMBus host status register */ + smbus_reset(); + /* Clear SMBus host data 0 register */ + outb(0x00, SMBHSTDAT0); + + /* Wait for SMBUS */ + smbus_wait_until_ready(); + +} + +void spd_read(u8 addr, spd_raw_data spd) +{ + u8 reg; + int i, regs; + reg = smbus_read_byte(addr, 2); + if(reg != 0x0b) + { + printk(BIOS_DEBUG, "SMBUS device %x not a DDR3 module\n", addr); + spd[2] = 0; + return; + } + + reg = smbus_read_byte(addr, 0); + reg &= 0xf; + if (reg == 0x3) { + regs = 256; + } else if (reg == 0x2) { + regs = 176; + } else if (reg == 0x1) { + regs = 128; + } else { + printk(BIOS_INFO, "No DIMM present at %x\n", addr); + spd[2] = 0; + return; + } + printk(BIOS_DEBUG, "SPD Data for DIMM %x \n", addr); + for (i = 0; i < regs; i++) { + reg = smbus_read_byte(addr, i); + //printk(BIOS_DEBUG, " Offset %u = 0x%x \n", i, reg ); + spd[i] = reg; + } +} + +void dump_spd_data(void) +{ + int dimm, offset, regs; + unsigned int reg; + spd_raw_data spd; + dimm_attr dimmx; + + for (dimm = 0x50; dimm < 0x52; dimm++) { + reg = smbus_read_byte(dimm, 2); + if(reg != 0x0b) + { + printk(BIOS_DEBUG, + "SMBUS device %x not a DDR3 module\n", dimm); + continue; + } + + reg = smbus_read_byte(dimm, 0); + reg &= 0xf; + if (reg == 0x3) { + regs = 256; + } else if (reg == 0x2) { + regs = 176; + } else if (reg == 0x1) { + regs = 128; + } else { + printk(BIOS_INFO, "No DIMM present at %x\n", dimm); + regs = 0; + continue; + } + printk(BIOS_DEBUG, "SPD Data for DIMM %x \n", dimm); + for (offset = 0; offset < regs; offset++) { + reg = smbus_read_byte(dimm, offset); + //printk(BIOS_DEBUG, " Offset %u = 0x%x \n", offset, reg ); + spd[offset] = reg; + } + + spd_decode_ddr3(&dimmx, spd); + dram_print_spd_ddr3(&dimmx); + + } +} + diff --git a/src/northbridge/via/vx900/early_vx900.h b/src/northbridge/via/vx900/early_vx900.h new file mode 100644 index 0000000..798cac0 --- /dev/null +++ b/src/northbridge/via/vx900/early_vx900.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef EARLY_VX900_H +#define EARLY_VX900_H + +#include <stdint.h> + +#include "raminit.h" + +void enable_smbus(void); +void dump_spd_data(void); +void spd_read(u8 addr, spd_raw_data spd); + +#endif /* EARLY_VX900_H */ diff --git a/src/northbridge/via/vx900/romstrap.inc b/src/northbridge/via/vx900/romstrap.inc new file mode 100644 index 0000000..8e54627 --- /dev/null +++ b/src/northbridge/via/vx900/romstrap.inc @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * (Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer) + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * Copyright (C) 2009 One Laptop per Child, Association, Inc. + * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file constructs the ROM strap table for VX900 */ + + .section ".romstrap", "a", @progbits + + .globl __romstrap_start +__romstrap_start: +tblpointer: + .long 0x77886047 + .long 0x00777777 + .long 0x00000000 + .long 0x00000000 + .long 0x00888888 + .long 0x00AA1111 + .long 0x00000000 + .long 0x00000000 + +/* + * The pointer to above table should be at 0xffffffd0, + * the table itself MUST be aligned to 128B it seems! + */ +rspointers: + .long tblpointer // It will be 0xffffffd0 + + .globl __romstrap_end + +__romstrap_end: +.previous diff --git a/src/northbridge/via/vx900/romstrap.lds b/src/northbridge/via/vx900/romstrap.lds new file mode 100644 index 0000000..b51c979 --- /dev/null +++ b/src/northbridge/via/vx900/romstrap.lds @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * (Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD) + * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/> + */ + +SECTIONS { + . = (0x100000000 - 0x2c) - (__romstrap_end - __romstrap_start); + .romstrap (.): { + *(.romstrap) + } +} diff --git a/src/northbridge/via/vx900/vx900.h b/src/northbridge/via/vx900/vx900.h new file mode 100644 index 0000000..2137daf --- /dev/null +++ b/src/northbridge/via/vx900/vx900.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#define VX800_ACPI_IO_BASE 0x0400 + +#define VX900_NB_IOAPIC_ID 0x2 +#define VX900_NB_IOAPIC_BASE 0xfecc000 + +#define VX900_SB_IOAPIC_ID 0x1 +#define VX900_SB_IOAPIC_BASE 0xfec0000 \ No newline at end of file

1 0

New patch to review: 9d152c1 coreboot: Add generic SMBUS implementation
by Alexandru Gagniuc 09 Aug '11

09 Aug '11

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/143 -gerrit commit 9d152c129b6f9fdd084185ed67cc1fc31529ad74 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Tue Aug 9 01:26:52 2011 -0500 coreboot: Add generic SMBUS implementation Early SMBUS code with similar functionality is duplicated for all southbridges. Add a generic SMBUS implementation, with functions declared weak, so that they can be overridden by the southbridge code if necessary. Change-Id: I0861b7a3f098115182ae6de9f016dd671c500bad Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/devices/smbus/early_smbus.c | 141 +++++++++++++++++++++++++++++++++++++++ src/devices/smbus/smbus.h | 100 +++++++++++++++++++++++++++ 2 files changed, 241 insertions(+), 0 deletions(-) diff --git a/src/devices/smbus/early_smbus.c b/src/devices/smbus/early_smbus.c new file mode 100644 index 0000000..4583aca --- /dev/null +++ b/src/devices/smbus/early_smbus.c @@ -0,0 +1,141 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ +/** + * @file post_codes.h + * + * This file defines the implementations for the functions defined in smbus.h + * These are a generic SMBUS implementation, which should work with a majority + * of chipsets. + * They are marked weak so that they can be overridden by the chipset code if + * necessary. + */ + +#include "smbus.h" + +/** + * \brief Brief delay for SMBUS transactions + */ +__attribute__((weak)) +void __smbus_delay(void) +{ + inb(0x80); +} + +/** + * \brief Clear the SMBUS host status register + */ +__attribute__((weak)) +void __smbus_reset(u16 __smbus_io_base) +{ + outb(0xdf, SMBHSTSTAT); +} + +/** + * \brief Print an error, should it occur. If no error, just exit. + * + * @param host_status The data returned on the host status register after + * a transaction is processed. + * @param loops The number of times a transaction was attempted. + * @return 0 if no error occurred + * 1 if an error was detected + */ +__attribute__((weak)) +int __smbus_print_error(u8 host_status, int loops, u16 __smbus_io_base) +{ + /* Check if there actually was an error. */ + if ((host_status == 0x00 || host_status == 0x40 || + host_status == 0x42) && (loops < SMBUS_TIMEOUT)) + return 0; + + if (loops >= SMBUS_TIMEOUT) + printsmbus("SMBus timeout\n"); + if (host_status & (1 << 4)) + printsmbus("Interrupt/SMI# was Failed Bus Transaction\n"); + if (host_status & (1 << 3)) + printsmbus("Bus error\n"); + if (host_status & (1 << 2)) + printsmbus("Device error\n"); + if (host_status & (1 << 1)) + printsmbus("Interrupt/SMI# completed successfully\n"); + if (host_status & (1 << 0)) + printsmbus("Host busy\n"); + return 1; +} + +/** + * \brief Checks if the SMBUS is currently busy with a transaction + */ +__attribute__((weak)) +int __smbus_is_busy(u16 __smbus_io_base) +{ + /* Check if bit 0 of the status register is 1 (busy) or 0 (ready) */ + return ( (inb(SMBHSTSTAT) & (1 << 0)) == 1); +} + +/** + * \brief Wait for the SMBUS to become ready to process a new transaction. + */ +__attribute__((weak)) +int __smbus_wait_until_ready(u16 __smbus_io_base) +{ + int loops; + + printsmbus("Waiting until SMBus ready\n"); + + /* Loop up to SMBUS_TIMEOUT times, waiting for bit 0 of the + * SMBus Host Status register to go to 0, indicating the operation + * was completed successfully. I don't remember why I did it this way, + * but I think it was because ROMCC was running low on registers */ + loops = 0; + while (__smbus_is_busy(__smbus_io_base) && loops < SMBUS_TIMEOUT) + ++loops; + + return __smbus_print_error(inb(SMBHSTSTAT), loops, __smbus_io_base); +} + +/** + * \brief Read a byte from the SMBUS. + * + * @param dimm The address location of the DIMM on the SMBus. + * @param offset The offset the data is located at. + */ +__attribute__((weak)) +u8 __smbus_read_byte(u8 dimm, u8 offset, u16 __smbus_io_base) +{ + u8 val; + + /* Initialize SMBUS sequence */ + __smbus_reset(__smbus_io_base); + /* Clear host data port. */ + outb(0x00, SMBHSTDAT0); + + __smbus_wait_until_ready(__smbus_io_base); + + /* Actual addr to reg format. */ + dimm = (dimm << 1); + dimm |= 1; /* read command */ + outb(dimm, SMBXMITADD); + outb(offset, SMBHSTCMD); + /* Start transaction, byte data read. */ + outb(0x48, SMBHSTCTL); + __smbus_wait_until_ready(__smbus_io_base); + + val = inb(SMBHSTDAT0); + return val; +} \ No newline at end of file diff --git a/src/devices/smbus/smbus.h b/src/devices/smbus/smbus.h new file mode 100644 index 0000000..c730669 --- /dev/null +++ b/src/devices/smbus/smbus.h @@ -0,0 +1,100 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/** + * @file post_codes.h + * + * This file defines the prototypes for several common SMBUS functions + * These functions are prefixed with __smbus_ so that they do not conflict with + * the dozens of similar (duplicated) implementations in many southbridges. + * + * As a last parameter, the SMBUS functions take a u16 value __smbus_io_base, + * which represents the base IO port for smbus transactions + */ + +#include <arch/io.h> + +/** + * \brief SMBUS IO ports in relation to the base IO port + */ +#define SMBHSTSTAT __smbus_io_base + 0x0 +#define SMBSLVSTAT __smbus_io_base + 0x1 +#define SMBHSTCTL __smbus_io_base + 0x2 +#define SMBHSTCMD __smbus_io_base + 0x3 +#define SMBXMITADD __smbus_io_base + 0x4 +#define SMBHSTDAT0 __smbus_io_base + 0x5 +#define SMBHSTDAT1 __smbus_io_base + 0x6 +#define SMBBLKDAT __smbus_io_base + 0x7 +#define SMBSLVCTL __smbus_io_base + 0x8 +#define SMBTRNSADD __smbus_io_base + 0x9 +#define SMBSLVDATA __smbus_io_base + 0xa + +#define SMBUS_TIMEOUT (100*1000*10) + +/** + * \brief printk macro for SMBUS debugging + */ +#if defined(CONFIG_DEBUG_SMBUS_SETUP) && (CONFIG_DEBUG_SMBUS_SETUP) +#define printsmbus(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__) +#else +#define printsmbus(x, ...) +#endif + + +void __smbus_reset(u16 __smbus_io_base); +int __smbus_print_error(u8 host_status, int loops, u16 __smbus_io_base); +int __smbus_is_busy(u16 __smbus_io_base); +int __smbus_wait_until_ready(u16 __smbus_io_base); +u8 __smbus_read_byte(u8 dimm, u8 offset, u16 __smbus_io_base); + +void __smbus_delay(void); + +#if defined(SMBUS_IO_BASE) && (SMBUS_IO_BASE != 0) + +__attribute__((always_inline, unused)) +static void smbus_reset(void) +{ + __smbus_reset(SMBUS_IO_BASE); +} + +__attribute__((always_inline, unused)) +static int smbus_is_busy(void) +{ + return __smbus_is_busy(SMBUS_IO_BASE); +} + +__attribute__((always_inline, unused)) +static int smbus_wait_until_ready(void) +{ + return __smbus_wait_until_ready(SMBUS_IO_BASE); +} + +__attribute__((always_inline, unused)) +static int smbus_print_error(u8 host_status, int loops) +{ + return __smbus_print_error(host_status, loops, SMBUS_IO_BASE); +} + +__attribute__((always_inline, unused)) +static u8 smbus_read_byte(u8 dimm, u8 offset) +{ + return __smbus_read_byte(dimm, offset, SMBUS_IO_BASE); +} + +#endif \ No newline at end of file

1 0

Modifying Coreboot to support a new processor
by Dsouza, Malcolm 09 Aug '11

09 Aug '11

Hi Everyone, I trust all are in the best of health. I am planning to use Coreboot as the BIOS for the new Intel 2nd Generation Processors. However Coreboot does not support this processor or its associated chipset. To better understand the efforts needed in the respective areas, I have hence begun comparing various features present in the datasheets of the Intel chipsets Coreboot presently supports with the chipset I plan to use. Based on these findings I am trying to come to the conclusion about the areas in the code that will require modifications. Is this the right approach? Or should I try differently? Please send me your suggestions. Thanks and Regards! ________________________________ Information contained and transmitted by this e-mail is confidential and proprietary to iGATE Patni and its affiliates and is intended for use only by the recipient. If you are not the intended recipient, you are hereby notified that any dissemination, distribution, copying or use of this e-mail is strictly prohibited and you are requested to delete this e-mail immediately and notify the originator or mailadmin(a)igatepatni.com. iGATE Patni does not enter into any agreement with any party by e-mail. Any views expressed by an individual do not necessarily reflect the view of iGATE Patni. iGATE Patni is not responsible for the consequences of any actions taken on the basis of information provided, through this email. The contents of an attachment to this e-mail may contain software viruses, which could damage your own computer system. While iGATE Patni has taken every reasonable precaution to minimise this risk, we cannot accept liability for any damage which you sustain as a result of software viruses. You should carry out your own virus checks before opening an attachment. To know more about iGATE Patni please visit www.igatepatni.com.

2 1

Parsing coreboot tables from Linux driver
by Philip Prindeville 08 Aug '11

08 Aug '11

I'm adding a Geos platform driver that needs to be able to confirm that it's running on the correct hardware, and it does this by locating the Coreboot tables and parsing them for the vendor/part fields. Unfortunately, it's not working entirely. I borrowed code from flashrom's cbtable.c and tweaked it: ... #define BYTES_TO_MAP (1024*1024) struct lb_record *coreboot_init(void) { uint8_t *table_area; unsigned long addr, start; struct lb_header *lb_table; struct lb_record *rec, *last; start = 0x0; table_area = phys_to_virt(start); printk(KERN_INFO "trying %#x (%#x)\n", start, table_area); lb_table = find_lb_table(table_area, 0x00000, 0x1000); printk(KERN_INFO "find_lb_table returns %#x\n", lb_table); if (!lb_table) { printk(KERN_INFO "2nd try %#x (%#x)\n", start, table_area); lb_table = find_lb_table(table_area, 0xf0000 - start, BYTES_TO_MAP - start); printk(KERN_INFO "find_lb_table returns %#x\n", lb_table); } if (lb_table) { struct lb_forward *forward = (struct lb_forward *) (((char *)lb_table) + lb_table->header_bytes); printk(KERN_INFO "forward=%#x\n", forward); if (forward->tag == LB_TAG_FORWARD) { start = forward->forward; start &= ~(PAGE_SIZE - 1); table_area = phys_to_virt(start); printk(KERN_INFO "3rd try %#x (%#x)\n", start, table_area); lb_table = find_lb_table(table_area, 0x00000, 0x1000); printk(KERN_INFO "find_lb_table returns %#x\n", lb_table); } } if (!lb_table) { msg_pinfo("No coreboot table found.\n"); return NULL; } addr = ((char *)lb_table) - ((char *)table_area) + start; msg_pinfo("coreboot table found at 0x%lx.\n", (unsigned long)lb_table - (unsigned long)table_area + start); rec = (struct lb_record *)(((char *)lb_table) + lb_table->header_bytes); last = (struct lb_record *)(((char *)rec) + lb_table->table_bytes); msg_pdbg("coreboot header(%d) checksum: %04x table(%d) checksum: %04x entries: %d\n", lb_table->header_bytes, lb_table->header_checksum, lb_table->table_bytes, lb_table->table_checksum, lb_table->table_entries); search_lb_records(rec, last, addr + lb_table->header_bytes); return rec; } EXPORT_SYMBOL(coreboot_init); const char *coreboot_vendor(void) { return lb_vendor; } EXPORT_SYMBOL(coreboot_vendor); const char *coreboot_part(void) { return lb_part; } EXPORT_SYMBOL(coreboot_part); And obviously threw in some debugging. Here's what I get when I run it: rying 0x0 (0xc0000000) find_lb_table returns 0xc0000500 forward=0xc0000518 3rd try 0x1f7d1000 (0xdf7d1000) BUG: unable to handle kernel paging request at df7d1000 IP: [<c10fe1fe>] find_lb_table+0x26/0x11b *pde = 017fb067 *pte = 00000000 Oops: 0000 [#1] last sysfs file: Modules linked in: Pid: 1, comm: swapper Not tainted 2.6.39.3 #1 Bochs Bochs EIP: 0060:[<c10fe1fe>] EFLAGS: 00010287 CPU: 0 EIP is at find_lb_table+0x26/0x11b EAX: df7d1000 EBX: df7d1000 ECX: 00000004 EDX: 00000000 ESI: df7d1000 EDI: c122ea56 EBP: 00001000 ESP: dec3bf8c DS: 007b ES: 007b FS: 0000 GS: 0000 SS: 0068 Process swapper (pid: 1, ti=dec3a000 task=dec38000 task.ti=dec3a000) Stack: df7d1000 00000000 1f7d1000 c0000500 df7d1000 00000000 c10fe45b c122eb05 1f7d1000 df7d1000 00000000 c1286631 00000000 c1291dab 00000000 c10010fa c1291d8d c12b554c c1286631 00000000 00000000 c12866af 00000000 c11cb796 Call Trace: [<c10fe45b>] ? coreboot_init+0xb2/0x13a [<c1286631>] ? start_kernel+0x269/0x269 [<c1291dab>] ? geos_init+0x1e/0x50 [<c10010fa>] ? do_one_initcall+0x6f/0x10d [<c1291d8d>] ? sysenter_setup+0x2c4/0x2c4 [<c1286631>] ? start_kernel+0x269/0x269 [<c12866af>] ? kernel_init+0x7e/0xf7 [<c11cb796>] ? kernel_thread_helper+0x6/0xd Code: 0f b7 c0 5f c3 55 57 56 53 83 ec 08 01 d0 89 cd 89 04 24 89 54 24 04 e9 ee 00 00 00 8b 1c 24 bf 56 ea 22 c1 89 de b9 04 00 00 00 <f3> a6 0f 85 ce 00 00 00 8b 44 24 04 03 43 0c 50 ff 74 24 08 68 EIP: [<c10fe1fe>] find_lb_table+0x26/0x11b SS:ESP 0068:dec3bf8c CR2: 00000000df7d1000 ---[ end trace 93d72a36b9146f22 ]--- Kernel panic - not syncing: Attempted to kill init! Pid: 1, comm: swapper Tainted: G D 2.6.39.3 #1 Call Trace: [<c11c981e>] ? panic+0x4d/0x12a [<c101f1e7>] ? do_exit+0x226/0x57d [<c1004200>] ? oops_end+0x82/0x86 [<c101565a>] ? no_context+0x10c/0x116 [<c1015940>] ? vmalloc_sync_all+0xa9/0xa9 [<c101576b>] ? bad_area_nosemaphore+0xa/0xc [<c1015a9d>] ? do_page_fault+0x15d/0x350 [<c111a255>] ? check_modem_status+0x184/0x184 [<c101cf09>] ? __call_console_drivers+0x41/0x4d [<c1015940>] ? vmalloc_sync_all+0xa9/0xa9 [<c11cb01c>] ? error_code+0x58/0x60 [<c11c0000>] ? br_multicast_add_group+0x480/0x495 [<c1015940>] ? vmalloc_sync_all+0xa9/0xa9 [<c10fe1fe>] ? find_lb_table+0x26/0x11b [<c10fe45b>] ? coreboot_init+0xb2/0x13a [<c1286631>] ? start_kernel+0x269/0x269 [<c1291dab>] ? geos_init+0x1e/0x50 [<c10010fa>] ? do_one_initcall+0x6f/0x10d [<c1291d8d>] ? sysenter_setup+0x2c4/0x2c4 [<c1286631>] ? start_kernel+0x269/0x269 [<c12866af>] ? kernel_init+0x7e/0xf7 [<c11cb796>] ? kernel_thread_helper+0x6/0xd What am I missing? What's wrong with the forward pointer? Thanks, -Philip

1 0

Trac reminder: list of new ticket(s)
by coreboot tracker 08 Aug '11

08 Aug '11

1 0

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coreboot August 2011