Hi, thank you both for the answers. I have studied libpci from
libpayload and removed that device list generation with mallocs. Done a
bunch of trial-error cleanup and now chipset enable and probing for
flash works in ramstage's top of hardwaremain function with this line
x86_setup_mtrrs(36); //from cpu init routine
see attached log: ramstage_with_mtrr.txt.
Also attaching nonworking logs in romstage and ramstage.
Now the question is how these mtrrs should be set in cache_as_ram.inc or
maybe I'm totally wrong? :)