coreboot August 2011

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217 discussions

New patch to review: 4e4140f Remove debugging code, or convert it to be selected by kconfig
by Jonathan A. Kollasch 03 Aug '11

03 Aug '11

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/130 -gerrit commit 4e4140fb91b21116877205b6ce5370803eda8d83 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Wed Aug 3 13:56:24 2011 -0500 Remove debugging code, or convert it to be selected by kconfig Change-Id: Ib6cd82badeb6401e065ee14c2a04c78f61a87dd4 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/mainboard/msi/ms7135/romstage.c | 11 +---------- 1 files changed, 1 insertions(+), 10 deletions(-) diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index 5feef79..80b3c19 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -112,10 +112,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Halt if there was a built in self test failure */ report_bist_failure(bist); -#if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); -#endif - needs_reset = setup_coherent_ht_domain(); wait_all_core0_started(); @@ -140,17 +136,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_smbus(); -#if 0 +#if CONFIG_DEBUG_SMBUS dump_spd_registers(&ctrl[0]); dump_smbus_registers(); #endif sdram_initialize(nodes, ctrl); -#if 0 - print_pci_devices(); - dump_pci_devices(); -#endif - post_cache_as_ram(); }

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Patch merged into master: 523ae5d Use preferred style of fixed-width integer types
by gerrit＠coreboot.org 03 Aug '11

03 Aug '11

the following patch was just integrated into master: commit 523ae5d776879621fabe6f338c1b8c808636a57d Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Mon Aug 1 14:15:28 2011 -0500 Use preferred style of fixed-width integer types Change-Id: I1abaaa2af4de940584039f9b8c348bb57fb611e0 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> See http://review.coreboot.org/125 for details. -gerrit

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New patch to review: 36161df Do not compile nuvoton superio for all board
by Alexandru Gagniuc 03 Aug '11

03 Aug '11

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/129 -gerrit commit 36161df7a4fb2733be2659fa2a395cccc27907ba Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Wed Aug 3 09:14:59 2011 -0500 Do not compile nuvoton superio for all board The nuvoton WPCM450 code is compiled for all boards regardless of whether or not they use it. Compile it only for boards needing it. Change-Id: Iaf4cf2c479eb3238863f0771be799f02a8cc3421 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/supermicro/h8qgi/Kconfig | 1 + src/mainboard/supermicro/h8scm_fam10/Kconfig | 1 + src/superio/nuvoton/Makefile.inc | 2 +- src/superio/nuvoton/wpcm450/Makefile.inc | 2 +- 4 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig index 286cb17..22760d2 100755 --- a/src/mainboard/supermicro/h8qgi/Kconfig +++ b/src/mainboard/supermicro/h8qgi/Kconfig @@ -28,6 +28,7 @@ config BOARD_SPECIFIC_OPTIONS select SOUTHBRIDGE_AMD_SR5650 select SOUTHBRIDGE_AMD_SP5100 select SUPERIO_WINBOND_W83627DHG + select SUPERIO_NUVOTON_WPCM450 select BOARD_HAS_FADT select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE diff --git a/src/mainboard/supermicro/h8scm_fam10/Kconfig b/src/mainboard/supermicro/h8scm_fam10/Kconfig index 7742133..cbd3119 100755 --- a/src/mainboard/supermicro/h8scm_fam10/Kconfig +++ b/src/mainboard/supermicro/h8scm_fam10/Kconfig @@ -10,6 +10,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_AMD_SR5650 select SOUTHBRIDGE_AMD_SP5100 select SUPERIO_WINBOND_W83627HF + select SUPERIO_NUVOTON_WPCM450 select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE select GENERATE_PIRQ_TABLE diff --git a/src/superio/nuvoton/Makefile.inc b/src/superio/nuvoton/Makefile.inc index 2f2ea96..4553dd8 100644 --- a/src/superio/nuvoton/Makefile.inc +++ b/src/superio/nuvoton/Makefile.inc @@ -17,4 +17,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -subdirs-y += wpcm450 +subdirs-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += wpcm450 diff --git a/src/superio/nuvoton/wpcm450/Makefile.inc b/src/superio/nuvoton/wpcm450/Makefile.inc index db88097..c70b2fb 100644 --- a/src/superio/nuvoton/wpcm450/Makefile.inc +++ b/src/superio/nuvoton/wpcm450/Makefile.inc @@ -18,6 +18,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += early_init.c +romstage-y += early_init.c ramstage-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += superio.c

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New patch to review: b53bf7f northbridge/intel/i440bx: Registered SDRAM modules support and fixes
by Keith Hui 03 Aug '11

03 Aug '11

Keith Hui (buurin(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/128 -gerrit commit b53bf7f4780362a7cc92d9947891ea492ca7163d Author: Keith Hui <buurin(a)gmail.com> Date: Tue Aug 2 22:28:14 2011 -0400 northbridge/intel/i440bx: Registered SDRAM modules support and fixes Adds support for initializing registered SDRAM modules on Intel 440BX northbridge. Drops unneeded romcc-inspired programming tricks. Only set nbxecc flags (see 440BX datasheet, page 3-16) when a non-ECC module has been detected in a row via SPD; also drops an unneeded intermediate variable used in setting them. Boot tested on ASUS P2B-LS with regular and registered ECC SDRAM under Linux and memtest86+. Change-Id: Idc99d49567cca55f819d6b0e98952b1c3256498a Signed-off-by: Keith Hui <buurin(a)gmail.com> --- src/northbridge/intel/i440bx/raminit.c | 64 +++++++++++++++++++------------ 1 files changed, 39 insertions(+), 25 deletions(-) diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index 9fc124b..232b872 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -258,7 +258,7 @@ static const u8 register_values[] = { * 01 4 KB * 10 8 KB * 11 Reserved - * + * * RPS bits Corresponding DRB register * [01:00] DRB[0], row 0 * [03:02] DRB[1], row 1 @@ -721,19 +721,23 @@ static struct dimm_size spd_get_dimm_size(unsigned int device) */ static void set_dram_row_attributes(void) { - int i, dra, drb, col, width, value, rps, edosd, ecc, nbxecc; + int i, dra, drb, col, width, value, rps; u8 bpr; /* Top 8 bits of PGPOL */ + u8 nbxecc = 0; /* NBXCFG[31:24] */ + u8 edo, sd, regsd; /* EDO, SDRAM, registered SDRAM */ - edosd = 0; + edo = 0; + sd = 0; + regsd = 1; rps = 0; drb = 0; bpr = 0; - nbxecc = 0xff; for (i = 0; i < DIMM_SOCKETS; i++) { unsigned int device; device = DIMM0 + i; bpr >>= 2; + nbxecc >>= 2; /* First check if a DIMM is actually present. */ value = spd_read_byte(device, SPD_MEMORY_TYPE); @@ -742,13 +746,13 @@ static void set_dram_row_attributes(void) || value == SPD_MEMORY_TYPE_SDRAM) { if (value == SPD_MEMORY_TYPE_EDO) { - edosd |= 0x02; + edo = 1; } else if (value == SPD_MEMORY_TYPE_SDRAM) { - edosd |= 0x04; + sd = 1; } PRINT_DEBUG("Found DIMM in slot %d\n", i); - if (edosd == 0x06) { + if (edo && sd) { print_err("Mixing EDO/SDRAM unsupported!\n"); die("HALT\n"); } @@ -764,23 +768,37 @@ static void set_dram_row_attributes(void) * TODO: Other register than NBXCFG also needs this * ECC information. */ - ecc = spd_read_byte(device, SPD_DIMM_CONFIG_TYPE); + value = spd_read_byte(device, SPD_DIMM_CONFIG_TYPE); /* Data width */ width = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB); /* Exclude error checking data width from page size calculations */ - if (ecc) { + if (value) { value = spd_read_byte(device, SPD_ERROR_CHECKING_SDRAM_WIDTH); width -= value; /* ### ECC */ /* Clear top 2 bits to help set up NBXCFG. */ - ecc &= 0x3f; + nbxecc &= 0x3f; } else { /* Without ECC, top 2 bits should be 11. */ - ecc |= 0xc0; + nbxecc |= 0xc0; + } + + /* If any installed DIMM is *not* registered, this system cannot be + * configured for registered SDRAM. + * By registered, only the address and control lines need to be, which + * we can tell by reading SPD byte 21, bit 1. + */ + value = spd_read_byte(device, SPD_MODULE_ATTRIBUTES); + + PRINT_DEBUG("DIMM is "); + if ((value & MODULE_REGISTERED) == 0) { + regsd = 0; + PRINT_DEBUG("not "); } + PRINT_DEBUG("registered\n"); /* Calculate page size in bits. */ value = ((1 << col) * width); @@ -801,7 +819,6 @@ static void set_dram_row_attributes(void) * Second bank of 1-bank DIMMs "doesn't have * ECC" - or anything. */ - ecc |= 0x80; if (dra == 2) { dra = 0x0; /* 2KB */ } else if (dra == 4) { @@ -878,7 +895,6 @@ static void set_dram_row_attributes(void) /* If there's no DIMM in the slot, set dra to 0x00. */ dra = 0x00; - ecc = 0xc0; /* Still have to propagate DRB over. */ drb &= 0xff; drb |= (drb << 8); @@ -895,7 +911,6 @@ static void set_dram_row_attributes(void) drb >>= 8; rps |= (dra & 0x0f) << (i * 4); - nbxecc = (nbxecc >> 2) | (ecc & 0xc0); } /* Set paging policy register. */ @@ -910,20 +925,19 @@ static void set_dram_row_attributes(void) pci_write_config8(NB, NBXCFG + 3, nbxecc); PRINT_DEBUG("NBXECC[31:24] has been set to 0x%02x\n", nbxecc); - /* Set DRAMC[4:3] to proper memory type (EDO/SDRAM). - * TODO: Registered SDRAM support. - */ - edosd &= 0x07; - if (edosd & 0x02) { - edosd |= 0x00; - } else if (edosd & 0x04) { - edosd |= 0x08; + /* Set DRAMC[4:3] to proper memory type (EDO/SDRAM/Registered SDRAM). */ + + /* i will be used to set DRAMC[4:3]. */ + if (regsd && sd) { + i = 0x10; // Registered SDRAM + } else if (sd) { + i = 0x08; // SDRAM + } else { + i = 0; // EDO } - edosd &= 0x18; - /* edosd is now in the form needed for DRAMC[4:3]. */ value = pci_read_config8(NB, DRAMC) & 0xe7; - value |= edosd; + value |= i; pci_write_config8(NB, DRAMC, value); PRINT_DEBUG("DRAMC has been set to 0x%02x\n", value); }

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Patch set updated: 1f23d3b Add voltage control of southbridge and RAM on ms7135
by Jonathan A. Kollasch 02 Aug '11

02 Aug '11

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/126 -gerrit commit 1f23d3b27abed80ee846807a2fe0421d72226679 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Mon Aug 1 14:24:02 2011 -0500 Add voltage control of southbridge and RAM on ms7135 Change-Id: I5d79b4838f69cad56d58363608b801f8b1d3ab43 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/mainboard/msi/ms7135/cmos.layout | 16 +++++++++++-- src/mainboard/msi/ms7135/romstage.c | 39 +++++++++++++++++++++++++-------- 2 files changed, 42 insertions(+), 13 deletions(-) diff --git a/src/mainboard/msi/ms7135/cmos.layout b/src/mainboard/msi/ms7135/cmos.layout index 53fdef5..694554d 100644 --- a/src/mainboard/msi/ms7135/cmos.layout +++ b/src/mainboard/msi/ms7135/cmos.layout @@ -43,6 +43,8 @@ entries 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu +448 4 e 10 ram_voltage +452 4 e 11 nf4_voltage 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers @@ -74,10 +76,10 @@ enumerations 7 0 Network 7 1 HDD 7 2 Floppy +#7 3 ROM 7 8 Fallback_Network 7 9 Fallback_HDD 7 10 Fallback_Floppy -#7 3 ROM 8 0 400Mhz 8 1 333Mhz 8 2 266Mhz @@ -91,8 +93,16 @@ enumerations 9 6 25.0% 9 7 12.5% -checksums +10 0 2.55 +10 1 2.50 +10 2 2.60 +10 3 2.65 +10 4 2.70 -checksum 392 983 984 +11 0 1.50 +11 1 1.55 +11 2 1.60 +checksums +checksum 392 983 984 diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index 8609142..1b1c119 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -48,6 +48,10 @@ #include "cpu/amd/dualcore/dualcore.c" #include <spd.h> +#if CONFIG_HAVE_OPTION_TABLE +#include "option_table.h" +#endif + #define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1) static void memreset(int controllers, const struct mem_controller *ctrl) { } @@ -66,6 +70,27 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" #include "northbridge/amd/amdk8/early_ht.c" +static void ms7135_set_ram_voltage(void) +{ + u8 b; + b = read_option(ram_voltage, 0); + if (b > 4) /* default if above 2.70v */ + b = 0; + printk(BIOS_INFO, "setting RAM voltage %08x\n", b); + ck804_smbus_write_byte(1, 0x2f, 0x00, b); +} + +static void ms7135_set_nf4_voltage(void) +{ + u8 b; + b = read_option(nf4_voltage, 0); + if (b > 2) /* default if above 1.60v */ + b = 0; + b |= 0x10; + printk(BIOS_INFO, "setting NF4 voltage %08x\n", b); + ck804_smbus_write_byte(1, 0x2f, 0x02, b); +} + static void sio_setup(void) { uint32_t dword; @@ -112,10 +137,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Halt if there was a built in self test failure */ report_bist_failure(bist); -#if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); -#endif - needs_reset = setup_coherent_ht_domain(); wait_all_core0_started(); @@ -140,17 +161,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_smbus(); -#if 0 + ms7135_set_nf4_voltage(); + ms7135_set_ram_voltage(); + +#if CONFIG_DEBUG_SMBUS dump_spd_registers(&ctrl[0]); dump_smbus_registers(); #endif sdram_initialize(nodes, ctrl); -#if 0 - print_pci_devices(); - dump_pci_devices(); -#endif - post_cache_as_ram(); }

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Patch set updated: a421bfc Add voltage control of southbridge and RAM on ms7135
by Jonathan A. Kollasch 02 Aug '11

02 Aug '11

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/126 -gerrit commit a421bfc242ff938dfa334dc8b7f5567bd5b0df16 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Mon Aug 1 14:24:02 2011 -0500 Add voltage control of southbridge and RAM on ms7135 Change-Id: I5d79b4838f69cad56d58363608b801f8b1d3ab43 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/mainboard/msi/ms7135/cmos.layout | 16 +++++++++++-- src/mainboard/msi/ms7135/romstage.c | 39 +++++++++++++++++++++++++-------- 2 files changed, 42 insertions(+), 13 deletions(-) diff --git a/src/mainboard/msi/ms7135/cmos.layout b/src/mainboard/msi/ms7135/cmos.layout index 53fdef5..694554d 100644 --- a/src/mainboard/msi/ms7135/cmos.layout +++ b/src/mainboard/msi/ms7135/cmos.layout @@ -43,6 +43,8 @@ entries 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu +448 4 e 10 ram_voltage +452 4 e 11 nf4_voltage 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers @@ -74,10 +76,10 @@ enumerations 7 0 Network 7 1 HDD 7 2 Floppy +#7 3 ROM 7 8 Fallback_Network 7 9 Fallback_HDD 7 10 Fallback_Floppy -#7 3 ROM 8 0 400Mhz 8 1 333Mhz 8 2 266Mhz @@ -91,8 +93,16 @@ enumerations 9 6 25.0% 9 7 12.5% -checksums +10 0 2.55 +10 1 2.50 +10 2 2.60 +10 3 2.65 +10 4 2.70 -checksum 392 983 984 +11 0 1.50 +11 1 1.55 +11 2 1.60 +checksums +checksum 392 983 984 diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index 8609142..1590745 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -48,6 +48,10 @@ #include "cpu/amd/dualcore/dualcore.c" #include <spd.h> +#if CONFIG_HAVE_OPTION_TABLE +#include "option_table.h" +#endif + #define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1) static void memreset(int controllers, const struct mem_controller *ctrl) { } @@ -66,6 +70,27 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" #include "northbridge/amd/amdk8/early_ht.c" +static void ms7135_set_ram_voltage(void) +{ + u8 b; + b = read_option(ram_voltage, 0); + if (b > 4) /* default if above 2.70v */ + b = 0; + printk("setting RAM voltage %08x\n", b); + ck804_smbus_write_byte(1, 0x2f, 0x00, b); +} + +static void ms7135_set_nf4_voltage(void) +{ + u8 b; + b = read_option(nf4_voltage, 0); + if (b > 2) /* default if above 1.60v */ + b = 0; + b |= 0x10; + printk("setting NF4 voltage %08x\n", b); + ck804_smbus_write_byte(1, 0x2f, 0x02, b); +} + static void sio_setup(void) { uint32_t dword; @@ -112,10 +137,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Halt if there was a built in self test failure */ report_bist_failure(bist); -#if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); -#endif - needs_reset = setup_coherent_ht_domain(); wait_all_core0_started(); @@ -140,17 +161,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_smbus(); -#if 0 + ms7135_set_nf4_voltage(); + ms7135_set_ram_voltage(); + +#if CONFIG_DEBUG_SMBUS dump_spd_registers(&ctrl[0]); dump_smbus_registers(); #endif sdram_initialize(nodes, ctrl); -#if 0 - print_pci_devices(); - dump_pci_devices(); -#endif - post_cache_as_ram(); }

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Re: [coreboot] libpci accesses in CAR, I need a suggestion
by Tadas Slotkus 01 Aug '11

01 Aug '11

Hi, thank you both for the answers. I have studied libpci from libpayload and removed that device list generation with mallocs. Done a bunch of trial-error cleanup and now chipset enable and probing for flash works in ramstage's top of hardwaremain function with this line included: x86_setup_mtrrs(36); //from cpu init routine see attached log: ramstage_with_mtrr.txt. Also attaching nonworking logs in romstage and ramstage. Now the question is how these mtrrs should be set in cache_as_ram.inc or maybe I'm totally wrong? :) Thanks, Tadas

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New patch to review: df8d54c Initialize ACPI to prevent spurious events at OS boot
by Jonathan A. Kollasch 01 Aug '11

01 Aug '11

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/127 -gerrit commit df8d54c4372f1e851c413c5903db20284eb57c06 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Mon Aug 1 15:17:08 2011 -0500 Initialize ACPI to prevent spurious events at OS boot Change-Id: I7e1138360f18ba857cf533baa8ec1db555aebcde Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/southbridge/nvidia/ck804/lpc.c | 20 ++++++++++++++++++++ 1 files changed, 20 insertions(+), 0 deletions(-) diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index d371882..b66a569 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -28,6 +28,7 @@ #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> +#include <delay.h> #include <bitops.h> #include <arch/io.h> #include <arch/ioapic.h> @@ -104,6 +105,23 @@ static void rom_dummy_write(device_t dev) pci_write_config8(dev, 0x6d, new); } +static void lpc_acpi_init(u16 base) +{ + u16 word; + + printk(BIOS_SPEW, "%s: base = %x \n", __func__, base); + + /* clear sleep, set SCI_EN */ + word = inw(base + 4); + word &= ~(7 << 10); + word |= 1; + outw(word, base + 4); + udelay(100); /* seems to be needed */ + + /* clear ACPI PM1 event status */ + outw(0xffff, base + 0); +} + unsigned pm_base = 0; static void lpc_init(device_t dev) @@ -169,6 +187,8 @@ static void lpc_init(device_t dev) /* Initialize ISA DMA. */ isa_dma_init(); + lpc_acpi_init(pm_base); + rom_dummy_write(dev); }

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Patch set updated: 0f196d4 cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.
by Keith Hui 01 Aug '11

01 Aug '11

Keith Hui (buurin(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/122 -gerrit commit 0f196d4cf39e680389a2098e10739d8545397203 Author: Keith Hui <buurin(a)gmail.com> Date: Wed Jul 27 23:06:16 2011 -0400 cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs. Bring from coreboot v1 support for initializing L2 cache on Slot 1 Pentium II/III CPUs, code names Klamath, Deschutes and Katmai. Build tested on ASUS P2B-LS and P3B-F. Boot tested on P2B-LS with Pentium III 600MHz, Katmai core. Also add missing include of model_68x in slot_1, to address a similar problem fixed for model_6bx by r5945. Also change Deschutes CPU init sequence to match Katmai. Change-Id: I502e8481d1a20f0a2504685e7be16b57f59c8257 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- src/cpu/intel/model_65x/model_65x_init.c | 10 +- src/cpu/intel/model_67x/model_67x_init.c | 4 + src/cpu/intel/slot_1/Makefile.inc | 2 + src/cpu/intel/slot_1/l2_cache.c | 810 ++++++++++++++++++++++++++++++ src/include/cpu/intel/l2_cache.h | 101 ++++ 5 files changed, 924 insertions(+), 3 deletions(-) diff --git a/src/cpu/intel/model_65x/model_65x_init.c b/src/cpu/intel/model_65x/model_65x_init.c index 8f9fc66..ef97597 100644 --- a/src/cpu/intel/model_65x/model_65x_init.c +++ b/src/cpu/intel/model_65x/model_65x_init.c @@ -27,6 +27,7 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> +#include <cpu/intel/l2_cache.h> static u32 microcode_updates[] = { #include "microcode-410-MU16522d.h" @@ -56,14 +57,17 @@ static u32 microcode_updates[] = { static void model_65x_init(device_t dev) { + /* Update the microcode */ + intel_update_microcode(microcode_updates); + + /* Initialize L2 cache */ + p6_configure_l2_cache(); + /* Turn on caching if we haven't already */ x86_enable_cache(); x86_setup_mtrrs(36); x86_mtrr_check(); - /* Update the microcode */ - intel_update_microcode(microcode_updates); - /* Enable the local cpu apics */ setup_lapic(); }; diff --git a/src/cpu/intel/model_67x/model_67x_init.c b/src/cpu/intel/model_67x/model_67x_init.c index 76a840e..0c9b3d2 100644 --- a/src/cpu/intel/model_67x/model_67x_init.c +++ b/src/cpu/intel/model_67x/model_67x_init.c @@ -26,6 +26,7 @@ #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> #include <cpu/x86/msr.h> +#include <cpu/intel/l2_cache.h> static const uint32_t microcode_updates[] = { /* Include microcode updates here. */ @@ -46,6 +47,9 @@ static void model_67x_init(device_t cpu) /* Update the microcode */ intel_update_microcode(microcode_updates); + /* Initialize L2 cache */ + p6_configure_l2_cache(); + /* Turn on caching if we haven't already */ x86_enable_cache(); diff --git a/src/cpu/intel/slot_1/Makefile.inc b/src/cpu/intel/slot_1/Makefile.inc index 297ef18..a4de6e0 100644 --- a/src/cpu/intel/slot_1/Makefile.inc +++ b/src/cpu/intel/slot_1/Makefile.inc @@ -19,9 +19,11 @@ ## ramstage-y += slot_1.c +ramstage-y += l2_cache.c subdirs-y += ../model_6xx subdirs-y += ../model_65x subdirs-y += ../model_67x +subdirs-y += ../model_68x subdirs-y += ../model_6bx subdirs-y += ../../x86/tsc subdirs-y += ../../x86/mtrr diff --git a/src/cpu/intel/slot_1/l2_cache.c b/src/cpu/intel/slot_1/l2_cache.c new file mode 100644 index 0000000..9a694e0 --- /dev/null +++ b/src/cpu/intel/slot_1/l2_cache.c @@ -0,0 +1,810 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 Denis Dowling <dpd(a)alphalink.com.au> + * Copyright (C) 2010 Keith Hui <buurin(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Intel Pentium L2 Cache initialization. + * This code was developed by reverse engineering + * the BIOS. Where the code accesses documented + * registers I have added comments as best I can. + * Some undocumented registers on the Pentium II are + * used so some of the documentation is incomplete. + * + * References: + * Intel Architecture Software Developer's Manual + * Volume 3B: System Programming Guide, Part 2 (#253669) + * Appendix B.9 + */ + +/* This code is ported from coreboot v1. + * The L2 cache initalization sequence here only apply to SECC/SECC2 P6 family + * CPUs with Klamath (63x), Deschutes (65x) and Katmai (67x) cores. + * It is not required for Coppermine (68x) and Tualatin (6bx) cores. + * It is currently not known if Celerons with Mendocino (66x) core require the + * special initialization. + * Covington-core Celerons do not have L2 cache. + */ + +#include <stdint.h> +#include <console/console.h> +#include <string.h> +#include <cpu/cpu.h> +#include <cpu/x86/mtrr.h> +#include <cpu/intel/l2_cache.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/msr.h> + +/* Latency Tables */ +struct latency_entry { + u8 key; + u8 value; +}; +/* +Latency maps for Deschutes and Katmai. +No such mapping is available for Klamath. + +Cache latency to +be written to L2 -----++++ +control register |||| +0000 xx 00 -----> 000 cccc 0 +|||| 00 66MHz +|||| 10 100MHz +|||| 01 133MHz (Katmai "B" only) +++++------ CPU frequency multiplier + +0000 2x +0001 3x +0010 4x +0011 5x +0100 2.5x +0101 3.5x +0110 4.5x +0111 5.5x +1000 6x +1001 7x +1010 8x +1011 Reserved +1100 6.5x +1101 7.5x +1110 1.5x +1111 2x + +*/ +static const struct latency_entry latency_650_t0[] = { + {0x10, 0x02}, {0x50, 0x02}, {0x20, 0x04}, {0x60, 0x06}, + {0x00, 0x08}, {0x40, 0x0C}, {0x12, 0x06}, {0x52, 0x0A}, + {0x22, 0x0E}, {0x62, 0x10}, {0x02, 0x10}, {0xFF, 0x00} +}; + +static const struct latency_entry latency_650_t1[] = { + {0x12, 0x14}, {0x52, 0x16}, {0x22, 0x16}, {0x62, 0x16}, + {0xFF, 0x00} +}; + +static const struct latency_entry latency_670_t0[] = { + {0x60, 0x06}, {0x00, 0x08}, {0x12, 0x06}, {0x52, 0x0A}, + {0x22, 0x0E}, {0x62, 0x10}, {0x02, 0x10}, {0x42, 0x02}, + {0x11, 0x0E}, {0x51, 0x0C}, {0x21, 0x02}, {0x61, 0x10}, + {0x01, 0x10}, {0x41, 0x02}, {0xFF, 0x00} +}; + +static const struct latency_entry latency_670_t1[] = { + {0x22, 0x18}, {0x62, 0x18}, {0x02, 0x1A}, {0x11, 0x18}, + {0xFF, 0x00} +}; + +static const struct latency_entry latency_670_t2[] = { + {0x22, 0x12}, {0x62, 0x14}, {0x02, 0x16}, {0x42, 0x1E}, + {0x11, 0x12}, {0x51, 0x16}, {0x21, 0x1E}, {0x61, 0x14}, + {0x01, 0x16}, {0x41, 0x1E}, {0xFF, 0x00} +}; + +/* Latency tables for 650 model/type */ +static const struct latency_entry *latency_650[] = { + latency_650_t0, latency_650_t1, latency_650_t1 +}; + +/* Latency tables for 670 model/type */ +static const struct latency_entry *latency_670[] = { + latency_670_t0, latency_670_t1, latency_670_t2 +}; + +int calculate_l2_latency(void) +{ + u32 eax, l, signature; + const struct latency_entry *latency_table, *le; + msr_t msr; + + /* First, attempt to get cache latency value from + IA32_PLATFORM_ID[56:53]. (L2 Cache Latency Read) + */ + msr = rdmsr(IA32_PLATFORM_ID); + + printk(BIOS_DEBUG,"rdmsr(IA32_PLATFORM_ID) = %x:%x\n", msr.hi, msr.lo); + + l = (msr.hi >> 20) & 0x1e; + + if (l == 0) { + /* If latency value isn't available from + IA32_PLATFORM_ID[56:53], read it from + L2 control register 0 for lookup from + tables. */ + int t, a; + + /* The raw code is read from L2 register 0, bits [7:4]. */ + a = read_l2(0); + if (a < 0) + return -1; + + a &= 0xf0; + + if ((a & 0x20) == 0) + t = 0; + else if (a == 0x20) + t = 1; + else if (a == 0x30) + t = 2; + else + return -1; + + printk(BIOS_DEBUG,"L2 latency type = %x\n", t); + + /* Get CPUID family/model */ + signature = cpuid_eax(1) & 0xfff0; + + /* Read EBL_CR_POWERON */ + msr = rdmsr(EBL_CR_POWERON); + /* Get clock multiplier and FSB frequency. + * Multiplier is in [25:22]. + * FSB is in [19:18] in Katmai, [19] in Deschutes ([18] is zero for them). + */ + eax = msr.lo >> 18; + if (signature == 0x650) { + eax &= ~0xf2; + latency_table = latency_650[t]; + } else if (signature == 0x670) { + eax &= ~0xf3; + latency_table = latency_670[t]; + } else + return -1; + + /* Search table for matching entry */ + for (le = latency_table; le->key != eax; le++) { + /* Fail if we get to the end of the table */ + if (le->key == 0xff) { + printk(BIOS_DEBUG, "Could not find key %02x in latency table\n", eax); + return -1; + } + } + + l = le->value; + } + + printk(BIOS_DEBUG,"L2 Cache latency is %d\n", l / 2); + + /* Writes the calculated latency in BBL_CR_CTL3[4:1]. */ + msr = rdmsr(BBL_CR_CTL3); + msr.lo &= 0xffffffe1; + msr.lo |= l; + wrmsr(BBL_CR_CTL3, msr); + + return 0; +} + + +/* Setup address, data_high:data_low into the L2 + * control registers and then issue command with correct cache way + */ +int signal_l2(u32 address, u32 data_high, u32 data_low, int way, u8 command) +{ + int i; + msr_t msr; + + /* Write L2 Address to BBL_CR_ADDR */ + msr.lo = address; + msr.hi = 0; + wrmsr(BBL_CR_ADDR, msr); + + /* Write data to BBL_CR_D{0..3} */ + msr.lo = data_low; + msr.hi = data_high; + for (i = BBL_CR_D0; i <= BBL_CR_D3; i++) { + wrmsr(i, msr); + } + + /* Put the command and way into BBL_CR_CTL */ + msr = rdmsr(BBL_CR_CTL); + msr.lo = (msr.lo & 0xfffffce0) | command | (way << 8); + wrmsr(BBL_CR_CTL, msr); + + /* Trigger L2 controller */ + msr.lo = 0; + msr.hi = 0; + wrmsr(BBL_CR_TRIG, msr); + + /* Poll the controller to see when done */ + for (i = 0; i < 0x100; i++) { + /* Read BBL_CR_BUSY */ + msr = rdmsr(BBL_CR_BUSY); + /* If not busy then return */ + if ((msr.lo & 1) == 0) + return 0; + } + + /* Return timeout code */ + return -1; +} + +/* Read the L2 Cache controller register at given address */ +int read_l2(u32 address) +{ + msr_t msr; + + /* Send a L2 Control Register Read to L2 controller */ + if (signal_l2(address << 5, 0, 0, 0, L2CMD_CR) != 0) + return -1; + + /* If OK then get the result from BBL_CR_ADDR */ + msr = rdmsr(BBL_CR_ADDR); + return (msr.lo >> 0x15); + +} + +/* Write data into the L2 controller register at address */ +int write_l2(u32 address, u32 data) +{ + int v1, v2, i; + + v1 = read_l2(0); + if (v1 < 0) + return -1; + + v2 = read_l2(2); + if (v2 < 0) + return -1; + + if ((v1 & 0x20) == 0) { + v2 &= 0x3; + v2++; + } else + v2 &= 0x7; + + /* This write has to be replicated to a number of places. Not sure what. */ + + for (i = 0; i < v2; i++) { + + u32 data1, data2; + // Bits legend + // data1 = ffffffff + // data2 = 000000dc + // address = 00aaaaaa + // Final address signalled: + // 000fffff fff000c0 000dcaaa aaa00000 + data1 = data & 0xff; + data1 = data1 << 21; + data2 = (i << 11) & 0x1800; + data1 |= data2; + data2 <<= 6; + data2 &= 0x20000; + data1 |= data2; + + /* Signal L2 controller */ + if (signal_l2((address << 5) | data1, 0, 0, 0, 3)) + return -1; + } + return 0; +} + +/* Write data_high:data_low into the cache at address1. Test address2 + * to see if the same data is returned. Return 0 if the data matches. + * return lower 16 bits if mismatched data if mismatch. Return -1 + * on error + */ +int test_l2_address_alias(u32 address1, u32 address2, + u32 data_high, u32 data_low) +{ + int d; + msr_t msr; + + /* Tag Write with Data Write for L2 */ + if (signal_l2(address1, data_high, data_low, 0, L2CMD_TWW)) + return -1; + + /* Tag Read with Data Read for L2 */ + if (signal_l2(address2, 0, 0, 0, L2CMD_TRR)) + return -1; + + /* Read data from BBL_CR_D[0-3] */ + for (d = BBL_CR_D0; d <= BBL_CR_D3; d++) { + msr = rdmsr(d); + if (msr.lo != data_low || msr.hi != data_high) + return (msr.lo & 0xffff); + } + + return 0; +} + +/* Calculates the L2 cache size. + * + * Reference: Intel(R) 64 and IA-32 Architectures Software Developer�s Manual + * Volume 3B: System Programming Guide, Part 2, Intel pub. 253669, pg. B-172. + * + */ +int calculate_l2_cache_size(void) +{ + int v; + msr_t msr; + u32 cache_setting; + u32 address, size, eax, bblcr3; + + v = read_l2(0); + if (v < 0) + return -1; + if ((v & 0x20) == 0) { + msr = rdmsr(BBL_CR_CTL3); + bblcr3 = msr.lo & ~BBLCR3_L2_SIZE; + /* + * Successively write in all the possible cache size per bank + * into BBL_CR_CTL3[17:13], starting from 256KB (00001) to 4MB (10000), + * and read the last value written and accepted by the cache. + * + * No idea why these bits are writable at all. + */ + for (cache_setting = BBLCR3_L2_SIZE_256K; + cache_setting <= BBLCR3_L2_SIZE_4M; cache_setting <<= 1) { + + eax = bblcr3 | cache_setting; + msr.lo = eax; + wrmsr(BBL_CR_CTL3, msr); + msr = rdmsr(BBL_CR_CTL3); + + /* Value not accepted */ + if (msr.lo != eax) + break; + } + + /* Backtrack to the last value that worked... */ + cache_setting >>= 1; + + /* and write it into BBL_CR_CTL3 */ + msr.lo &= ~BBLCR3_L2_SIZE; + msr.lo |= (cache_setting & BBLCR3_L2_SIZE); + + wrmsr(BBL_CR_CTL3, msr); + + printk(BIOS_DEBUG,"Maximum cache mask is %x\n", cache_setting); + + /* For now, BBL_CR_CTL3 has the highest cache "size" that register + * will accept. Now we'll ping the cache and see where it wraps. + */ + + /* Write aaaaaaaa:aaaaaaaa to address 0 in the l2 cache. + * If this "alias test" returns an "address", it means the + * cache cannot be written to properly, and we have a problem. + */ + v = test_l2_address_alias(0, 0, 0xaaaaaaaa, 0xaaaaaaaa); + if (v != 0) + return -1; + + /* Start with 32K wrap point (256KB actually) */ + size = 1; + address = 0x8000; + + while (1) { + v = test_l2_address_alias(address, 0, 0x55555555, + 0x55555555); + // Write failed. + if (v < 0) + return -1; + // It wraps here. + else if (v == 0) + break; + + size <<= 1; + address <<= 1; + + if (address > 0x200000) + return -1; + } + + /* Mask size */ + size &= 0x3e; + + /* Shift to [17:13] */ + size <<= 12; + + /* Set this into BBL_CR_CTL3 */ + msr = rdmsr(BBL_CR_CTL3); + msr.lo &= ~BBLCR3_L2_SIZE; + msr.lo |= size; + wrmsr(BBL_CR_CTL3, msr); + + printk(BIOS_DEBUG,"L2 Cache Mask is %x\n", size); + + /* Shift to [6:2] */ + size >>= 11; + + v = read_l2(2); + + if (v < 0) + return -1; + + printk(BIOS_DEBUG,"L2(2): %x ", v); + + v &= 0x3; + + /* Shift size right by v */ + size >>= v; + + /* Or in this size */ + v |= size; + + printk(BIOS_DEBUG,"-> %x\n", v); + + if (write_l2(2, v) != 0) + return -1; + } else { + // Some cache size information is available from L2 registers. + // Work from there. + int b, c; + + v = read_l2(2); + + printk(BIOS_DEBUG,"L2(2) = %x\n", v); + + if (v < 0) + return -1; + + // L2 register 2 bitmap: cc---bbb + b = v & 0x7; + c = v >> 6; + + v = 1 << c * b; + + v &= 0xf; + + printk(BIOS_DEBUG,"Calculated a = %x\n", v); + + if (v == 0) + return -1; + + /* Shift to 17:14 */ + v <<= 14; + + /* Write this size into BBL_CR_CTL3 */ + msr = rdmsr(BBL_CR_CTL3); + msr.lo &= ~BBLCR3_L2_SIZE; + msr.lo |= v; + wrmsr(BBL_CR_CTL3, msr); + } + + return 0; +} + +// L2 physical address range can be found from L2 control register 3, bits [2:0]. +int calculate_l2_physical_address_range(void) +{ + int r0, r3; + msr_t msr; + + r3 = read_l2(3); + if (r3 < 0) + return -1; + + r0 = read_l2(0); + if (r0 < 0) + return -1; + + if (r0 & 0x20) + r3 = 0x7; + else + r3 &= 0x7; + + printk(BIOS_DEBUG,"L2 Physical Address Range is %dM\n", (1 << r3) * 512); + + /* Shift into [22:20] to be saved into BBL_CR_CTL3. */ + r3 = r3 << 20; + + msr = rdmsr(BBL_CR_CTL3); + msr.lo &= ~BBLCR3_L2_PHYSICAL_RANGE; + msr.lo |= r3; + wrmsr(BBL_CR_CTL3, msr); + + return 0; +} + +int set_l2_ecc(void) +{ + u32 eax; + const u32 data1 = 0xaa55aa55; + const u32 data2 = 0xaaaaaaaa; + msr_t msr; + + /* Set User Supplied ECC in BBL_CR_CTL */ + msr = rdmsr(BBL_CR_CTL); + msr.lo |= BBLCR3_L2_SUPPLIED_ECC; + wrmsr(BBL_CR_CTL, msr); + + /* Write a value into the L2 Data ECC register BBL_CR_DECC */ + msr.lo = data1; + msr.hi = 0; + wrmsr(BBL_CR_DECC, msr); + + if (test_l2_address_alias(0, 0, data2, data2) < 0) + return -1; + + /* Read back ECC from BBL_CR_DECC */ + msr = rdmsr(BBL_CR_DECC); + eax = msr.lo; + + if (eax == data1) { + printk(BIOS_DEBUG,"L2 ECC Checking is enabled\n"); + + /* Set ECC Check Enable in BBL_CR_CTL3 */ + msr = rdmsr(BBL_CR_CTL3); + msr.lo |= BBLCR3_L2_ECC_CHECK_ENABLE; + wrmsr(BBL_CR_CTL3, msr); + } + + /* Clear User Supplied ECC in BBL_CR_CTL */ + msr = rdmsr(BBL_CR_CTL); + msr.lo &= ~BBLCR3_L2_SUPPLIED_ECC; + wrmsr(BBL_CR_CTL, msr); + + return 0; +} + +/* + * This is the function called from CPU initialization + * driver to set up P6 family L2 cache. + */ + +int p6_configure_l2_cache(void) +{ + msr_t msr, bblctl3; + unsigned int eax; + u16 signature; + int cache_size, bank; + int result, calc_eax; + int v, a; + + int badclk1, badclk2, clkratio; + int crctl3_or; + + printk(BIOS_INFO, "Configuring L2 cache... "); + + /* Read BBL_CR_CTL3 */ + bblctl3 = rdmsr(BBL_CR_CTL3); + /* If bit 23 (L2 Hardware disable) is set then done */ + /* These would be Covington core Celerons with no L2 cache */ + if (bblctl3.lo & BBLCR3_L2_NOT_PRESENT) { + printk(BIOS_INFO,"hardware disabled\n"); + return 0; + } + + signature = cpuid_eax(1) & 0xfff0; + + /* Klamath-specific bit settings for certain + preliminary checks. + */ + if (signature == 0x630) { + clkratio = 0x1c00000; + badclk2 = 0x1000000; + crctl3_or = 0x44000; + } else { + clkratio = 0x3c00000; + badclk2 = 0x3000000; + crctl3_or = 0x40000; + } + badclk1 = 0xc00000; + + /* Read EBL_CR_POWERON */ + msr = rdmsr(EBL_CR_POWERON); + eax = msr.lo; + /* Mask out [22-25] Clock frequency ratio */ + eax &= clkratio; + if (eax == badclk1 || eax == badclk2) { + printk(BIOS_ERR, "Incorrect clock frequency ratio %x\n", eax); + return -1; + } + + disable_cache(); + + /* Mask out from BBL_CR_CTL3: + * [0] L2 Configured + * [5] ECC Check Enable + * [6] Address Parity Check Enable + * [7] CRTN Parity Check Enable + * [8] L2 Enabled + * [12:11] Number of L2 banks + * [17:13] Cache size per bank + * [18] (Set below) + * [22:20] L2 Physical Address Range Support + */ + bblctl3.lo &= 0xff88061e; + /* Set: + * [17:13] = 00010 = 512Kbyte Cache size per bank (63x) + * [17:13] = 00000 = 128Kbyte Cache size per bank (all others) + * [18] Cache state error checking enable + */ + bblctl3.lo |= crctl3_or; + + /* Write BBL_CR_CTL3 */ + wrmsr(BBL_CR_CTL3, bblctl3); + + if (signature != 0x630) { + eax = bblctl3.lo; + + /* Set the l2 latency in BBL_CR_CTL3 */ + if (calculate_l2_latency() != 0) + goto bad; + + /* Read the new latency values back */ + bblctl3 = rdmsr(BBL_CR_CTL3); + calc_eax = bblctl3.lo; + + /* Write back the original default value */ + bblctl3.lo = eax; + wrmsr(BBL_CR_CTL3, bblctl3); + + /* Write BBL_CR_CTL3[27:26] (reserved??) to bits [1:0] of L2 register 4. + * Apparently all other bits must be preserved, hence these code. + */ + + v = (calc_eax >> 26) & 0x3; + + printk(BIOS_DEBUG,"write_l2(4, %x)\n", v); + + a = read_l2(4); + if (a >= 0) + { + a &= 0xfffc; + a |= v; + a = write_l2(4, a); + /* a now contains result code from write_l2() */ + } + if (a != 0) + goto bad; + + /* Restore the correct latency value into BBL_CR_CTL3 */ + bblctl3.lo = calc_eax; + wrmsr(BBL_CR_CTL3, bblctl3); + } /* ! 63x CPU */ + + /* Read L2 register 0 */ + v = read_l2(0); + + /* If L2(0)[5] set (and can be read properly), enable CRTN and address parity + */ + if (v >= 0 && (v & 0x20)) { + bblctl3 = rdmsr(BBL_CR_CTL3); + bblctl3.lo |= (BBLCR3_L2_ADDR_PARITY_ENABLE | + BBLCR3_L2_CRTN_PARITY_ENABLE); + wrmsr(BBL_CR_CTL3, bblctl3); + } + + /* If something goes wrong at L2 ECC setup, cache ECC + * will just remain disabled. + */ + set_l2_ecc(); + + if (calculate_l2_physical_address_range() != 0) { + printk(BIOS_ERR, "Failed to calculate L2 physical address range"); + goto bad; + } + + if (calculate_l2_cache_size() != 0) { + printk(BIOS_ERR, "Failed to calculate L2 cache size"); + goto bad; + } + + /* Turn on cache. Only L1 is active at this time. */ + enable_cache(); + + /* Get the calculated cache size from BBL_CR_CTL3[17:13] */ + bblctl3 = rdmsr(BBL_CR_CTL3); + cache_size = (bblctl3.lo & BBLCR3_L2_SIZE); + if (cache_size == 0) + cache_size = 0x1000; + cache_size = cache_size << 3; + + /* TODO: Cache size above is per bank. We're supposed to get + * the number of banks from BBL_CR_CTL3[12:11]. + * Confirm that this still provides the correct answer. + */ + bank = (bblctl3.lo >> 11) & 0x3; + if (bank == 0) + bank = 1; + + printk(BIOS_INFO, "size %dK... ", cache_size * bank * 4 / 1024); + + /* Write to all cache lines to initialize */ + + while (cache_size > 0) { + + /* Each cache line is 32 bytes. */ + cache_size -= 32; + + /* Update each way */ + + /* We're supposed to get L2 associativity from BBL_CR_CTL3[10:9]. + * But this code only applies to certain members of the P6 processor family + * and since all P6 processors have 4-way L2 cache, we can safely assume + * 4 way for all cache operations. + */ + + for (v = 0; v < 4; v++) { + /* Send Tag Write w/Data Write (TWW) to L2 controller + * MESI = Invalid + */ + if (signal_l2(cache_size, 0, 0, v, L2CMD_TWW | L2CMD_MESI_I) != 0) { + printk(BIOS_ERR, "Failed on signal_l2(%x, %x)\n", + cache_size, v); + goto bad; + } + } + } + printk(BIOS_DEBUG, "L2 Cache lines initialized\n"); + + /* Disable cache */ + disable_cache(); + + /* Set L2 cache configured in BBL_CR_CTL3 */ + bblctl3 = rdmsr(BBL_CR_CTL3); + bblctl3.lo |= BBLCR3_L2_CONFIGURED; + wrmsr(BBL_CR_CTL3, bblctl3); + + /* Invalidate cache and discard unsaved writes */ + asm volatile ("invd"); + + /* Write 0 to L2 control register 5 */ + if (write_l2(5, 0) != 0) { + printk(BIOS_ERR,"write_l2(5, 0) failed\n"); + goto done; + } + + bblctl3 = rdmsr(BBL_CR_CTL3); + if (signature == 0x650) { + /* Change the L2 latency to 0101 then back to + * original value. I don't know why this is needed - dpd + */ + eax = bblctl3.lo; + bblctl3.lo &= ~BBLCR3_L2_LATENCY; + bblctl3.lo |= 0x0a; + wrmsr(BBL_CR_CTL3, bblctl3); + bblctl3.lo = eax; + wrmsr(BBL_CR_CTL3, bblctl3); + } + + /* Enable L2 in BBL_CR_CTL3 */ + bblctl3.lo |= BBLCR3_L2_ENABLED; + wrmsr(BBL_CR_CTL3, bblctl3); + + /* Turn on cache. Both L1 and L2 are now active. Wahoo! */ +done: + result = 0; + goto out; +bad: + result = -1; +out: + printk(BIOS_INFO, "done.\n"); + return result; +} + diff --git a/src/include/cpu/intel/l2_cache.h b/src/include/cpu/intel/l2_cache.h new file mode 100644 index 0000000..a31fd9c --- /dev/null +++ b/src/include/cpu/intel/l2_cache.h @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Keith Hui <buurin(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + */ + +/* The L2 cache definitions here only apply to SECC/SECC2 P6 family CPUs + * with Klamath (63x), Deschutes (65x) and Katmai (67x) cores. + * It is not required for Coppermine (68x) and Tualatin (6bx) cores. + * It is currently not known if Celerons with Mendocino core require + * the special initialization. + * Covington-core Celerons do not have L2 cache. + */ + +/* This is a straight port from coreboot v1. */ + +#ifndef __P6_L2_CACHE_H +#define __P6_L2_CACHE_H + +#define IA32_PLATFORM_ID 0x17 +#define EBL_CR_POWERON 0x2A + +#define BBL_CR_D0 0x88 +#define BBL_CR_D1 0x89 +#define BBL_CR_D2 0x8A +#define BBL_CR_D3 0x8B + +#define BBL_CR_ADDR 0x116 +#define BBL_CR_DECC 0x118 +#define BBL_CR_CTL 0x119 +#define BBL_CR_TRIG 0x11A +#define BBL_CR_BUSY 0x11B +#define BBL_CR_CTL3 0x11E + +#define BBLCR3_L2_CONFIGURED (1<<0) +/* bits [4:1] */ +#define BBLCR3_L2_LATENCY 0x1e +#define BBLCR3_L2_ECC_CHECK_ENABLE (1<<5) +#define BBLCR3_L2_ADDR_PARITY_ENABLE (1<<6) +#define BBLCR3_L2_CRTN_PARITY_ENABLE (1<<7) +#define BBLCR3_L2_ENABLED (1<<8) +/* bits [17:13] */ +#define BBLCR3_L2_SIZE (0x1f << 13) +#define BBLCR3_L2_SIZE_256K (0x01 << 13) +#define BBLCR3_L2_SIZE_512K (0x02 << 13) +#define BBLCR3_L2_SIZE_1M (0x04 << 13) +#define BBLCR3_L2_SIZE_2M (0x08 << 13) +#define BBLCR3_L2_SIZE_4M (0x10 << 13) +/* bits [22:20] */ +#define BBLCR3_L2_PHYSICAL_RANGE (0x7 << 20); +/* TODO: This bitmask does not agree with Intel's documentation. + * Get confirmation one way or another. + */ +#define BBLCR3_L2_SUPPLIED_ECC 0x40000 + +#define BBLCR3_L2_HARDWARE_DISABLE (1<<23) +/* Also known as... */ +#define BBLCR3_L2_NOT_PRESENT (1<<23) + +/* L2 commands */ +#define L2CMD_RLU 0x0c /* 01100 Data read w/ LRU update */ +#define L2CMD_TRR 0x0e /* 01110 Tag read with data read */ +#define L2CMD_TI 0x0f /* 01111 Tag inquiry */ +#define L2CMD_CR 0x02 /* 00010 L2 control register read */ +#define L2CMD_CW 0x03 /* 00011 L2 control register write */ +#define L2CMD_TWR 0x08 /* 010-- Tag read w/ data read */ +#define L2CMD_TWW 0x1c /* 111-- Tag write w/ data write */ +#define L2CMD_TW 0x10 /* 100-- Tag write */ +/* MESI encode for L2 commands above */ +#define L2CMD_MESI_M 3 +#define L2CMD_MESI_E 2 +#define L2CMD_MESI_S 1 +#define L2CMD_MESI_I 0 + +extern int calculate_l2_latency(void); +extern int signal_l2(u32 address_low, u32 data_high, u32 data_low, int way, u8 command); +extern int read_l2(u32 address); +extern int write_l2(u32 address, u32 data); +extern int test_l2_address_alias(u32 address1, u32 address2, u32 data_high, u32 data_low); +extern int calculate_l2_cache_size(void); +extern int calculate_l2_physical_address_range(void); +extern int set_l2_ecc(void); + +extern int p6_configure_l2_cache(void); + +#endif /* __P6_L2_CACHE_H */

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New patch to review: aad6f2a Add voltage control of southbridge and RAM on ms7135
by Jonathan A. Kollasch 01 Aug '11

01 Aug '11

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/126 -gerrit commit aad6f2ab566dffc055e7a1403348c3b38c120751 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Mon Aug 1 14:24:02 2011 -0500 Add voltage control of southbridge and RAM on ms7135 Change-Id: I5d79b4838f69cad56d58363608b801f8b1d3ab43 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/mainboard/msi/ms7135/cmos.layout | 16 +++++++++-- src/mainboard/msi/ms7135/romstage.c | 49 ++++++++++++++++++++++++++------- 2 files changed, 51 insertions(+), 14 deletions(-) diff --git a/src/mainboard/msi/ms7135/cmos.layout b/src/mainboard/msi/ms7135/cmos.layout index 53fdef5..694554d 100644 --- a/src/mainboard/msi/ms7135/cmos.layout +++ b/src/mainboard/msi/ms7135/cmos.layout @@ -43,6 +43,8 @@ entries 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu +448 4 e 10 ram_voltage +452 4 e 11 nf4_voltage 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers @@ -74,10 +76,10 @@ enumerations 7 0 Network 7 1 HDD 7 2 Floppy +#7 3 ROM 7 8 Fallback_Network 7 9 Fallback_HDD 7 10 Fallback_Floppy -#7 3 ROM 8 0 400Mhz 8 1 333Mhz 8 2 266Mhz @@ -91,8 +93,16 @@ enumerations 9 6 25.0% 9 7 12.5% -checksums +10 0 2.55 +10 1 2.50 +10 2 2.60 +10 3 2.65 +10 4 2.70 -checksum 392 983 984 +11 0 1.50 +11 1 1.55 +11 2 1.60 +checksums +checksum 392 983 984 diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index 8609142..dc01b6a 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -48,6 +48,10 @@ #include "cpu/amd/dualcore/dualcore.c" #include <spd.h> +#if CONFIG_HAVE_OPTION_TABLE +#include "option_table.h" +#endif + #define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1) static void memreset(int controllers, const struct mem_controller *ctrl) { } @@ -66,6 +70,31 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" #include "northbridge/amd/amdk8/early_ht.c" +static void ms7135_set_ram_voltage(void) +{ + u8 b; + b = read_option(ram_voltage, 0); + if (b > 4) /* default if above 2.70v */ + b = 0; + print_debug("setting RAM voltage "); + print_debug_hex8(b); + print_debug("\n"); + ck804_smbus_write_byte(1, 0x2f, 0x00, b); +} + +static void ms7135_set_nf4_voltage(void) +{ + u8 b; + b = read_option(nf4_voltage, 0); + if (b > 2) /* default if above 1.60v */ + b = 0; + b |= 0x10; + print_debug("setting NF4 voltage "); + print_debug_hex8(b); + print_debug("\n"); + ck804_smbus_write_byte(1, 0x2f, 0x02, b); +} + static void sio_setup(void) { uint32_t dword; @@ -107,14 +136,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) bsp_apicid = init_cpus(cpu_init_detectedx); w83627thg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +#if CONFIG_USBDEBUG + ck804_enable_usbdebug(USBDEBUG_DEFAULT_PORT); + early_usbdebug_init(); +#endif console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); -#if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); -#endif + enable_smbus(); + + ms7135_set_nf4_voltage(); + ms7135_set_ram_voltage(); needs_reset = setup_coherent_ht_domain(); @@ -138,19 +172,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) //It's the time to set ctrl now; fill_mem_ctrl(nodes, ctrl, spd_addr); - enable_smbus(); - -#if 0 +#if CONFIG_DEBUG_SMBUS dump_spd_registers(&ctrl[0]); dump_smbus_registers(); #endif sdram_initialize(nodes, ctrl); -#if 0 - print_pci_devices(); - dump_pci_devices(); -#endif - post_cache_as_ram(); }

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coreboot August 2011