Frank Vibrans III (frank.vibrans(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/113
-gerrit
commit 0a1a4205c7198b22597ace1bd2ddf301beee70cf
Author: efdesign98 <efdesign98(a)gmail.com>
Date: Wed Jul 20 20:11:46 2011 -0600
Add SSE3 dependent code
This change separates out changes that were initially found
in the commit for XHCI and AHCI changes to "arch/x86/Makefile.
inc". It also corrects a comment. The SSE3 dependent code
adds a pair of CR4 access functions and a blob of code that
re-sets CR4.OSFXSR and CR4.OSXMMEXCPT.
Change-Id: Id97256978da81589d97dcae97981a049101b5258
Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com>
Signed-off-by: efdesign98 <efdesign98(a)gmail.com>
---
src/cpu/x86/lapic/lapic_cpu_init.c | 33 ++++++++++++++++++++++++++++++++-
1 files changed, 32 insertions(+), 1 deletions(-)
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
old mode 100644
new mode 100755
index 53bbe79..53ea60d
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -262,7 +262,7 @@ int start_cpu(device_t cpu)
if (result) {
result = 0;
- /* Wait 1s or until the new the new cpu calls in */
+ /* Wait 1s or until the new cpu calls in */
for(count = 0; count < 100000 ; count++) {
if (secondary_stack == 0) {
result = 1;
@@ -338,6 +338,26 @@ void stop_this_cpu(void)
}
#endif
+#ifdef __SSE3__
+static __inline__ __attribute__((always_inline)) unsigned long readcr4(void)
+{
+ unsigned long value;
+ __asm__ __volatile__ (
+ "mov %%cr4, %[value]"
+ : [value] "=a" (value));
+ return value;
+}
+
+static __inline__ __attribute__((always_inline)) void writecr4(unsigned long Data)
+{
+ __asm__ __volatile__ (
+ "mov %%eax, %%cr4"
+ :
+ : "a" (Data)
+ );
+}
+#endif
+
/* C entry point of secondary cpus */
void secondary_cpu_init(void)
{
@@ -347,6 +367,17 @@ void secondary_cpu_init(void)
spin_lock(&start_cpu_lock);
#endif
#endif
+
+#ifdef __SSE3__
+ /*
+ * Seems that CR4 was cleared when AP start via lapic_start_cpu()
+ * Turn on CR4.OSFXSR and CR4.OSXMMEXCPT when SSE options enabled
+ */
+ u32 cr4_val;
+ cr4_val = readcr4();
+ cr4_val |= (1 << 9 | 1 << 10);
+ writecr4(cr4_val);
+#endif
cpu_initialize();
#if CONFIG_SERIAL_CPU_INIT == 1
#if CONFIG_MAX_CPUS>2
1
0
21 Jul '11
Frank Vibrans III (frank.vibrans(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/109
-gerrit
commit 67d217308b5962665168afefc5cb442461500735
Author: efdesign98 <efdesign98(a)gmail.com>
Date: Wed Jul 20 19:59:22 2011 -0600
Add xhcbios and ahcibios rom handling
This change adds xhci and ahci bios rom handling that
is similar to the vgabios rom handling in the arch/x86
Makefile.inc to the Persimmon and Torpedo mainboards.
It also adds the basis for AHCI BIOS rom handling to
the Persimmon Kconfig.
Change-Id: I527a906323ae483cfa2ca0785f3adb43e88fd84b
Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com>
Signed-off-by: efdesign98 <efdesign98(a)gmail.com>
---
src/mainboard/amd/persimmon/Kconfig | 14 ++++++++++++++
src/mainboard/amd/persimmon/Makefile.inc | 7 +++++++
src/mainboard/amd/torpedo/Makefile.inc | 14 ++++++++++++++
3 files changed, 35 insertions(+), 0 deletions(-)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
old mode 100644
new mode 100755
diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig
index 034984c..c4eac67 100644
--- a/src/mainboard/amd/persimmon/Kconfig
+++ b/src/mainboard/amd/persimmon/Kconfig
@@ -119,6 +119,20 @@ config VGA_BIOS_ID
string
default "1002,9802"
+config AHCI_BIOS
+ bool
+ default n
+
+#config AHCI_BIOS_FILE
+# string "AHCI ROM path and filename"
+# depends on AHCI_BIOS
+# default "rom/ahci/sb900.bin"
+
+config AHCI_BIOS_ID
+ string "AHCI device PCI IDs"
+ depends on AHCI_BIOS
+ default "1002,4391"
+
config DRIVERS_PS2_KEYBOARD
bool
default n
diff --git a/src/mainboard/amd/persimmon/Makefile.inc b/src/mainboard/amd/persimmon/Makefile.inc
index 0f17032..de3564a 100644
--- a/src/mainboard/amd/persimmon/Makefile.inc
+++ b/src/mainboard/amd/persimmon/Makefile.inc
@@ -17,6 +17,13 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
+ifeq ($(CONFIG_AHCI_BIOS),y)
+stripped_ahcibios_id = $(call strip_quotes,$(CONFIG_AHCI_BIOS_ID))
+cbfs-files-$(CONFIG_AHCI_BIOS) += pci$(stripped_ahcibios_id).rom
+pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FILE))
+pci$(stripped_ahcibios_id).rom-type := optionrom
+endif
+
romstage-y += buildOpts.c
romstage-y += agesawrapper.c
romstage-y += dimmSpd.c
diff --git a/src/mainboard/amd/torpedo/Makefile.inc b/src/mainboard/amd/torpedo/Makefile.inc
index 051d936..1a7dc95 100755
--- a/src/mainboard/amd/torpedo/Makefile.inc
+++ b/src/mainboard/amd/torpedo/Makefile.inc
@@ -17,6 +17,20 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
+ifeq ($(CONFIG_AHCI_BIOS),y)
+stripped_ahcibios_id = $(call strip_quotes,$(CONFIG_AHCI_BIOS_ID))
+cbfs-files-$(CONFIG_AHCI_BIOS) += pci$(stripped_ahcibios_id).rom
+pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FILE))
+pci$(stripped_ahcibios_id).rom-type := optionrom
+endif
+
+ifeq ($(CONFIG_XHC_BIOS),y)
+stripped_xhcbios_id = $(call strip_quotes,$(CONFIG_XHC_BIOS_ID))
+cbfs-files-$(CONFIG_XHC_BIOS) += pci$(stripped_xhcbios_id).rom
+pci$(stripped_xhcbios_id).rom-file := $(call strip_quotes,$(CONFIG_XHC_BIOS_FILE))
+pci$(stripped_xhcbios_id).rom-type := optionrom
+endif
+
romstage-y += buildOpts.c
romstage-y += agesawrapper.c
romstage-y += dimmSpd.c
1
0
Frank Vibrans III (frank.vibrans(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/107
-gerrit
commit ffd6569be08138b3fddc778b48b1efd64bba1809
Author: efdesign98 <efdesign98(a)gmail.com>
Date: Wed Jul 20 12:37:58 2011 -0600
Update AMD SR5650 and SB700
This updates the code for the AMD SR5650 and SB700 southbridges.
Among other things, it changes the romstage.c files by replacing a
.C file include with a pair of .H file includes. The .C file is
now added to the romstage in the SB700 or SR5650 Makefile.inc.
file to the romstage and ramstage elements. This particular change
affects all mainboards that use the SB700, and their changes are
include herein. These mainboards are:
Advansus a785e,
AMD Mahogany, Mahogany-fam10, Tilapia-fam10,
Asrock 939a785gmh,
Asus m4a78-em, m4a785-m,
Gigabyte ma785gm,
Iei Kino-780am2-fam10
Jetway pa78vm5
Supermicro h8scm_fam10
The nuvoton/wpcm450 earlysetup interface is changed because the file
is no longer included in the mainboard romstage.c files.
Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33
Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com>
Signed-off-by: efdesign98 <efdesign98(a)gmail.com>
---
src/cpu/amd/car/post_cache_as_ram.c | 1 +
src/mainboard/advansus/a785e-i/Makefile.inc | 15 +-
src/mainboard/amd/inagua/Makefile.inc | 4 +
src/mainboard/amd/mahogany/mainboard.c | 5 +-
src/mainboard/amd/mahogany/romstage.c | 5 +-
src/mainboard/amd/mahogany_fam10/mainboard.c | 5 +-
src/mainboard/amd/mahogany_fam10/romstage.c | 6 +-
src/mainboard/amd/tilapia_fam10/Kconfig | 9 +
src/mainboard/amd/tilapia_fam10/mainboard.c | 7 +-
src/mainboard/amd/tilapia_fam10/romstage.c | 5 +-
src/mainboard/asrock/939a785gmh/mainboard.c | 5 +-
src/mainboard/asrock/939a785gmh/romstage.c | 7 +-
src/mainboard/asus/m4a78-em/mainboard.c | 10 +-
src/mainboard/asus/m4a78-em/romstage.c | 5 +-
src/mainboard/asus/m4a785-m/mainboard.c | 9 +-
src/mainboard/asus/m4a785-m/romstage.c | 5 +-
src/mainboard/gigabyte/ma785gmt/mainboard.c | 9 +-
src/mainboard/gigabyte/ma785gmt/romstage.c | 5 +-
src/mainboard/gigabyte/ma78gm/mainboard.c | 5 +-
src/mainboard/gigabyte/ma78gm/romstage.c | 5 +-
src/mainboard/iei/kino-780am2-fam10/mainboard.c | 5 +-
src/mainboard/iei/kino-780am2-fam10/romstage.c | 5 +-
src/mainboard/jetway/pa78vm5/mainboard.c | 5 +-
src/mainboard/jetway/pa78vm5/romstage.c | 5 +-
src/mainboard/supermicro/h8scm_fam10/Kconfig | 2 -
src/mainboard/supermicro/h8scm_fam10/mainboard.c | 37 +----
src/mainboard/supermicro/h8scm_fam10/romstage.c | 15 +-
src/northbridge/amd/amdk8/reset_test.c | 3 +-
src/southbridge/amd/sb700/Makefile.inc | 5 +
src/southbridge/amd/sb700/early_setup.c | 44 ++----
src/southbridge/amd/sb700/pmio.c | 55 ++++++
src/southbridge/amd/sb700/pmio.h | 34 ++++
src/southbridge/amd/sb700/reset.c | 46 +++++-
src/southbridge/amd/sb700/sata.c | 2 +-
src/southbridge/amd/sb700/sb700.h | 10 +
src/southbridge/amd/sb700/sm.c | 28 +++-
src/southbridge/amd/sb700/smbus.c | 89 +++++-----
src/southbridge/amd/sb700/smbus.h | 10 +-
src/southbridge/amd/sb700/usb.c | 1 +
src/southbridge/amd/sr5650/Makefile.inc | 2 +
src/southbridge/amd/sr5650/cmn.h | 10 +-
src/southbridge/amd/sr5650/early_setup.c | 196 +++++++++++-----------
src/southbridge/amd/sr5650/pcie.c | 86 ++++++++---
src/southbridge/amd/sr5650/sr5650.c | 25 ++-
src/southbridge/amd/sr5650/sr5650.h | 7 +-
src/superio/nuvoton/wpcm450/Makefile.inc | 1 +
src/superio/nuvoton/wpcm450/early_init.c | 4 +-
src/superio/nuvoton/wpcm450/wpcm450.h | 2 +
src/vendorcode/amd/agesa/f14/Lib/amdlib.c | 24 ++--
49 files changed, 537 insertions(+), 348 deletions(-)
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index e8f0c92..270c542 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -4,6 +4,7 @@
#include <string.h>
#include <arch/stages.h>
#include <cpu/x86/mtrr.h>
+#include "cbmem.h"
#include "cpu/amd/car/disable_cache_as_ram.c"
#include "cpu/x86/mtrr/earlymtrr.c"
diff --git a/src/mainboard/advansus/a785e-i/Makefile.inc b/src/mainboard/advansus/a785e-i/Makefile.inc
old mode 100644
new mode 100755
index a81d135..cf8ec26
--- a/src/mainboard/advansus/a785e-i/Makefile.inc
+++ b/src/mainboard/advansus/a785e-i/Makefile.inc
@@ -6,14 +6,15 @@ ramstage-y += pmio.c
#SB800 CIMx share AGESA V5 lib code
ifneq ($(CONFIG_AMD_AGESA),y)
- romstage-y += ../../../vendorcode/amd/agesa/f14/Lib/amdlib.c
- ramstage-y += ../../../vendorcode/amd/agesa/f14/Lib/amdlib.c
+ AGESA_ROOT ?= src/vendorcode/amd/agesa/f14
+ romstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c
+ ramstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c
- AGESA_INC := -Isrc/vendorcode/amd/agesa/f14/ \
- -Isrc/vendorcode/amd/agesa/f14/Include \
- -Isrc/vendorcode/amd/agesa/f14/Proc/IDS/ \
- -Isrc/vendorcode/amd/agesa/f14/Proc/CPU/ \
- -Isrc/vendorcode/amd/agesa/f14/Proc/CPU/Family
+ AGESA_INC := -I$(AGESA_ROOT)/ \
+ -I$(AGESA_ROOT)/Include \
+ -I$(AGESA_ROOT)/Proc/IDS/ \
+ -I$(AGESA_ROOT)/Proc/CPU/ \
+ -I$(AGESA_ROOT)/Proc/CPU/Family
CFLAGS += $(AGESA_INC)
endif
diff --git a/src/mainboard/amd/inagua/Makefile.inc b/src/mainboard/amd/inagua/Makefile.inc
old mode 100644
new mode 100755
index 88af2b7..564d196
--- a/src/mainboard/amd/inagua/Makefile.inc
+++ b/src/mainboard/amd/inagua/Makefile.inc
@@ -31,3 +31,7 @@ ramstage-y += PlatformGnbPcie.c
ramstage-y += reset.c
ramstage-y += pmio.c
+
+AGESA_ROOT ?= src/vendorcode/amd/agesa/f14
+subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += ../../../../$(AGESA_ROOT)
+#subdirs-$(CONFIG_AMD_CIMX) += ../../../vendorcode/amd/cimx
diff --git a/src/mainboard/amd/mahogany/mainboard.c b/src/mainboard/amd/mahogany/mainboard.c
index 9d471d0..0ccef10 100644
--- a/src/mainboard/amd/mahogany/mainboard.c
+++ b/src/mainboard/amd/mahogany/mainboard.c
@@ -25,11 +25,10 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
-#include <southbridge/amd/sb700/sb700.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "chip.h"
-#define SMBUS_IO_BASE 0x6000
-
uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c
index b4c9635..5c9d538 100644
--- a/src/mainboard/amd/mahogany/romstage.c
+++ b/src/mainboard/amd/mahogany/romstage.c
@@ -44,7 +44,8 @@
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
-#include "southbridge/amd/sb700/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */
static void memreset(int controllers, const struct mem_controller *ctrl) { }
@@ -52,7 +53,7 @@ static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(u32 device, u32 address)
{
- return smbus_read_byte(device, address);
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdk8/amdk8.h"
diff --git a/src/mainboard/amd/mahogany_fam10/mainboard.c b/src/mainboard/amd/mahogany_fam10/mainboard.c
index 7ed615d..2cbeaf1 100644
--- a/src/mainboard/amd/mahogany_fam10/mainboard.c
+++ b/src/mainboard/amd/mahogany_fam10/mainboard.c
@@ -25,11 +25,10 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
-#include <southbridge/amd/sb700/sb700.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "chip.h"
-#define SMBUS_IO_BASE 0x6000
-
uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 680e60d..4d26ca3 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -48,7 +48,8 @@
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
-#include "southbridge/amd/sb700/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdfam10/debug.c"
#include <spd.h>
@@ -56,7 +57,7 @@ static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
- return smbus_read_byte(device, address);
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
@@ -73,7 +74,6 @@ static int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
-#include "southbridge/amd/sb700/early_setup.c"
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
diff --git a/src/mainboard/amd/tilapia_fam10/Kconfig b/src/mainboard/amd/tilapia_fam10/Kconfig
old mode 100644
new mode 100755
index b18115b..e9d6081
--- a/src/mainboard/amd/tilapia_fam10/Kconfig
+++ b/src/mainboard/amd/tilapia_fam10/Kconfig
@@ -83,4 +83,13 @@ config RAMBASE
hex
default 0x200000
+config VGA_BIOS
+ bool
+ default n
+
+config VGA_BIOS_ID
+ string
+ depends on VGA_BIOS
+ default "1002,9615"
+
endif # BOARD_AMD_TILAPIA_FAM10
diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c
old mode 100644
new mode 100755
index 84ff928..357bdac
--- a/src/mainboard/amd/tilapia_fam10/mainboard.c
+++ b/src/mainboard/amd/tilapia_fam10/mainboard.c
@@ -26,15 +26,12 @@
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include <southbridge/amd/sb700/sb700.h>
+#include "southbridge/amd/sb700/smbus.h"
#include "chip.h"
#define ADT7461_ADDRESS 0x4C
#define ARA_ADDRESS 0x0C /* Alert Response Address */
-extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
-extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
- u8 val);
-
#define ADT7461_read_byte(address) \
do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
#define ARA_read_byte(address) \
@@ -42,8 +39,6 @@ extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
#define ADT7461_write_byte(address, val) \
do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
-#define SMBUS_IO_BASE 0x6000
-
uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
old mode 100644
new mode 100755
index 3a85a15..48b13be
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -48,14 +48,15 @@
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
-#include "southbridge/amd/sb700/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdfam10/debug.c"
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
- return smbus_read_byte(device, address);
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
diff --git a/src/mainboard/asrock/939a785gmh/mainboard.c b/src/mainboard/asrock/939a785gmh/mainboard.c
index 1cf1731..945a19f 100644
--- a/src/mainboard/asrock/939a785gmh/mainboard.c
+++ b/src/mainboard/asrock/939a785gmh/mainboard.c
@@ -25,11 +25,10 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
-#include <southbridge/amd/sb700/sb700.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "chip.h"
-#define SMBUS_IO_BASE 0x6000
-
uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c
index b0ae247..bd45c16 100644
--- a/src/mainboard/asrock/939a785gmh/romstage.c
+++ b/src/mainboard/asrock/939a785gmh/romstage.c
@@ -45,7 +45,8 @@
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
-#include "southbridge/amd/sb700/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */
#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
@@ -56,7 +57,7 @@ static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(u32 device, u32 address)
{
- return smbus_read_byte(device, address);
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdk8/amdk8.h"
@@ -101,7 +102,7 @@ static void sio_init(void)
pnp_write_config(GPIO2345_DEV, 0xe4, 0x0e); /* data */
pnp_write_config(GPIO2345_DEV, 0xe5, 0x00); /* No inversion */
- /* GPIO30 - unknown output, set to 0
+ /* GPIO30 - unknown output, set to 0
GPI31 - unknown input NC?
GPI32 - unknown input NC?
GPIO33 - unknown output, set to 0.
diff --git a/src/mainboard/asus/m4a78-em/mainboard.c b/src/mainboard/asus/m4a78-em/mainboard.c
index 910fce1..6042d07 100644
--- a/src/mainboard/asus/m4a78-em/mainboard.c
+++ b/src/mainboard/asus/m4a78-em/mainboard.c
@@ -24,17 +24,11 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
-#include <southbridge/amd/sb700/sb700.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "chip.h"
-extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
-extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
- u8 val);
-
-
-#define SMBUS_IO_BASE 0x6000
-
uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index 0675ee6..b14a7c6 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -48,14 +48,15 @@
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
-#include "southbridge/amd/sb700/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdfam10/debug.c"
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
- return smbus_read_byte(device, address);
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c
index a5a15e8..e490f31 100644
--- a/src/mainboard/asus/m4a785-m/mainboard.c
+++ b/src/mainboard/asus/m4a785-m/mainboard.c
@@ -24,16 +24,13 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
-#include <southbridge/amd/sb700/sb700.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "chip.h"
#define ADT7461_ADDRESS 0x4C
#define ARA_ADDRESS 0x0C /* Alert Response Address */
-extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
-extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
- u8 val);
-
#define ADT7461_read_byte(address) \
do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
#define ARA_read_byte(address) \
@@ -41,8 +38,6 @@ extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
#define ADT7461_write_byte(address, val) \
do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
-#define SMBUS_IO_BASE 0x6000
-
uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 0675ee6..b14a7c6 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -48,14 +48,15 @@
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
-#include "southbridge/amd/sb700/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdfam10/debug.c"
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
- return smbus_read_byte(device, address);
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
diff --git a/src/mainboard/gigabyte/ma785gmt/mainboard.c b/src/mainboard/gigabyte/ma785gmt/mainboard.c
index d6c95e0..768c9e1 100644
--- a/src/mainboard/gigabyte/ma785gmt/mainboard.c
+++ b/src/mainboard/gigabyte/ma785gmt/mainboard.c
@@ -25,16 +25,13 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
-#include <southbridge/amd/sb700/sb700.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "chip.h"
#define ADT7461_ADDRESS 0x4C
#define ARA_ADDRESS 0x0C /* Alert Response Address */
-extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
-extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
- u8 val);
-
#define ADT7461_read_byte(address) \
do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
#define ARA_read_byte(address) \
@@ -42,8 +39,6 @@ extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
#define ADT7461_write_byte(address, val) \
do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
-#define SMBUS_IO_BASE 0x6000
-
uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index 8f3f55d..fcf023b 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -44,14 +44,15 @@
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
-#include "southbridge/amd/sb700/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdfam10/debug.c"
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
- return smbus_read_byte(device, address);
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
diff --git a/src/mainboard/gigabyte/ma78gm/mainboard.c b/src/mainboard/gigabyte/ma78gm/mainboard.c
index dcb3799..1a00af6 100644
--- a/src/mainboard/gigabyte/ma78gm/mainboard.c
+++ b/src/mainboard/gigabyte/ma78gm/mainboard.c
@@ -26,11 +26,10 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
-#include <southbridge/amd/sb700/sb700.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "chip.h"
-#define SMBUS_IO_BASE 0x6000
-
uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index c34fa5b..80b8d90 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -48,14 +48,15 @@
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
-#include "southbridge/amd/sb700/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdfam10/debug.c"
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
- return smbus_read_byte(device, address);
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
diff --git a/src/mainboard/iei/kino-780am2-fam10/mainboard.c b/src/mainboard/iei/kino-780am2-fam10/mainboard.c
index 379efe5..4d0cd09 100644
--- a/src/mainboard/iei/kino-780am2-fam10/mainboard.c
+++ b/src/mainboard/iei/kino-780am2-fam10/mainboard.c
@@ -25,11 +25,10 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
-#include <southbridge/amd/sb700/sb700.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "chip.h"
-#define SMBUS_IO_BASE 0x6000
-
uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index 192b47a..58b1845 100644
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -48,7 +48,8 @@
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
-#include "southbridge/amd/sb700/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdfam10/debug.c"
#define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1)
@@ -57,7 +58,7 @@ static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
- return smbus_read_byte(device, address);
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
diff --git a/src/mainboard/jetway/pa78vm5/mainboard.c b/src/mainboard/jetway/pa78vm5/mainboard.c
index 188cadf..6d0ceba 100644
--- a/src/mainboard/jetway/pa78vm5/mainboard.c
+++ b/src/mainboard/jetway/pa78vm5/mainboard.c
@@ -26,11 +26,10 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
-#include <southbridge/amd/sb700/sb700.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "chip.h"
-#define SMBUS_IO_BASE 0x6000
-
uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index 4ffcade..11bda6a 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -49,7 +49,8 @@
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
-#include "southbridge/amd/sb700/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdfam10/debug.c"
#if CONFIG_TTYS0_BASE == 0x2f8
@@ -62,7 +63,7 @@ static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
- return smbus_read_byte(device, address);
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
diff --git a/src/mainboard/supermicro/h8scm_fam10/Kconfig b/src/mainboard/supermicro/h8scm_fam10/Kconfig
old mode 100644
new mode 100755
index e0547ab..7742133
--- a/src/mainboard/supermicro/h8scm_fam10/Kconfig
+++ b/src/mainboard/supermicro/h8scm_fam10/Kconfig
@@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_OPTION_TABLE
select GENERATE_PIRQ_TABLE
select GENERATE_MP_TABLE
- select HAVE_MAINBOARD_RESOURCES
select HAVE_HARD_RESET
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select LIFT_BSP_APIC_ID
@@ -24,7 +23,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select BOARD_ROMSIZE_KB_2048
select RAMINIT_SYSINFO
select ENABLE_APIC_EXT_ID
- select GFXUMA
config MAINBOARD_DIR
string
diff --git a/src/mainboard/supermicro/h8scm_fam10/mainboard.c b/src/mainboard/supermicro/h8scm_fam10/mainboard.c
old mode 100644
new mode 100755
index e6ed22b..90b5335
--- a/src/mainboard/supermicro/h8scm_fam10/mainboard.c
+++ b/src/mainboard/supermicro/h8scm_fam10/mainboard.c
@@ -29,9 +29,6 @@
#include <southbridge/amd/sr5650/cmn.h>
#include "chip.h"
-#define SMBUS_IO_BASE 0x6000
-
-uint64_t uma_memory_base, uma_memory_size;
void set_pcie_reset(void);
void set_pcie_dereset(void);
@@ -95,47 +92,17 @@ static void h8scm_enable(device_t dev)
printk
(BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
__func__, msr2.lo, msr2.hi);
-#if (CONFIG_GFXUMA == 1)
-
- /* refer to UMA Size Consideration in 780 BDG. */
- switch (msr.lo) {
- case 0x10000000: /* 256M system memory */
- uma_memory_size = 0x4000000; /* 64M recommended UMA */
- break;
-
- case 0x20000000: /* 512M system memory */
- uma_memory_size = 0x8000000; /* 128M recommended UMA */
- break;
-
- default: /* 1GB and above system memory */
- uma_memory_size = 0x10000000; /* 256M recommended UMA */
- break;
- }
-#else
- /* TODO: TOP_MEM2 */
- uma_memory_size = 0;//0x8000000; /* 128M recommended UMA */
-#endif
- uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */
- printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
- __func__, uma_memory_size, uma_memory_base);
set_pcie_dereset();
/* get_ide_dma66(); */
}
+#if (CONFIG_HAVE_MAINBOARD_RESOURCES == 1)
int add_mainboard_resources(struct lb_memory *mem)
{
- /* UMA is removed from system memory in the northbridge code, but
- * in some circumstances we want the memory mentioned as reserved.
- */
-#if (CONFIG_GFXUMA == 1)
- printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
- uma_memory_base, uma_memory_size);
- lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
- uma_memory_size);
-#endif
return 0;
}
+#endif
struct chip_operations mainboard_ops = {
CHIP_NAME("AMD H8SCM Mainboard")
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
old mode 100644
new mode 100755
index 8101d2f..6e6e394
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -42,13 +42,14 @@
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
-#include "superio/nuvoton/wpcm450/early_init.c"
#include <usbdebug.h>
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/amd/sb700/early_setup.c"
-#include "southbridge/amd/sr5650/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
+#include "southbridge/amd/sr5650/sr5650.h"
+#include "superio/nuvoton/wpcm450/wpcm450.h"
#include "northbridge/amd/amdfam10/debug.c"
static void activate_spd_rom(const struct mem_controller *ctrl)
@@ -57,7 +58,7 @@ static void activate_spd_rom(const struct mem_controller *ctrl)
static int spd_read_byte(u32 device, u32 address)
{
- return smbus_read_byte(device, address);
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
@@ -102,7 +103,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
- disable_pcie_bridge();
+ /* SR56x0 pcie bridges block pci_locate_device() before pcie training.
+ * disable all pcie bridges on SR56x0 to work around it
+ */
+ sr5650_disable_pcie_bridge();
sb7xx_51xx_lpc_port80();
}
@@ -181,7 +185,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* run _early_setup before soft-reset. */
sr5650_early_setup();
- disable_pcie_bridge();
sb7xx_51xx_early_setup();
#if CONFIG_SET_FIDVID
diff --git a/src/northbridge/amd/amdk8/reset_test.c b/src/northbridge/amd/amdk8/reset_test.c
index b775813..bee3faa 100644
--- a/src/northbridge/amd/amdk8/reset_test.c
+++ b/src/northbridge/amd/amdk8/reset_test.c
@@ -44,7 +44,8 @@ static inline void distinguish_cpu_resets(unsigned nodeid)
pci_write_config32(device, HT_INIT_CONTROL, htic);
}
-static void set_bios_reset(void)
+void __attribute__ ((weak)) set_bios_reset(void);
+void __attribute__ ((weak)) set_bios_reset(void)
{
u32 htic;
htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
diff --git a/src/southbridge/amd/sb700/Makefile.inc b/src/southbridge/amd/sb700/Makefile.inc
old mode 100644
new mode 100755
index 8e8e029..e174e8b
--- a/src/southbridge/amd/sb700/Makefile.inc
+++ b/src/southbridge/amd/sb700/Makefile.inc
@@ -1,11 +1,16 @@
driver-y += sb700.c
driver-y += usb.c
driver-y += lpc.c
+driver-y += smbus.c
driver-y += sm.c
driver-y += ide.c
driver-y += sata.c
driver-y += hda.c
driver-y += pci.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c
+romstage-y += reset.c
ramstage-y += reset.c
romstage-y += enable_usbdebug.c
+
+romstage-y += early_setup.c
+romstage-y += smbus.c
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
old mode 100644
new mode 100755
index a5e76c7..1f46da2
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -20,14 +20,19 @@
#ifndef _SB700_EARLY_SETUP_C_
#define _SB700_EARLY_SETUP_C_
+#include <stdint.h>
+#include <arch/cpu.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+
#include <reset.h>
#include <arch/cpu.h>
#include <cbmem.h>
#include "sb700.h"
-#include "smbus.c"
+#include "smbus.h"
-#define SMBUS_IO_BASE 0x6000 /* Is it a temporary SMBus I/O base address? */
- /*SIZE 0x40 */
static void pmio_write(u8 reg, u8 value)
{
@@ -129,7 +134,7 @@ static u8 set_sb700_revision(void)
* Console output through any port besides 0x3f8 is unsupported.
* If you use FWH ROMs, you have to setup IDSEL.
***************************************/
-static void sb7xx_51xx_lpc_init(void)
+void sb7xx_51xx_lpc_init(void)
{
u8 reg8;
u32 reg32;
@@ -216,7 +221,7 @@ void sb7xx_51xx_disable_wideio(u8 wio_index)
}
/* what is its usage? */
-static u32 get_sbdn(u32 bus)
+u32 __attribute__ ((weak)) get_sbdn(u32 bus)
{
device_t dev;
@@ -233,7 +238,7 @@ static u8 dual_core(void)
/*
* RPR 2.4 C-state and VID/FID change for the K8 platform.
*/
-static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
+void __attribute__((weak)) enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
{
u8 byte;
byte = pmio_read(0x9a);
@@ -284,22 +289,6 @@ static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
pmio_write(0x67, 0x6);
}
-void hard_reset(void)
-{
- set_bios_reset();
-
- /* full reset */
- outb(0x0a, 0x0cf9);
- outb(0x0e, 0x0cf9);
-}
-
-void soft_reset(void)
-{
- set_bios_reset();
- /* link reset */
- outb(0x06, 0x0cf9);
-}
-
void sb7xx_51xx_pci_port80(void)
{
u8 byte;
@@ -681,7 +670,7 @@ static void sb700_por_init(void)
/*
* It should be called during early POST after memory detection and BIOS shadowing but before PCI bus enumeration.
*/
-static void sb7xx_51xx_before_pci_init(void)
+void sb7xx_51xx_before_pci_init(void)
{
sb700_pci_cfg();
}
@@ -689,18 +678,13 @@ static void sb7xx_51xx_before_pci_init(void)
/*
* This function should be called after enable_sb700_smbus().
*/
-static void sb7xx_51xx_early_setup(void)
+void sb7xx_51xx_early_setup(void)
{
printk(BIOS_INFO, "sb700_early_setup()\n");
sb700_por_init();
sb700_acpi_init();
}
-static int smbus_read_byte(u32 device, u32 address)
-{
- return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
-}
-
int s3_save_nvram_early(u32 dword, int size, int nvram_pos)
{
int i;
@@ -732,7 +716,7 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
}
#if CONFIG_HAVE_ACPI_RESUME == 1
-static int acpi_is_wakeup_early(void)
+int acpi_is_wakeup_early(void)
{
u16 tmp;
tmp = inw(ACPI_PM1_CNT_BLK);
diff --git a/src/southbridge/amd/sb700/pmio.c b/src/southbridge/amd/sb700/pmio.c
new file mode 100755
index 0000000..baded54
--- /dev/null
+++ b/src/southbridge/amd/sb700/pmio.c
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#include <arch/io.h> /*inb, outb*/
+#include "pmio.h"
+
+static void pmio_write_index(u16 port_base, u8 reg, u8 value)
+{
+ outb(reg, port_base);
+ outb(value, port_base + 1);
+}
+
+static u8 pmio_read_index(u16 port_base, u8 reg)
+{
+ outb(reg, port_base);
+ return inb(port_base + 1);
+}
+
+void pm_iowrite(u8 reg, u8 value)
+{
+ pmio_write_index(PM_INDEX, reg, value);
+}
+
+u8 pm_ioread(u8 reg)
+{
+ return pmio_read_index(PM_INDEX, reg);
+}
+
+void pm2_iowrite(u8 reg, u8 value)
+{
+ pmio_write_index(PM2_INDEX, reg, value);
+}
+
+u8 pm2_ioread(u8 reg)
+{
+ return pmio_read_index(PM2_INDEX, reg);
+}
+
diff --git a/src/southbridge/amd/sb700/pmio.h b/src/southbridge/amd/sb700/pmio.h
new file mode 100755
index 0000000..207fdc2
--- /dev/null
+++ b/src/southbridge/amd/sb700/pmio.h
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#ifndef _PMIO_H_
+#define _PMIO_H_
+
+#define PM_INDEX 0xCD6
+#define PM_DATA 0xCD7
+#define PM2_INDEX 0xCD0
+#define PM2_DATA 0xCD1
+
+void pm_iowrite(u8 reg, u8 value);
+u8 pm_ioread(u8 reg);
+void pm2_iowrite(u8 reg, u8 value);
+u8 pm2_ioread(u8 reg);
+
+#endif
diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c
old mode 100644
new mode 100755
index 32ee66b..27ca32e
--- a/src/southbridge/amd/sb700/reset.c
+++ b/src/southbridge/amd/sb700/reset.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ * Copyright (C) 2010 - 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,17 +17,51 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <reset.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
+#include <reset.h> /* hard_reset, soft_rest*/
+#include <arch/io.h> /* inb, outb */
+#include <arch/romcc_io.h> /* pci_read_config32, device_t, PCI_DEV */
-#include "../../../northbridge/amd/amdk8/reset_test.c"
+#define HT_INIT_CONTROL 0x6C
+#define HTIC_BIOSR_Detect (1<<5)
+
+#if CONFIG_MAX_PHYSICAL_CPUS > 32
+#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
+#else
+#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
+#endif
+
+static void set_bios_reset(void)
+{
+ u32 nodes;
+ u32 htic;
+ device_t dev;
+ int i;
+
+ nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
+ for(i = 0; i < nodes; i++) {
+ dev = NODE_PCI(i, 0);
+ htic = pci_read_config32(dev, HT_INIT_CONTROL);
+ htic &= ~HTIC_BIOSR_Detect;
+ pci_write_config32(dev, HT_INIT_CONTROL, htic);
+ }
+}
void hard_reset(void)
{
set_bios_reset();
+
/* Try rebooting through port 0xcf9 */
- /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
+ /* Actually it is not a real hard_reset
+ * --- it only reset coherent link table, but not reset link freq and width
+ */
outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
}
+
+void soft_reset(void)
+{
+ set_bios_reset();
+ /* link reset */
+ outb(0x06, 0x0cf9);
+}
+
diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c
old mode 100644
new mode 100755
index 89eba4b..411baf5
--- a/src/southbridge/amd/sb700/sata.c
+++ b/src/southbridge/amd/sb700/sata.c
@@ -280,7 +280,7 @@ static void sata_init(struct device *dev)
}
static struct pci_operations lops_pci = {
- /* .set_subsystem = pci_dev_set_subsystem, */
+ .set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations sata_ops = {
diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h
old mode 100644
new mode 100755
index 60eea47..794dd96
--- a/src/southbridge/amd/sb700/sb700.h
+++ b/src/southbridge/amd/sb700/sb700.h
@@ -63,8 +63,11 @@ void sb7xx_51xx_enable(device_t dev);
#ifdef __PRE_RAM__
void sb7xx_51xx_lpc_port80(void);
void sb7xx_51xx_pci_port80(void);
+void sb7xx_51xx_lpc_init(void);
void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base);
void sb7xx_51xx_disable_wideio(u8 wio_index);
+void sb7xx_51xx_early_setup(void);
+void sb7xx_51xx_before_pci_init(void);
#else
#include <device/pci.h>
/* allow override in mainboard.c */
@@ -72,8 +75,15 @@ void sb7xx_51xx_setup_sata_phys(struct device *dev);
#endif
+#if CONFIG_HAVE_ACPI_RESUME == 1
+int acpi_is_wakeup_early(void);
+#endif
+
int s3_save_nvram_early(u32 dword, int size, int nvram_pos);
int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
void enable_usbdebug(unsigned int port);
+
+u32 __attribute__ ((weak)) get_sbdn(u32 bus);
+void __attribute__((weak)) enable_fid_change_on_sb(u32 sbbusn, u32 sbdn);
#endif /* SB700_H */
diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c
old mode 100644
new mode 100755
index 7d341df..05065b6
--- a/src/southbridge/amd/sb700/sm.c
+++ b/src/southbridge/amd/sb700/sm.c
@@ -30,7 +30,7 @@
#include <arch/ioapic.h>
#include <stdlib.h>
#include "sb700.h"
-#include "smbus.c"
+#include "smbus.h"
#define NMI_OFF 0
@@ -95,6 +95,20 @@ static void sm_init(device_t dev)
byte |= 4 << 2; /* set NumSerIrqBits=4 */
pci_write_config8(dev, 0x69, byte);
+ /* Sx State Settings
+ * Note: These 2 registers need to be set correctly for the S-state
+ * to work properly. Otherwise the system may hang during resume
+ * from the S-state.
+ */
+ /*Use 8us clock for delays in the S-state resume timing sequence.*/
+ byte = pm_ioread(0x65);
+ byte &= ~(1 << 7);
+ pm_iowrite(0x65, byte);
+ /* Delay the APIC interrupt to the CPU until the system has fully resumed from the S-state. */
+ byte = pm_ioread(0x68);
+ byte |= 1 << 2;
+ pm_iowrite(0x68, byte);
+
/* IRQ0From8254 */
byte = pci_read_config8(dev, 0x41);
byte &= ~(1 << 7);
@@ -219,10 +233,10 @@ static void sm_init(device_t dev)
* Transactions for the K8 Platform (for All Revisions) */
abcfg_reg(0x10090, 1 << 8, 1 << 8);
- /* ACPI_SOFT_CLOCK_THROTTLE_PERIOD */
+ /* Set ACPI Software clock Throttling Period to 244 us*/
byte = pm_ioread(0x68);
byte &= ~(3 << 6);
- byte |= (2 << 6); /* 224us */
+ byte |= (2 << 6); /* 244us */
pm_iowrite(0x68, byte);
if (REV_SB700_A15 == rev) {
@@ -367,16 +381,16 @@ static void sb700_sm_read_resources(device_t dev)
res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */
res->align = 8;
res->gran = 8;
- res->flags = IORESOURCE_MEM | IORESOURCE_FIXED;
+ res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED;
- /* Linux ACPI crashes when it is 1. For late debugging. */
+ /* HPET */
res = new_resource(dev, 0xB4); /* TODO: test hpet */
res->base = 0xfed00000; /* reset hpet to widely accepted address */
res->size = 0x400;
res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */
res->align = 8;
res->gran = 8;
- res->flags = IORESOURCE_MEM | IORESOURCE_FIXED;
+ res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED;
/* dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; */
@@ -387,7 +401,7 @@ static void sb700_sm_read_resources(device_t dev)
res->limit = 0xFFFFUL; /* res->base + res->size -1; */
res->align = 8;
res->gran = 8;
- res->flags = IORESOURCE_IO | IORESOURCE_FIXED;
+ res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED;
compact_resources(dev);
}
diff --git a/src/southbridge/amd/sb700/smbus.c b/src/southbridge/amd/sb700/smbus.c
old mode 100644
new mode 100755
index e47bcee..6edc3de
--- a/src/southbridge/amd/sb700/smbus.c
+++ b/src/southbridge/amd/sb700/smbus.c
@@ -22,6 +22,51 @@
#include "smbus.h"
+void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val)
+{
+ u32 tmp;
+
+ outl((reg_space & 0x3) << 30 | reg_addr, AB_INDX);
+ tmp = inl(AB_DATA);
+ /* rpr 4.2
+ * For certain revisions of the chip, the ABCFG registers,
+ * with an address of 0x100NN (where 'N' is any hexadecimal
+ * number), require an extra programming step.*/
+ reg_addr & 0x10000 ? outl(0, AB_INDX) : NULL;
+
+ tmp &= ~mask;
+ tmp |= val;
+
+ /* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<30 | reg_addr); */
+ outl((reg_space & 0x3) << 30 | reg_addr, AB_INDX); /* probably we dont have to do it again. */
+ outl(tmp, AB_DATA);
+ reg_addr & 0x10000 ? outl(0, AB_INDX) : NULL;
+}
+
+/* space = 0: AX_INDXC, AX_DATAC
+ * space = 1: AX_INDXP, AX_DATAP
+ */
+void alink_ax_indx(u32 space, u32 axindc, u32 mask, u32 val)
+{
+ u32 tmp;
+
+ /* read axindc to tmp */
+ outl(space << 30 | space << 3 | 0x30, AB_INDX);
+ outl(axindc, AB_DATA);
+ outl(space << 30 | space << 3 | 0x34, AB_INDX);
+ tmp = inl(AB_DATA);
+
+ tmp &= ~mask;
+ tmp |= val;
+
+ /* write tmp */
+ outl(space << 30 | space << 3 | 0x30, AB_INDX);
+ outl(axindc, AB_DATA);
+ outl(space << 30 | space << 3 | 0x34, AB_INDX);
+ outl(tmp, AB_DATA);
+}
+
+
static inline void smbus_delay(void)
{
outb(inb(0x80), 0x80);
@@ -177,48 +222,4 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val)
return 0;
}
-static void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val)
-{
- u32 tmp;
-
- outl((reg_space & 0x3) << 30 | reg_addr, AB_INDX);
- tmp = inl(AB_DATA);
- /* rpr 4.2
- * For certain revisions of the chip, the ABCFG registers,
- * with an address of 0x100NN (where 'N' is any hexadecimal
- * number), require an extra programming step.*/
- reg_addr & 0x10000 ? outl(0, AB_INDX) : NULL;
-
- tmp &= ~mask;
- tmp |= val;
-
- /* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<30 | reg_addr); */
- outl((reg_space & 0x3) << 30 | reg_addr, AB_INDX); /* probably we dont have to do it again. */
- outl(tmp, AB_DATA);
- reg_addr & 0x10000 ? outl(0, AB_INDX) : NULL;
-}
-
-/* space = 0: AX_INDXC, AX_DATAC
- * space = 1: AX_INDXP, AX_DATAP
- */
-static inline void alink_ax_indx(u32 space /*c or p? */ , u32 axindc,
- u32 mask, u32 val)
-{
- u32 tmp;
-
- /* read axindc to tmp */
- outl(space << 30 | space << 3 | 0x30, AB_INDX);
- outl(axindc, AB_DATA);
- outl(space << 30 | space << 3 | 0x34, AB_INDX);
- tmp = inl(AB_DATA);
-
- tmp &= ~mask;
- tmp |= val;
-
- /* write tmp */
- outl(space << 30 | space << 3 | 0x30, AB_INDX);
- outl(axindc, AB_DATA);
- outl(space << 30 | space << 3 | 0x34, AB_INDX);
- outl(tmp, AB_DATA);
-}
#endif
diff --git a/src/southbridge/amd/sb700/smbus.h b/src/southbridge/amd/sb700/smbus.h
old mode 100644
new mode 100755
index c21a1dc..9ddfc35
--- a/src/southbridge/amd/sb700/smbus.h
+++ b/src/southbridge/amd/sb700/smbus.h
@@ -20,6 +20,13 @@
#ifndef SB700_SMBUS_H
#define SB700_SMBUS_H
+#include <stdint.h>
+#include "stddef.h"
+#include <arch/io.h>
+
+#define SMBUS_IO_BASE 0x6000 /* Is it a temporary SMBus I/O base address? */
+ /*SIZE 0x40 */
+
#define SMBHSTSTAT 0x0
#define SMBSLVSTAT 0x1
#define SMBHSTCTRL 0x2
@@ -56,10 +63,11 @@
#define axindxp_reg(reg, mask, val) \
alink_ax_indx(1, (reg), (mask), (val))
+void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val);
+void alink_ax_indx(u32 space, u32 axindc, u32 mask, u32 val);
int do_smbus_recv_byte(u32 smbus_io_base, u32 device);
int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val);
int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
-
#endif
diff --git a/src/southbridge/amd/sb700/usb.c b/src/southbridge/amd/sb700/usb.c
old mode 100644
new mode 100755
index 2957dc5..7932401
--- a/src/southbridge/amd/sb700/usb.c
+++ b/src/southbridge/amd/sb700/usb.c
@@ -178,6 +178,7 @@ static void usb_init2(struct device *dev)
dword |= 1 << 8;
dword &= ~(1 << 27); /* 6.23 */
}
+ pci_write_config32(dev, 0x50, dword);
printk(BIOS_DEBUG, "rpr 6.23, final dword=%x\n", dword);
}
diff --git a/src/southbridge/amd/sr5650/Makefile.inc b/src/southbridge/amd/sr5650/Makefile.inc
index a2d10d7..0a4ce39 100644
--- a/src/southbridge/amd/sr5650/Makefile.inc
+++ b/src/southbridge/amd/sr5650/Makefile.inc
@@ -1,3 +1,5 @@
driver-y += sr5650.c
driver-y += pcie.c
driver-y += ht.c
+
+romstage-y += early_setup.c
diff --git a/src/southbridge/amd/sr5650/cmn.h b/src/southbridge/amd/sr5650/cmn.h
old mode 100644
new mode 100755
index e94fcdd..6692b86
--- a/src/southbridge/amd/sr5650/cmn.h
+++ b/src/southbridge/amd/sr5650/cmn.h
@@ -20,13 +20,21 @@
#ifndef __SR5650_CMN_H__
#define __SR5650_CMN_H__
+#include <arch/io.h>
+
#define NBMISC_INDEX 0x60
#define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */
#define NBMC_INDEX 0xE8
#define NBPCIE_INDEX 0xE0
-#define EXT_CONF_BASE_ADDRESS 0xE0000000
+#define EXT_CONF_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
#define TEMP_MMIO_BASE_ADDRESS 0xC0000000
+#define axindxc_reg(reg, mask, val) \
+ alink_ax_indx(0, (reg), (mask), (val))
+
+#define AB_INDX 0xCD8
+#define AB_DATA (AB_INDX+4)
+
static inline u32 nb_read_index(device_t dev, u32 index_reg, u32 index)
{
pci_write_config32(dev, index_reg, index);
diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c
old mode 100644
new mode 100755
index 5f7438c..50f836e
--- a/src/southbridge/amd/sr5650/early_setup.c
+++ b/src/southbridge/amd/sr5650/early_setup.c
@@ -17,20 +17,50 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <stdint.h>
+#include <arch/cpu.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/msr.h>
#include "sr5650.h"
#include "cmn.h"
+/* space = 0: AX_INDXC, AX_DATAC
+ * space = 1: AX_INDXP, AX_DATAP
+ */
+static void alink_ax_indx(u32 space, u32 axindc, u32 mask, u32 val)
+{
+ u32 tmp;
+
+ /* read axindc to tmp */
+ outl(space << 30 | space << 3 | 0x30, AB_INDX);
+ outl(axindc, AB_DATA);
+ outl(space << 30 | space << 3 | 0x34, AB_INDX);
+ tmp = inl(AB_DATA);
+
+ tmp &= ~mask;
+ tmp |= val;
+
+ /* write tmp */
+ outl(space << 30 | space << 3 | 0x30, AB_INDX);
+ outl(axindc, AB_DATA);
+ outl(space << 30 | space << 3 | 0x34, AB_INDX);
+ outl(tmp, AB_DATA);
+}
+
+
/* family 10 only, for reg > 0xFF */
-#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1
+#if (CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1) || (CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 == 1)
static void set_fam10_ext_cfg_enable_bits(device_t fam10_dev, u32 reg_pos, u32 mask,
u32 val)
{
u32 reg_old, reg;
- reg = reg_old = Get_NB32(fam10_dev, reg_pos);
+ reg = reg_old = pci_read_config32(fam10_dev, reg_pos);
reg &= ~mask;
reg |= val;
if (reg != reg_old) {
- Set_NB32(fam10_dev, reg_pos, reg);
+ pci_write_config32(fam10_dev, reg_pos, reg);
}
}
#else
@@ -113,17 +143,19 @@ static const u8 sr5650_ibias[] = {
[0xe] = 0xC6, /* 2.6Ghz HyperTransport 3 only */
};
-static void sr5650_htinit(void)
+void sr5650_htinit(void)
{
/*
* About HT, it has been done in enumerate_ht_chain().
*/
- device_t cpu_f0, sr5650_f0, clk_f1, cpu1_f0;
+ device_t cpu_f0, sr5650_f0, clk_f1;
u32 reg;
- u8 cpu_ht_freq, ibias;
+ u8 cpu_ht_freq, cpu_htfreq_max, ibias;
+ u8 sbnode;
+ u8 sblink;
+ u16 linkfreq_reg;
+ u16 linkfreqext_reg;
- cpu_f0 = PCI_DEV(0, 0x18, 0);
- cpu1_f0 = PCI_DEV(0, 0x19, 0);
/************************
* get cpu's ht freq, in cpu's function 0, offset 0x88
* bit11-8, specifics the maximum operation frequency of the link's transmitter clock.
@@ -133,16 +165,36 @@ static void sr5650_htinit(void)
* please see the table sr5650_ibias about the value and its corresponding frequency.
************************/
/* Link0, Link1 are for connection between P0 and P1.
- * Link2 should be 0xC8?
* TODO: Check the topology of the MP and NB. Or we just read the nbconfig? */
/* NOTE: In most cases, we only have one CPU. In that case, we should read 0x88. */
- reg = pci_read_config32(cpu1_f0, 0x0);
- reg = pci_read_config32(cpu_f0,
- reg == 0 || reg == -1 ? 0x88 : 0xC8
- );
+ /* Find out the node ID and the Link ID that
+ * connects to the Southbridge (system IO hub).
+ */
+ sbnode = (pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60) >> 8) & 7;
+ sblink = (pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64) >> 8) & 3; /* bit[10] sublink, bit[9,8] link. */
+ cpu_f0 = PCI_DEV(0, (0x18 + sbnode), 0);
+
+ /*
+ * link freq reg of Link0, 1, 2, 3 is 0x88, 0xA8, 0xC8, 0xE8 respectively
+ * link freq ext reg of Link0, 1, 2, 3 is 0x9C, 0xBC, 0xDC, 0xFC respectively
+ */
+ linkfreq_reg = 0x88 + (sblink << 5);
+ linkfreqext_reg = 0x9C + (sblink << 5);
+ reg = pci_read_config32(cpu_f0, linkfreq_reg);
+
cpu_ht_freq = (reg & 0xf00) >> 8;
- printk(BIOS_INFO, "sr5650_htinit cpu_ht_freq=%x.\n", cpu_ht_freq);
+
+ /* Freq[4] is only valid for revision D and later processors */
+ if (cpuid_eax(1) >= 0x100F80) {
+ cpu_htfreq_max = 0x14;
+ cpu_ht_freq |= ((pci_read_config32(cpu_f0, linkfreqext_reg) & 0x01) << 4);
+ } else {
+ cpu_htfreq_max = 0x0F;
+ }
+
+ printk(BIOS_INFO, "sr5650_htinit: Node %x Link %x, HT freq=%x.\n",
+ sbnode, sblink, cpu_ht_freq);
sr5650_f0 = PCI_DEV(0, 0, 0);
clk_f1 = PCI_DEV(0, 0, 1); /* We need to make sure the F1 is accessible. */
@@ -162,13 +214,13 @@ static void sr5650_htinit(void)
set_nbcfg_enable_bits(clk_f1, 0xD8, 0x3FF, ibias);
/* Optimizes chipset HT transmitter drive strength */
set_htiu_enable_bits(sr5650_f0, 0x2A, 0x3, 0x3);
- } else if ((cpu_ht_freq > 0x6) && (cpu_ht_freq < 0xf)) {
+ } else if ((cpu_ht_freq > 0x6) && (cpu_ht_freq < cpu_htfreq_max)) {
printk(BIOS_INFO, "sr5650_htinit: HT3 mode\n");
/* Enable Protocol checker */
set_htiu_enable_bits(sr5650_f0, 0x1E, 0xFFFFFFFF, 0x7FFFFFFC);
- #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 /* save some spaces */
+#if (CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1) || (CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 == 1) /* save some spaces */
/* HT3 mode, RPR 5.4.3 */
set_nbcfg_enable_bits(sr5650_f0, 0x9c, 0x3 << 16, 0);
@@ -189,83 +241,36 @@ static void sr5650_htinit(void)
/* Enables strict TM4 detection */
set_htiu_enable_bits(sr5650_f0, 0x15, 0x1 << 22, 0x1 << 22);
+ /* Optimizes chipset HT transmitter drive strength */
+ set_htiu_enable_bits(sr5650_f0, 0x2A, 0x3 << 0, 0x1 << 0);
+
/* HyperTransport 3 Processor register settings to be done in northbridge */
+
/* Enables error-retry mode */
- set_fam10_ext_cfg_enable_bits(cpu_f0, 0x130, 1 << 0, 1 << 0);
- set_fam10_ext_cfg_enable_bits(cpu_f0, 0x134, 1 << 0, 1 << 0); /* TODO: Check if it is needed to set other node. */
- set_fam10_ext_cfg_enable_bits(cpu_f0, 0x138, 1 << 0, 1 << 0);
+ set_fam10_ext_cfg_enable_bits(cpu_f0, 0x130 + (sblink << 2), 1 << 0, 1 << 0);
+
/* Enables scrambling */
- set_fam10_ext_cfg_enable_bits(cpu_f0, 0x170, 1 << 3, 1 << 3);
- set_fam10_ext_cfg_enable_bits(cpu_f0, 0x174, 1 << 3, 1 << 3); /* TODO: Check if it is needed to set other node. */
- set_fam10_ext_cfg_enable_bits(cpu_f0, 0x178, 1 << 3, 1 << 3);
+ set_fam10_ext_cfg_enable_bits(cpu_f0, 0x170 + (sblink << 2), 1 << 3, 1 << 3);
+
/* Enables transmitter de-emphasis
- * This depends on the PCB design and the trace */
+ * This depends on the PCB design and the trace
+ */
/* Disables command throttling */
set_fam10_ext_cfg_enable_bits(cpu_f0, 0x168, 1 << 10, 1 << 10);
+
/* Sets Training 0 Time. See T0Time table for encodings */
- set_fam10_ext_cfg_enable_bits(cpu_f0, 0x16C, 0x3F, 0x20);
+ /* AGESA have set it to recommanded value already
+ * The recommended values are 14h(2us) if F0x[18C:170][LS2En]=0
+ * and 26h(12us) if F0x[18C:170][LS2En]=1
+ */
+ //set_fam10_ext_cfg_enable_bits(cpu_f0, 0x16C, 0x3F, 0x26);
+
/* HT Buffer Allocation for Ganged Links!!! */
- #endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 */
+#endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 */
}
}
-#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 != 1 /* save some spaces */
-/*******************************************************
-* Optimize k8 with UMA.
-* See BKDG_NPT_0F guide for details.
-* The processor node is addressed by its Node ID on the HT link and can be
-* accessed with a device number in the PCI configuration space on Bus0.
-* The Node ID 0 is mapped to Device 24 (0x18), the Node ID 1 is mapped
-* to Device 25, and so on.
-* The processor implements configuration registers in PCI configuration
-* space using the following four headers
-* Function0: HT technology configuration
-* Function1: Address map configuration
-* Function2: DRAM and HT technology Trace mode configuration
-* Function3: Miscellaneous configuration
-*******************************************************/
-static void k8_optimization(void)
-{
- device_t k8_f0, k8_f2, k8_f3;
- msr_t msr;
-
- printk(BIOS_INFO, "k8_optimization()\n");
- k8_f0 = PCI_DEV(0, 0x18, 0);
- k8_f2 = PCI_DEV(0, 0x18, 2);
- k8_f3 = PCI_DEV(0, 0x18, 3);
-
- pci_write_config32(k8_f0, 0x90, 0x01700169); /* CIM NPT_Optimization */
- set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 28, 0 << 28);
- set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 26 | 1 << 27,
- 1 << 26 | 1 << 27);
- set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 11, 1 << 11);
- /* set_nbcfg_enable_bits(k8_f0, 0x84, 1 << 11 | 1 << 13 | 1 << 15, 1 << 11 | 1 << 13 | 1 << 15); */ /* TODO */
-
- pci_write_config32(k8_f3, 0x70, 0x51220111); /* CIM NPT_Optimization */
- pci_write_config32(k8_f3, 0x74, 0x50404021);
- pci_write_config32(k8_f3, 0x78, 0x08002A00);
- if (pci_read_config32(k8_f3, 0xE8) & 0x3<<12)
- pci_write_config32(k8_f3, 0x7C, 0x0000211A); /* dual core */
- else
- pci_write_config32(k8_f3, 0x7C, 0x0000212B); /* single core */
- set_nbcfg_enable_bits_8(k8_f3, 0xDC, 0xFF, 0x25);
-
- set_nbcfg_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5);
- set_nbcfg_enable_bits(k8_f2, 0x94, 0xF << 24, 7 << 24);
- set_nbcfg_enable_bits(k8_f2, 0x90, 1 << 10, 0 << 10);
- set_nbcfg_enable_bits(k8_f2, 0xA0, 3 << 2, 3 << 2);
- set_nbcfg_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5);
-
- msr = rdmsr(0xC001001F);
- msr.lo &= ~(1 << 9);
- msr.hi &= ~(1 << 4);
- wrmsr(0xC001001F, msr);
-}
-#else
-#define k8_optimization() do{}while(0)
-#endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 != 1 */
-
-#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 /* save some spaces */
+#if (CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1) || (CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 == 1) /* save some spaces */
void fam10_optimization(void)
{
device_t cpu_f0, cpu_f2, cpu_f3;
@@ -340,13 +345,12 @@ static void sr5650_por_misc_index_init(device_t nb_dev)
set_nbmisc_enable_bits(nb_dev, 0x2B, 1 << 15 | 1 << 27, 1 << 15 | 1 << 27);
set_nbmisc_enable_bits(nb_dev, 0x2C, 1 << 0 | 1 << 1 | 1 << 5 | 1 << 4 | 1 << 10, 1 << 0 | 1 << 1 | 1 << 5);
set_nbmisc_enable_bits(nb_dev, 0x32, 0x3F << 20, 0x2A << 20);
- set_nbmisc_enable_bits(nb_dev, 0x34, 1 << 7 | 1 << 15 | 1 << 23 | 1 << 31, 0); /* bit31 BTS fail */
+ set_nbmisc_enable_bits(nb_dev, 0x34, 1 << 7 | 1 << 15 | 1 << 23, 0);
set_nbmisc_enable_bits(nb_dev, 0x35, 0x3F << 26, 0x2A << 26);
set_nbmisc_enable_bits(nb_dev, 0x37, 0xfff << 20, 0xddd << 20);
set_nbmisc_enable_bits(nb_dev, 0x37, 7 << 11, 0);
/* PCIE CDR setting */
set_nbmisc_enable_bits(nb_dev, 0x38, 0xFFFFFFFF, 0xC0C0C0);
- set_nbmisc_enable_bits(nb_dev, 0x39, 1 << 31, 0); /* bit31 BTS fail */
set_nbmisc_enable_bits(nb_dev, 0x22, 0xFFFFFFFF, (1 << 27) | (0x8 << 12) | (0x8 << 16) | (0x8 << 20));
set_nbmisc_enable_bits(nb_dev, 0x22, 1 << 1 | 1 << 2 | 1 << 6 | 1 << 7, 1 << 1 | 1 << 2 | 1 << 6 | 1 << 7);
@@ -381,7 +385,7 @@ static void sr5650_por_misc_index_init(device_t nb_dev)
set_nbmisc_enable_bits(nb_dev, 0x47, 0xFFFFFFFF, 0x0000000B);
set_nbmisc_enable_bits(nb_dev, 0x12, 0xFFFFFFFF, 0x00FB5555);
- set_nbmisc_enable_bits(nb_dev, 0x0C, 0xFFFFFFFF, 0x001f37EC);
+ set_nbmisc_enable_bits(nb_dev, 0x0C, 0xFFFFFFFF, 0x001F37FC);
set_nbmisc_enable_bits(nb_dev, 0x15, 0xFFFFFFFF, 0x0);
/* NB_PROG_DEVICE_REMAP */
@@ -478,7 +482,7 @@ static void sr5650_por_init(device_t nb_dev)
}
/* enable CFG access to Dev8, which is the SB P2P Bridge */
-static void enable_sr5650_dev8(void)
+void enable_sr5650_dev8(void)
{
set_nbmisc_enable_bits(PCI_DEV(0, 0, 0), 0x00, 1 << 6, 1 << 6);
}
@@ -486,14 +490,14 @@ static void enable_sr5650_dev8(void)
/*
* Compliant with CIM_33's AtiNBInitEarlyPost (AtiInitNBBeforePCIInit).
*/
-static void sr5650_before_pci_init(void)
+void sr5650_before_pci_init(void)
{
}
/*
* The calling sequence is same as CIM.
*/
-static void sr5650_early_setup(void)
+void sr5650_early_setup(void)
{
device_t nb_dev = PCI_DEV(0, 0, 0);
printk(BIOS_INFO, "sr5650_early_setup()\n");
@@ -513,28 +517,24 @@ static void sr5650_early_setup(void)
break;
}
-#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1
-
fam10_optimization();
-#else
- k8_optimization();
-#endif
-
sr5650_por_init(nb_dev);
}
/**
- * @brief disable GPP1 Port0,1, GPP3a Port0,1,2,3,4,5
+ * @brief disable GPP1 Port0,1, GPP2, GPP3a Port0,1,2,3,4,5, GPP3b
*
*/
-void disable_pcie_bridge(void)
+void sr5650_disable_pcie_bridge(void)
{
u32 mask;
u32 reg;
device_t nb_dev = PCI_DEV(0, 0, 0);
- mask = (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) |
- (1 << 16) | (1 << 17);
+ mask = (1 << 2) | (1 << 3); /*GPP1*/
+ mask |= (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | (1 << 16) | (1 << 17); /*GPP3a*/
+ mask |= (1 << 18) | (1 << 19); /*GPP2*/
+ mask |= (1 << 20); /*GPP3b*/
reg = mask;
set_nbmisc_enable_bits(nb_dev, 0x0c, mask, reg);
}
diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c
old mode 100644
new mode 100755
index 3ad5a7d..37743ca
--- a/src/southbridge/amd/sr5650/pcie.c
+++ b/src/southbridge/amd/sr5650/pcie.c
@@ -267,23 +267,25 @@ void disable_pcie_bar3(device_t nb_dev)
}
/*
-*/
+ * GEN2 Software Compliance
+ */
void init_gen2(device_t nb_dev, device_t dev, u8 port)
{
u32 reg, val;
+
/* for A11 (0x89 == 0) */
reg = 0x34;
- if (port <= 3){
+ if (port <= 3) {
val = 1<<5;
- }else{
+ } else {
val = 1<<31;
- if (port >= 9 )
+ if (port >= 9)
reg = 0x39;
}
- /* todo: check for rev > a11
+ /* TODO: check for rev > a11 */
switch (port) {
- case 2;
+ case 2:
reg = 0x34;
val = 1<<5;
break;
@@ -300,7 +302,9 @@ void init_gen2(device_t nb_dev, device_t dev, u8 port)
reg = 0x39;
val = 1<<31;
break;
- case 7..9:
+ case 7:
+ case 8:
+ case 9:
reg = 0x37;
val = 1<<port;
break;
@@ -312,9 +316,11 @@ void init_gen2(device_t nb_dev, device_t dev, u8 port)
reg = 0;
break;
}
- */
+
+ /* Enables GEN2 capability of the device */
set_pcie_enable_bits(dev, 0xA4, 0x1, 0x1);
- pci_ext_write_config32(nb_dev, dev, 0x88, 0xF0, 1<<2); /* LINK_CRTL2*/
+ /* Advertise the link speed to be Gen2 */
+ pci_ext_write_config32(nb_dev, dev, 0x88, 0xF0, 1<<2); /* LINK_CRTL2 */
set_nbmisc_enable_bits(nb_dev, reg, val, val);
}
@@ -409,7 +415,7 @@ static void gpp12_cpl_buf_alloc(device_t nb_dev, device_t dev)
}
}
-#if 0 /* BTS report error without this function. But some board
+#if 1 /* BTS report error without this function. But some board
* fail to boot. Leave it here for future debug. */
/*
@@ -424,6 +430,7 @@ static void EnableLclkGating(device_t dev)
device_t nb_dev = dev_find_slot(0, 0);
device_t clk_f1= dev_find_slot(0, 1);
+ reg = 0xE8;
port = dev->path.pci.devfn >> 3;
switch (port) {
//PCIE_CORE_INDEX_GPP1
@@ -436,7 +443,6 @@ static void EnableLclkGating(device_t dev)
//PCIE_CORE_INDEX_GPP2
case 11:
case 12:
- reg = 0xE8;
value = 1 << 28;
break;
@@ -444,13 +450,11 @@ static void EnableLclkGating(device_t dev)
case 4 ... 7:
case 9:
case 10:
- reg = 0xE8;
value = 1 << 31;
break;
//PCIE_CORE_INDEX_GPP3b;
case 13:
- reg = 0xE8;
value = 1 << 25;
break;
@@ -541,6 +545,14 @@ void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
/* 4.4.2.step13.6. Set REGS_LC_ALLOW_TX_L1_CONTROL to allow TX to
prevent LC from going to L1 when there are outstanding completions.*/
set_pcie_enable_bits(dev, 0x02, 1 << 15, 1 << 15);
+
+ /* Enables the PLL power down when all lanes are inactive.
+ * It should be on in GPP.
+ */
+ if (gpp_sb_sel == PCIE_CORE_INDEX_GPP3a || gpp_sb_sel == PCIE_CORE_INDEX_GPP3b || gpp_sb_sel == PCIE_CORE_INDEX_SB) {
+ set_pcie_enable_bits(nb_dev, 0x02 | gpp_sb_sel, 1 << 3, 1 << 3);
+ }
+
/* 4.4.2.step13.7. Set REGS_LC_DONT_GO_TO_L0S_IF_L1_ARMED to prevent
lc to go to from L0 to Rcv_L0s if L1 is armed. */
set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11);
@@ -594,8 +606,11 @@ void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
* RPR typo- it says enable but the bit setting says disable.
* Disable it here and we enable it later. */
set_pcie_enable_bits(dev, 0xA4, 1 << 0, 1 << 0);
- /* 4.4.2.step13.21. */
- /* 4.4.2.step13.22 */
+
+ /* 4.4.2.step13.21. Legacy Hot Plug -CMOS Option */
+ /* NOTE: This feature can be enabled only for Hot-Plug slots implemented on SR5690 platform. */
+
+ /* 4.4.2.step13.22. Native PCIe Mode -CMOS Option */
/* Enable native PME. */
set_pcie_enable_bits(dev, 0x10, 1 << 3, 1 < 3);
/* This bit when set indicates that the PCIe Link associated with this port
@@ -607,7 +622,7 @@ void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
/* Enables flushing of TLPs when Data Link is down. */
set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19);
- /* 4.4.2.step14. Server Class Hot Plug Feature */
+ /* 4.4.2.step14. Server Class Hot Plug Feature. NOTE: This feature is not supported on SR5670 and SR5650 */
/* 4.4.2 step14.1: Advertising Hot Plug Capabilities */
/* 4.4.2.step14.2: Firmware Upload */
/* 4.4.2.Step14.3: SBIOS Acknowledgment to Firmware of Successful Firmware Upload */
@@ -630,11 +645,13 @@ void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
if ( port == 8 )
set_pcie_enable_bits(dev, 0xA0, 0, 1 << 23);
+#if 0 //SR56x0 pcie Gen2 code is not tested yet, we should enable it again when test finished.
/* set automatic Gen2 support, needs mainboard config option as Gen2 can cause issues on some platforms. */
init_gen2(nb_dev, dev, port);
set_pcie_enable_bits(dev, 0xA4, 1 << 29, 1 << 29);
set_pcie_enable_bits(dev, 0xC0, 1 << 15, 0);
set_pcie_enable_bits(dev, 0xA2, 1 << 13, 0);
+#endif
/* Hotplug Support - bit5 + bit6 capable and surprise */
pci_ext_write_config32(nb_dev, dev, 0x6c, 0x60, 0x60);
@@ -715,12 +732,13 @@ void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
/* 4.4..7.1 TXCLK Gating in L1, Enables powering down TXCLK clock pads on the receive side. */
set_pcie_enable_bits(nb_dev, 0x40 | gpp_sb_sel, 1 << 6, 1 << 6);
- /* Step 21: Register Locking PCIE Misc. Late Core sttting - Must move somewhere do PciInitLate FIXME */
- /* Lock HWInit Register */
- //set_pcie_enable_bits(nb_dev, 0x10 | gpp_sb_sel, 1 << 0, 1 << 0);
+ /* Step 20: Disables immediate RCB timeout on link down */
+ if (!((pci_read_config32(dev, 0x6C ) >> 6) & 0x01)) {
+ set_pcie_enable_bits(dev, 0x70, 1 << 19, 0 << 19);
+ }
/* Step 27: LCLK Gating */
- //EnableLclkGating(dev);
+ EnableLclkGating(dev);
/* Set Common Clock */
/* If dev present, set PcieCapPtr+0x10, BIT6);
@@ -734,6 +752,34 @@ void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
}
}
+/**
+ * Step 21: Register Locking
+ * Lock HWInit Register of each pcie core
+ */
+static void lock_hwinitreg(device_t nb_dev)
+{
+ /* Step 21: Register Locking, Lock HWInit Register */
+ set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_GPP1, 1 << 0, 1 << 0);
+ set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_SB, 1 << 0, 1 << 0);
+ set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_GPP2, 1 << 0, 1 << 0);
+ set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_GPP3a, 1 << 0, 1 << 0);
+ set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_GPP3b, 1 << 0, 1 << 0);
+}
+
+/**
+ * Lock HWInit Register
+ */
+void sr56x0_lock_hwinitreg(void)
+{
+ device_t nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+
+ /* Lock HWInit Register */
+ lock_hwinitreg(nb_dev);
+
+ /* Lock HWInit Register NBMISCIND:0x0 NBCNTL[7] HWINIT_WR_LOCK */
+ set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 7, 1 << 7);
+}
+
/*****************************************
* Compliant with CIM_33's PCIEConfigureGPPCore
*****************************************/
diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c
old mode 100644
new mode 100755
index 616ca44..14b919d
--- a/src/southbridge/amd/sr5650/sr5650.c
+++ b/src/southbridge/amd/sr5650/sr5650.c
@@ -266,15 +266,21 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
}
/*
-* Compliant with CIM_33's ATINB_SetToms.
-* Set Top Of Memory below and above 4G.
-*/
+ * Set Top Of Memory below and above 4G.
+ */
void sr5650_set_tom(device_t nb_dev)
{
- extern u64 uma_memory_base;
+ msr_t sysmem;
+
+ /* The system top memory in SR56X0. */
+ sysmem = rdmsr(0xc001001A);
+ printk(BIOS_DEBUG, "Sysmem TOM = %x_%x\n", sysmem.hi, sysmem.lo);
+ pci_write_config32(nb_dev, 0x90, sysmem.lo);
- /* set TOM */
- pci_write_config32(nb_dev, 0x90, uma_memory_base);
+ sysmem = rdmsr(0xc001001D);
+ printk(BIOS_DEBUG, "Sysmem TOM2 = %x_%x\n", sysmem.hi, sysmem.lo);
+ htiu_write_index(nb_dev, 0x31, sysmem.hi);
+ htiu_write_index(nb_dev, 0x30, sysmem.lo | 1);
}
u32 get_vid_did(device_t dev)
@@ -308,7 +314,7 @@ void sr5650_nb_pci_table(device_t nb_dev)
temp8 &= ~(1<<1);
pci_write_config8(nb_dev, 0x8d, temp8);
- /* set temporary NB TOM to 0x40000000. */
+ /* The system top memory in SR56X0. */
sr5650_set_tom(nb_dev);
/* Program NB HTIU table. */
@@ -424,6 +430,11 @@ void sr5650_enable(device_t dev)
default:
printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev));
}
+
+ /* Lock HWInit Register after the last device was done */
+ if (dev_ind == 13) {
+ sr56x0_lock_hwinitreg();
+ }
}
struct chip_operations southbridge_amd_sr5650_ops = {
diff --git a/src/southbridge/amd/sr5650/sr5650.h b/src/southbridge/amd/sr5650/sr5650.h
old mode 100644
new mode 100755
index 5da3544..1b5112b
--- a/src/southbridge/amd/sr5650/sr5650.h
+++ b/src/southbridge/amd/sr5650/sr5650.h
@@ -103,6 +103,10 @@ void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add);
void enable_pcie_bar3(device_t nb_dev);
void disable_pcie_bar3(device_t nb_dev);
+void enable_sr5650_dev8(void);
+void sr5650_htinit(void);
+void sr5650_early_setup(void);
+void sr5650_before_pci_init(void);
void sr5650_enable(device_t dev);
void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port);
void sr5650_gfx_init(device_t nb_dev, device_t dev, u32 port);
@@ -112,8 +116,9 @@ void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port);
u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port);
void pcie_config_misc_clk(device_t nb_dev);
void fam10_optimization(void);
-void disable_pcie_bridge(void);
+void sr5650_disable_pcie_bridge(void);
u32 get_vid_did(device_t dev);
void sr5650_nb_pci_table(device_t nb_dev);
void init_gen2(device_t nb_dev, device_t dev, u8 port);
+void sr56x0_lock_hwinitreg(void);
#endif /* SR5650_H */
diff --git a/src/superio/nuvoton/wpcm450/Makefile.inc b/src/superio/nuvoton/wpcm450/Makefile.inc
index dc7ed36..c70b2fb 100644
--- a/src/superio/nuvoton/wpcm450/Makefile.inc
+++ b/src/superio/nuvoton/wpcm450/Makefile.inc
@@ -18,5 +18,6 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
+romstage-y += early_init.c
ramstage-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += superio.c
diff --git a/src/superio/nuvoton/wpcm450/early_init.c b/src/superio/nuvoton/wpcm450/early_init.c
old mode 100644
new mode 100755
index eb80c94..94bef02
--- a/src/superio/nuvoton/wpcm450/early_init.c
+++ b/src/superio/nuvoton/wpcm450/early_init.c
@@ -18,7 +18,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <arch/io.h>
#include <arch/romcc_io.h>
+#include <device/pnp_def.h>
#include "wpcm450.h"
static void wpcm450_pnp_set_logical_device(u8 dev, u16 port)
@@ -41,7 +43,7 @@ static void wpcm450_pnp_set_iobase(u8 dev, u16 port, u8 index, u16 iobase)
outb(iobase&0xFF, port+1);
}
-static void wpcm450_enable_dev(u8 dev, u16 port, u16 iobase)
+void wpcm450_enable_dev(u8 dev, u16 port, u16 iobase)
{
wpcm450_pnp_set_logical_device(dev, port);
wpcm450_pnp_set_enable(dev, port, 0);
diff --git a/src/superio/nuvoton/wpcm450/wpcm450.h b/src/superio/nuvoton/wpcm450/wpcm450.h
old mode 100644
new mode 100755
index bf50c85..46f3cc5
--- a/src/superio/nuvoton/wpcm450/wpcm450.h
+++ b/src/superio/nuvoton/wpcm450/wpcm450.h
@@ -25,4 +25,6 @@
#define WPCM450_SP1 0x03 /* Com1 */
#define WPCM450_KBCK 0x06 /* Keyboard */
+void wpcm450_enable_dev(u8 dev, u16 port, u16 iobase);
+
#endif
diff --git a/src/vendorcode/amd/agesa/f14/Lib/amdlib.c b/src/vendorcode/amd/agesa/f14/Lib/amdlib.c
index c3364d3..3fc5112 100644
--- a/src/vendorcode/amd/agesa/f14/Lib/amdlib.c
+++ b/src/vendorcode/amd/agesa/f14/Lib/amdlib.c
@@ -551,8 +551,8 @@ LibAmdIoRMW (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
- UINT32 TempData;
- UINT32 TempMask;
+ UINT32 TempData = 0;
+ UINT32 TempMask = 0;
UINT32 Value;
LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask);
LibAmdIoRead (AccessWidth, IoAddress, &Value, StdHeader);
@@ -584,8 +584,8 @@ LibAmdIoPoll (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
- UINT32 TempData;
- UINT32 TempMask;
+ UINT32 TempData = 0;
+ UINT32 TempMask = 0;
UINT32 Value;
LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask);
do {
@@ -688,8 +688,8 @@ LibAmdMemRMW (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
- UINT32 TempData;
- UINT32 TempMask;
+ UINT32 TempData = 0;
+ UINT32 TempMask = 0;
UINT32 Value;
LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask);
LibAmdMemRead (AccessWidth, MemAddress, &Value, StdHeader);
@@ -721,8 +721,8 @@ LibAmdMemPoll (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
- UINT32 TempData;
- UINT32 TempMask;
+ UINT32 TempData = 0;
+ UINT32 TempMask = 0;
UINT32 Value;
LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask);
do {
@@ -849,8 +849,8 @@ LibAmdPciRMW (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
- UINT32 TempData;
- UINT32 TempMask;
+ UINT32 TempData = 0;
+ UINT32 TempMask = 0;
UINT32 Value;
LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask);
LibAmdPciRead (AccessWidth, PciAddress, &Value, StdHeader);
@@ -882,8 +882,8 @@ LibAmdPciPoll (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
- UINT32 TempData;
- UINT32 TempMask;
+ UINT32 TempData = 0;
+ UINT32 TempMask = 0;
UINT32 Value;
LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask);
do {
1
0
21 Jul '11
Frank Vibrans III (frank.vibrans(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/108
-gerrit
commit 5f3f7fd213785ff3f78af15300a6e8e9797ac96d
Author: efdesign98 <efdesign98(a)gmail.com>
Date: Wed Jul 20 13:23:04 2011 -0600
Add the SuperMicro H8QGI platform
This set adds support for the SuperMicro H8QGI mainboard.
It is a publicly available 4 socket board using AMD Family
10 cpus and AMD SR5650 and SB700 bridges.
Change-Id: I196704f79db4c45382559c5ee0619dc8d96ff140
Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com>
Signed-off-by: efdesign98 <efdesign98(a)gmail.com>
---
src/mainboard/supermicro/Kconfig | 3 +
src/mainboard/supermicro/h8qgi/BiosCallOuts.c | 516 +++++++
src/mainboard/supermicro/h8qgi/BiosCallOuts.h | 78 +
src/mainboard/supermicro/h8qgi/Kconfig | 129 ++
src/mainboard/supermicro/h8qgi/Makefile.inc | 33 +
src/mainboard/supermicro/h8qgi/OptionsIds.h | 66 +
src/mainboard/supermicro/h8qgi/acpi/cpstate.asl | 75 +
src/mainboard/supermicro/h8qgi/acpi/ide.asl | 244 +++
src/mainboard/supermicro/h8qgi/acpi/routing.asl | 222 +++
src/mainboard/supermicro/h8qgi/acpi/sata.asl | 149 ++
src/mainboard/supermicro/h8qgi/acpi/usb.asl | 161 ++
src/mainboard/supermicro/h8qgi/acpi_tables.c | 295 ++++
src/mainboard/supermicro/h8qgi/agesawrapper.c | 1169 ++++++++++++++
src/mainboard/supermicro/h8qgi/agesawrapper.h | 87 ++
src/mainboard/supermicro/h8qgi/buildOpts.c | 541 +++++++
src/mainboard/supermicro/h8qgi/chip.h | 23 +
src/mainboard/supermicro/h8qgi/cmos.layout | 118 ++
src/mainboard/supermicro/h8qgi/devicetree.cb | 176 +++
src/mainboard/supermicro/h8qgi/dimmSpd.c | 229 +++
src/mainboard/supermicro/h8qgi/dsdt.asl | 1849 +++++++++++++++++++++++
src/mainboard/supermicro/h8qgi/fadt.c | 201 +++
src/mainboard/supermicro/h8qgi/get_bus_conf.c | 154 ++
src/mainboard/supermicro/h8qgi/irq_tables.c | 122 ++
src/mainboard/supermicro/h8qgi/mainboard.c | 73 +
src/mainboard/supermicro/h8qgi/mptable.c | 200 +++
src/mainboard/supermicro/h8qgi/platform_oem.c | 50 +
src/mainboard/supermicro/h8qgi/platform_oem.h | 29 +
src/mainboard/supermicro/h8qgi/romstage.c | 132 ++
28 files changed, 7124 insertions(+), 0 deletions(-)
diff --git a/src/mainboard/supermicro/Kconfig b/src/mainboard/supermicro/Kconfig
old mode 100644
new mode 100755
index 8483d6f..80ffd6a
--- a/src/mainboard/supermicro/Kconfig
+++ b/src/mainboard/supermicro/Kconfig
@@ -13,6 +13,8 @@ config BOARD_SUPERMICRO_H8QME_FAM10
bool "H8QME-2+ (Fam10)"
config BOARD_SUPERMICRO_H8SCM_FAM10
bool "H8SCM (Fam10)"
+config BOARD_SUPERMICRO_H8QGI
+ bool "H8QGI"
config BOARD_SUPERMICRO_X6DAI_G
bool "X6DAi-G"
config BOARD_SUPERMICRO_X6DHE_G2
@@ -31,6 +33,7 @@ source "src/mainboard/supermicro/h8dmr/Kconfig"
source "src/mainboard/supermicro/h8dmr_fam10/Kconfig"
source "src/mainboard/supermicro/h8qme_fam10/Kconfig"
source "src/mainboard/supermicro/h8scm_fam10/Kconfig"
+source "src/mainboard/supermicro/h8qgi/Kconfig"
source "src/mainboard/supermicro/x6dai_g/Kconfig"
source "src/mainboard/supermicro/x6dhe_g2/Kconfig"
source "src/mainboard/supermicro/x6dhe_g/Kconfig"
diff --git a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c
new file mode 100755
index 0000000..b7f0124
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c
@@ -0,0 +1,516 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "agesawrapper.h"
+#include "amdlib.h"
+#include "BiosCallOuts.h"
+#include "Ids.h"
+#include "OptionsIds.h"
+#include "heapManager.h"
+
+STATIC BIOS_CALLOUT_STRUCT BiosCallouts[REQUIRED_CALLOUTS] =
+{
+ {
+ AGESA_ALLOCATE_BUFFER,
+ BiosAllocateBuffer
+ },
+
+ {
+ AGESA_DEALLOCATE_BUFFER,
+ BiosDeallocateBuffer
+ },
+
+ {
+ AGESA_DO_RESET,
+ BiosReset
+ },
+
+ {
+ AGESA_LOCATE_BUFFER,
+ BiosLocateBuffer
+ },
+
+ {
+ AGESA_READ_SPD,
+ BiosReadSpd
+ },
+
+ {
+ AGESA_READ_SPD_RECOVERY,
+ BiosDefaultRet
+ },
+
+ {
+ AGESA_RUNFUNC_ONAP,
+ BiosRunFuncOnAp
+ },
+
+ {
+ AGESA_GET_IDS_INIT_DATA,
+ BiosGetIdsInitData
+ },
+
+ {
+ AGESA_HOOKBEFORE_DQS_TRAINING,
+ BiosHookBeforeDQSTraining
+ },
+
+ {
+ AGESA_HOOKBEFORE_DRAM_INIT,
+ BiosHookBeforeDramInit
+ },
+ {
+ AGESA_HOOKBEFORE_EXIT_SELF_REF,
+ BiosHookBeforeExitSelfRefresh
+ },
+};
+
+extern AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info);
+
+AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ UINTN i;
+ AGESA_STATUS CalloutStatus;
+
+ for (i = 0; i < REQUIRED_CALLOUTS; i++) {
+ if (BiosCallouts[i].CalloutName == Func) {
+ break;
+ }
+ }
+
+ if(i >= REQUIRED_CALLOUTS) {
+ return AGESA_UNSUPPORTED;
+ }
+
+ CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr);
+
+ return CalloutStatus;
+}
+
+
+CONST IDS_NV_ITEM IdsData[] =
+{
+ /*{
+ AGESA_IDS_NV_MAIN_PLL_CON,
+ 0x1
+ },
+ {
+ AGESA_IDS_NV_MAIN_PLL_FID_EN,
+ 0x1
+ },
+ {
+ AGESA_IDS_NV_MAIN_PLL_FID,
+ 0x8
+ },
+
+ {
+ AGESA_IDS_NV_CUSTOM_NB_PSTATE,
+ },
+ {
+ AGESA_IDS_NV_CUSTOM_NB_P0_DIV_CTRL,
+ },
+ {
+ AGESA_IDS_NV_CUSTOM_NB_P1_DIV_CTRL,
+ },
+ {
+ AGESA_IDS_NV_FORCE_NB_PSTATE,
+ },
+ */
+ {
+ 0xFFFF,
+ 0xFFFF
+ }
+};
+
+#define NUM_IDS_ENTRIES (sizeof (IdsData) / sizeof (IDS_NV_ITEM))
+
+AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ UINTN i;
+ IDS_NV_ITEM *IdsPtr;
+
+ IdsPtr = ((IDS_CALLOUT_STRUCT *) ConfigPtr)->IdsNvPtr;
+
+ if (Data == IDS_CALLOUT_INIT) {
+ for (i = 0; i < NUM_IDS_ENTRIES; i++) {
+ IdsPtr[i].IdsNvValue = IdsData[i].IdsNvValue;
+ IdsPtr[i].IdsNvId = IdsData[i].IdsNvId;
+ }
+ }
+ return AGESA_SUCCESS;
+}
+
+
+AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ UINT32 AvailableHeapSize;
+ UINT8 *BiosHeapBaseAddr;
+ UINT32 CurrNodeOffset;
+ UINT32 PrevNodeOffset;
+ UINT32 FreedNodeOffset;
+ UINT32 BestFitNodeOffset;
+ UINT32 BestFitPrevNodeOffset;
+ UINT32 NextFreeOffset;
+ BIOS_BUFFER_NODE *CurrNodePtr;
+ BIOS_BUFFER_NODE *FreedNodePtr;
+ BIOS_BUFFER_NODE *BestFitNodePtr;
+ BIOS_BUFFER_NODE *BestFitPrevNodePtr;
+ BIOS_BUFFER_NODE *NextFreePtr;
+ BIOS_HEAP_MANAGER *BiosHeapBasePtr;
+ AGESA_BUFFER_PARAMS *AllocParams;
+
+ AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr);
+ AllocParams->BufferPointer = NULL;
+
+ AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER);
+ BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
+ BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
+
+ if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) {
+ /* First allocation */
+ CurrNodeOffset = sizeof (BIOS_HEAP_MANAGER);
+ CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+ CurrNodePtr->BufferHandle = AllocParams->BufferHandle;
+ CurrNodePtr->BufferSize = AllocParams->BufferLength;
+ CurrNodePtr->NextNodeOffset = 0;
+ AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof (BIOS_BUFFER_NODE);
+
+ /* Update the remaining free space */
+ FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof (BIOS_BUFFER_NODE);
+ FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+ FreedNodePtr->BufferSize = AvailableHeapSize - sizeof (BIOS_BUFFER_NODE) - CurrNodePtr->BufferSize;
+ FreedNodePtr->NextNodeOffset = 0;
+
+ /* Update the offsets for Allocated and Freed nodes */
+ BiosHeapBasePtr->StartOfAllocatedNodes = CurrNodeOffset;
+ BiosHeapBasePtr->StartOfFreedNodes = FreedNodeOffset;
+ } else {
+ /* Find out whether BufferHandle has been allocated on the heap. */
+ /* If it has, return AGESA_BOUNDS_CHK */
+ CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+ CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+
+ while (CurrNodeOffset != 0) {
+ CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+ if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) {
+ return AGESA_BOUNDS_CHK;
+ }
+ CurrNodeOffset = CurrNodePtr->NextNodeOffset;
+ /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points
+ to the end of the allocated nodes list.
+ */
+
+ }
+ /* Find the node that best fits the requested buffer size */
+ FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
+ PrevNodeOffset = FreedNodeOffset;
+ BestFitNodeOffset = 0;
+ BestFitPrevNodeOffset = 0;
+ while (FreedNodeOffset != 0) {
+ FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+ if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) {
+ if (BestFitNodeOffset == 0) {
+ /* First node that fits the requested buffer size */
+ BestFitNodeOffset = FreedNodeOffset;
+ BestFitPrevNodeOffset = PrevNodeOffset;
+ } else {
+ /* Find out whether current node is a better fit than the previous nodes */
+ BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
+ if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) {
+ BestFitNodeOffset = FreedNodeOffset;
+ BestFitPrevNodeOffset = PrevNodeOffset;
+ }
+ }
+ }
+ PrevNodeOffset = FreedNodeOffset;
+ FreedNodeOffset = FreedNodePtr->NextNodeOffset;
+ } /* end of while loop */
+
+
+ if (BestFitNodeOffset == 0) {
+ /* If we could not find a node that fits the requested buffer */
+ /* size, return AGESA_BOUNDS_CHK */
+ return AGESA_BOUNDS_CHK;
+ } else {
+ BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
+ BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset);
+
+ /* If BestFitNode is larger than the requested buffer, fragment the node further */
+ if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) {
+ NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE);
+
+ NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset);
+ NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE));
+ NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset;
+ } else {
+ /* Otherwise, next free node is NextNodeOffset of BestFitNode */
+ NextFreeOffset = BestFitNodePtr->NextNodeOffset;
+ }
+
+ /* If BestFitNode is the first buffer in the list, then update
+ StartOfFreedNodes to reflect the new free node
+ */
+ if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) {
+ BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset;
+ } else {
+ BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset;
+ }
+
+ /* Add BestFitNode to the list of Allocated nodes */
+ CurrNodePtr->NextNodeOffset = BestFitNodeOffset;
+ BestFitNodePtr->BufferSize = AllocParams->BufferLength;
+ BestFitNodePtr->BufferHandle = AllocParams->BufferHandle;
+ BestFitNodePtr->NextNodeOffset = 0;
+
+ /* Remove BestFitNode from list of Freed nodes */
+ AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof (BIOS_BUFFER_NODE);
+ }
+ }
+
+ return AGESA_SUCCESS;
+}
+
+AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+
+ UINT8 *BiosHeapBaseAddr;
+ UINT32 AllocNodeOffset;
+ UINT32 PrevNodeOffset;
+ UINT32 NextNodeOffset;
+ UINT32 FreedNodeOffset;
+ UINT32 EndNodeOffset;
+ BIOS_BUFFER_NODE *AllocNodePtr;
+ BIOS_BUFFER_NODE *PrevNodePtr;
+ BIOS_BUFFER_NODE *FreedNodePtr;
+ BIOS_BUFFER_NODE *NextNodePtr;
+ BIOS_HEAP_MANAGER *BiosHeapBasePtr;
+ AGESA_BUFFER_PARAMS *AllocParams;
+
+ BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
+ BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
+
+ AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
+
+ /* Find target node to deallocate in list of allocated nodes.
+ Return AGESA_BOUNDS_CHK if the BufferHandle is not found
+ */
+ AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+ AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+ PrevNodeOffset = AllocNodeOffset;
+
+ while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) {
+ if (AllocNodePtr->NextNodeOffset == 0) {
+ return AGESA_BOUNDS_CHK;
+ }
+ PrevNodeOffset = AllocNodeOffset;
+ AllocNodeOffset = AllocNodePtr->NextNodeOffset;
+ AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+ }
+
+ /* Remove target node from list of allocated nodes */
+ PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
+ PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
+
+ /* Zero out the buffer, and clear the BufferHandle */
+ LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof (BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader));
+ AllocNodePtr->BufferHandle = 0;
+ AllocNodePtr->BufferSize += sizeof (BIOS_BUFFER_NODE);
+
+ /* Add deallocated node in order to the list of freed nodes */
+ FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
+ FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+
+ EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize;
+
+ if (AllocNodeOffset < FreedNodeOffset) {
+ /* Add to the start of the freed list */
+ if (EndNodeOffset == FreedNodeOffset) {
+ /* If the freed node is adjacent to the first node in the list, concatenate both nodes */
+ AllocNodePtr->BufferSize += FreedNodePtr->BufferSize;
+ AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset;
+
+ /* Clear the BufferSize and NextNodeOffset of the previous first node */
+ FreedNodePtr->BufferSize = 0;
+ FreedNodePtr->NextNodeOffset = 0;
+
+ } else {
+ /* Otherwise, add freed node to the start of the list
+ Update NextNodeOffset and BufferSize to include the
+ size of BIOS_BUFFER_NODE
+ */
+ AllocNodePtr->NextNodeOffset = FreedNodeOffset;
+ }
+ /* Update StartOfFreedNodes to the new first node */
+ BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset;
+ } else {
+ /* Traverse list of freed nodes to find where the deallocated node
+ should be place
+ */
+ NextNodeOffset = FreedNodeOffset;
+ NextNodePtr = FreedNodePtr;
+ while (AllocNodeOffset > NextNodeOffset) {
+ PrevNodeOffset = NextNodeOffset;
+ if (NextNodePtr->NextNodeOffset == 0) {
+ break;
+ }
+ NextNodeOffset = NextNodePtr->NextNodeOffset;
+ NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
+ }
+
+ /* If deallocated node is adjacent to the next node,
+ concatenate both nodes
+ */
+ if (NextNodeOffset == EndNodeOffset) {
+ NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
+ AllocNodePtr->BufferSize += NextNodePtr->BufferSize;
+ AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset;
+
+ NextNodePtr->BufferSize = 0;
+ NextNodePtr->NextNodeOffset = 0;
+ } else {
+ /*AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; */
+ AllocNodePtr->NextNodeOffset = NextNodeOffset;
+ }
+ /* If deallocated node is adjacent to the previous node,
+ concatenate both nodes
+ */
+ PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
+ EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize;
+ if (AllocNodeOffset == EndNodeOffset) {
+ PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
+ PrevNodePtr->BufferSize += AllocNodePtr->BufferSize;
+
+ AllocNodePtr->BufferSize = 0;
+ AllocNodePtr->NextNodeOffset = 0;
+ } else {
+ PrevNodePtr->NextNodeOffset = AllocNodeOffset;
+ }
+ }
+ return AGESA_SUCCESS;
+}
+
+AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ UINT32 AllocNodeOffset;
+ UINT8 *BiosHeapBaseAddr;
+ BIOS_BUFFER_NODE *AllocNodePtr;
+ BIOS_HEAP_MANAGER *BiosHeapBasePtr;
+ AGESA_BUFFER_PARAMS *AllocParams;
+
+ AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
+
+ BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
+ BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
+
+ AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+ AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+
+ while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) {
+ if (AllocNodePtr->NextNodeOffset == 0) {
+ AllocParams->BufferPointer = NULL;
+ AllocParams->BufferLength = 0;
+ return AGESA_BOUNDS_CHK;
+ } else {
+ AllocNodeOffset = AllocNodePtr->NextNodeOffset;
+ AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+ }
+ }
+
+ AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof (BIOS_BUFFER_NODE));
+ AllocParams->BufferLength = AllocNodePtr->BufferSize;
+
+ return AGESA_SUCCESS;
+
+}
+
+AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ AGESA_STATUS Status;
+
+ Status = agesawrapper_amdlaterunaptask (Data, ConfigPtr);
+ return Status;
+}
+
+AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ AGESA_STATUS Status;
+ UINT8 Value;
+ UINTN ResetType;
+ AMD_CONFIG_PARAMS *StdHeader;
+
+ ResetType = Data;
+ StdHeader = ConfigPtr;
+
+ //
+ // Perform the RESET based upon the ResetType. In case of
+ // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to
+ // AmdResetManager. During the critical condition, where reset is required
+ // immediately, the reset will be invoked directly by writing 0x04 to port
+ // 0xCF9 (Reset Port).
+ //
+ switch (ResetType) {
+ case WARM_RESET_WHENEVER:
+ case COLD_RESET_WHENEVER:
+ break;
+
+ case WARM_RESET_IMMEDIATELY:
+ case COLD_RESET_IMMEDIATELY:
+ Value = 0x06;
+ LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader);
+ break;
+
+ default:
+ break;
+ }
+
+ Status = 0;
+ return Status;
+}
+
+AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ AGESA_STATUS Status;
+ Status = AmdMemoryReadSPD (Func, Data, ConfigPtr);
+
+ return Status;
+}
+
+AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ return AGESA_UNSUPPORTED;
+}
+
+/* Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ return AGESA_SUCCESS;
+}
+
+/* Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ return AGESA_SUCCESS;
+}
+
+/* Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ return AGESA_SUCCESS;
+}
+
diff --git a/src/mainboard/supermicro/h8qgi/BiosCallOuts.h b/src/mainboard/supermicro/h8qgi/BiosCallOuts.h
new file mode 100755
index 0000000..24a05fb
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/BiosCallOuts.h
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BIOS_CALLOUT_H_
+#define _BIOS_CALLOUT_H_
+
+#include "Porting.h"
+#include "AGESA.h"
+
+#define REQUIRED_CALLOUTS 12
+#define BIOS_HEAP_START_ADDRESS 0x00010000
+#define BIOS_HEAP_SIZE 0x20000 /* 64MB */
+
+typedef struct _BIOS_HEAP_MANAGER {
+ //UINT32 AvailableSize;
+ UINT32 StartOfAllocatedNodes;
+ UINT32 StartOfFreedNodes;
+} BIOS_HEAP_MANAGER;
+
+typedef struct _BIOS_BUFFER_NODE {
+ UINT32 BufferHandle;
+ UINT32 BufferSize;
+ UINT32 NextNodeOffset;
+} BIOS_BUFFER_NODE;
+
+/*
+ * CALLOUTS
+ */
+AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+
+/* REQUIRED CALLOUTS
+ * AGESA ADVANCED CALLOUTS - CPU
+ */
+AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+
+/* AGESA ADVANCED CALLOUTS - MEMORY */
+AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr);
+
+/* BIOS DEFAULT RET */
+AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+
+/* Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+/* Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+/* Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+#define SB_GPIO_REG02 2
+#define SB_GPIO_REG09 9
+#define SB_GPIO_REG10 10
+#define SB_GPIO_REG15 15
+#define SB_GPIO_REG17 17
+#define SB_GPIO_REG21 21
+#define SB_GPIO_REG25 25
+#define SB_GPIO_REG28 28
+#endif //_BIOS_CALLOUT_H_
+
diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig
new file mode 100755
index 0000000..286cb17
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/Kconfig
@@ -0,0 +1,129 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+if BOARD_SUPERMICRO_H8QGI
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select ARCH_X86
+ select CPU_AMD_AGESA_FAMILY10
+ select NORTHBRIDGE_AMD_AGESA_FAMILY10_ROOT_COMPLEX
+ select NORTHBRIDGE_AMD_AGESA_FAMILY10
+ select SOUTHBRIDGE_AMD_SR5650
+ select SOUTHBRIDGE_AMD_SP5100
+ select SUPERIO_WINBOND_W83627DHG
+ select BOARD_HAS_FADT
+ select HAVE_BUS_CONFIG
+ select HAVE_OPTION_TABLE
+ select HAVE_PIRQ_TABLE
+ select HAVE_MP_TABLE
+ select HAVE_HARD_RESET
+ select SERIAL_CPU_INIT
+ select AMDMCT
+ select HAVE_ACPI_TABLES
+ select BOARD_ROMSIZE_KB_2048
+ select TINY_BOOTBLOCK
+ #select MMCONF_SUPPORT_DEFAULT #TODO enable it to resolve Multicore IO conflict
+
+config AMD_AGESA
+ bool
+ default y
+
+config MAINBOARD_DIR
+ string
+ default supermicro/h8qgi
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "H8QGI"
+
+config HW_MEM_HOLE_SIZEK
+ hex
+ default 0x200000
+
+config MAX_CPUS
+ int
+ default 64
+
+config MAX_PHYSICAL_CPUS
+ int
+ default 16
+
+config HW_MEM_HOLE_SIZE_AUTO_INC
+ bool
+ default n
+
+config MEM_TRAIN_SEQ
+ int
+ default 2
+
+config IRQ_SLOT_COUNT
+ int
+ default 11
+
+config RAMTOP
+ hex
+ default 0x1000000
+
+config HEAP_SIZE
+ hex
+ default 0xc0000
+
+config STACK_SIZE
+ hex
+ default 0x10000
+
+config ACPI_SSDTX_NUM
+ int
+ default 0
+
+config RAMBASE
+ hex
+ default 0x200000
+
+config SIO_PORT
+ hex
+ default 0x164E
+ help
+ though UARTs are on the NUVOTON BMC, port 0x164E
+ PS2 keyboard and mouse are on SUPERIO_WINBOND_W83627DHG, port 0x2E
+
+config DRIVERS_PS2_KEYBOARD
+ bool
+ default y
+
+config WARNINGS_ARE_ERRORS
+ bool
+ default n
+
+config ONBOARD_VGA_IS_PRIMARY
+ bool
+ default y
+
+config VGA_BIOS
+ bool
+ default n
+
+config VGA_BIOS_ID
+ string
+ depends on VGA_BIOS
+ default "102b,0532"
+
+endif # BOARD_SUPERMICRO_H8QGI
+
diff --git a/src/mainboard/supermicro/h8qgi/Makefile.inc b/src/mainboard/supermicro/h8qgi/Makefile.inc
new file mode 100755
index 0000000..211387d
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/Makefile.inc
@@ -0,0 +1,33 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+romstage-y += buildOpts.c
+romstage-y += agesawrapper.c
+romstage-y += dimmSpd.c
+romstage-y += BiosCallOuts.c
+romstage-y += platform_oem.c
+
+ramstage-y += buildOpts.c
+ramstage-y += agesawrapper.c
+ramstage-y += dimmSpd.c
+ramstage-y += BiosCallOuts.c
+ramstage-y += platform_oem.c
+
+AGESA_ROOT ?= $(src)/vendorcode/amd/agesa/f10/
+subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += ../../../../$(AGESA_ROOT)
diff --git a/src/mainboard/supermicro/h8qgi/OptionsIds.h b/src/mainboard/supermicro/h8qgi/OptionsIds.h
new file mode 100755
index 0000000..eb756df
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/OptionsIds.h
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/**
+ * @file
+ *
+ * IDS Option File
+ *
+ * This file is used to switch on/off IDS features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $
+ */
+#ifndef _OPTION_IDS_H_
+#define _OPTION_IDS_H_
+
+/**
+ *
+ * This file generates the defaults tables for the Integrated Debug Support
+ * Module. The documented build options are imported from a user controlled
+ * file for processing. The build options for the Integrated Debug Support
+ * Module are listed below:
+ *
+ * IDSOPT_IDS_ENABLED
+ * IDSOPT_ERROR_TRAP_ENABLED
+ * IDSOPT_CONTROL_ENABLED
+ * IDSOPT_TRACING_ENABLED
+ * IDSOPT_PERF_ANALYSIS
+ * IDSOPT_ASSERT_ENABLED
+ * IDS_DEBUG_PORT
+ * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+ *
+ **/
+
+#define IDSOPT_IDS_ENABLED TRUE
+//#define IDSOPT_CONTROL_ENABLED TRUE
+#define IDSOPT_TRACING_ENABLED TRUE
+//#define IDSOPT_PERF_ANALYSIS TRUE
+#define IDSOPT_ASSERT_ENABLED TRUE
+//#undef IDSOPT_DEBUG_ENABLED
+//#define IDSOPT_DEBUG_ENABLED FALSE
+//#undef IDSOPT_HOST_SIMNOW
+//#define IDSOPT_HOST_SIMNOW FALSE
+//#undef IDSOPT_HOST_HDT
+//#define IDSOPT_HOST_HDT FALSE
+//#define IDS_DEBUG_PORT 0x80
+
+#endif
diff --git a/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl b/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl
new file mode 100755
index 0000000..5eca9cc
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This file defines the processor and performance state capability
+ * for each core in the system. It is included into the DSDT for each
+ * core. It assumes that each core of the system has the same performance
+ * characteristics.
+*/
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001)
+ {
+ Scope (\_PR) {
+ Processor(CPU0,0,0x808,0x06) {
+ #include "cpstate.asl"
+ }
+ Processor(CPU1,1,0x0,0x0) {
+ #include "cpstate.asl"
+ }
+ Processor(CPU2,2,0x0,0x0) {
+ #include "cpstate.asl"
+ }
+ Processor(CPU3,3,0x0,0x0) {
+ #include "cpstate.asl"
+ }
+ }
+*/
+ /* P-state support: The maximum number of P-states supported by the */
+ /* CPUs we'll use is 6. */
+ /* Get from AMI BIOS. */
+ Name(_PSS, Package(){
+ Package ()
+ {
+ 0x00000AF0,
+ 0x0000BF81,
+ 0x00000002,
+ 0x00000002,
+ 0x00000000,
+ 0x00000000
+ },
+
+ Package ()
+ {
+ 0x00000578,
+ 0x000076F2,
+ 0x00000002,
+ 0x00000002,
+ 0x00000001,
+ 0x00000001
+ }
+ })
+
+ Name(_PCT, Package(){
+ ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
+ ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
+ })
+
+ Method(_PPC, 0){
+ Return(0)
+ }
diff --git a/src/mainboard/supermicro/h8qgi/acpi/ide.asl b/src/mainboard/supermicro/h8qgi/acpi/ide.asl
new file mode 100755
index 0000000..c79c18c
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/acpi/ide.asl
@@ -0,0 +1,244 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+Scope (_SB) {
+ Device(PCI0) {
+ Device(IDEC) {
+ Name(_ADR, 0x00140001)
+ #include "ide.asl"
+ }
+ }
+}
+*/
+
+/* Some timing tables */
+Name(UDTT, Package(){ /* Udma timing table */
+ 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */
+})
+
+Name(MDTT, Package(){ /* MWDma timing table */
+ 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */
+})
+
+Name(POTT, Package(){ /* Pio timing table */
+ 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */
+})
+
+/* Some timing register value tables */
+Name(MDRT, Package(){ /* MWDma timing register table */
+ 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */
+})
+
+Name(PORT, Package(){
+ 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */
+})
+
+OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
+ Field(ICRG, AnyAcc, NoLock, Preserve)
+{
+ PPTS, 8, /* Primary PIO Slave Timing */
+ PPTM, 8, /* Primary PIO Master Timing */
+ OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */
+ PMTM, 8, /* Primary MWDMA Master Timing */
+ OFFSET(0x08), PPCR, 8, /* Primary PIO Control */
+ OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */
+ PPSM, 4, /* Primary PIO slave Mode */
+ OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */
+ OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */
+ PDSM, 4, /* Primary UltraDMA Mode */
+}
+
+Method(GTTM, 1) /* get total time*/
+{
+ Store(And(Arg0, 0x0F), Local0) /* Recovery Width */
+ Increment(Local0)
+ Store(ShiftRight(Arg0, 4), Local1) /* Command Width */
+ Increment(Local1)
+ Return(Multiply(30, Add(Local0, Local1)))
+}
+
+Device(PRID)
+{
+ Name (_ADR, Zero)
+ Method(_GTM, 0)
+ {
+ NAME(OTBF, Buffer(20) { /* out buffer */
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+ })
+
+ CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */
+ CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */
+ CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */
+ CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
+ CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
+
+ /* Just return if the channel is disabled */
+ If(And(PPCR, 0x01)) { /* primary PIO control */
+ Return(OTBF)
+ }
+
+ /* Always tell them independent timing available and IOChannelReady used on both drives */
+ Or(BFFG, 0x1A, BFFG)
+
+ Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */
+ Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */
+
+ If(And(PDCR, 0x01)) { /* It's under UDMA mode */
+ Or(BFFG, 0x01, BFFG)
+ Store(DerefOf(Index(UDTT, PDMM)), DSD0)
+ }
+ Else {
+ Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */
+ }
+
+ If(And(PDCR, 0x02)) { /* It's under UDMA mode */
+ Or(BFFG, 0x04, BFFG)
+ Store(DerefOf(Index(UDTT, PDSM)), DSD1)
+ }
+ Else {
+ Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */
+ }
+
+ Return(OTBF) /* out buffer */
+ } /* End Method(_GTM) */
+
+ Method(_STM, 3, NotSerialized)
+ {
+ NAME(INBF, Buffer(20) { /* in buffer */
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+ })
+
+ CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */
+ CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */
+ CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */
+ CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
+ CreateDwordField(INBF, 16, BFFG) /*buffer flag */
+
+ Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
+ Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
+ Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
+ Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
+
+ Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
+ Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
+
+ If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */
+ Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
+ Divide(Local0, 7, PDMM,)
+ Or(PDCR, 0x01, PDCR)
+ }
+ Else {
+ If(LNotEqual(DSD0, 0xFFFFFFFF)) {
+ Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
+ Store(DerefOf(Index(MDRT, Local0)), PMTM)
+ }
+ }
+
+ If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */
+ Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
+ Divide(Local0, 7, PDSM,)
+ Or(PDCR, 0x02, PDCR)
+ }
+ Else {
+ If(LNotEqual(DSD1, 0xFFFFFFFF)) {
+ Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
+ Store(DerefOf(Index(MDRT, Local0)), PMTS)
+ }
+ }
+ /* Return(INBF) */
+ } /*End Method(_STM) */
+ Device(MST)
+ {
+ Name(_ADR, 0)
+ Method(_GTF) {
+ Name(CMBF, Buffer(21) {
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+ })
+ CreateByteField(CMBF, 1, POMD)
+ CreateByteField(CMBF, 8, DMMD)
+ CreateByteField(CMBF, 5, CMDA)
+ CreateByteField(CMBF, 12, CMDB)
+ CreateByteField(CMBF, 19, CMDC)
+
+ Store(0xA0, CMDA)
+ Store(0xA0, CMDB)
+ Store(0xA0, CMDC)
+
+ Or(PPMM, 0x08, POMD)
+
+ If(And(PDCR, 0x01)) {
+ Or(PDMM, 0x40, DMMD)
+ }
+ Else {
+ Store(Match
+ (MDTT, MLE, GTTM(PMTM),
+ MTR, 0, 0), Local0)
+ If(LLess(Local0, 3)) {
+ Or(0x20, Local0, DMMD)
+ }
+ }
+ Return(CMBF)
+ }
+ } /* End Device(MST) */
+
+ Device(SLAV)
+ {
+ Name(_ADR, 1)
+ Method(_GTF) {
+ Name(CMBF, Buffer(21) {
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+ })
+ CreateByteField(CMBF, 1, POMD)
+ CreateByteField(CMBF, 8, DMMD)
+ CreateByteField(CMBF, 5, CMDA)
+ CreateByteField(CMBF, 12, CMDB)
+ CreateByteField(CMBF, 19, CMDC)
+
+ Store(0xB0, CMDA)
+ Store(0xB0, CMDB)
+ Store(0xB0, CMDC)
+
+ Or(PPSM, 0x08, POMD)
+
+ If(And(PDCR, 0x02)) {
+ Or(PDSM, 0x40, DMMD)
+ }
+ Else {
+ Store(Match
+ (MDTT, MLE, GTTM(PMTS),
+ MTR, 0, 0), Local0)
+ If(LLess(Local0, 3)) {
+ Or(0x20, Local0, DMMD)
+ }
+ }
+ Return(CMBF)
+ }
+ } /* End Device(SLAV) */
+}
diff --git a/src/mainboard/supermicro/h8qgi/acpi/routing.asl b/src/mainboard/supermicro/h8qgi/acpi/routing.asl
new file mode 100755
index 0000000..8bc06f6
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/acpi/routing.asl
@@ -0,0 +1,222 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+ )
+ {
+ #include "routing.asl"
+ }
+*/
+
+/* Routing is in System Bus scope */
+Scope(\_SB) {
+ Name(PR0, Package(){
+ /* NB devices */
+ /* Bus 0, Dev 0 - SR5650 HT */
+ Package() { 0xFFFF, Zero, INTA, Zero },
+
+ /* Bus 0, Dev 1 - CLKCONFIG */
+
+ /* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */
+ Package() {0x0002FFFF, 0, INTE, 0 },
+
+ /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+
+ /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+ Package() {0x0004FFFF, 0, INTE, 0 },
+
+ /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+
+ /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
+
+ /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
+
+ /* Bus 0, Dev 8 - Southbridge port (normally hidden) */
+
+ /* Bus 0, Dev 9 - PCIe Bridge */
+
+ /* Bus 0, Dev a - PCIe Bridge */
+
+ /* Bus 0, Dev b - PCIe Bridge */
+ Package() {0x000BFFFF, 0, INTG, 0 },
+
+ /* Bus 0, Dev c - PCIe Bridge */
+ Package() {0x000CFFFF, 0, INTG, 0 },
+
+ /* Bus 0, Dev d - PCIe Bridge for Intel 82576 Giga NIC*/
+ Package() {0x000DFFFF, 0, INTG, 0 },
+
+ /* SB devices */
+ /* Bus 0, Dev 17 - SATA controller */
+ Package() {0x0011FFFF, 0, INTG, 0 },
+
+ /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
+ * EHCI, dev 18, 19 func 2 */
+ Package() {0x0012FFFF, 0, INTA, 0 },
+ Package() {0x0012FFFF, 1, INTB, 0 },
+ Package() {0x0012FFFF, 2, INTC, 0 },
+ Package() {0x0012FFFF, 3, INTD, 0 },
+
+ Package() {0x0013FFFF, 0, INTC, 0 },
+ Package() {0x0013FFFF, 1, INTD, 0 },
+ Package() {0x0013FFFF, 2, INTA, 0 },
+ Package() {0x0013FFFF, 2, INTB, 0 },
+
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
+ Package(){0x0014FFFF, 0, INTA, 0 },
+ Package(){0x0014FFFF, 1, INTB, 0 },
+ Package(){0x0014FFFF, 2, INTC, 0 },
+ Package(){0x0014FFFF, 3, INTD, 0 },
+ })
+
+ Name(APR0, Package(){
+ /* NB devices in APIC mode */
+ /* Bus 0, Dev 0 - SR5650 HT */
+ Package() { 0xFFFF, Zero, Zero, 16 },
+
+ /* Bus 0, Dev 1 - CLKCONFIG */
+
+ /* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot (GFX0) */
+ Package() {0x0002FFFF, 0, 0, 0x34 },
+
+ /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+
+ /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+ Package() {0x0004FFFF, 0, 0, 0x34 },
+
+ /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+
+ /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
+
+ /* Bus 0, Dev 7 - PCIe Bridge */
+
+ /* Bus 0, Dev 8 - Southbridge port (normally hidden) */
+
+ /* Bus 0, Dev 9 - PCIe Bridge */
+
+ /* Bus 0, Dev A - PCIe Bridge */
+
+ /* Bus 0, Dev B - PCIe Bridge */
+ Package() {0x000BFFFF, 0, 0, 0x36 },
+
+ /* Bus 0, Dev C - PCIe Bridge */
+ Package() {0x000CFFFF, 0, 0, 0x36 },
+
+ /* Bus 0, Dev D - PCIe Bridge For Intel 82576 Giga NIC*/
+ Package() {0x000DFFFF, 0, 0, 0x36 },
+
+ /* SB devices in APIC mode */
+ /* Bus 0, Dev 17 - SATA controller */
+ Package() {0x0011FFFF, 0, 0, 0x16 },
+
+ /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
+ * EHCI, dev 18, 19 func 2 */
+ Package( ){0x0012FFFF, 0, 0, 16 },
+ Package() {0x0012FFFF, 1, 0, 17 },
+ Package() {0x0012FFFF, 2, 0, 18 },
+ Package() {0x0012FFFF, 3, 0, 19 },
+
+ Package() {0x0013FFFF, 0, 0, 18 },
+ Package() {0x0013FFFF, 1, 0, 19 },
+ Package() {0x0013FFFF, 2, 0, 16 },
+ Package() {0x0013FFFF, 3, 0, 17 },
+
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
+ Package() {0x0014FFFF, 0, 0, 16 },
+ Package() {0x0014FFFF, 1, 0, 17 },
+ Package() {0x0014FFFF, 2, 0, 18 },
+ Package() {0x0014FFFF, 3, 0, 19 },
+ })
+
+ Name(PS2, Package(){
+ /* The external GFX - Hooked to PCIe slot 4 */
+ Package() {0x0000FFFF, 0, INTC, 0 },
+ Package() {0x0000FFFF, 1, INTD, 0 },
+ Package() {0x0000FFFF, 2, INTA, 0 },
+ Package() {0x0000FFFF, 3, INTB, 0 },
+ })
+ Name(APS2, Package(){
+ /* The external GFX - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, 0, 0x18 },
+ Package(){0x0000FFFF, 1, 0, 0x19 },
+ Package(){0x0000FFFF, 2, 0, 0x1A },
+ Package(){0x0000FFFF, 3, 0, 0x1B },
+ })
+
+ Name(PS4, Package(){
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+ })
+ Name(APS4, Package(){
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, 0, 0x2C },
+ Package(){0x0000FFFF, 1, 0, 0x2D },
+ Package(){0x0000FFFF, 2, 0, 0x2E },
+ Package(){0x0000FFFF, 3, 0, 0x2F },
+ })
+
+ Name(PSb, Package(){
+ /* PCIe slot - Hooked to PCIe slot 11 */
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+ })
+ Name(APSb, Package(){
+ /* PCIe slot - Hooked to PCIe */
+ Package(){0x0000FFFF, 0, 0, 0x20 },
+ Package(){0x0000FFFF, 1, 0, 0x21 },
+ Package(){0x0000FFFF, 2, 0, 0x22 },
+ Package(){0x0000FFFF, 3, 0, 0x23 },
+ })
+
+ Name(PSc, Package(){
+ /* PCIe slot - Hooked to PCIe slot 12 */
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+ })
+ Name(APSc, Package(){
+ /* PCIe slot - Hooked to PCIe */
+ Package(){0x0000FFFF, 0, 0, 0x24 },
+ Package(){0x0000FFFF, 1, 0, 0x25 },
+ Package(){0x0000FFFF, 2, 0, 0x26 },
+ Package(){0x0000FFFF, 3, 0, 0x27 },
+ })
+
+ Name(PSd, Package(){
+ /* PCIe slot - Hooked to PCIe slot 13 */
+ Package(){0x0000FFFF, 0, INTB, 0 },
+ Package(){0x0000FFFF, 1, INTC, 0 },
+ Package(){0x0000FFFF, 2, INTD, 0 },
+ Package(){0x0000FFFF, 3, INTA, 0 },
+ })
+ Name(APSd, Package(){
+ /* PCIe slot - Hooked to PCIe */
+ Package(){0x0000FFFF, 0, 0, 0x28 },
+ Package(){0x0000FFFF, 1, 0, 0x29 },
+ Package(){0x0000FFFF, 2, 0, 0x2A },
+ Package(){0x0000FFFF, 3, 0, 0x2B },
+ })
+}
diff --git a/src/mainboard/supermicro/h8qgi/acpi/sata.asl b/src/mainboard/supermicro/h8qgi/acpi/sata.asl
new file mode 100755
index 0000000..bd4acf0
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/acpi/sata.asl
@@ -0,0 +1,149 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* simple name description */
+
+/*
+Scope (_SB) {
+ Device(PCI0) {
+ Device(SATA) {
+ Name(_ADR, 0x00110000)
+ #include "sata.asl"
+ }
+ }
+}
+*/
+
+Name(STTM, Buffer(20) {
+ 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+ 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+ 0x1f, 0x00, 0x00, 0x00
+})
+
+/* Start by clearing the PhyRdyChg bits */
+Method(_INI) {
+ \_GPE._L1F()
+}
+
+Device(PMRY)
+{
+ Name(_ADR, 0)
+ Method(_GTM, 0x0, NotSerialized) {
+ Return(STTM)
+ }
+ Method(_STM, 0x3, NotSerialized) {}
+
+ Device(PMST) {
+ Name(_ADR, 0)
+ Method(_STA,0) {
+ if (LGreater(P0IS,0)) {
+ return (0x0F) /* sata is visible */
+ }
+ else {
+ return (0x00) /* sata is missing */
+ }
+ }
+ }/* end of PMST */
+
+ Device(PSLA)
+ {
+ Name(_ADR, 1)
+ Method(_STA,0) {
+ if (LGreater(P1IS,0)) {
+ return (0x0F) /* sata is visible */
+ }
+ else {
+ return (0x00) /* sata is missing */
+ }
+ }
+ } /* end of PSLA */
+} /* end of PMRY */
+
+
+Device(SEDY)
+{
+ Name(_ADR, 1) /* IDE Scondary Channel */
+ Method(_GTM, 0x0, NotSerialized) {
+ Return(STTM)
+ }
+ Method(_STM, 0x3, NotSerialized) {}
+
+ Device(SMST)
+ {
+ Name(_ADR, 0)
+ Method(_STA,0) {
+ if (LGreater(P2IS,0)) {
+ return (0x0F) /* sata is visible */
+ }
+ else {
+ return (0x00) /* sata is missing */
+ }
+ }
+ } /* end of SMST */
+
+ Device(SSLA)
+ {
+ Name(_ADR, 1)
+ Method(_STA,0) {
+ if (LGreater(P3IS,0)) {
+ return (0x0F) /* sata is visible */
+ }
+ else {
+ return (0x00) /* sata is missing */
+ }
+ }
+ } /* end of SSLA */
+} /* end of SEDY */
+
+/* SATA Hot Plug Support */
+Scope(\_GPE) {
+ Method(_L1F,0x0,NotSerialized) {
+ if (\_SB.P0PR) {
+ if (LGreater(\_SB.P0IS,0)) {
+ sleep(32)
+ }
+ Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+ store(one, \_SB.P0PR)
+ }
+
+ if (\_SB.P1PR) {
+ if (LGreater(\_SB.P1IS,0)) {
+ sleep(32)
+ }
+ Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+ store(one, \_SB.P1PR)
+ }
+
+ if (\_SB.P2PR) {
+ if (LGreater(\_SB.P2IS,0)) {
+ sleep(32)
+ }
+ Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+ store(one, \_SB.P2PR)
+ }
+
+ if (\_SB.P3PR) {
+ if (LGreater(\_SB.P3IS,0)) {
+ sleep(32)
+ }
+ Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+ store(one, \_SB.P3PR)
+ }
+ }
+}
diff --git a/src/mainboard/supermicro/h8qgi/acpi/usb.asl b/src/mainboard/supermicro/h8qgi/acpi/usb.asl
new file mode 100755
index 0000000..181d685
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/acpi/usb.asl
@@ -0,0 +1,161 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* simple name description */
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+ )
+ {
+ #include "usb.asl"
+ }
+*/
+Method(UCOC, 0) {
+ Sleep(20)
+ Store(0x13,CMTI)
+ Store(0,GPSL)
+}
+
+/* USB Port 0 overcurrent uses Gpm 0 */
+If(LLessEqual(UOM0,9)) {
+ Scope (\_GPE) {
+ Method (_L13) {
+ UCOC()
+ if(LEqual(GPB0,PLC0)) {
+ Not(PLC0,PLC0)
+ Store(PLC0, \_SB.PT0D)
+ }
+ }
+ }
+}
+
+/* USB Port 1 overcurrent uses Gpm 1 */
+If (LLessEqual(UOM1,9)) {
+ Scope (\_GPE) {
+ Method (_L14) {
+ UCOC()
+ if (LEqual(GPB1,PLC1)) {
+ Not(PLC1,PLC1)
+ Store(PLC1, \_SB.PT1D)
+ }
+ }
+ }
+}
+
+/* USB Port 2 overcurrent uses Gpm 2 */
+If (LLessEqual(UOM2,9)) {
+ Scope (\_GPE) {
+ Method (_L15) {
+ UCOC()
+ if (LEqual(GPB2,PLC2)) {
+ Not(PLC2,PLC2)
+ Store(PLC2, \_SB.PT2D)
+ }
+ }
+ }
+}
+
+/* USB Port 3 overcurrent uses Gpm 3 */
+If (LLessEqual(UOM3,9)) {
+ Scope (\_GPE) {
+ Method (_L16) {
+ UCOC()
+ if (LEqual(GPB3,PLC3)) {
+ Not(PLC3,PLC3)
+ Store(PLC3, \_SB.PT3D)
+ }
+ }
+ }
+}
+
+/* USB Port 4 overcurrent uses Gpm 4 */
+If (LLessEqual(UOM4,9)) {
+ Scope (\_GPE) {
+ Method (_L19) {
+ UCOC()
+ if (LEqual(GPB4,PLC4)) {
+ Not(PLC4,PLC4)
+ Store(PLC4, \_SB.PT4D)
+ }
+ }
+ }
+}
+
+/* USB Port 5 overcurrent uses Gpm 5 */
+If (LLessEqual(UOM5,9)) {
+ Scope (\_GPE) {
+ Method (_L1A) {
+ UCOC()
+ if (LEqual(GPB5,PLC5)) {
+ Not(PLC5,PLC5)
+ Store(PLC5, \_SB.PT5D)
+ }
+ }
+ }
+}
+
+/* USB Port 6 overcurrent uses Gpm 6 */
+If (LLessEqual(UOM6,9)) {
+ Scope (\_GPE) {
+ /* Method (_L1C) { */
+ Method (_L06) {
+ UCOC()
+ if (LEqual(GPB6,PLC6)) {
+ Not(PLC6,PLC6)
+ Store(PLC6, \_SB.PT6D)
+ }
+ }
+ }
+}
+
+/* USB Port 7 overcurrent uses Gpm 7 */
+If (LLessEqual(UOM7,9)) {
+ Scope (\_GPE) {
+ /* Method (_L1D) { */
+ Method (_L07) {
+ UCOC()
+ if (LEqual(GPB7,PLC7)) {
+ Not(PLC7,PLC7)
+ Store(PLC7, \_SB.PT7D)
+ }
+ }
+ }
+}
+
+/* USB Port 8 overcurrent uses Gpm 8 */
+If (LLessEqual(UOM8,9)) {
+ Scope (\_GPE) {
+ Method (_L17) {
+ if (LEqual(G8IS,PLC8)) {
+ Not(PLC8,PLC8)
+ Store(PLC8, \_SB.PT8D)
+ }
+ }
+ }
+}
+
+/* USB Port 9 overcurrent uses Gpm 9 */
+If (LLessEqual(UOM9,9)) {
+ Scope (\_GPE) {
+ Method (_L0E) {
+ if (LEqual(G9IS,0)) {
+ Store(1,\_SB.PT9D)
+ }
+ }
+ }
+}
diff --git a/src/mainboard/supermicro/h8qgi/acpi_tables.c b/src/mainboard/supermicro/h8qgi/acpi_tables.c
new file mode 100755
index 0000000..b8ce0b0
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/acpi_tables.c
@@ -0,0 +1,295 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/io.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <cpu/amd/amdfam10_sysconf.h>
+#include "agesawrapper.h"
+
+#define DUMP_ACPI_TABLES 0
+
+#if DUMP_ACPI_TABLES == 1
+static void dump_mem(u32 start, u32 end)
+{
+
+ u32 i;
+ print_debug("dump_mem:");
+ for (i = start; i < end; i++) {
+ if ((i & 0xf) == 0) {
+ printk(BIOS_DEBUG, "\n%08x:", i);
+ }
+ printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
+ }
+ print_debug("\n");
+}
+#endif
+
+extern const unsigned char AmlCode[];
+extern const unsigned char AmlCode_ssdt[];
+
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+ /* Just a dummy */
+ return current;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ device_t dev;
+ u32 dword;
+ u32 gsi_base = 0;
+ u32 apicid_sp5100;
+ u32 apicid_sr5650;
+
+ /*
+ * AGESA v5 Apply apic enumeration rules
+ * For systems with >= 16 APICs, put the IO-APICs at 0..n and
+ * put the local-APICs at m..z
+ * For systems with < 16 APICs, put the Local-APICs at 0..n and
+ * put the IO-APICs at (n + 1)..z
+ */
+#if CONFIG_MAX_CPUS >= 16
+ apicid_sp5100 = 0x0;
+#else
+ apicid_sp5100 = CONFIG_MAX_CPUS + 1
+#endif
+ apicid_sr5650 = apicid_sp5100 + 1;
+
+ /* create all subtables for processors */
+ current = acpi_create_madt_lapics(current);
+
+ /* Write sp5100 IOAPIC, only one */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ apicid_sp5100,
+ IO_APIC_ADDR,
+ 0
+ );
+
+ /* IOAPIC on rs5690 */
+ gsi_base += IO_APIC_INTERRUPTS; /* SP5100 has 24 IOAPIC entries. */
+ dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+ if (dev) {
+ pci_write_config32(dev, 0xF8, 0x1);
+ dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ apicid_sr5650,
+ dword,
+ gsi_base
+ );
+ }
+
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current,
+ 0, //BUS
+ 0, //SOURCE
+ 2, //gsirq
+ 0 //flags
+ );
+
+ /* 0: mean bus 0--->ISA */
+ /* 0: PIC 0 */
+ /* 2: APIC 2 */
+ /* 5 mean: 0101 --> Edige-triggered, Active high */
+
+ /* create all subtables for processors */
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1);
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1);
+ /* 1: LINT1 connect to NMI */
+
+ return current;
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+ // Not implemented
+ return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+ /* No NUMA, no SRAT */
+ return current;
+}
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+ unsigned long current;
+ acpi_rsdp_t *rsdp;
+ acpi_rsdt_t *rsdt;
+ //acpi_hpet_t *hpet;
+ acpi_madt_t *madt;
+ acpi_srat_t *srat;
+ acpi_slit_t *slit;
+ acpi_fadt_t *fadt;
+ acpi_facs_t *facs;
+ acpi_header_t *dsdt;
+ //acpi_header_t *ssdt;
+
+ get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
+
+ /* Align ACPI tables to 16 bytes */
+ start = (start + 0x0f) & -0x10;
+ current = start;
+
+ printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
+
+ /* We need at least an RSDP and an RSDT Table */
+ rsdp = (acpi_rsdp_t *) current;
+ current += sizeof(acpi_rsdp_t);
+ rsdt = (acpi_rsdt_t *) current;
+ current += sizeof(acpi_rsdt_t);
+
+ /* clear all table memory */
+ memset((void *)start, 0, current - start);
+
+ acpi_write_rsdp(rsdp, rsdt, NULL);
+ acpi_write_rsdt(rsdt);
+
+ /* FACS */
+ printk(BIOS_DEBUG, "ACPI: * FACS\n");
+ facs = (acpi_facs_t *) current;
+ current += sizeof(acpi_facs_t);
+ acpi_create_facs(facs);
+
+ /* DSDT */
+ printk(BIOS_DEBUG, "ACPI: * DSDT\n");
+ dsdt = (acpi_header_t *)current;
+ memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+ current += dsdt->length;
+ memcpy(dsdt, &AmlCode, dsdt->length);
+ printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length);
+ /* FADT */
+ printk(BIOS_DEBUG, "ACPI: * FADT\n");
+ fadt = (acpi_fadt_t *) current;
+ current += sizeof(acpi_fadt_t);
+
+ acpi_create_fadt(fadt, facs, dsdt);
+ acpi_add_table(rsdp, fadt);
+
+ /*
+ * We explicitly add these tables later on:
+ */
+#ifdef UNUSED_CODE // Don't need HPET table. we have one in dsdt
+ current = ( current + 0x07) & -0x08;
+ printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current);
+ hpet = (acpi_hpet_t *) current;
+ current += sizeof(acpi_hpet_t);
+ acpi_create_hpet(hpet);
+ acpi_add_table(rsdp, hpet);
+#endif
+
+ /* If we want to use HPET Timers Linux wants an MADT */
+ current = ( current + 0x07) & -0x08;
+ printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current);
+ madt = (acpi_madt_t *) current;
+ acpi_create_madt(madt);
+ current += madt->header.length;
+ acpi_add_table(rsdp, madt);
+
+ /* SRAT */
+ current = ( current + 0x07) & -0x08;
+ printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current);
+ srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
+ if (srat != NULL) {
+ memcpy((void *)current, srat, srat->header.length);
+ srat = (acpi_srat_t *) current;
+ //acpi_create_srat(srat);
+ current += srat->header.length;
+ acpi_add_table(rsdp, srat);
+ }
+
+ /* SLIT */
+ current = ( current + 0x07) & -0x08;
+ printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current);
+ slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
+ if (slit != NULL) {
+ memcpy((void *)current, slit, slit->header.length);
+ slit = (acpi_slit_t *) current;
+ //acpi_create_slit(slit);
+ current += slit->header.length;
+ acpi_add_table(rsdp, slit);
+ }
+
+ /* SSDT */
+ /* NOTE: we not update_ssdt, so ssdt only contain initialize value from ssdt.asl */
+#ifdef UNUSED_CODE
+ current = ( current + 0x0f) & -0x10;
+ printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current);
+ ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
+ if (ssdt != NULL) {
+ memcpy(current, ssdt, ssdt->length);
+ ssdt = (acpi_header_t *) current;
+ current += ssdt->length;
+ }
+ else {
+ ssdt = (acpi_header_t *) current;
+ memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
+ current += ssdt->length;
+ memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
+ /* recalculate checksum */
+ ssdt->checksum = 0;
+ ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
+ }
+ acpi_add_table(rsdp,ssdt);
+
+ printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current);
+#endif
+
+ /* DSDT */
+ current = ( current + 0x07) & -0x08;
+ printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current);
+ dsdt = (acpi_header_t *)current; // it will used by fadt
+ memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+ current += dsdt->length;
+ memcpy(dsdt, &AmlCode, dsdt->length);
+ printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length);
+
+#if DUMP_ACPI_TABLES == 1
+ printk(BIOS_DEBUG, "rsdp\n");
+ dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
+
+ printk(BIOS_DEBUG, "rsdt\n");
+ dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
+
+ printk(BIOS_DEBUG, "madt\n");
+ dump_mem(madt, ((void *)madt) + madt->header.length);
+
+ printk(BIOS_DEBUG, "srat\n");
+ dump_mem(srat, ((void *)srat) + srat->header.length);
+
+ printk(BIOS_DEBUG, "slit\n");
+ dump_mem(slit, ((void *)slit) + slit->header.length);
+
+ printk(BIOS_DEBUG, "ssdt\n");
+ dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
+
+ printk(BIOS_DEBUG, "fadt\n");
+ dump_mem(fadt, ((void *)fadt) + fadt->header.length);
+#endif
+
+ printk(BIOS_INFO, "ACPI: done.\n");
+ return current;
+}
diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.c b/src/mainboard/supermicro/h8qgi/agesawrapper.c
new file mode 100755
index 0000000..186c708
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/agesawrapper.c
@@ -0,0 +1,1169 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*----------------------------------------------------------------------------------------
+ * M O D U L E S U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include "agesawrapper.h"
+#include "BiosCallOuts.h"
+#include "cpuRegisters.h"
+#include "cpuCacheInit.h"
+#include "cpuApicUtilities.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "Dispatcher.h"
+#include "cpuCacheInit.h"
+#include "amdlib.h"
+#include "platform_oem.h"
+#include "Filecode.h"
+#include "heapManager.h"
+#include <cpuFamilyTranslation.h> /* CPU_SPECIFIC_SERVICES */
+
+#define FILECODE UNASSIGNED_FILE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/* ACPI table pointers returned by AmdInitLate */
+VOID *DmiTable = NULL;
+VOID *AcpiPstate = NULL;
+VOID *AcpiSrat = NULL;
+VOID *AcpiSlit = NULL;
+
+VOID *AcpiWheaMce = NULL;
+VOID *AcpiWheaCmc = NULL;
+//VOID *AcpiAlib = NULL;
+
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S A N D S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * P R O T O T Y P E S O F L O C A L F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * E X P O R T E D F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------
+ * L O C A L F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+static UINT32 agesawrapper_amdinitcpuio(VOID)
+{
+ AGESA_STATUS Status;
+ UINT32 PciData;
+ PCI_ADDR PciAddress;
+ AMD_CONFIG_PARAMS StdHeader;
+ UINT32 nodes;
+ UINT32 node;
+ UINT32 sblink;
+ UINT32 i;
+
+ /* get the number of coherent nodes in the system */
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60);
+ LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ nodes = ((PciData >> 4) & 7) + 1; //NodeCnt[2:0]
+
+ /* Find out the Link ID of Node0 that connects to the
+ * Southbridge (system IO hub). e.g. family10 MCM Processor,
+ * sbLink is Processor0 Link2, internal Node0 Link3
+ */
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64);
+ LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ sblink = (PciData >> 8) & 3; //assume ganged
+
+ /* Enable MMIO on AMD CPU Address Map Controller for all nodes */
+ for (node = 0; node < nodes; node++) {
+ /* clear all MMIO Mapped Base/Limit Registers */
+ for (i = 0; i < 8; i++) {
+ PciData = 0x00000000;
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80 + i*8);
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84 + i*8);
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ }
+
+ /* clear all IO Space Base/Limit Registers */
+ for (i = 0; i < 4; i++) {
+ PciData = 0x00000000;
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4 + i*8);
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0 + i*8);
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ }
+
+ /* Set VGA Ram MMIO 0000A0000-0000BFFFF to Node0 sbLink */
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84);
+ PciData = 0x00000B00;
+ PciData |= sblink << 4;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80);
+ PciData = 0x00000A03;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+ /* Set F0000000-FFFFFFFF to Node0 sbLink. */
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x8C);
+ PciData = 0x00FFFF00;
+ PciData |= sblink << 4;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ PciData = 0x00F00000 | 0x03;
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x88);
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+ /* Set MMCONF space to Node0 sbLink with NP set.
+ * default E0000000-EFFFFFFF
+ * Just have all mmio set to non-posted,
+ * coreboot not implemente the range by range setting yet.
+ */
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xBC);
+ PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000);//1MB each bus
+ PciData = (PciData >> 8) & 0xFFFFFF00;
+ PciData |= 0x80; //NP
+ PciData |= sblink << 4;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xB8);
+ PciData = (PCIE_BASE_ADDRESS >> 8) | 0x03;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+
+ /* Start to set IO 0x9000-0xEFFF to Node0 sbLink with ISA&VGA set. */
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4);
+ PciData = 0x0000E000;
+ PciData |= sblink << 4;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0);
+ PciData = 0x00009033;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ }
+
+ Status = AGESA_SUCCESS;
+ return (UINT32)Status;
+}
+
+UINT32 agesawrapper_amdinitmmio(VOID)
+{
+ AGESA_STATUS Status;
+ UINT64 MsrReg;
+ AMD_CONFIG_PARAMS StdHeader;
+
+ /*
+ * Set the MMIO Configuration Base Address and Bus Range onto
+ * MMIO configuration base Address MSR register.
+ */
+ MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
+ LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
+
+ /*
+ * Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
+ */
+ LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader);
+ MsrReg = MsrReg | (1ULL << 46);
+ LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
+
+ /* Set ROM cache onto WP to decrease post time */
+ MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5;
+ LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
+ MsrReg = (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800;
+ LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
+
+ Status = AGESA_SUCCESS;
+ return (UINT32)Status;
+}
+
+UINT32 agesawrapper_amdinitreset(VOID)
+{
+ AGESA_STATUS status = AGESA_SUCCESS;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ AMD_RESET_PARAMS AmdResetParams;
+
+ LibAmdMemFill(&AmdParamStruct,
+ 0,
+ sizeof(AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ LibAmdMemFill(&AmdResetParams,
+ 0,
+ sizeof(AMD_RESET_PARAMS),
+ &(AmdResetParams.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
+ AmdParamStruct.AllocationMethod = ByHost;
+ AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
+ AmdParamStruct.NewStructPtr = &AmdResetParams;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = NULL;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+ AmdCreateStruct(&AmdParamStruct);
+ AmdResetParams.HtConfig.Depth = 0;
+
+ //MARG34PI disabled AGESA_ENTRY_INIT_RESET by default
+ //but we need to call AmdCreateStruct to call HeapManagerInit, or the event log not work
+#if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE)
+ status = AmdInitReset((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
+#endif
+ if (status != AGESA_SUCCESS)
+ agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
+ AmdReleaseStruct(&AmdParamStruct);
+
+ return (UINT32)status;
+}
+
+UINT32 agesawrapper_amdinitearly(VOID)
+{
+ AGESA_STATUS status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
+ UINT32 TscRateInMhz;
+ CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+ LibAmdMemFill(&AmdParamStruct,
+ 0,
+ sizeof(AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
+ AmdParamStruct.AllocationMethod = PreMemHeap;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+ AmdCreateStruct(&AmdParamStruct);
+
+ AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
+ OemCustomizeInitEarly(AmdEarlyParamsPtr);
+
+ status = AmdInitEarly((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
+ if (status != AGESA_SUCCESS)
+ agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
+
+ GetCpuServicesOfCurrentCore(&FamilySpecificServices, &AmdParamStruct.StdHeader);
+ FamilySpecificServices->GetTscRate(FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader);
+ printk(BIOS_DEBUG, "BSP Frequency: %luMHz\n", TscRateInMhz);
+
+ AmdReleaseStruct(&AmdParamStruct);
+ return (UINT32)status;
+}
+
+UINT32 agesawrapper_amdinitpost(VOID)
+{
+ AGESA_STATUS status;
+ UINT16 i;
+ UINT32 *HeadPtr;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ BIOS_HEAP_MANAGER *BiosManagerPtr;
+ UINT32 TscRateInMhz;
+ CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+ LibAmdMemFill(&AmdParamStruct,
+ 0,
+ sizeof(AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
+ AmdParamStruct.AllocationMethod = PreMemHeap;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+ AmdCreateStruct(&AmdParamStruct);
+ status = AmdInitPost((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
+ if (status != AGESA_SUCCESS)
+ agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
+ AmdReleaseStruct(&AmdParamStruct);
+
+ /* Initialize heap space */
+ BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
+
+ HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof(BIOS_HEAP_MANAGER));
+ for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof(BIOS_HEAP_MANAGER)/4)); i++) {
+ *HeadPtr = 0x00000000;
+ HeadPtr++;
+ }
+ BiosManagerPtr->StartOfAllocatedNodes = 0;
+ BiosManagerPtr->StartOfFreedNodes = 0;
+
+ GetCpuServicesOfCurrentCore (&FamilySpecificServices, &AmdParamStruct.StdHeader);
+ FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader);
+ printk(BIOS_DEBUG, "BSP Frequency: %luMHz\n", TscRateInMhz);
+
+ return (UINT32)status;
+}
+
+UINT32 agesawrapper_amdinitenv(VOID)
+{
+ AGESA_STATUS status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+
+ LibAmdMemFill(&AmdParamStruct,
+ 0,
+ sizeof(AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
+ AmdParamStruct.AllocationMethod = PostMemDram;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+ AmdCreateStruct(&AmdParamStruct);
+ status = AmdInitEnv((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
+ if (status != AGESA_SUCCESS)
+ agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
+
+ AmdReleaseStruct(&AmdParamStruct);
+ return (UINT32)status;
+}
+
+VOID * agesawrapper_getlateinitptr(int pick)
+{
+ switch (pick) {
+ case PICK_DMI:
+ return DmiTable;
+
+ case PICK_PSTATE:
+ return AcpiPstate;
+
+ case PICK_SRAT:
+ return AcpiSrat;
+
+ case PICK_SLIT:
+ return AcpiSlit;
+ case PICK_WHEA_MCE:
+ return AcpiWheaMce;
+ case PICK_WHEA_CMC:
+ return AcpiWheaCmc;
+/*
+ case PICK_ALIB:
+ return AcpiAlib;
+*/
+ default:
+ return NULL;
+ }
+
+ return NULL;
+}
+
+UINT32 agesawrapper_amdinitmid(VOID)
+{
+ AGESA_STATUS status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+
+ /* Enable MMIO on AMD CPU Address Map Controller */
+ agesawrapper_amdinitcpuio();
+
+ LibAmdMemFill(&AmdParamStruct,
+ 0,
+ sizeof(AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
+ AmdParamStruct.AllocationMethod = PostMemDram;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+ AmdCreateStruct(&AmdParamStruct);
+ status = AmdInitMid((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
+ if (status != AGESA_SUCCESS)
+ agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
+ AmdReleaseStruct(&AmdParamStruct);
+
+ return (UINT32)status;
+}
+
+UINT32 agesawrapper_amdinitlate(VOID)
+{
+ AGESA_STATUS Status;
+ AMD_LATE_PARAMS AmdLateParams;
+
+ LibAmdMemFill(&AmdLateParams,
+ 0,
+ sizeof(AMD_LATE_PARAMS),
+ &(AmdLateParams.StdHeader));
+
+ AmdLateParams.StdHeader.AltImageBasePtr = 0;
+ AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdLateParams.StdHeader.Func = 0;
+ AmdLateParams.StdHeader.ImageBasePtr = 0;
+ AmdLateParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
+
+ Status = AmdInitLate(&AmdLateParams);
+ if (Status != AGESA_SUCCESS) {
+ agesawrapper_amdreadeventlog(AmdLateParams.StdHeader.HeapStatus);
+ ASSERT(Status == AGESA_SUCCESS);
+ }
+
+ DmiTable = AmdLateParams.DmiTable;
+ AcpiPstate = AmdLateParams.AcpiPState;
+ AcpiSrat = AmdLateParams.AcpiSrat;
+ AcpiSlit = AmdLateParams.AcpiSlit;
+
+ AcpiWheaMce = AmdLateParams.AcpiWheaMce;
+ AcpiWheaCmc = AmdLateParams.AcpiWheaCmc;
+ //AcpiAlib = AmdLateParams.AcpiAlib;
+
+ return (UINT32)Status;
+}
+
+/**
+ * @param[in] UINTN ApicIdOfCore,
+ * @param[in] AP_EXE_PARAMS *LaunchApParams
+ */
+UINT32 agesawrapper_amdlaterunaptask(UINT32 Data, VOID *ConfigPtr)
+{
+ AGESA_STATUS Status;
+ AMD_LATE_PARAMS AmdLateParams;
+
+ LibAmdMemFill(&AmdLateParams,
+ 0,
+ sizeof(AMD_LATE_PARAMS),
+ &(AmdLateParams.StdHeader));
+
+ AmdLateParams.StdHeader.AltImageBasePtr = 0;
+ AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdLateParams.StdHeader.Func = 0;
+ AmdLateParams.StdHeader.ImageBasePtr = 0;
+ AmdLateParams.StdHeader.HeapStatus = HEAP_TEMP_MEM;
+
+ printk(BIOS_DEBUG, "AmdLateRunApTask on Core: %x\n", (uint32_t)Data);
+ Status = AmdLateRunApTask((AP_EXE_PARAMS *)ConfigPtr);
+ if (Status != AGESA_SUCCESS) {
+ agesawrapper_amdreadeventlog(AmdLateParams.StdHeader.HeapStatus);
+ ASSERT(Status <= AGESA_UNSUPPORTED);
+ }
+
+ DmiTable = AmdLateParams.DmiTable;
+ AcpiPstate = AmdLateParams.AcpiPState;
+ AcpiSrat = AmdLateParams.AcpiSrat;
+ AcpiSlit = AmdLateParams.AcpiSlit;
+
+ AcpiWheaMce = AmdLateParams.AcpiWheaMce;
+ AcpiWheaCmc = AmdLateParams.AcpiWheaCmc;
+ // AcpiAlib = AmdLateParams.AcpiAlib;
+
+ return (UINT32)Status;
+}
+
+/**
+ *
+ */
+static void agesa_bound_check(EVENT_PARAMS *event)
+{
+ switch (event->EventInfo) {
+ case CPU_ERROR_HEAP_IS_FULL:
+ printk(BIOS_DEBUG, "Heap allocation for specified buffer handle failed as heap is full\n");
+ break;
+
+ case CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED:
+ printk(BIOS_DEBUG, "Allocation incomplete as buffer has previously been allocated\n");
+ break;
+
+ case CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT:
+ printk(BIOS_DEBUG, "Unable to locate buffer handle or deallocate heap as buffer handle cannot be located\n");
+ break;
+
+ case CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT:
+ printk(BIOS_DEBUG, "Unable to locate pointer to the heap buffer\n");
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ *
+ */
+static void agesa_alert(EVENT_PARAMS *event)
+{
+ switch (event->EventInfo) {
+ case MEM_ALERT_USER_TMG_MODE_OVERRULED:
+ printk(BIOS_DEBUG, "Socket %lx Dct %lx Channel %lx "
+ "TIMING_MODE_SPECIFIC is requested but can not be applied to current configurations.\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case MEM_ALERT_ORG_MISMATCH_DIMM:
+ printk(BIOS_DEBUG, "Socket %lx Dct %lx Channel %lx "
+ "DIMM organization miss-match\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case MEM_ALERT_BK_INT_DIS:
+ printk(BIOS_DEBUG, "Socket %lx Dct %lx Channel %lx "
+ "Bank interleaving disable for internal issue\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case CPU_EVENT_BIST_ERROR:
+ printk(BIOS_DEBUG, "BIST error: %lx reported on Socket %lx Core %lx\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case HT_EVENT_HW_SYNCFLOOD:
+ printk(BIOS_DEBUG, "HT_EVENT_DATA_HW_SYNCFLOOD error on Socket %lx Link %lx\n",
+ event->DataParam1,
+ event->DataParam2);
+ break;
+
+ case HT_EVENT_HW_HTCRC:
+ printk(BIOS_DEBUG, "HT_EVENT_HW_HTCRC error on Socket %lx Link %lx Lanemask:%lx\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ *
+ */
+static void agesa_warning(EVENT_PARAMS *event)
+{
+/*
+ if (event->EventInfo == CPU_EVENT_STACK_REENTRY) {
+ printk(BIOS_DEBUG,
+ "The stack has already been enabled and this is a
+ redundant invocation of AMD_ENABLE_STACK. There is no event logged and
+ no data values. The event sub-class is returned along with the status code\n");
+ return;
+ }
+*/
+
+ switch (event->EventInfo >> 24) {
+ case 0x04:
+ printk(BIOS_DEBUG, "Memory: Socket %lx Dct %lx Channel%lx ",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case 0x08:
+ printk(BIOS_DEBUG, "Processor: ");
+ break;
+
+ case 0x10:
+ printk(BIOS_DEBUG, "Hyper Transport: ");
+ break;
+
+ default:
+ break;
+ }
+
+ switch (event->EventInfo) {
+ case MEM_WARNING_UNSUPPORTED_QRDIMM:
+ printk(BIOS_DEBUG, "QR DIMMs detected but not supported\n");
+ break;
+
+ case MEM_WARNING_UNSUPPORTED_UDIMM:
+ printk(BIOS_DEBUG, "Unbuffered DIMMs detected but not supported\n");
+ break;
+
+ case MEM_WARNING_UNSUPPORTED_SODIMM:
+ printk(BIOS_DEBUG, "SO-DIMMs detected but not supported");
+ break;
+
+ case MEM_WARNING_UNSUPPORTED_X4DIMM:
+ printk(BIOS_DEBUG, "x4 DIMMs detected but not supported");
+ break;
+
+ case MEM_WARNING_UNSUPPORTED_RDIMM:
+ printk(BIOS_DEBUG, "Registered DIMMs detected but not supported");
+ break;
+
+/*
+ case MEM_WARNING_UNSUPPORTED_LRDIMM:
+ printk(BIOS_DEBUG, "Load Reduced DIMMs detected but not supported");
+ break;
+*/
+
+ case MEM_WARNING_NO_SPDTRC_FOUND:
+ printk(BIOS_DEBUG, "NO_SPDTRC_FOUND");
+ break;
+
+ case MEM_WARNING_EMP_NOT_SUPPORTED:
+ printk(BIOS_DEBUG, "Processor is not capable for EMP");//
+ break;
+
+ case MEM_WARNING_EMP_CONFLICT:
+ printk(BIOS_DEBUG, "EMP cannot be enabled if channel interleaving bank interleaving, or bank swizzle is enabled\n");//
+ break;
+
+ case MEM_WARNING_EMP_NOT_ENABLED:
+ printk(BIOS_DEBUG, "Memory size is not power of two\n");//
+ break;
+
+ case MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED:
+ printk(BIOS_DEBUG, "MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED\n");
+ break;
+
+ case MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED:
+ printk(BIOS_DEBUG, "MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED\n");
+ break;
+
+ case MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED:
+ printk(BIOS_DEBUG, "MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED\n");
+ break;
+
+ case MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED:
+ printk(BIOS_DEBUG, "MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED\n");
+ break;
+
+ case MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED:
+ printk(BIOS_DEBUG, "MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED\n");
+ break;
+
+/*
+ case MEM_WARNING_INITIAL_DDR3VOLT_NONZERO:
+ printk(BIOS_DEBUG, "MEM_WARNING_INITIAL_DDR3VOLT_NONZERO\n");
+ break;
+
+ case MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO:
+ printk(BIOS_DEBUG, "MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO\n");
+ break;
+*/
+
+ case CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR:
+ printk(BIOS_DEBUG, "Allocation rule number that has been violated:");
+ if ((event->EventInfo & 0x000000FF) == 0x01) {
+ printk(BIOS_DEBUG, "AGESA_CACHE_SIZE_REDUCED\n");
+ } else if ((event->EventInfo & 0x000000FF) == 0x02) {
+ printk(BIOS_DEBUG, "AGESA_CACHE_REGIONS_ACROSS_1MB\n");
+ } else if ((event->EventInfo & 0x000000FF) == 0x03) {
+ printk(BIOS_DEBUG, "AGESA_CACHE_REGIONS_ACROSS_4GB\n");
+ }
+ printk(BIOS_DEBUG, "cache region index:%lx, start:%lx size:%lx\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case CPU_WARNING_ADJUSTED_LEVELING_MODE:
+ printk(BIOS_DEBUG, "CPU_WARNING_ADJUSTED_LEVELING_MODE "
+ "requested: %lx, actual level:%lx\n",
+ event->DataParam1,
+ event->DataParam2);
+ break;
+
+ case CPU_EVENT_PM_PSTATE_OVERCURRENT:
+ printk(BIOS_DEBUG, "CPU_EVENT_PM_PSTATE_OVERCURRENT "
+ "Socket: %lx, Pstate:%lx\n",
+ event->DataParam1,
+ event->DataParam2);
+ break;
+
+ case CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG:
+ printk(BIOS_DEBUG, "CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG\n");
+ break;
+
+/*
+ case CPU_EVENT_UNKNOWN_PROCESSOR_REVISION:
+ printk(BIOS_DEBUG, "CPU_EVENT_UNKNOWN_PROCESSOR_REVISION, socket: %lx, cpuid:%lx\n",
+ event->DataParam1,
+ event->DataParam2);
+ break;
+*/
+
+ case HT_EVENT_OPT_REQUIRED_CAP_RETRY:
+ printk(BIOS_DEBUG, "HT_EVENT_OPT_REQUIRED_CAP_RETRY, Socket %lx Link %lx Depth %lx\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case HT_EVENT_OPT_REQUIRED_CAP_GEN3:
+ printk(BIOS_DEBUG, "HT_EVENT_OPT_REQUIRED_CAP_GEN3, Socket %lx Link %lx Depth %lx\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case HT_EVENT_OPT_UNUSED_LINKS:
+ printk(BIOS_DEBUG, "HT_EVENT_OPT_UNUSED_LINKS, SocketA%lx LinkA%lx SocketB%lx LinkB%lx\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3,
+ event->DataParam4);
+ break;
+
+ case HT_EVENT_OPT_LINK_PAIR_EXCEED:
+ printk(BIOS_DEBUG, "HT_EVENT_OPT_LINK_PAIR_EXCEED, SocketA%lx MasterLink%lx SocketB%lx AltLink%lx\n",
+
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3,
+ event->DataParam4);
+ default:
+ break;
+ }
+}
+
+/**
+ *
+ */
+static void agesa_error(EVENT_PARAMS *event)
+{
+
+ switch (event->EventInfo >> 24) {
+ case 0x04:
+ printk(BIOS_DEBUG, "Memory: Socket %lx Dct %lx Channel%lx ",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case 0x08:
+ printk(BIOS_DEBUG, "Processor: ");
+ break;
+
+ case 0x10:
+ printk(BIOS_DEBUG, "Hyper Transport: ");
+ break;
+
+ default:
+ break;
+ }
+
+ switch (event->EventInfo) {
+ case MEM_ERROR_NO_DQS_POS_RD_WINDOW:
+ printk(BIOS_DEBUG, "No DQS Position window for RD DQS\n");
+ break;
+
+ case MEM_ERROR_SMALL_DQS_POS_RD_WINDOW:
+ printk(BIOS_DEBUG, "Small DQS Position window for RD DQS\n");
+ break;
+
+ case MEM_ERROR_NO_DQS_POS_WR_WINDOW:
+ printk(BIOS_DEBUG, "No DQS Position window for WR DQS\n");
+ break;
+
+ case MEM_ERROR_SMALL_DQS_POS_WR_WINDOW:
+ printk(BIOS_DEBUG, "Small DQS Position window for WR DQS\n");
+ break;
+
+ case MEM_ERROR_ECC_DIS:
+ printk(BIOS_DEBUG, "ECC has been disabled as a result of an internal issue\n");
+ break;
+
+ case MEM_ERROR_DIMM_SPARING_NOT_ENABLED:
+ printk(BIOS_DEBUG, "DIMM sparing has not been enabled for an internal issues\n");
+ break;
+
+ case MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE:
+ printk(BIOS_DEBUG, "Receive Enable value is too large\n");
+ break;
+ case MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW:
+ printk(BIOS_DEBUG, "There is no DQS receiver enable window\n");
+ break;
+
+ case MEM_ERROR_DRAM_ENABLED_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling DramEnabled bit\n");
+ break;
+
+ case MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling DctAccessDone bit\n");
+ break;
+
+ case MEM_ERROR_SEND_CTRL_WORD_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling SendCtrlWord bit\n");
+ break;
+
+ case MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling PrefDramTrainMode bit\n");
+ break;
+
+ case MEM_ERROR_ENTER_SELF_REF_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling EnterSelfRef bit\n");
+ break;
+
+ case MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling FreqChgInProg bit\n");
+ break;
+
+ case MEM_ERROR_EXIT_SELF_REF_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling ExitSelfRef bit\n");
+ break;
+
+ case MEM_ERROR_SEND_MRS_CMD_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling SendMrsCmd bit\n");
+ break;
+
+ case MEM_ERROR_SEND_ZQ_CMD_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling SendZQCmd bit\n");
+ break;
+
+ case MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling DctExtraAccessDone bit\n");
+ break;
+
+ case MEM_ERROR_MEM_CLR_BUSY_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling MemClrBusy bit\n");
+ break;
+
+ case MEM_ERROR_MEM_CLEARED_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling MemCleared bit\n");
+ break;
+
+ case MEM_ERROR_FLUSH_WR_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling FlushWr bit\n");
+ break;
+
+ case MEM_ERROR_MAX_LAT_NO_WINDOW:
+ printk(BIOS_DEBUG, "Fail to find pass during Max Rd Latency training\n");
+ break;
+
+ case MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL:
+ printk(BIOS_DEBUG, "Fail to launch training code on an AP\n");
+ break;
+
+ case MEM_ERROR_PARALLEL_TRAINING_TIME_OUT:
+ printk(BIOS_DEBUG, "Fail to finish parallel training\n");
+ break;
+
+ case MEM_ERROR_NO_ADDRESS_MAPPING:
+ printk(BIOS_DEBUG, "No address mapping found for a dimm\n");
+ break;
+
+ case MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT:
+ printk(BIOS_DEBUG, "There is no DQS receiver enable window and the value is equal to the largest value\n");
+ break;
+
+ case MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE:
+ printk(BIOS_DEBUG, "Receive Enable value is too large and is 1 less than limit\n");
+ break;
+
+ case MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR:
+ printk(BIOS_DEBUG, "SPD Checksum error for NV_SPDCHK_RESTRT\n");
+ break;
+
+ case MEM_ERROR_NO_CHIPSELECT:
+ printk(BIOS_DEBUG, "No chipselects found\n");
+ break;
+
+ case MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM:
+ printk(BIOS_DEBUG, "Unbuffered dimm is not supported at 333MHz\n");
+ break;
+
+ case MEM_ERROR_WL_PRE_OUT_OF_RANGE:
+ printk(BIOS_DEBUG, "Returned PRE value during write levelizzation was out of range\n");
+ break;
+
+ case CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE:
+ printk(BIOS_DEBUG, "No heap is allocated for BrandId structure\n");
+ break;
+
+ case CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED:
+ printk(BIOS_DEBUG, "Unable to load micro code patch\n");
+ break;
+
+ case CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE:
+ printk(BIOS_DEBUG, "No heap is allocated for the Pstate structure\n");
+ break;
+
+/*
+ case CPU_ERROR_PM_NB_PSTATE_MISMATCH:
+ printk(BIOS_DEBUG, "NB P-state indicated by Index was disabled due to mismatch between processors\n");
+ break;
+*/
+
+ case CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR:
+ printk(BIOS_DEBUG, "Allocation rule number that has been violated:");
+ if ((event->EventInfo & 0x000000FF) == 0x04) {
+ printk(BIOS_DEBUG, "AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY\n");
+ } else if ((event->EventInfo & 0x000000FF) == 0x05) {
+ printk(BIOS_DEBUG, "AGESA_START_ADDRESS_LESS_D0000\n");
+ } else if ((event->EventInfo & 0x000000FF) == 0x06) {
+ printk(BIOS_DEBUG, "AGESA_THREE_CACHE_REGIONS_ABOVE_1MB\n");
+ } else if ((event->EventInfo & 0x000000FF) == 0x07) {
+ printk(BIOS_DEBUG, "AGESA_DEALLOCATE_CACHE_REGIONS\n");
+ }
+ printk(BIOS_DEBUG, "cache region index:%lx, start:%lx size:%lx\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case HT_EVENT_COH_NO_TOPOLOGY:
+ printk(BIOS_DEBUG, "no Matching Topology was found during coherent initializatio TotalHtNodes: %lx\n",
+ event->DataParam1);
+ break;
+
+ case HT_EVENT_NCOH_BUID_EXCEED:
+ printk(BIOS_DEBUG, "there is a limit of 32 unit IDs per chain Socket%lx Link%lx Depth%lx"
+ "Current BUID: %lx, Unit Count: %lx\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3,
+ event->DataParam4 >> 16,
+ event->DataParam4 & 0x0000FFFF);
+ break;
+
+ case HT_EVENT_NCOH_BUS_MAX_EXCEED:
+ printk(BIOS_DEBUG, "maximum auto bus limit exceeded, Socket %lx Link %lx Bus %lx\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case HT_EVENT_NCOH_CFG_MAP_EXCEED:
+ printk(BIOS_DEBUG, "there is a limit of four non-coherent chains, Socket %lx Link %lx\n",
+ event->DataParam1,
+ event->DataParam2);
+ break;
+
+ case HT_EVENT_NCOH_DEVICE_FAILED:
+ printk(BIOS_DEBUG, "after assigning an IO Device an ID, it does not respond at the new ID"
+ "Socket %lx Link %lx Depth %lx DeviceID %lx\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3,
+ event->DataParam4);
+ default:
+ break;
+ }
+}
+/**
+ *
+ */
+static void agesa_critical(EVENT_PARAMS *event)
+{
+ switch (event->EventInfo) {
+ case MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3:
+ printk(BIOS_DEBUG, "Socket: %lx, Heap allocation error for DMI table for DDR3\n",
+ event->DataParam1);
+ break;
+
+ case MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2:
+ printk(BIOS_DEBUG, "Socket: %lx, Heap allocation error for DMI table for DDR2\n",
+ event->DataParam1);
+ break;
+
+ case MEM_ERROR_UNSUPPORTED_DIMM_CONFIG:
+ printk(BIOS_DEBUG, "Socket: %lx, Dimm population is not supported\n",
+ event->DataParam1);
+ break;
+
+ case HT_EVENT_COH_PROCESSOR_TYPE_MIX:
+ printk(BIOS_DEBUG, "Socket %lx Link %lx TotalSockets %lx, HT_EVENT_COH_PROCESSOR_TYPE_MIX \n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case HT_EVENT_COH_MPCAP_MISMATCH:
+ printk(BIOS_DEBUG, "Socket %lx Link %lx MpCap %lx TotalSockets %lx, HT_EVENT_COH_MPCAP_MISMATCH\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3,
+ event->DataParam4);
+ default:
+ break;
+ }
+}
+
+/**
+ *
+ */
+static void agesa_fatal(EVENT_PARAMS *event)
+{
+
+ switch (event->EventInfo >> 24) {
+ case 0x04:
+ printk(BIOS_DEBUG, "Memory: Socket %lx Dct %lx Channel%lx ",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case 0x08:
+ printk(BIOS_DEBUG, "Processor: ");
+ break;
+
+ case 0x10:
+ printk(BIOS_DEBUG, "Hyper Transport: ");
+ break;
+
+ default:
+ break;
+ }
+
+ switch (event->EventInfo) {
+ case MEM_ERROR_MINIMUM_MODE:
+ printk(BIOS_DEBUG, "Running in minimum mode\n");
+ break;
+
+ case MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM:
+ printk(BIOS_DEBUG, "DIMM modules are missmatched\n");
+ break;
+
+ case MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM:
+ printk(BIOS_DEBUG, "No DIMMs have been foun\n");
+ break;
+
+ case MEM_ERROR_MISMATCH_DIMM_CLOCKS:
+ printk(BIOS_DEBUG, "DIMM clocks miss-matched\n");
+ break;
+
+ case MEM_ERROR_NO_CYC_TIME:
+ printk(BIOS_DEBUG, "No cycle time found\n");
+ break;
+ case MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS:
+ printk(BIOS_DEBUG, "Heap allocation error with dynamic storing of trained timings\n");
+ break;
+
+ case MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs:
+ printk(BIOS_DEBUG, "Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT\n");
+ break;
+
+ case MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV:
+ printk(BIOS_DEBUG, "Heap allocation error with REMOTE_TRAINING_ENV\n");
+ break;
+
+ case MEM_ERROR_HEAP_ALLOCATE_FOR_SPD:
+ printk(BIOS_DEBUG, "Heap allocation error for SPD data\n");
+ break;
+
+ case MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA:
+ printk(BIOS_DEBUG, "Heap allocation error for RECEIVED_DATA during parallel training\n");
+ break;
+
+ case MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS:
+ printk(BIOS_DEBUG, "Heap allocation error for S3 \"SPECIAL_CASE_REGISTER\"\n");
+ break;
+
+ case MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA:
+ printk(BIOS_DEBUG, "Heap allocation error for Training Data\n");
+ break;
+
+ case MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK:
+ printk(BIOS_DEBUG, "Heap allocation error for DIMM Identify \"MEM_NB_BLOCK\"\n");
+ break;
+
+ case MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM:
+ printk(BIOS_DEBUG, "No Constructor for DIMM Identify\n");
+ break;
+
+ case MEM_ERROR_VDDIO_UNSUPPORTED:
+ printk(BIOS_DEBUG, "VDDIO of the dimms on the board is not supported\n");
+ break;
+
+ case CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT:
+ printk(BIOS_DEBUG, "Socket: %lx, All PStates exceeded the motherboard current limit on specified socket\n",
+ event->DataParam1);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ *
+ * Interprte the agesa event log to an user readable string
+ */
+static void interpret_agesa_eventlog(EVENT_PARAMS *event)
+{
+ switch (event->EventClass) {
+ case AGESA_BOUNDS_CHK:
+ agesa_bound_check(event);
+ break;
+
+ case AGESA_ALERT:
+ agesa_alert(event);
+ break;
+
+ case AGESA_WARNING:
+ agesa_warning(event);
+ break;
+
+ case AGESA_ERROR:
+ agesa_error(event);
+ break;
+
+ case AGESA_CRITICAL:
+ agesa_critical(event);
+ break;
+
+ case AGESA_FATAL:
+ agesa_fatal(event);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @param HeapStatus -the current HeapStatus
+ */
+UINT32 agesawrapper_amdreadeventlog(UINT8 HeapStatus)
+{
+ AGESA_STATUS Status;
+ EVENT_PARAMS AmdEventParams;
+
+ LibAmdMemFill(&AmdEventParams,
+ 0,
+ sizeof(EVENT_PARAMS),
+ &(AmdEventParams.StdHeader));
+
+ AmdEventParams.StdHeader.AltImageBasePtr = 0;
+ AmdEventParams.StdHeader.CalloutPtr = NULL;
+ AmdEventParams.StdHeader.Func = 0;
+ AmdEventParams.StdHeader.ImageBasePtr = 0;
+ /* I have to know the current HeapStatus to Locate the EventLogHeapPointer */
+ AmdEventParams.StdHeader.HeapStatus = HeapStatus;
+ Status = AmdReadEventLog(&AmdEventParams);
+ while (AmdEventParams.EventClass != 0) {
+ printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
+ printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
+ printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
+ interpret_agesa_eventlog(&AmdEventParams);
+ Status = AmdReadEventLog(&AmdEventParams);
+ }
+
+ return (UINT32)Status;
+}
+
diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.h b/src/mainboard/supermicro/h8qgi/agesawrapper.h
new file mode 100755
index 0000000..43c7d10
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/agesawrapper.h
@@ -0,0 +1,87 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*----------------------------------------------------------------------------------------
+ * M O D U L E S U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#ifndef _AGESAWRAPPER_H_
+#define _AGESAWRAPPER_H_
+
+#include <stdint.h>
+#include "Porting.h"
+#include "AGESA.h"
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
+
+enum {
+ PICK_DMI, /* DMI Interface */
+ PICK_PSTATE, /* Acpi Pstate SSDT Table */
+ PICK_SRAT, /* SRAT Table */
+ PICK_SLIT, /* SLIT Table */
+ PICK_WHEA_MCE, /* WHEA MCE table */
+ PICK_WHEA_CMC, /* WHEA CMV table */
+ PICK_ALIB, /* SACPI SSDT table with ALIB implementation */
+};
+
+
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S A N D S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef struct {
+ UINT32 CalloutName;
+ AGESA_STATUS (*CalloutPtr)(UINT32 Func, UINT32 Data, VOID* ConfigPtr);
+} BIOS_CALLOUT_STRUCT;
+
+/*----------------------------------------------------------------------------------------
+ * P R O T O T Y P E S O F L O C A L F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * E X P O R T E D F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------
+ * L O C A L F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+UINT32 agesawrapper_amdinitreset (void);
+UINT32 agesawrapper_amdinitearly (void);
+UINT32 agesawrapper_amdinitenv (void);
+UINT32 agesawrapper_amdinitlate (void);
+UINT32 agesawrapper_amdinitpost (void);
+UINT32 agesawrapper_amdinitmid (void);
+UINT32 agesawrapper_amdreadeventlog (UINT8 HeapStatus);
+UINT32 agesawrapper_amdinitmmio (void);
+void *agesawrapper_getlateinitptr (int pick);
+UINT32 agesawrapper_amdlaterunaptask(UINT32 Data, VOID *ConfigPtr);
+
+#endif
diff --git a/src/mainboard/supermicro/h8qgi/buildOpts.c b/src/mainboard/supermicro/h8qgi/buildOpts.c
new file mode 100755
index 0000000..02cf79b
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/buildOpts.c
@@ -0,0 +1,541 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "AGESA.h"
+#include "CommonReturns.h"
+#include "AdvancedApi.h"
+#include <PlatformMemoryConfiguration.h>
+#include "Filecode.h"
+#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
+
+/* AGESA will check the OEM configuration during preprocessing stage,
+ * coreboot enable -Wundef option, so we should make sure we have all contanstand defined
+ */
+/* MEMORY_BUS_SPEED */
+#define DDR400_FREQUENCY 200 ///< DDR 400
+#define DDR533_FREQUENCY 266 ///< DDR 533
+#define DDR667_FREQUENCY 333 ///< DDR 667
+#define DDR800_FREQUENCY 400 ///< DDR 800
+#define DDR1066_FREQUENCY 533 ///< DDR 1066
+#define DDR1333_FREQUENCY 667 ///< DDR 1333
+#define DDR1600_FREQUENCY 800 ///< DDR 1600
+#define DDR1866_FREQUENCY 933 ///< DDR 1866
+#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
+
+/* QUANDRANK_TYPE*/
+#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
+#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
+
+/* USER_MEMORY_TIMING_MODE */
+#define TIMING_MODE_AUTO 0 ///< Use best rate possible
+#define TIMING_MODE_LIMITED 1 ///< Set user top limit
+#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
+
+/* POWER_DOWN_MODE */
+#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
+#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
+
+/* User makes option selections here
+ * Comment out the items wanted to be included in the build.
+ * Uncomment those items you with to REMOVE from the build.
+ */
+//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
+//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
+//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
+//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
+//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
+//#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
+//#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
+//#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
+#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE
+//#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
+////#define BLDOPT_REMOVE_ACPI_PSTATES TRUE
+////#define BLDOPT_REMOVE_SRAT TRUE
+////#define BLDOPT_REMOVE_SLIT TRUE
+//#define BLDOPT_REMOVE_WHEA TRUE
+//#define BLDOPT_REMOVE_DMI TRUE
+//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
+//#define BLDOPT_REMOVE_HT_ASSIST TRUE
+//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
+
+/* Build configuration values here.
+ */
+#define BLDCFG_VRM_CURRENT_LIMIT 120000
+#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0
+#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 0
+#define BLDCFG_PLAT_NUM_IO_APICS 3
+#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
+#define BLDCFG_MEM_INIT_PSTATE 0
+#define BLDCFG_AMD_PSTATE_CAP_VALUE 0
+
+#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_SERVER
+
+#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY//1600
+#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
+#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
+#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
+#define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE
+#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE
+#define BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB TRUE
+#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING FALSE//TRUE
+#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE//TRUE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE//TRUE
+#define BLDCFG_MEMORY_POWER_DOWN FALSE
+#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHANNEL
+#define BLDCFG_ONLINE_SPARE FALSE
+#define BLDCFG_BANK_SWIZZLE TRUE
+#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
+#define BLDCFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY
+#define BLDCFG_DQS_TRAINING_CONTROL TRUE
+#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
+#define BLDCFG_USE_BURST_MODE FALSE
+#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
+#define BLDCFG_ENABLE_ECC_FEATURE TRUE
+#define BLDCFG_ECC_REDIRECTION FALSE
+#define BLDCFG_SCRUB_IC_RATE 0
+#define BLDCFG_ECC_SYNC_FLOOD TRUE
+#define BLDCFG_ECC_SYMBOL_SIZE 4
+
+#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
+#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
+
+/**
+ * Enable Message Based C1e CPU feature in multi-socket systems.
+ * BLDCFG_PLATFORM_C1E_OPDATA element be defined with a valid IO port value,
+ * else the feature cannot be enabled.
+ */
+#define BLDCFG_PLATFORM_C1E_MODE C1eModeMsgBased
+#define BLDCFG_PLATFORM_C1E_OPDATA 0x80//TODO
+//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0
+//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0
+
+#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
+#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000
+#define BLDCFG_1GB_ALIGN FALSE
+//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C'
+//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
+//
+
+// Select the platform control flow mode for performance tuning.
+#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm
+
+/**
+ * Enable the probe filtering performance tuning feature.
+ * The probe filter provides filtering of broadcast probes to
+ * improve link bandwidth and performance for multi- node systems.
+ *
+ * This feature may interact with other performance features.
+ * TRUE -Enable the feature (default) if supported by all processors,
+ * based on revision and presence of L3 cache.
+ * The feature is not enabled if there are no coherent HT links.
+ * FALSE -Do not enable the feature regardless of the configuration.
+ */
+//TODO enable it,
+//but AGESA set PFMode = 0; //PF Disable, HW never set PFInitDone
+//hang in F10HtAssistInit() do{...} while(PFInitDone != 1)
+#define BLDCFG_USE_HT_ASSIST FALSE
+
+/**
+ * The socket and link match values are platform specific
+ */
+CONST MANUAL_BUID_SWAP_LIST ROMDATA h8qgi_manual_swaplist[2] =
+{
+ {
+ /* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */
+ HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
+
+ { //BUID Swap List
+ { //BUID Swaps
+ /* Each Non-coherent chain may have a list of device swaps,
+ * Each item specify a device will be swap from its current id to a new one
+ */
+ /* FromID 0x00 is the chain with the southbridge */
+ /* 'Move' device zero to device zero, All others are non applicable */
+ {0x00, 0x00}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
+ {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
+ {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
+ {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
+ {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
+ {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
+ {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
+ {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
+ },
+
+ { //The ordered final BUIDs
+ /* Specify the final BUID to be zero, All others are non applicable */
+ 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ }
+ }
+ },
+
+ /* The 2nd element in the array merely terminates the list */
+ {
+ HT_LIST_TERMINAL,
+ }
+};
+
+#if CONFIG_HT3_SUPPORT == 1
+/**
+ * The socket and link match values are platform specific
+ *
+ */
+CONST CPU_TO_CPU_PCB_LIMITS ROMDATA h8qgi_cpu2cpu_limit_list[2] =
+{
+ {
+ /* On the reference platform, these settings apply to all coherent links */
+ HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
+
+ /* Set incoming and outgoing links to 16 bit widths, and 3.2GHz frequencies */
+ HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_3200M,
+ },
+
+ /* The 2nd element in the array merely terminates the list */
+ {
+ HT_LIST_TERMINAL,
+ }
+};
+
+CONST IO_PCB_LIMITS ROMDATA h8qgi_io_limit_list[2] =
+{
+ {
+ /* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */
+ HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
+
+ /* Set upstream and downstream links to 16 bit widths, and limit frequencies to 3.2GHz */
+ HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_3200M, //Actually IO hub only support 2600M MAX
+ },
+
+ /* The 2nd element in the array merely terminates the list */
+ {
+ HT_LIST_TERMINAL,
+ }
+};
+#else //CONFIG_HT3_SUPPORT == 0
+CONST CPU_TO_CPU_PCB_LIMITS ROMDATA h8qgi_cpu2cpu_limit_list[2] =
+{
+ {
+ /* On the reference platform, these settings apply to all coherent links */
+ HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
+
+ /* Set incoming and outgoing links to 16 bit widths, and 1GHz frequencies */
+ HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_HT1_ONLY,
+ },
+
+ /* The 2nd element in the array merely terminates the list */
+ {
+ HT_LIST_TERMINAL,
+ }
+};
+
+CONST IO_PCB_LIMITS ROMDATA h8qgi_io_limit_list[2] =
+{
+ {
+ /* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */
+ HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
+
+ /* Set incoming and outgoing links to 16 bit widths, and 1GHz frequencies */
+ HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_HT1_ONLY,
+ },
+
+ /* The 2nd element in the array merely terminates the list */
+ {
+ HT_LIST_TERMINAL
+ }
+};
+#endif //CONFIG_HT3_SUPPORT == 0
+
+/**
+ * HyperTransport links will typically require an equalization at high frequencies.
+ * This is called deemphasis.
+ *
+ * Deemphasis is specified as levels, for example, -3 db.
+ * There are two levels for each link, its receiver deemphasis level and its DCV level,
+ * which is based on the far side transmitter's deemphasis.
+ * For each link, different levels may be required at each link frequency.
+ *
+ * Coherent connections between processors should have an entry for the port on each processor.
+ * There should be one entry for the host root port of each non-coherent chain.
+ *
+ * AGESA initialization code does not set deemphasis on IO Devices.
+ * A default is provided for internal links of MCM processors, and
+ * those links will generally not need deemphasis structures.
+ */
+CONST CPU_HT_DEEMPHASIS_LEVEL ROMDATA h8qgi_deemphasis_list[] =
+{
+ /* Socket, Link, LowFreq, HighFreq, Receiver Deemphasis, Dcv Deemphasis */
+
+ /* Non-coherent link deemphasis. */
+ {0, 2, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
+ {0, 2, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5},
+ {0, 2, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5},
+ {0, 2, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7},
+ {0, 2, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7},
+ {0, 2, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9},
+
+ /* Coherent link deemphasis. */
+ {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
+ {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus3},
+ {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus6},
+ {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus6},
+ {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus8},
+ {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2600M, HT_FREQUENCY_MAX, DeemphasisLevelMinus11pre8, DcvLevelMinus11},
+
+ /* End of the list */
+ {
+ HT_LIST_TERMINAL
+ }
+};
+
+/**
+ * For systems using socket infrastructure that permits strapping the SBI
+ * address for each socket, this should be used to provide a socket ID value.
+ * This is referred to as the hardware method for socket naming, and is the
+ * preferred solution.
+ */
+/*
+ * I do NOT know howto config socket id in simnow,
+ * so use this software way to make HT works in simnow,
+ * real hardware do not need this Socket Map.
+ *
+ * A physical socket map for a 4 G34 Sockets MCM processors topology,
+ * reference the mainboard schemantic in detail.
+ *
+ */
+CONST SYSTEM_PHYSICAL_SOCKET_MAP ROMDATA h8qgi_socket_map[] =
+{
+#define HT_SOCKET0 0
+#define HT_SOCKET1 1
+#define HT_SOCKET2 2
+#define HT_SOCKET3 3
+
+/**
+ * 0-3 are sublink 0, 4-7 are sublink 1
+ */
+#define HT_LINK0A 0
+#define HT_LINK1A 1
+#define HT_LINK2A 2
+#define HT_LINK3A 3
+#define HT_LINK0B 4
+#define HT_LINK1B 5
+#define HT_LINK2B 6
+#define HT_LINK3B 7
+
+ /* Source Socket, Link, Target Socket */
+ {HT_SOCKET0, HT_LINK0A, HT_SOCKET1},
+ {HT_SOCKET0, HT_LINK0B, HT_SOCKET3},
+ {HT_SOCKET0, HT_LINK1A, HT_SOCKET1},
+ {HT_SOCKET0, HT_LINK1B, HT_SOCKET3},
+ {HT_SOCKET0, HT_LINK3A, HT_SOCKET2},
+ {HT_SOCKET0, HT_LINK3B, HT_SOCKET2},
+
+ {HT_SOCKET1, HT_LINK0A, HT_SOCKET2},
+ {HT_SOCKET1, HT_LINK0B, HT_SOCKET3},
+ {HT_SOCKET1, HT_LINK1A, HT_SOCKET0},
+ {HT_SOCKET1, HT_LINK1B, HT_SOCKET2},
+ {HT_SOCKET1, HT_LINK3A, HT_SOCKET0},
+ {HT_SOCKET1, HT_LINK3B, HT_SOCKET3},
+
+ {HT_SOCKET2, HT_LINK0A, HT_SOCKET3},
+ {HT_SOCKET2, HT_LINK0B, HT_SOCKET0},
+ {HT_SOCKET2, HT_LINK1A, HT_SOCKET3},
+ {HT_SOCKET2, HT_LINK1B, HT_SOCKET1},
+ {HT_SOCKET2, HT_LINK3A, HT_SOCKET1},
+ {HT_SOCKET2, HT_LINK3B, HT_SOCKET0},
+
+ {HT_SOCKET3, HT_LINK0A, HT_SOCKET2},
+ {HT_SOCKET3, HT_LINK0B, HT_SOCKET1},
+ {HT_SOCKET3, HT_LINK1A, HT_SOCKET1},
+ {HT_SOCKET3, HT_LINK1B, HT_SOCKET0},
+ {HT_SOCKET3, HT_LINK3A, HT_SOCKET0},
+ {HT_SOCKET3, HT_LINK3B, HT_SOCKET2},
+
+};
+
+CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] =
+{
+ {AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull},
+ {AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull},
+ {AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull},
+ {AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000ull},
+ {AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000ull},
+ {AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000ull},
+ {AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000ull},
+ {AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818ull},
+ {AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818ull},
+ {AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818ull},
+ {AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818ull},
+ {CPU_LIST_TERMINAL}
+};
+
+#define BLDCFG_BUID_SWAP_LIST &h8qgi_manual_swaplist
+#define BLDCFG_HTFABRIC_LIMITS_LIST &h8qgi_cpu2cpu_limit_list
+#define BLDCFG_HTCHAIN_LIMITS_LIST &h8qgi_io_limit_list
+#define BLDCFG_PLATFORM_DEEMPHASIS_LIST &h8qgi_deemphasis_list
+#define BLDCFG_AP_MTRR_SETTINGS_LIST &h8qgi_ap_mtrr_list
+//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP &h8qgi_socket_map
+
+
+/* Process the options...
+ * This file include MUST occur AFTER the user option selection settings
+ */
+#define AGESA_ENTRY_INIT_RESET FALSE//TRUE
+#define AGESA_ENTRY_INIT_RECOVERY FALSE
+#define AGESA_ENTRY_INIT_EARLY TRUE
+#define AGESA_ENTRY_INIT_POST TRUE
+#define AGESA_ENTRY_INIT_ENV TRUE
+#define AGESA_ENTRY_INIT_MID TRUE
+#define AGESA_ENTRY_INIT_LATE TRUE
+#define AGESA_ENTRY_INIT_S3SAVE TRUE
+#define AGESA_ENTRY_INIT_RESUME TRUE
+#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
+#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
+
+#include "GnbInterface.h" /*prototype for GnbInterfaceStub*/
+#include "MaranelloInstall.h"
+
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+ //
+ // The following macros are supported (use comma to separate macros):
+ //
+ // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
+ // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
+ // AGESA will base on this value to disable unused MemClk to save power.
+ // Example:
+ // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
+ // Bit AM3/S1g3 pin name
+ // 0 M[B,A]_CLK_H/L[0]
+ // 1 M[B,A]_CLK_H/L[1]
+ // 2 M[B,A]_CLK_H/L[2]
+ // 3 M[B,A]_CLK_H/L[3]
+ // 4 M[B,A]_CLK_H/L[4]
+ // 5 M[B,A]_CLK_H/L[5]
+ // 6 M[B,A]_CLK_H/L[6]
+ // 7 M[B,A]_CLK_H/L[7]
+ // And platform has the following routing:
+ // CS0 M[B,A]_CLK_H/L[4]
+ // CS1 M[B,A]_CLK_H/L[2]
+ // CS2 M[B,A]_CLK_H/L[3]
+ // CS3 M[B,A]_CLK_H/L[5]
+ // Then platform can specify the following macro:
+ // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
+ //
+ // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
+ // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
+ // AGESA will base on this value to tristate unused CKE to save power.
+ //
+ // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
+ // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
+ // AGESA will base on this value to tristate unused ODT pins to save power.
+ //
+ // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
+ // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
+ // AGESA will base on this value to tristate unused Chip select to save power.
+ //
+ // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
+ // Specifies the number of DIMM slots per channel.
+ //
+ // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
+ // Specifies the number of Chip selects per channel.
+ //
+ // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
+ // Specifies the number of channels per socket.
+ //
+ // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
+ // Specifies DDR bus speed of channel ChannelID on socket SocketID.
+ //
+ // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
+ // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
+ //
+ // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
+ // Byte6Seed, Byte7Seed, ByteEccSeed)
+ // Specifies the write leveling seed for a channel of a socket.
+ //
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), //max 3
+ PSO_END
+};
+
+/*
+ * These tables are optional and may be used to adjust memory timing settings
+ */
+
+//HY Customer table
+UINT8 AGESA_MEM_TABLE_HY[][sizeof (MEM_TABLE_ALIAS)] =
+{
+ // Hardcoded Memory Training Values
+
+ // The following macro should be used to override training values for your platform
+ //
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20),
+ //
+ // NOTE:
+ // The following training hardcode values are example values that were taken from a tilapia motherboard
+ // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in
+ // the table and replace the byte lane values with your own.
+ //
+ // ------------------ BYTE LANES ----------------------
+ // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC
+ // Write Data Timing
+ // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0
+ // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1
+ // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0
+ // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1
+
+ // DQS Receiver Enable
+ // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
+ // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1
+ // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0
+ // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1
+
+ // Write DQS Delays
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1
+
+ // Read DQS Delays
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1
+ //--------------------------------------------------------------------------------------------------------------------------------------------------
+ // TABLE END
+ NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table
+};
+UINT8 SizeOfTableHy = sizeof (AGESA_MEM_TABLE_HY) / sizeof (AGESA_MEM_TABLE_HY[0]);
+
diff --git a/src/mainboard/supermicro/h8qgi/chip.h b/src/mainboard/supermicro/h8qgi/chip.h
new file mode 100755
index 0000000..a252705
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/chip.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config {};
diff --git a/src/mainboard/supermicro/h8qgi/cmos.layout b/src/mainboard/supermicro/h8qgi/cmos.layout
new file mode 100755
index 0000000..3b98cbb
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/cmos.layout
@@ -0,0 +1,118 @@
+#*****************************************************************************
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#*****************************************************************************
+
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+#96 288 r 0 temporary_filler
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+386 1 e 1 ECC_memory
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+395 1 e 1 hw_scrubber
+396 1 e 1 interleave_chip_selects
+397 2 e 8 max_mem_clock
+399 1 e 2 multi_core
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+416 4 e 7 boot_first
+420 4 e 7 boot_second
+424 4 e 7 boot_third
+428 4 h 0 boot_index
+432 8 h 0 boot_countdown
+440 4 e 9 slow_cpu
+444 1 e 1 nmi
+445 1 e 1 iommu
+728 256 h 0 user_data
+984 16 h 0 check_sum
+# Reserve the extended AMD configuration registers
+1000 24 r 0 amd_reserved
+
+
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Network
+7 1 HDD
+7 2 Floppy
+7 8 Fallback_Network
+7 9 Fallback_HDD
+7 10 Fallback_Floppy
+#7 3 ROM
+8 0 400Mhz
+8 1 333Mhz
+8 2 266Mhz
+8 3 200Mhz
+9 0 off
+9 1 87.5%
+9 2 75.0%
+9 3 62.5%
+9 4 50.0%
+9 5 37.5%
+9 6 25.0%
+9 7 12.5%
+
+checksums
+
+checksum 392 983 984
+
+
diff --git a/src/mainboard/supermicro/h8qgi/devicetree.cb b/src/mainboard/supermicro/h8qgi/devicetree.cb
new file mode 100755
index 0000000..9afaac7
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/devicetree.cb
@@ -0,0 +1,176 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+chip northbridge/amd/agesa/family10/root_complex
+ device lapic_cluster 0 on
+ chip cpu/amd/agesa/family10
+ device lapic 0x10 on end
+ end
+ end
+ device pci_domain 0 on
+ subsystemid 0x15d9 0xab11 inherit #SuperMicro
+ chip northbridge/amd/agesa/family10 # CPU side of HT root complex
+ device pci 18.0 on end # link 0
+ device pci 18.0 on end # link 1
+ device pci 18.0 on end # link 2
+ device pci 18.0 on # link3 SB on socket0 link 2, on internal Node0 Link 3
+ chip southbridge/amd/sr5650 # Southbridge PCI side of HT Root complex
+ device pci 0.0 on end # HT Root Complex 0x9600
+ device pci 0.1 off end # CLKCONFIG
+ device pci 2.0 on end # GPP1 Port0 x16 SLOT4, 0x5A16
+ device pci 3.0 off end # GPP1 Port1
+ device pci 4.0 off end # GPP3a Port0 x4 SAS
+ device pci 5.0 off end # GPP3a Port1
+ device pci 6.0 off end # GPP3a Port2
+ device pci 7.0 off end # GPP3a Port3
+ device pci 8.0 off end # NB/SB Link P2P bridge, should be hidden at boot time
+ device pci 9.0 off end # GPP3a Port4 x1 NC
+ device pci a.0 off end # GPP3a Port5 x1 NC
+ device pci b.0 off end # GPP2 Port0 (Not for sr5650)
+ device pci c.0 off end # GPP2 Port1 (Not for sr5650/sr5670)
+ device pci d.0 on end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576
+ register "gpp1_configuration" = "0" # Configuration 16:0 default
+ register "gpp2_configuration" = "1" # Configuration 8:8
+ register "gpp3a_configuration" = "2" # Configuration 4:1:1:0:0:0
+ #register "gpp3a_configuration" = "11" # Configuration 1:1:1:1:1:1
+ register "port_enable" = "0x2104"
+ end #southbridge/amd/sr5650
+ chip southbridge/amd/sp5100 # it is under NB/SB Link, but on the same pci bus
+ device pci 11.0 on end # SATA
+ device pci 12.0 on end # USB1
+ device pci 12.1 on end # USB1
+ device pci 12.2 on end # USB1
+ device pci 13.0 on end # USB2
+ device pci 13.1 on end # USB2
+ device pci 13.2 on end # USB2
+ device pci 14.0 on end # SM
+ device pci 14.1 on end # IDE 0x439c
+ device pci 14.2 off end # HDA 0x4383, h8qgi doesnt have codec.
+ device pci 14.3 on # LPC 0x439d
+ chip superio/winbond/w83627dhg
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ ## though UARTs are on the NUVOTON BMC, superio only used to support PS2 KB/MS##
+ device pnp 2e.5 on # PS/2 keyboard & mouse
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 0x01 #keyboard
+ irq 0x72 = 0x0C #mouse
+ end
+ #device pnp 2e.6 off # SPI
+ #end
+ device pnp 2e.307 off # GPIO6
+ end
+ device pnp 2e.8 off # WDTO#, PLED
+ end
+ device pnp 2e.009 off # GPIO2
+ end
+ device pnp 2e.109 off # GPIO3
+ end
+ device pnp 2e.209 off # GPIO4
+ end
+ device pnp 2e.309 off # GPIO5
+ end
+ device pnp 2e.a off # ACPI
+ end
+ device pnp 2e.b off # HWM
+ io 0x60 = 0x290
+ end
+ device pnp 2e.c off # PECI, SST
+ end
+ end #superio/winbond/w83627dhg
+ end # LPC
+ device pci 14.4 on end # PCI 0x4384
+ device pci 14.5 on end # USB 3
+ register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
+ end # southbridge/amd/sp5100
+ end # device pci 18.0
+
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ device pci 18.4 on end
+
+ device pci 19.0 on end
+ device pci 19.1 on end
+ device pci 19.2 on end
+ device pci 19.3 on end
+ device pci 19.4 on end
+
+
+ device pci 1a.0 on end
+ device pci 1a.0 on end
+ device pci 1a.0 on end
+ device pci 1a.0 on # another 56x0 on socket 1 Link 2, internal Node0 link 3
+ end
+ device pci 1a.1 on end
+ device pci 1a.2 on end
+ device pci 1a.3 on end
+ device pci 1a.4 on end
+
+ device pci 1b.0 on end
+ device pci 1b.1 on end
+ device pci 1b.2 on end
+ device pci 1b.3 on end
+ device pci 1b.4 on end
+
+
+ device pci 1c.0 on end
+ device pci 1c.1 on end
+ device pci 1c.2 on end
+ device pci 1c.3 on end
+ device pci 1c.4 on end
+
+ device pci 1d.0 on end
+ device pci 1d.1 on end
+ device pci 1d.2 on end
+ device pci 1d.3 on end
+ device pci 1d.4 on end
+
+
+ device pci 1e.0 on end
+ device pci 1e.1 on end
+ device pci 1e.2 on end
+ device pci 1e.3 on end
+ device pci 1e.4 on end
+
+ device pci 1f.0 on end
+ device pci 1f.1 on end
+ device pci 1f.2 on end
+ device pci 1f.3 on end
+ device pci 1f.4 on end
+
+ end #chip northbridge/amd/agesa/family10 # CPU side of HT root complex
+ end #pci_domain
+end #northbridge/amd/agesa/family10/root_complex
+
diff --git a/src/mainboard/supermicro/h8qgi/dimmSpd.c b/src/mainboard/supermicro/h8qgi/dimmSpd.c
new file mode 100755
index 0000000..4ff21ee
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/dimmSpd.c
@@ -0,0 +1,229 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "Porting.h"
+#include "AGESA.h"
+#include "amdlib.h"
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_ids.h>
+
+AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info);
+#define DIMENSION(array)(sizeof (array)/ sizeof (array [0]))
+
+/* SP5100 GPIO 53-56 contoled by SMBUS PCI_Reg 0x52 */
+#define SP5100_GPIO53_56 0x52
+
+/**
+ * TODO not support all GPIO yet
+ * @param reg -GPIO Cntrl Register
+ * @param out -GPIO bitmap
+ * @param out -GPIO enable bitmap
+ */
+static void sp5100_set_gpio(u8 reg, u8 out, u8 enable)
+{
+ u8 value;
+ device_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBUS
+
+ value = pci_read_config8(sm_dev, reg);
+ value &= ~(enable);
+ value |= out;
+ value &= ~(enable << 4);
+ pci_write_config8(sm_dev, reg, value);
+}
+
+/*-----------------------------------------------------------------------------
+ *
+ * SPD address table - porting required
+ */
+static const UINT8 spdAddressLookup [8] [4] [2] = { // socket, channel, dimm
+ /* socket 0 */
+ {
+ {0xAE, 0xAC},
+ {0xAA, 0xA8},
+ {0xA6, 0xA4},
+ {0xA2, 0xA0},
+ },
+ /* socket 1 */
+ {
+ {0xAE, 0xAC},
+ {0xAA, 0xA8},
+ {0xA6, 0xA4},
+ {0xA2, 0xA0},
+ },
+ /* socket 2 */
+ {
+ {0xAE, 0xAC},
+ {0xAA, 0xA8},
+ {0xA6, 0xA4},
+ {0xA2, 0xA0},
+ },
+ /* socket 3 */
+ {
+ {0xAE, 0xAC},
+ {0xAA, 0xA8},
+ {0xA6, 0xA4},
+ {0xA2, 0xA0},
+ },
+};
+
+/*-----------------------------------------------------------------------------
+ *
+ * readSmbusByteData - read a single SPD byte from any offset
+ */
+
+static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
+{
+ unsigned int status;
+ UINT64 limit;
+
+ address |= 1; // set read bit
+
+ outb(0xFF, iobase + 0); // clear error status
+ outb(0x1F, iobase + 1); // clear error status
+ outb(offset, iobase + 3); // offset in eeprom
+ outb(address, iobase + 4); // slave address and read bit
+ outb(0x48, iobase + 2); // read byte command
+
+ // time limit to avoid hanging for unexpected error status (should never happen)
+ limit = __rdtsc () + 2000000000 / 10;
+ for (;;)
+ {
+ status = inb(iobase);
+ if (__rdtsc () > limit) break;
+ if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting
+ if ((status & 1) == 1) continue; // HostBusy set, keep waiting
+ break;
+ }
+
+ buffer [0] = inb(iobase + 5);
+ if (status == 2) status = 0; // check for done with no errors
+ return status;
+}
+
+/*-----------------------------------------------------------------------------
+ *
+ * readSmbusByte - read a single SPD byte from the default offset
+ * this function is faster function readSmbusByteData
+ */
+
+static int readSmbusByte (int iobase, int address, char *buffer)
+{
+ unsigned int status;
+ UINT64 limit;
+
+ outb(0xFF, iobase + 0); // clear error status
+ outb(0x44, iobase + 2); // read command
+
+ // time limit to avoid hanging for unexpected error status
+ limit = __rdtsc () + 2000000000 / 10;
+ for (;;)
+ {
+ status = inb(iobase);
+ if (__rdtsc () > limit) break;
+ if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting
+ if ((status & 1) == 1) continue; // HostBusy set, keep waiting
+ break;
+ }
+
+ buffer [0] = inb(iobase + 5);
+ if (status == 2) status = 0; // check for done with no errors
+ return status;
+}
+
+/*---------------------------------------------------------------------------
+ *
+ * readspd - Read one or more SPD bytes from a DIMM.
+ * Start with offset zero and read sequentially.
+ * Optimization relies on autoincrement to avoid
+ * sending offset for every byte.
+ * Reads 128 bytes in 7-8 ms at 400 KHz.
+ */
+
+static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count)
+{
+ int index, error;
+
+ /* read the first byte using offset zero */
+ error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0);
+ if (error) {
+ return error;
+ }
+
+ /* read the remaining bytes using auto-increment for speed */
+ for (index = 1; index < count; index++)
+ {
+ error = readSmbusByte (iobase, SmbusSlaveAddress, buffer + index);
+ if (error)
+ return error;
+ }
+
+ return 0;
+}
+
+static void writePmReg (int reg, int data)
+{
+ outb(reg, 0xCD6);
+ outb(data, 0xCD7);
+}
+
+static void setupFch (int ioBase)
+{
+ writePmReg (0x2D, ioBase >> 8);
+ writePmReg (0x2C, ioBase | 1);
+ writePmReg (0x29, 0x80);
+ writePmReg (0x28, 0x61);
+ outb(66000000 / 400000 / 4, ioBase + 0x0E); // set SMBus clock to 400 KHz
+}
+
+AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info)
+{
+ int spdAddress, ioBase;
+ u8 i2c_channel;
+ device_t sm_dev;
+
+ if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR;
+ if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR;
+ if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR;
+ i2c_channel = (UINT8) info->SocketId;
+
+ /* set ght i2c channel
+ * GPIO54,53 control the HC4052 S1,S0
+ * S1 S0 true table
+ * 0 0 channel 1 (Socket1)
+ * 0 1 channel 2 (Socket2)
+ * 1 0 channel 3 (Socket3)
+ * 1 1 channel 4 (Socket4)
+ */
+ sp5100_set_gpio(SP5100_GPIO53_56, i2c_channel, 0x03);
+
+ spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId];
+ if (spdAddress == 0)
+ return AGESA_ERROR;
+
+ /*
+ * SMBus Base Address was set during southbridge early setup.
+ * e.g. sb700 IO mapped SMBUS_IO_BASE 0x6000
+ */
+ sm_dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB700_SM), 0);
+ ioBase = pci_read_config32(sm_dev, 0x90) & (0xFFFFFFF0);
+ setupFch(ioBase);
+
+ return readspd(ioBase, spdAddress, (void *)info->Buffer, 256);
+}
diff --git a/src/mainboard/supermicro/h8qgi/dsdt.asl b/src/mainboard/supermicro/h8qgi/dsdt.asl
new file mode 100755
index 0000000..f509fc6
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/dsdt.asl
@@ -0,0 +1,1849 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* DefinitionBlock Statement */
+DefinitionBlock (
+ "DSDT.AML", /* Output filename */
+ "DSDT", /* Signature */
+ 0x02, /* DSDT Revision, needs to be 2 for 64bit */
+ "AMD ", /* OEMID */
+ "H8QGI ", /* TABLE ID */
+ 0x00010001 /* OEM Revision */
+ )
+{ /* Start of ASL file */
+ /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */
+
+ /* Data to be patched by the BIOS during POST */
+ /* FIXME the patching is not done yet! */
+ /* Memory related values */
+ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
+ Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+ Name(PBLN, 0x0) /* Length of BIOS area */
+
+ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
+ Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
+
+ Name(HPBA, 0xFED00000) /* Base address of HPET table */
+ Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
+
+ /* USB overcurrent mapping pins. */
+ Name(UOM0, 0)
+ Name(UOM1, 2)
+ Name(UOM2, 0)
+ Name(UOM3, 7)
+ Name(UOM4, 2)
+ Name(UOM5, 2)
+ Name(UOM6, 6)
+ Name(UOM7, 2)
+ Name(UOM8, 6)
+ Name(UOM9, 6)
+
+ /* Some global data */
+ Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+ Name(OSV, Ones) /* Assume nothing */
+ Name(PMOD, One) /* Assume APIC */
+
+ /*
+ * Processor Object
+ *
+ */
+ Scope (\_PR) { /* define processor scope */
+ Processor(
+ P000, /* name space name */
+ 0x00, /* Unique number for this processor */
+ 0x810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ //#include "acpi/cpstate.asl"
+ }
+ Processor(P001, 0x01, 0x00000000, 0x00) {}
+ Processor(P002, 0x02, 0x00000000, 0x00) {}
+ Processor(P003, 0x03, 0x00000000, 0x00) {}
+ Processor(P004, 0x04, 0x00000000, 0x00) {}
+ Processor(P005, 0x05, 0x00000000, 0x00) {}
+ Processor(P006, 0x06, 0x00000000, 0x00) {}
+ Processor(P007, 0x07, 0x00000000, 0x00) {}
+ Processor(P008, 0x08, 0x00000000, 0x00) {}
+ Processor(P009, 0x09, 0x00000000, 0x00) {}
+ Processor(P00A, 0x0A, 0x00000000, 0x00) {}
+ Processor(P00B, 0x0B, 0x00000000, 0x00) {}
+ Processor(P00C, 0x0C, 0x00000000, 0x00) {}
+ Processor(P00D, 0x0D, 0x00000000, 0x00) {}
+ Processor(P00E, 0x0E, 0x00000000, 0x00) {}
+ Processor(P00F, 0x0F, 0x00000000, 0x00) {}
+ Processor(P010, 0x10, 0x00000000, 0x00) {}
+ Processor(P011, 0x11, 0x00000000, 0x00) {}
+ Processor(P012, 0x12, 0x00000000, 0x00) {}
+ Processor(P013, 0x13, 0x00000000, 0x00) {}
+ Processor(P014, 0x14, 0x00000000, 0x00) {}
+ Processor(P015, 0x15, 0x00000000, 0x00) {}
+ Processor(P016, 0x16, 0x00000000, 0x00) {}
+ Processor(P017, 0x17, 0x00000000, 0x00) {}
+ Processor(P018, 0x18, 0x00000000, 0x00) {}
+ Processor(P019, 0x19, 0x00000000, 0x00) {}
+ Processor(P01A, 0x1A, 0x00000000, 0x00) {}
+ Processor(P01B, 0x1B, 0x00000000, 0x00) {}
+ Processor(P01C, 0x1C, 0x00000000, 0x00) {}
+ Processor(P01D, 0x1D, 0x00000000, 0x00) {}
+ Processor(P01E, 0x1E, 0x00000000, 0x00) {}
+ Processor(P01F, 0x1F, 0x00000000, 0x00) {}
+ Processor(P020, 0x20, 0x00000000, 0x00) {}
+ Processor(P021, 0x21, 0x00000000, 0x00) {}
+ Processor(P022, 0x22, 0x00000000, 0x00) {}
+ Processor(P023, 0x23, 0x00000000, 0x00) {}
+ Processor(P024, 0x24, 0x00000000, 0x00) {}
+ Processor(P025, 0x25, 0x00000000, 0x00) {}
+ Processor(P026, 0x26, 0x00000000, 0x00) {}
+ Processor(P027, 0x27, 0x00000000, 0x00) {}
+ Processor(P028, 0x28, 0x00000000, 0x00) {}
+ Processor(P029, 0x29, 0x00000000, 0x00) {}
+ Processor(P02A, 0x2A, 0x00000000, 0x00) {}
+ Processor(P02B, 0x2B, 0x00000000, 0x00) {}
+ Processor(P02C, 0x2C, 0x00000000, 0x00) {}
+ Processor(P02D, 0x2D, 0x00000000, 0x00) {}
+ Processor(P02E, 0x2E, 0x00000000, 0x00) {}
+ Processor(P02F, 0x2F, 0x00000000, 0x00) {}
+ Alias (P000, CPU0)
+ Alias (P001, CPU1)
+ Alias (P002, CPU2)
+ Alias (P003, CPU3)
+ Alias (P004, CPU4)
+ Alias (P005, CPU5)
+ Alias (P006, CPU6)
+ Alias (P007, CPU7)
+ Alias (P008, CPU8)
+ } /* End _PR scope */
+
+ /* PIC IRQ mapping registers, C00h-C01h */
+ OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
+ Field(PRQM, ByteAcc, NoLock, Preserve) {
+ PRQI, 0x00000008,
+ PRQD, 0x00000008, /* Offset: 1h */
+ }
+ IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
+ PINA, 0x00000008, /* Index 0 */
+ PINB, 0x00000008, /* Index 1 */
+ PINC, 0x00000008, /* Index 2 */
+ PIND, 0x00000008, /* Index 3 */
+ AINT, 0x00000008, /* Index 4 */
+ SINT, 0x00000008, /* Index 5 */
+ , 0x00000008, /* Index 6 */
+ AAUD, 0x00000008, /* Index 7 */
+ AMOD, 0x00000008, /* Index 8 */
+ PINE, 0x00000008, /* Index 9 */
+ PINF, 0x00000008, /* Index A */
+ PING, 0x00000008, /* Index B */
+ PINH, 0x00000008, /* Index C */
+ }
+
+ /* PCI Error control register */
+ OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
+ Field(PERC, ByteAcc, NoLock, Preserve) {
+ SENS, 0x00000001,
+ PENS, 0x00000001,
+ SENE, 0x00000001,
+ PENE, 0x00000001,
+ }
+
+ /* Client Management index/data registers */
+ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
+ Field(CMT, ByteAcc, NoLock, Preserve) {
+ CMTI, 8,
+ /* Client Management Data register */
+ G64E, 1,
+ G64O, 1,
+ G32O, 2,
+ , 2,
+ GPSL, 2,
+ }
+
+ /* GPM Port register */
+ OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
+ Field(GPT, ByteAcc, NoLock, Preserve) {
+ GPB0,1,
+ GPB1,1,
+ GPB2,1,
+ GPB3,1,
+ GPB4,1,
+ GPB5,1,
+ GPB6,1,
+ GPB7,1,
+ }
+
+ /* Flash ROM program enable register */
+ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
+ Field(FRE, ByteAcc, NoLock, Preserve) {
+ , 0x00000006,
+ FLRE, 0x00000001,
+ }
+
+ /* PM2 index/data registers */
+ OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
+ Field(PM2R, ByteAcc, NoLock, Preserve) {
+ PM2I, 0x00000008,
+ PM2D, 0x00000008,
+ }
+
+ /* Power Management I/O registers */
+ OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
+ Field(PIOR, ByteAcc, NoLock, Preserve) {
+ PIOI, 0x00000008,
+ PIOD, 0x00000008,
+ }
+ IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
+ Offset(0x00), /* MiscControl */
+ , 1,
+ T1EE, 1,
+ T2EE, 1,
+ Offset(0x01), /* MiscStatus */
+ , 1,
+ T1E, 1,
+ T2E, 1,
+ Offset(0x04), /* SmiWakeUpEventEnable3 */
+ , 7,
+ SSEN, 1,
+ Offset(0x07), /* SmiWakeUpEventStatus3 */
+ , 7,
+ CSSM, 1,
+ Offset(0x10), /* AcpiEnable */
+ , 6,
+ PWDE, 1,
+ Offset(0x1C), /* ProgramIoEnable */
+ , 3,
+ MKME, 1,
+ IO3E, 1,
+ IO2E, 1,
+ IO1E, 1,
+ IO0E, 1,
+ Offset(0x1D), /* IOMonitorStatus */
+ , 3,
+ MKMS, 1,
+ IO3S, 1,
+ IO2S, 1,
+ IO1S, 1,
+ IO0S,1,
+ Offset(0x20), /* AcpiPmEvtBlk */
+ APEB, 16,
+ Offset(0x36), /* GEvtLevelConfig */
+ , 6,
+ ELC6, 1,
+ ELC7, 1,
+ Offset(0x37), /* GPMLevelConfig0 */
+ , 3,
+ PLC0, 1,
+ PLC1, 1,
+ PLC2, 1,
+ PLC3, 1,
+ PLC8, 1,
+ Offset(0x38), /* GPMLevelConfig1 */
+ , 1,
+ PLC4, 1,
+ PLC5, 1,
+ , 1,
+ PLC6, 1,
+ PLC7, 1,
+ Offset(0x3B), /* PMEStatus1 */
+ GP0S, 1,
+ GM4S, 1,
+ GM5S, 1,
+ APS, 1,
+ GM6S, 1,
+ GM7S, 1,
+ GP2S, 1,
+ STSS, 1,
+ Offset(0x55), /* SoftPciRst */
+ SPRE, 1,
+ , 1,
+ , 1,
+ PNAT, 1,
+ PWMK, 1,
+ PWNS, 1,
+
+ /* Offset(0x61), */ /* Options_1 */
+ /* ,7, */
+ /* R617,1, */
+
+ Offset(0x65), /* UsbPMControl */
+ , 4,
+ URRE, 1,
+ Offset(0x68), /* MiscEnable68 */
+ , 3,
+ TMTE, 1,
+ , 1,
+ Offset(0x92), /* GEVENTIN */
+ , 7,
+ E7IS, 1,
+ Offset(0x96), /* GPM98IN */
+ G8IS, 1,
+ G9IS, 1,
+ Offset(0x9A), /* EnhanceControl */
+ ,7,
+ HPDE, 1,
+ Offset(0xA8), /* PIO7654Enable */
+ IO4E, 1,
+ IO5E, 1,
+ IO6E, 1,
+ IO7E, 1,
+ Offset(0xA9), /* PIO7654Status */
+ IO4S, 1,
+ IO5S, 1,
+ IO6S, 1,
+ IO7S, 1,
+ }
+
+ /* PM1 Event Block
+ * First word is PM1_Status, Second word is PM1_Enable
+ */
+ OperationRegion(P1EB, SystemIO, APEB, 0x04)
+ Field(P1EB, ByteAcc, NoLock, Preserve) {
+ TMST, 1,
+ , 3,
+ BMST, 1,
+ GBST, 1,
+ Offset(0x01),
+ PBST, 1,
+ , 1,
+ RTST, 1,
+ , 3,
+ PWST, 1,
+ SPWS, 1,
+ Offset(0x02),
+ TMEN, 1,
+ , 4,
+ GBEN, 1,
+ Offset(0x03),
+ PBEN, 1,
+ , 1,
+ RTEN, 1,
+ , 3,
+ PWDA, 1,
+ }
+
+ OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
+ Field (GRAM, ByteAcc, Lock, Preserve)
+ {
+ Offset (0x10),
+ FLG0, 8
+ }
+
+ Scope(\_SB) {
+ /* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */
+ OperationRegion(PCFG, SystemMemory, PCBA, PCLN)
+ Field(PCFG, ByteAcc, NoLock, Preserve) {
+ /* Byte offsets are computed using the following technique:
+ * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
+ * The 8 comes from 8 functions per device, and 4096 bytes per function config space
+ */
+ Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
+ STB5, 32,
+ Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
+ PT0D, 1,
+ PT1D, 1,
+ PT2D, 1,
+ PT3D, 1,
+ PT4D, 1,
+ PT5D, 1,
+ PT6D, 1,
+ PT7D, 1,
+ PT8D, 1,
+ PT9D, 1,
+ Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
+ SBIE, 1,
+ SBME, 1,
+ Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
+ SBRI, 8,
+ Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
+ SBB1, 32,
+ Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
+ ,14,
+ P92E, 1, /* Port92 decode enable */
+ }
+
+ OperationRegion(SB5, SystemMemory, STB5, 0x1000)
+ Field(SB5, AnyAcc, NoLock, Preserve){
+ /* Port 0 */
+ Offset(0x120), /* Port 0 Task file status */
+ P0ER, 1,
+ , 2,
+ P0DQ, 1,
+ , 3,
+ P0BY, 1,
+ Offset(0x128), /* Port 0 Serial ATA status */
+ P0DD, 4,
+ , 4,
+ P0IS, 4,
+ Offset(0x12C), /* Port 0 Serial ATA control */
+ P0DI, 4,
+ Offset(0x130), /* Port 0 Serial ATA error */
+ , 16,
+ P0PR, 1,
+
+ /* Port 1 */
+ offset(0x1A0), /* Port 1 Task file status */
+ P1ER, 1,
+ , 2,
+ P1DQ, 1,
+ , 3,
+ P1BY, 1,
+ Offset(0x1A8), /* Port 1 Serial ATA status */
+ P1DD, 4,
+ , 4,
+ P1IS, 4,
+ Offset(0x1AC), /* Port 1 Serial ATA control */
+ P1DI, 4,
+ Offset(0x1B0), /* Port 1 Serial ATA error */
+ , 16,
+ P1PR, 1,
+
+ /* Port 2 */
+ Offset(0x220), /* Port 2 Task file status */
+ P2ER, 1,
+ , 2,
+ P2DQ, 1,
+ , 3,
+ P2BY, 1,
+ Offset(0x228), /* Port 2 Serial ATA status */
+ P2DD, 4,
+ , 4,
+ P2IS, 4,
+ Offset(0x22C), /* Port 2 Serial ATA control */
+ P2DI, 4,
+ Offset(0x230), /* Port 2 Serial ATA error */
+ , 16,
+ P2PR, 1,
+
+ /* Port 3 */
+ Offset(0x2A0), /* Port 3 Task file status */
+ P3ER, 1,
+ , 2,
+ P3DQ, 1,
+ , 3,
+ P3BY, 1,
+ Offset(0x2A8), /* Port 3 Serial ATA status */
+ P3DD, 4,
+ , 4,
+ P3IS, 4,
+ Offset(0x2AC), /* Port 3 Serial ATA control */
+ P3DI, 4,
+ Offset(0x2B0), /* Port 3 Serial ATA error */
+ , 16,
+ P3PR, 1,
+ }
+ }
+
+ #include "acpi/routing.asl"
+
+ Scope(\_SB) {
+ Method(CkOT, 0){
+ if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */
+ if(CondRefOf(\_OSI,Local1))
+ {
+ Store(1, OSTP) /* Assume some form of XP */
+ if (\_OSI("Windows 2006")) /* Vista */
+ {
+ Store(2, OSTP)
+ }
+ } else {
+ If(WCMP(\_OS,"Linux")) {
+ Store(3, OSTP) /* Linux */
+ } Else {
+ Store(4, OSTP) /* Gotta be WinCE */
+ }
+ }
+ Return(OSTP)
+ }
+
+ Method(_PIC, 0x01, NotSerialized)
+ {
+ If (Arg0)
+ {
+ \_SB.CIRQ()
+ }
+ Store(Arg0, PMOD)
+ }
+ Method(CIRQ, 0x00, NotSerialized){
+ Store(0, PINA)
+ Store(0, PINB)
+ Store(0, PINC)
+ Store(0, PIND)
+ Store(0, PINE)
+ Store(0, PINF)
+ Store(0, PING)
+ Store(0, PINH)
+ }
+
+ Name(IRQB, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Shared){15}
+ })
+
+ Name(IRQP, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
+ })
+
+ Name(PITF, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Exclusive){9}
+ })
+
+ Device(INTA) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 1)
+
+ Method(_STA, 0) {
+ if (PINA) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTA._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKA\\_DIS\n") */
+ Store(0, PINA)
+ } /* End Method(_SB.INTA._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKA\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTA._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKA\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINA, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTA._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKA\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINA)
+ } /* End Method(_SB.INTA._SRS) */
+ } /* End Device(INTA) */
+
+ Device(INTB) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 2)
+
+ Method(_STA, 0) {
+ if (PINB) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTB._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKB\\_DIS\n") */
+ Store(0, PINB)
+ } /* End Method(_SB.INTB._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKB\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTB._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKB\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINB, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTB._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKB\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINB)
+ } /* End Method(_SB.INTB._SRS) */
+ } /* End Device(INTB) */
+
+ Device(INTC) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 3)
+
+ Method(_STA, 0) {
+ if (PINC) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTC._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKC\\_DIS\n") */
+ Store(0, PINC)
+ } /* End Method(_SB.INTC._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKC\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTC._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKC\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINC, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTC._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKC\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINC)
+ } /* End Method(_SB.INTC._SRS) */
+ } /* End Device(INTC) */
+
+ Device(INTD) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 4)
+
+ Method(_STA, 0) {
+ if (PIND) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTD._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKD\\_DIS\n") */
+ Store(0, PIND)
+ } /* End Method(_SB.INTD._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKD\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTD._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKD\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIND, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTD._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKD\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PIND)
+ } /* End Method(_SB.INTD._SRS) */
+ } /* End Device(INTD) */
+
+ Device(INTE) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 5)
+
+ Method(_STA, 0) {
+ if (PINE) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTE._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKE\\_DIS\n") */
+ Store(0, PINE)
+ } /* End Method(_SB.INTE._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKE\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTE._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKE\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINE, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTE._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKE\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINE)
+ } /* End Method(_SB.INTE._SRS) */
+ } /* End Device(INTE) */
+
+ Device(INTF) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 6)
+
+ Method(_STA, 0) {
+ if (PINF) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTF._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKF\\_DIS\n") */
+ Store(0, PINF)
+ } /* End Method(_SB.INTF._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKF\\_PRS\n") */
+ Return(PITF)
+ } /* Method(_SB.INTF._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKF\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINF, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTF._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKF\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINF)
+ } /* End Method(_SB.INTF._SRS) */
+ } /* End Device(INTF) */
+
+ Device(INTG) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 7)
+
+ Method(_STA, 0) {
+ if (PING) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTG._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKG\\_DIS\n") */
+ Store(0, PING)
+ } /* End Method(_SB.INTG._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKG\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTG._CRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKG\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PING, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTG._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKG\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PING)
+ } /* End Method(_SB.INTG._SRS) */
+ } /* End Device(INTG) */
+
+ Device(INTH) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 8)
+
+ Method(_STA, 0) {
+ if (PINH) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTH._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKH\\_DIS\n") */
+ Store(0, PINH)
+ } /* End Method(_SB.INTH._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKH\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTH._CRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKH\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINH, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTH._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKH\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINH)
+ } /* End Method(_SB.INTH._SRS) */
+ } /* End Device(INTH) */
+
+ } /* End Scope(_SB) */
+
+
+ /* Supported sleep states: */
+ Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
+
+ If (LAnd(SSFG, 0x01)) {
+ Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
+ }
+ If (LAnd(SSFG, 0x02)) {
+ Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
+ }
+ If (LAnd(SSFG, 0x04)) {
+ Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
+ }
+ If (LAnd(SSFG, 0x08)) {
+ Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
+ }
+
+ Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
+
+ Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
+ Name(CSMS, 0) /* Current System State */
+
+ /* Wake status package */
+ Name(WKST,Package(){Zero, Zero})
+
+ /*
+ * \_PTS - Prepare to Sleep method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2, etc
+ *
+ * Exit:
+ * -none-
+ *
+ * The _PTS control method is executed at the beginning of the sleep process
+ * for S1-S5. The sleeping value is passed to the _PTS control method. This
+ * control method may be executed a relatively long time before entering the
+ * sleep state and the OS may abort the operation without notification to
+ * the ACPI driver. This method cannot modify the configuration or power
+ * state of any device in the system.
+ */
+ Method(\_PTS, 1) {
+ /* DBGO("\\_PTS\n") */
+ /* DBGO("From S0 to S") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+
+ /* Don't allow PCIRST# to reset USB */
+ if (LEqual(Arg0,3)){
+ Store(0,URRE)
+ }
+
+ /* Clear sleep SMI status flag and enable sleep SMI trap. */
+ /*Store(One, CSSM)
+ Store(One, SSEN)*/
+
+ /* On older chips, clear PciExpWakeDisEn */
+ /*if (LLessEqual(\_SB.SBRI, 0x13)) {
+ * Store(0,\_SB.PWDE)
+ *}
+ */
+
+ /* Clear wake status structure. */
+ Store(0, Index(WKST,0))
+ Store(0, Index(WKST,1))
+ \_SB.PCI0.SIOS (Arg0)
+ } /* End Method(\_PTS) */
+
+ /*
+ * The following method results in a "not a valid reserved NameSeg"
+ * warning so I have commented it out for the duration. It isn't
+ * used, so it could be removed.
+ *
+ *
+ * \_GTS OEM Going To Sleep method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
+ *
+ * Exit:
+ * -none-
+ *
+ * Method(\_GTS, 1) {
+ * DBGO("\\_GTS\n")
+ * DBGO("From S0 to S")
+ * DBGO(Arg0)
+ * DBGO("\n")
+ * }
+ */
+
+ /*
+ * \_BFS OEM Back From Sleep method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
+ *
+ * Exit:
+ * -none-
+ */
+ Method(\_BFS, 1) {
+ /* DBGO("\\_BFS\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+ }
+
+ /*
+ * \_WAK System Wake method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
+ *
+ * Exit:
+ * Return package of 2 DWords
+ * Dword 1 - Status
+ * 0x00000000 wake succeeded
+ * 0x00000001 Wake was signaled but failed due to lack of power
+ * 0x00000002 Wake was signaled but failed due to thermal condition
+ * Dword 2 - Power Supply state
+ * if non-zero the effective S-state the power supply entered
+ */
+ Method(\_WAK, 1) {
+ /* DBGO("\\_WAK\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+
+ /* Re-enable HPET */
+ Store(1,HPDE)
+
+ /* Restore PCIRST# so it resets USB */
+ if (LEqual(Arg0,3)){
+ Store(1,URRE)
+ }
+
+ /* Arbitrarily clear PciExpWakeStatus */
+ Store(PWST, PWST)
+
+ /* if(DeRefOf(Index(WKST,0))) {
+ * Store(0, Index(WKST,1))
+ * } else {
+ * Store(Arg0, Index(WKST,1))
+ * }
+ */
+ \_SB.PCI0.SIOW (Arg0)
+ Return(WKST)
+ } /* End Method(\_WAK) */
+
+ Scope(\_GPE) { /* Start Scope GPE */
+ /* General event 0 */
+ /* Method(_L00) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 1 */
+ /* Method(_L01) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 2 */
+ /* Method(_L02) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 3 */
+ Method(_L03) {
+ /* DBGO("\\_GPE\\_L00\n") */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* General event 4 */
+ /* Method(_L04) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 5 */
+ /* Method(_L05) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 6 - Used for GPM6, moved to USB.asl */
+ /* Method(_L06) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 7 - Used for GPM7, moved to USB.asl */
+ /* Method(_L07) {
+ * DBGO("\\_GPE\\_L07\n")
+ * }
+ */
+
+ /* Legacy PM event */
+ Method(_L08) {
+ /* DBGO("\\_GPE\\_L08\n") */
+ }
+
+ /* Temp warning (TWarn) event */
+ Method(_L09) {
+ /* DBGO("\\_GPE\\_L09\n") */
+ Notify (\_TZ.TZ00, 0x80)
+ }
+
+ /* Reserved */
+ /* Method(_L0A) {
+ * DBGO("\\_GPE\\_L0A\n")
+ * }
+ */
+
+ /* USB controller PME# */
+ Method(_L0B) {
+ /* DBGO("\\_GPE\\_L0B\n") */
+ Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* AC97 controller PME# */
+ /* Method(_L0C) {
+ * DBGO("\\_GPE\\_L0C\n")
+ * }
+ */
+
+ /* OtherTherm PME# */
+ /* Method(_L0D) {
+ * DBGO("\\_GPE\\_L0D\n")
+ * }
+ */
+
+ /* GPM9 SCI event - Moved to USB.asl */
+ /* Method(_L0E) {
+ * DBGO("\\_GPE\\_L0E\n")
+ * }
+ */
+
+ /* PCIe HotPlug event */
+ /* Method(_L0F) {
+ * DBGO("\\_GPE\\_L0F\n")
+ * }
+ */
+
+ /* ExtEvent0 SCI event */
+ Method(_L10) {
+ /* DBGO("\\_GPE\\_L10\n") */
+ }
+
+
+ /* ExtEvent1 SCI event */
+ Method(_L11) {
+ /* DBGO("\\_GPE\\_L11\n") */
+ }
+
+ /* PCIe PME# event */
+ /* Method(_L12) {
+ * DBGO("\\_GPE\\_L12\n")
+ * }
+ */
+
+ /* GPM0 SCI event - Moved to USB.asl */
+ /* Method(_L13) {
+ * DBGO("\\_GPE\\_L13\n")
+ * }
+ */
+
+ /* GPM1 SCI event - Moved to USB.asl */
+ /* Method(_L14) {
+ * DBGO("\\_GPE\\_L14\n")
+ * }
+ */
+
+ /* GPM2 SCI event - Moved to USB.asl */
+ /* Method(_L15) {
+ * DBGO("\\_GPE\\_L15\n")
+ * }
+ */
+
+ /* GPM3 SCI event - Moved to USB.asl */
+ /* Method(_L16) {
+ * DBGO("\\_GPE\\_L16\n")
+ * }
+ */
+
+ /* GPM8 SCI event - Moved to USB.asl */
+ /* Method(_L17) {
+ * DBGO("\\_GPE\\_L17\n")
+ * }
+ */
+
+ /* GPIO0 or GEvent8 event */
+ Method(_L18) {
+ /* DBGO("\\_GPE\\_L18\n") */
+ Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* GPM4 SCI event - Moved to USB.asl */
+ /* Method(_L19) {
+ * DBGO("\\_GPE\\_L19\n")
+ * }
+ */
+
+ /* GPM5 SCI event - Moved to USB.asl */
+ /* Method(_L1A) {
+ * DBGO("\\_GPE\\_L1A\n")
+ * }
+ */
+
+ /* Azalia SCI event */
+ Method(_L1B) {
+ /* DBGO("\\_GPE\\_L1B\n") */
+ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* GPM6 SCI event - Reassigned to _L06 */
+ /* Method(_L1C) {
+ * DBGO("\\_GPE\\_L1C\n")
+ * }
+ */
+
+ /* GPM7 SCI event - Reassigned to _L07 */
+ /* Method(_L1D) {
+ * DBGO("\\_GPE\\_L1D\n")
+ * }
+ */
+
+ /* GPIO2 or GPIO66 SCI event */
+ /* Method(_L1E) {
+ * DBGO("\\_GPE\\_L1E\n")
+ * }
+ */
+
+ /* SATA SCI event - Moved to sata.asl */
+ /* Method(_L1F) {
+ * DBGO("\\_GPE\\_L1F\n")
+ * }
+ */
+
+ } /* End Scope GPE */
+
+ #include "acpi/usb.asl"
+
+ /* System Bus */
+ Scope(\_SB) { /* Start \_SB scope */
+ #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */
+
+ /* _SB.PCI0 */
+ /* Note: Only need HID on Primary Bus */
+ Device(PCI0) {
+ External (TOM1) //assigned when update_ssdt()
+ External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
+
+ Name(_HID, EISAID("PNP0A03"))
+ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
+ Method(_BBN, 0) { /* Bus number = 0 */
+ Return(0)
+ }
+ Method(_STA, 0) {
+ /* DBGO("\\_SB\\PCI0\\_STA\n") */
+ Return(0x0B) /* Status is visible */
+ }
+
+ Method(_PRT,0) {
+ If(PMOD){ Return(APR0) } /* APIC mode */
+ Return (PR0) /* PIC Mode */
+ } /* end _PRT */
+
+ /* Describe the Northbridge devices */
+ Device(AMRT) {
+ Name(_ADR, 0x00000000)
+ } /* end AMRT */
+
+ /* The external GFX bridge */
+ Device(PBR2) {
+ Name(_ADR, 0x00020000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS2) } /* APIC mode */
+ Return (PS2) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR2 */
+
+ /* Dev3 is also an external GFX bridge */
+
+ Device(PBR4) {
+ Name(_ADR, 0x00040000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS4) } /* APIC mode */
+ Return (PS4) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR4 */
+
+ Device(PBRb) {
+ Name(_ADR, 0x000b0000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APSb) } /* APIC mode */
+ Return (PSb) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBRb */
+
+ Device(PBRc) {
+ Name(_ADR, 0x000c0000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APSc) } /* APIC mode */
+ Return (PSc) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBRc */
+
+ Device(PBRd) {
+ Name(_ADR, 0x000d0000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APSd) } /* APIC mode */
+ Return (PSd) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBRd */
+
+ /* Describe the Southbridge devices */
+ Device(STCR) {
+ Name(_ADR, 0x00110000)
+ #include "acpi/sata.asl"
+ } /* end STCR */
+
+ Device(UOH1) {
+ Name(_ADR, 0x00130000)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH1 */
+
+ Device(UOH2) {
+ Name(_ADR, 0x00130001)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH2 */
+
+ Device(UOH3) {
+ Name(_ADR, 0x00130002)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH3 */
+
+ Device(UOH4) {
+ Name(_ADR, 0x00130003)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH4 */
+
+ Device(UOH5) {
+ Name(_ADR, 0x00130004)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH5 */
+
+ Device(UEH1) {
+ Name(_ADR, 0x00130005)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UEH1 */
+
+ Device(SBUS) {
+ Name(_ADR, 0x00140000)
+ } /* end SBUS */
+
+ /* Primary (and only) IDE channel */
+ Device(IDEC) {
+ Name(_ADR, 0x00140001)
+ #include "acpi/ide.asl"
+ } /* end IDEC */
+
+ Device(AZHD) {
+ Name(_ADR, 0x00140002)
+ OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
+ Field(AZPD, AnyAcc, NoLock, Preserve) {
+ offset (0x42),
+ NSDI, 1,
+ NSDO, 1,
+ NSEN, 1,
+ offset (0x44),
+ IPCR, 4,
+ offset (0x54),
+ PWST, 2,
+ , 6,
+ PMEB, 1,
+ , 6,
+ PMST, 1,
+ offset (0x62),
+ MMCR, 1,
+ offset (0x64),
+ MMLA, 32,
+ offset (0x68),
+ MMHA, 32,
+ offset (0x6C),
+ MMDT, 16,
+ }
+
+ Method(_INI) {
+ If(LEqual(OSTP,3)){ /* If we are running Linux */
+ Store(zero, NSEN)
+ Store(one, NSDO)
+ Store(one, NSDI)
+ }
+ }
+ } /* end AZHD */
+
+ Device(LIBR) {
+ Name(_ADR, 0x00140003)
+ /* Method(_INI) {
+ * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
+ } */ /* End Method(_SB.SBRDG._INI) */
+
+ /* Real Time Clock Device */
+ Device(RTC0) {
+ Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
+ Name(_CRS, ResourceTemplate() {
+ IRQNoFlags(){8}
+ IO(Decode16,0x0070, 0x0070, 0, 2)
+ /* IO(Decode16,0x0070, 0x0070, 0, 4) */
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
+
+ Device(TMR) { /* Timer */
+ Name(_HID,EISAID("PNP0100")) /* System Timer */
+ Name(_CRS, ResourceTemplate() {
+ IRQNoFlags(){0}
+ IO(Decode16, 0x0040, 0x0040, 0, 4)
+ /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
+
+ Device(SPKR) { /* Speaker */
+ Name(_HID,EISAID("PNP0800")) /* AT style speaker */
+ Name(_CRS, ResourceTemplate() {
+ IO(Decode16, 0x0061, 0x0061, 0, 1)
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
+
+ Device(PIC) {
+ Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
+ Name(_CRS, ResourceTemplate() {
+ IRQNoFlags(){2}
+ IO(Decode16,0x0020, 0x0020, 0, 2)
+ IO(Decode16,0x00A0, 0x00A0, 0, 2)
+ /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
+ /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
+
+ Device(MAD) { /* 8257 DMA */
+ Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
+ Name(_CRS, ResourceTemplate() {
+ DMA(Compatibility,BusMaster,Transfer8){4}
+ IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
+ IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
+ IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
+ IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
+ IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
+ IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
+ }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
+ } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
+
+ Device(COPR) {
+ Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
+ Name(_CRS, ResourceTemplate() {
+ IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
+ IRQNoFlags(){13}
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+
+ Device (PS2M) {
+ Name (_HID, EisaId ("PNP0F13"))
+ Name (_CRS, ResourceTemplate () {
+ IO (Decode16, 0x0060, 0x0060, 0x00, 0x01)
+ IO (Decode16, 0x0064, 0x0064, 0x00, 0x01)
+ IRQNoFlags () {12}
+ })
+ Method (_STA, 0, NotSerialized) {
+ And (FLG0, 0x04, Local0)
+ If (LEqual (Local0, 0x04)) {
+ Return (0x0F)
+ } Else {
+ Return (0x00)
+ }
+ }
+ }
+
+ Device (PS2K) {
+ Name (_HID, EisaId ("PNP0303"))
+ Method (_STA, 0, NotSerialized) {
+ And (FLG0, 0x04, Local0)
+ If (LEqual (Local0, 0x04)) {
+ Return (0x0F)
+ } Else {
+ Return (0x00)
+ }
+ }
+ Name (_CRS, ResourceTemplate () {
+ IO (Decode16, 0x0060, 0x0060, 0x00, 0x01)
+ IO (Decode16, 0x0064, 0x0064, 0x00, 0x01)
+ IRQNoFlags () {1}
+ })
+ }
+
+#if 0 //acpi_create_hpet
+ Device(HPET) {
+ Name(_HID,EISAID("PNP0103"))
+ Name(CRS, ResourceTemplate() {
+ IRQNoFlags () {0}
+ IRQNoFlags () {2}
+ IRQNoFlags () {8}
+ Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, MNT) /* 1kb reserved space */
+ })
+ Method(_STA, 0, NotSerialized) {
+ Return(0x0F) /* sata is visible */
+ }
+ Method(_CRS, 0, NotSerialized) {
+ CreateDwordField(CRS, ^MNT._BAS, HPT)
+ Store(HPBA, HPT)
+ Return(CRS)
+ }
+ } /* End Device(_SB.PCI0.LIBR.HPET) */
+#endif
+ } /* end LIBR */
+
+ Device(HPBR) {
+ Name(_ADR, 0x00140004)
+ } /* end HostPciBr */
+
+ Device(ACAD) {
+ Name(_ADR, 0x00140005)
+ } /* end Ac97audio */
+
+ Device(ACMD) {
+ Name(_ADR, 0x00140006)
+ } /* end Ac97modem */
+
+ /* ITE8718 Support */
+ OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */
+ Field (IOID, ByteAcc, NoLock, Preserve)
+ {
+ SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */
+ }
+
+ IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x07),
+ LDN, 8, /* Logical Device Number */
+ Offset (0x20),
+ CID1, 8, /* Chip ID Byte 1, 0x87 */
+ CID2, 8, /* Chip ID Byte 2, 0x12 */
+ Offset (0x30),
+ ACTR, 8, /* Function activate */
+ Offset (0xF0),
+ APC0, 8, /* APC/PME Event Enable Register */
+ APC1, 8, /* APC/PME Status Register */
+ APC2, 8, /* APC/PME Control Register 1 */
+ APC3, 8, /* Environment Controller Special Configuration Register */
+ APC4, 8 /* APC/PME Control Register 2 */
+ }
+
+ /* Enter the 8718 MB PnP Mode */
+ Method (EPNP)
+ {
+ Store(0x87, SIOI)
+ Store(0x01, SIOI)
+ Store(0x55, SIOI)
+ Store(0x55, SIOI) /* 8718 magic number */
+ }
+ /* Exit the 8718 MB PnP Mode */
+ Method (XPNP)
+ {
+ Store (0x02, SIOI)
+ Store (0x02, SIOD)
+ }
+ /*
+ * Keyboard PME is routed to SB700 Gevent3. We can wake
+ * up the system by pressing the key.
+ */
+ Method (SIOS, 1)
+ {
+ /* We only enable KBD PME for S5. */
+ If (LLess (Arg0, 0x05))
+ {
+ EPNP()
+ /* DBGO("8718F\n") */
+
+ Store (0x4, LDN)
+ Store (One, ACTR) /* Enable EC */
+ /*
+ Store (0x4, LDN)
+ Store (0x04, APC4)
+ */ /* falling edge. which mode? Not sure. */
+
+ Store (0x4, LDN)
+ Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
+ Store (0x4, LDN)
+ Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
+
+ XPNP()
+ }
+ }
+ Method (SIOW, 1)
+ {
+ EPNP()
+ Store (0x4, LDN)
+ Store (Zero, APC0) /* disable keyboard PME */
+ Store (0x4, LDN)
+ Store (0xFF, APC1) /* clear keyboard PME status */
+ XPNP()
+ }
+
+ Name (CRS, ResourceTemplate ()
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x00FF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0100, // Length
+ ,,)
+ IO (Decode16,
+ 0x0CF8, // Range Minimum
+ 0x0CF8, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x03AF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x03B0, // Length
+ ,, , TypeStatic)
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x03E0, // Range Minimum
+ 0x0CF7, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0918, // Length
+ ,, , TypeStatic)
+
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x03B0, // Range Minimum
+ 0x03BB, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x000C, // Length
+ ,, , TypeStatic)
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x03C0, // Range Minimum
+ 0x03DF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0020, // Length
+ ,, , TypeStatic)
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x9000, // Range Minimum
+ 0xefff, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x6000, // Length
+ ,, , TypeStatic)
+ Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) // VGA memory space
+
+ Memory32Fixed (ReadOnly,
+ 0xE0000000, // Address Base
+ 0x10000000, // Address Length, (1MB each Bus, 256 Buses by default)
+ MMIO)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0xF0000000, // Range Minimum
+ 0xFFFFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x10000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ })
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ CreateDWordField (CRS, \_SB.PCI0.MMIO._BAS, BAS1)
+ CreateDWordField (CRS, \_SB.PCI0.MMIO._LEN, LEN1)
+ Store (PCBA, BAS1)
+ Store (PCLN, LEN1)
+
+ Return (CRS)
+ }
+
+ /*
+ *
+ * FIRST METHOD CALLED UPON BOOT
+ *
+ * 1. If debugging, print current OS and ACPI interpreter.
+ * 2. Get PCI Interrupt routing from ACPI VSM, this
+ * value is based on user choice in BIOS setup.
+ */
+ Method(_INI, 0) {
+ /* DBGO("\\_SB\\_INI\n") */
+ /* DBGO(" DSDT.ASL code from ") */
+ /* DBGO(__DATE__) */
+ /* DBGO(" ") */
+ /* DBGO(__TIME__) */
+ /* DBGO("\n Sleep states supported: ") */
+ /* DBGO("\n") */
+ /* DBGO(" \\_OS=") */
+ /* DBGO(\_OS) */
+ /* DBGO("\n \\_REV=") */
+ /* DBGO(\_REV) */
+ /* DBGO("\n") */
+
+ /* Determine the OS we're running on */
+ CkOT()
+ /* On older chips, clear PciExpWakeDisEn */
+ /*if (LLessEqual(\SBRI, 0x13)) {
+ * Store(0,\PWDE)
+ *}
+ */
+ } /* End Method(_SB._INI) */
+ } /* End Device(PCI0) */
+
+ Device(PWRB) { /* Start Power button device */
+ Name(_HID, EISAID("PNP0C0C"))
+ Name(_UID, 0xAA)
+ Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
+ Name(_STA, 0x0B) /* sata is invisible */
+ }
+ } /* End \_SB scope */
+
+ Scope(\_SI) {
+ Method(_SST, 1) {
+ /* DBGO("\\_SI\\_SST\n") */
+ /* DBGO(" New Indicator state: ") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+ }
+ } /* End Scope SI */
+
+ /* SMBUS Support */
+ Mutex (SBX0, 0x00)
+ OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
+ Field (SMB0, ByteAcc, NoLock, Preserve) {
+ HSTS, 8, /* SMBUS status */
+ SSTS, 8, /* SMBUS slave status */
+ HCNT, 8, /* SMBUS control */
+ HCMD, 8, /* SMBUS host cmd */
+ HADD, 8, /* SMBUS address */
+ DAT0, 8, /* SMBUS data0 */
+ DAT1, 8, /* SMBUS data1 */
+ BLKD, 8, /* SMBUS block data */
+ SCNT, 8, /* SMBUS slave control */
+ SCMD, 8, /* SMBUS shaow cmd */
+ SEVT, 8, /* SMBUS slave event */
+ SDAT, 8 /* SMBUS slave data */
+ }
+
+ Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
+ Store (0x1E, HSTS)
+ Store (0xFA, Local0)
+ While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
+ Stall (0x64)
+ Decrement (Local0)
+ }
+
+ Return (Local0)
+ }
+
+ Method (SWTC, 1, NotSerialized) {
+ Store (Arg0, Local0)
+ Store (0x07, Local2)
+ Store (One, Local1)
+ While (LEqual (Local1, One)) {
+ Store (And (HSTS, 0x1E), Local3)
+ If (LNotEqual (Local3, Zero)) { /* read sucess */
+ If (LEqual (Local3, 0x02)) {
+ Store (Zero, Local2)
+ }
+
+ Store (Zero, Local1)
+ }
+ Else {
+ If (LLess (Local0, 0x0A)) { /* read failure */
+ Store (0x10, Local2)
+ Store (Zero, Local1)
+ }
+ Else {
+ Sleep (0x0A) /* 10 ms, try again */
+ Subtract (Local0, 0x0A, Local0)
+ }
+ }
+ }
+
+ Return (Local2)
+ }
+
+ Method (SMBR, 3, NotSerialized) {
+ Store (0x07, Local0)
+ If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
+ Store (WCLR (), Local0) /* clear SMBUS status register before read data */
+ If (LEqual (Local0, Zero)) {
+ Release (SBX0)
+ Return (0x0)
+ }
+
+ Store (0x1F, HSTS)
+ Store (Or (ShiftLeft (Arg1, One), One), HADD)
+ Store (Arg2, HCMD)
+ If (LEqual (Arg0, 0x07)) {
+ Store (0x48, HCNT) /* read byte */
+ }
+
+ Store (SWTC (0x03E8), Local1) /* 1000 ms */
+ If (LEqual (Local1, Zero)) {
+ If (LEqual (Arg0, 0x07)) {
+ Store (DAT0, Local0)
+ }
+ }
+ Else {
+ Store (Local1, Local0)
+ }
+
+ Release (SBX0)
+ }
+
+ /* DBGO("the value of SMBusData0 register ") */
+ /* DBGO(Arg2) */
+ /* DBGO(" is ") */
+ /* DBGO(Local0) */
+ /* DBGO("\n") */
+
+ Return (Local0)
+ }
+
+ /* THERMAL */
+ Scope(\_TZ) {
+ Name (KELV, 2732)
+ Name (THOT, 800)
+ Name (TCRT, 850)
+
+ ThermalZone(TZ00) {
+ Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */
+ /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
+ Return(Add(0, 2730))
+ }
+ Method(_AL0,0) { /* Returns package of cooling device to turn on */
+ /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
+ Return(Package() {\_TZ.TZ00.FAN0})
+ }
+ Device (FAN0) {
+ Name(_HID, EISAID("PNP0C0B"))
+ Name(_PR0, Package() {PFN0})
+ }
+
+ PowerResource(PFN0,0,0) {
+ Method(_STA) {
+ Store(0xF,Local0)
+ Return(Local0)
+ }
+ Method(_ON) {
+ /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
+ }
+ Method(_OFF) {
+ /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
+ }
+ }
+
+ Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */
+ /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
+ Return (Add (THOT, KELV))
+ }
+ Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */
+ /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
+ Return (Add (TCRT, KELV))
+ }
+ Method(_TMP,0) { /* return current temp of this zone */
+ Store (SMBR (0x07, 0x4C,, 0x00), Local0)
+ If (LGreater (Local0, 0x10)) {
+ Store (Local0, Local1)
+ }
+ Else {
+ Add (Local0, THOT, Local0)
+ Return (Add (400, KELV))
+ }
+
+ Store (SMBR (0x07, 0x4C, 0x01), Local0)
+ /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
+ /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
+ If (LGreater (Local0, 0x10)) {
+ If (LGreater (Local0, Local1)) {
+ Store (Local0, Local1)
+ }
+
+ Multiply (Local1, 10, Local1)
+ Return (Add (Local1, KELV))
+ }
+ Else {
+ Add (Local0, THOT, Local0)
+ Return (Add (400 , KELV))
+ }
+ } /* end of _TMP */
+ } /* end of TZ00 */
+ }
+}
+/* End of ASL file */
diff --git a/src/mainboard/supermicro/h8qgi/fadt.c b/src/mainboard/supermicro/h8qgi/fadt.c
new file mode 100755
index 0000000..c2f714d
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/fadt.c
@@ -0,0 +1,201 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+/*
+ * ACPI - create the Fixed ACPI Description Tables (FADT)
+ */
+
+
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include "southbridge/amd/sb700/sb700.h"
+
+u16 pm_base = SB700_ACPI_IO_BASE;
+/* pm_base should be set in sb acpi */
+/* pm_base should be got from bar2 of sb700. Here I compact ACPI
+ * registers into 32 bytes limit.
+ * */
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+
+ pm_base &= 0xFFFF;
+ printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
+
+ /* Prepare the header */
+ memset((void *)fadt, 0, sizeof(acpi_fadt_t));
+ memcpy(header->signature, "FACP", 4);
+ header->length = 244;
+ header->revision = 3;
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, "AMD ", 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+ header->asl_compiler_revision = 0;
+
+ fadt->firmware_ctrl = (u32) facs;
+ fadt->dsdt = (u32) dsdt;
+ /* 3=Workstation,4=Enterprise Server, 7=Performance Server */
+ fadt->preferred_pm_profile = 0x03;
+ fadt->sci_int = 9;
+ /* disable system management mode by setting to 0: */
+ fadt->smi_cmd = 0;
+ fadt->acpi_enable = 0xf0;
+ fadt->acpi_disable = 0xf1;
+ fadt->s4bios_req = 0x0;
+ fadt->pstate_cnt = 0xe2;
+
+ pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF);
+ pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8);
+ pm_iowrite(0x62, ACPI_PM1_CNT_BLK & 0xFF);
+ pm_iowrite(0x63, ACPI_PM1_CNT_BLK >> 8);
+ pm_iowrite(0x64, ACPI_PM_TMR_BLK & 0xFF);
+ pm_iowrite(0x65, ACPI_PM_TMR_BLK >> 8);
+ pm_iowrite(0x68, ACPI_GPE0_BLK & 0xFF);
+ pm_iowrite(0x69, ACPI_GPE0_BLK >> 8);
+
+ /* CpuControl is in \_PR.CPU0, 6 bytes */
+ pm_iowrite(0x66, ACPI_CPU_CONTROL & 0xFF);
+ pm_iowrite(0x67, ACPI_CPU_CONTROL >> 8);
+
+ pm_iowrite(0x6A, 0); /* AcpiSmiCmdLo */
+ pm_iowrite(0x6B, 0); /* AcpiSmiCmdHi */
+
+ pm_iowrite(0x6C, ACPI_PMA_CNT_BLK & 0xFF);
+ pm_iowrite(0x6D, ACPI_PMA_CNT_BLK >> 8);
+
+ pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses
+ * the contents of the PM registers at
+ * index 60-6B to decode ACPI I/O address.
+ * AcpiSmiEn & SmiCmdEn*/
+ /* RTC_En_En, TMR_En_En, GBL_EN_EN */
+ outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
+ fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
+ fadt->pm1b_evt_blk = 0x0000;
+ fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
+ fadt->pm1b_cnt_blk = 0x0000;
+ fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
+ fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
+ fadt->gpe0_blk = ACPI_GPE0_BLK;
+ fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */
+
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ fadt->pm2_cnt_len = 1;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = 8;
+ fadt->gpe1_blk_len = 0;
+ fadt->gpe1_base = 0;
+
+ fadt->cst_cnt = 0xe3;
+ fadt->p_lvl2_lat = 101;
+ fadt->p_lvl3_lat = 1001;
+ fadt->flush_size = 0;
+ fadt->flush_stride = 0;
+ fadt->duty_offset = 1;
+ fadt->duty_width = 3;
+ fadt->day_alrm = 0; /* 0x7d these have to be */
+ fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */
+ fadt->century = 0; /* 0x7f to make rtc alrm work */
+ fadt->iapc_boot_arch = 0x3; /* See table 5-11 */
+ fadt->flags = 0x0001c1a5;/* 0x25; */
+
+ fadt->res2 = 0;
+
+ fadt->reset_reg.space_id = 1;
+ fadt->reset_reg.bit_width = 8;
+ fadt->reset_reg.bit_offset = 0;
+ fadt->reset_reg.resv = 0;
+ fadt->reset_reg.addrl = 0xcf9;
+ fadt->reset_reg.addrh = 0x0;
+
+ fadt->reset_value = 6;
+ fadt->x_firmware_ctl_l = (u32) facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (u32) dsdt;
+ fadt->x_dsdt_h = 0;
+
+ fadt->x_pm1a_evt_blk.space_id = 1;
+ fadt->x_pm1a_evt_blk.bit_width = 32;
+ fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.resv = 0;
+ fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
+ fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_evt_blk.space_id = 1;
+ fadt->x_pm1b_evt_blk.bit_width = 4;
+ fadt->x_pm1b_evt_blk.bit_offset = 0;
+ fadt->x_pm1b_evt_blk.resv = 0;
+ fadt->x_pm1b_evt_blk.addrl = 0x0;
+ fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+
+ fadt->x_pm1a_cnt_blk.space_id = 1;
+ fadt->x_pm1a_cnt_blk.bit_width = 16;
+ fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.resv = 0;
+ fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
+ fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_cnt_blk.space_id = 1;
+ fadt->x_pm1b_cnt_blk.bit_width = 2;
+ fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ fadt->x_pm1b_cnt_blk.resv = 0;
+ fadt->x_pm1b_cnt_blk.addrl = 0x0;
+ fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+
+ fadt->x_pm2_cnt_blk.space_id = 1;
+ fadt->x_pm2_cnt_blk.bit_width = 0;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.resv = 0;
+ fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;
+ fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = 32;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.resv = 0;
+ fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+
+
+ fadt->x_gpe0_blk.space_id = 1;
+ fadt->x_gpe0_blk.bit_width = 32;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.resv = 0;
+ fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
+ fadt->x_gpe0_blk.addrh = 0x0;
+
+
+ fadt->x_gpe1_blk.space_id = 1;
+ fadt->x_gpe1_blk.bit_width = 0;
+ fadt->x_gpe1_blk.bit_offset = 0;
+ fadt->x_gpe1_blk.resv = 0;
+ fadt->x_gpe1_blk.addrl = 0;
+ fadt->x_gpe1_blk.addrh = 0x0;
+
+ header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
+}
+
diff --git a/src/mainboard/supermicro/h8qgi/get_bus_conf.c b/src/mainboard/supermicro/h8qgi/get_bus_conf.c
new file mode 100755
index 0000000..14e6bca
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/get_bus_conf.c
@@ -0,0 +1,154 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <cpu/amd/amdfam10_sysconf.h>
+#include "agesawrapper.h"
+
+
+/* Global variables for MB layouts and these will be shared by irqtable mptable
+ * and acpi_tables busnum is default.
+ */
+u8 bus_isa;
+u8 bus_sp5100[2];
+u8 bus_sr5650[14];
+
+/*
+ * Here you only need to set value in pci1234 for HT-IO that could be installed or not
+ * You may need to preset pci1234 for HTIO board,
+ * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+ */
+u32 pci1234x[] = {
+ 0x0000ff0,
+};
+
+/*
+ * HT Chain device num, actually it is unit id base of every ht device in chain,
+ * assume every chain only have 4 ht device at most
+ */
+u32 hcdnx[] = {
+ 0x20202020,
+};
+
+u32 bus_type[256];
+
+u32 sbdn_sr5650;
+u32 sbdn_sp5100;
+
+static u32 get_bus_conf_done = 0;
+
+
+void get_bus_conf(void)
+{
+ u32 status;
+
+ device_t dev;
+ int i, j;
+
+ if (get_bus_conf_done == 1)
+ return; /* do it only once */
+
+ get_bus_conf_done = 1;
+
+ /*
+ * This is the call to AmdInitLate. It is really in the wrong place, conceptually,
+ * but functionally within the coreboot model, this is the best place to make the
+ * call. The logically correct place to call AmdInitLate is after PCI scan is done,
+ * after the decision about S3 resume is made, and before the system tables are
+ * written into RAM. The routine that is responsible for writing the tables is
+ * "write_tables", called near the end of "hardwaremain". There is no platform
+ * specific entry point between the S3 resume decision point and the call to
+ * "write_tables", and the next platform specific entry points are the calls to
+ * the ACPI table write functions. The first of ose would seem to be the right
+ * place, but other table write functions, e.g. the PIRQ table write function, are
+ * called before the ACPI tables are written. This routine is called at the beginning
+ * of each of the write functions called prior to the ACPI write functions, so this
+ * becomes the best place for this call.
+ */
+ status = agesawrapper_amdinitlate();
+ if(status) {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
+ }
+
+ sbdn_sp5100 = 0;
+
+ for (i = 0; i < 0; i++) {
+ bus_sp5100[i] = 0;
+ }
+ for (i = 0; i < ARRAY_SIZE(bus_sr5650); i++) {
+ bus_sr5650[i] = 0;
+ }
+
+ for (i = 0; i < 256; i++) {
+ bus_type[i] = 0; /* default ISA bus. */
+ }
+
+ bus_type[0] = 1; /* pci */
+
+ bus_sr5650[0] = (pci1234x[0] >> 16) & 0xff;
+ // bus_sp5100[0] = (sysconf.pci1234[0] >> 16) & 0xff;
+ bus_sp5100[0] = bus_sr5650[0];
+
+ /* sp5100 */
+ dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, 4));
+
+ if (dev) {
+ bus_sp5100[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+
+ bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_isa++;
+ for (j = bus_sp5100[1]; j < bus_isa; j++)
+ bus_type[j] = 1;
+ }
+
+ /* sr5650 */
+ for (i = 1; i < ARRAY_SIZE(bus_sr5650); i++) {
+ dev = dev_find_slot(bus_sr5650[0], PCI_DEVFN(sbdn_sr5650 + i, 0));
+ if (dev) {
+ bus_sr5650[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ if(255 != bus_sr5650[i]) {
+ bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_isa++;
+ bus_type[bus_sr5650[i]] = 1; /* PCI bus. */
+ }
+ }
+ }
+
+/*
+ for (i = 0; i < 4; i++) {
+ dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, i));
+ if (dev) {
+ bus_sp5100[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_isa++;
+ }
+ }
+ for (j = bus_sp5100[2]; j < bus_isa; j++)
+ bus_type[j] = 1;
+*/
+
+
+ /* I/O APICs: APIC ID Version State Address */
+ bus_isa = 10;
+}
diff --git a/src/mainboard/supermicro/h8qgi/irq_tables.c b/src/mainboard/supermicro/h8qgi/irq_tables.c
new file mode 100755
index 0000000..640a0a6
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/irq_tables.c
@@ -0,0 +1,122 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/pirq_routing.h>
+#include <cpu/amd/amdfam10_sysconf.h>
+
+
+static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
+ u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+ u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
+ u8 slot, u8 rfu)
+{
+ pirq_info->bus = bus;
+ pirq_info->devfn = devfn;
+ pirq_info->irq[0].link = link0;
+ pirq_info->irq[0].bitmap = bitmap0;
+ pirq_info->irq[1].link = link1;
+ pirq_info->irq[1].bitmap = bitmap1;
+ pirq_info->irq[2].link = link2;
+ pirq_info->irq[2].bitmap = bitmap2;
+ pirq_info->irq[3].link = link3;
+ pirq_info->irq[3].bitmap = bitmap3;
+ pirq_info->slot = slot;
+ pirq_info->rfu = rfu;
+}
+extern u8 bus_isa;
+extern u8 bus_sp5100[2];
+extern unsigned long sbdn_sp5100;
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+
+ struct irq_routing_table *pirq;
+ struct irq_info *pirq_info;
+ u32 slot_num;
+ u8 *v;
+
+ u8 sum = 0;
+ int i;
+
+
+ get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
+
+
+ /* Align the table to be 16 byte aligned. */
+ addr += 15;
+ addr &= ~15;
+
+ /* This table must be betweeen 0xf0000 & 0x100000 */
+ printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
+
+ pirq = (void *)(addr);
+ v = (u8 *) (addr);
+
+ pirq->signature = PIRQ_SIGNATURE;
+ pirq->version = PIRQ_VERSION;
+
+ pirq->rtr_bus = bus_sp5100[0];
+ pirq->rtr_devfn = ((sbdn_sp5100 + 0x14) << 3) | 4;
+
+ pirq->exclusive_irqs = 0;
+
+ pirq->rtr_vendor = 0x1002;
+ pirq->rtr_device = 0x4384;
+
+ pirq->miniport_data = 0;
+
+ memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+ pirq_info = (void *)(&pirq->checksum + 1);
+ slot_num = 0;
+
+
+ /* pci bridge */
+ write_pirq_info(pirq_info, bus_sp5100[0], ((sbdn_sp5100 + 0x14) << 3) | 4,
+ 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
+ 0);
+ pirq_info++;
+
+
+
+ slot_num++;
+
+
+
+ pirq->size = 32 + 16 * slot_num;
+
+ for (i = 0; i < pirq->size; i++)
+ sum += v[i];
+
+ sum = pirq->checksum - sum;
+
+ if (sum != pirq->checksum) {
+ pirq->checksum = sum;
+ }
+
+ printk(BIOS_INFO, "write_pirq_routing_table done.\n");
+
+ return (unsigned long)pirq_info;
+
+}
diff --git a/src/mainboard/supermicro/h8qgi/mainboard.c b/src/mainboard/supermicro/h8qgi/mainboard.c
new file mode 100755
index 0000000..f00b5a0
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/mainboard.c
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include "southbridge/amd/sr5650/cmn.h"
+#include "chip.h"
+
+void set_pcie_dereset(void);
+void set_pcie_reset(void);
+
+/**
+ *
+ */
+void set_pcie_reset(void)
+{
+}
+
+/**
+ * Release Resets to PCIe Links
+ * PCIE_RESET_GPIO1,2,4,5
+ */
+void set_pcie_dereset(void)
+{
+ device_t pcie_core_dev;
+
+ pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+ set_htiu_enable_bits(pcie_core_dev, 0xA8, 0x07000707, 0x07000707);
+ set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x00000007, 0x00000007);
+}
+
+
+/*************************************************
+* enable the dedicated function in h8qgi board.
+*************************************************/
+static void h8qgi_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+}
+
+#if (CONFIG_HAVE_MAINBOARD_RESOURCES == 1)
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+#endif
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
+ .enable_dev = h8qgi_enable,
+};
diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c
new file mode 100755
index 0000000..4d32f39
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/mptable.c
@@ -0,0 +1,200 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/cpu.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/amd/amdfam10_sysconf.h>
+
+extern u8 bus_sr5650[14];
+extern u8 bus_sp5100[2];
+extern u32 bus_type[256];
+extern u32 sbdn_sr5650;
+extern u32 sbdn_sp5100;
+
+
+static void *smp_write_config_table(void *v)
+{
+ struct mp_config_table *mc;
+ int bus_isa;
+ u32 apicid_sp5100;
+ u32 apicid_sr5650;
+ device_t dev;
+ u32 dword;
+ u8 byte;
+
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+ mptable_init(mc, LAPIC_ADDR);
+
+ smp_write_processors(mc);
+ get_bus_conf();
+ mptable_write_buses(mc, NULL, &bus_isa);
+
+ /*
+ * AGESA v5 Apply apic enumeration rules
+ * For systems with >= 16 APICs, put the IO-APICs at 0..n and
+ * put the local-APICs at m..z
+ * For systems with < 16 APICs, put the Local-APICs at 0..n and
+ * put the IO-APICs at (n + 1)..z
+ */
+#if CONFIG_MAX_CPUS >= 16
+ apicid_sp5100 = 0x0;
+#else
+ apicid_sp5100 = CONFIG_MAX_CPUS + 1
+#endif
+ apicid_sr5650 = apicid_sp5100 + 1;
+
+ //bus_sp5100[0], TODO: why bus_sp5100[0] use same value of bus_sr5650[0] assigned by get_pci1234(), instead of 0.
+ dev = dev_find_slot(0, PCI_DEVFN(sbdn_sp5100 + 0x14, 0));
+ if (dev) {
+ /* Set SP5100 IOAPIC ID */
+ dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
+ smp_write_ioapic(mc, apicid_sp5100, 0x20, dword);
+
+ /* Initialize interrupt mapping */
+ /* aza */
+ byte = pci_read_config8(dev, 0x63);
+ byte &= 0xf8;
+ byte |= 0; /* 0: INTA, ...., 7: INTH */
+ pci_write_config8(dev, 0x63, byte);
+ /* SATA */
+ dword = pci_read_config32(dev, 0xAC);
+ dword &= ~(7 << 26);
+ dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
+ /* dword |= 1<<22; PIC and APIC co exists */
+ pci_write_config32(dev, 0xAC, dword);
+
+ /*
+ * 00:12.0: PROG SATA : INT F
+ * 00:13.0: INTA USB_0
+ * 00:13.1: INTB USB_1
+ * 00:13.2: INTC USB_2
+ * 00:13.3: INTD USB_3
+ * 00:13.4: INTC USB_4
+ * 00:13.5: INTD USB2
+ * 00:14.1: INTA IDE
+ * 00:14.2: Prog HDA : INT E
+ * 00:14.5: INTB ACI
+ * 00:14.6: INTB MCI
+ */
+
+ /* Set RS5650 IOAPIC ID */
+ dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+ if (dev) {
+ pci_write_config32(dev, 0xF8, 0x1);
+ dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
+ smp_write_ioapic(mc, apicid_sr5650, 0x20, dword);
+ }
+
+ }
+
+ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+#define IO_LOCAL_INT(type, intr, apicid, pin) \
+ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+
+ mptable_add_isa_interrupts(mc, bus_isa, apicid_sp5100, 0);
+
+ /* PCI interrupts are level triggered, and are
+ * associated with a specific bus/device/function tuple.
+ */
+#define PCI_INT(bus, dev, int_sign, pin) \
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sp5100, (pin))
+
+ /* SMBUS */
+ //PCI_INT(0x0, 0x14, 0x0, 0x10); //not generate interrupt, 3Ch hardcoded to 0
+
+ /* HD Audio */
+ PCI_INT(0x0, 0x14, 0x2, 0x10);
+
+ /* USB */
+ /* OHCI0, OHCI1 hard-wired to 01h, corresponding to using INTA# */
+ /* EHCI hard-wired to 02h, corresponding to using INTB# */
+ /* USB1 */
+ PCI_INT(0x0, 0x12, 0x0, 0x10); /* OHCI0 Port 0~2 */
+ PCI_INT(0x0, 0x12, 0x1, 0x10); /* OHCI1 Port 3~5 */
+ PCI_INT(0x0, 0x12, 0x2, 0x11); /* EHCI Port 0~5 */
+
+ /* USB2 */
+ PCI_INT(0x0, 0x13, 0x0, 0x10); /* OHCI0 Port 6~8 */
+ PCI_INT(0x0, 0x13, 0x1, 0x10); /* OHCI1 Port 9~11 */
+ PCI_INT(0x0, 0x13, 0x2, 0x11); /* EHCI Port 6~11 */
+
+ /* USB3 EHCI hard-wired to 03h, corresponding to using INTC# */
+ PCI_INT(0x0, 0x14, 0x5, 0x12); /* OHCI0 Port 12~13 */
+
+ /* SATA */
+ PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG
+
+ /* on board NIC & Slot PCIE. */
+ /* configuration B doesnt need dev 5,6,7 */
+ /*
+ * PCI_INT(bus_sr5650[0x5], 0x0, 0x0, 0x11);
+ * PCI_INT(bus_sr5650[0x6], 0x0, 0x0, 0x12);
+ * PCI_INT(bus_sr5650[0x7], 0x0, 0x0, 0x13);
+ */
+
+ //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 28); /* dev d */
+ //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[13], (((0)<<2)|(1)), apicid_sr5650, 0); /* card behind dev13 */
+
+ /* PCI slots */
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14);
+ PCI_INT(bus_sp5100[1], 0x5, 0x1, 0x15);
+ PCI_INT(bus_sp5100[1], 0x5, 0x2, 0x16);
+ PCI_INT(bus_sp5100[1], 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_sp5100[1], 0x6, 0x0, 0x15);
+ PCI_INT(bus_sp5100[1], 0x6, 0x1, 0x16);
+ PCI_INT(bus_sp5100[1], 0x6, 0x2, 0x17);
+ PCI_INT(bus_sp5100[1], 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_sp5100[1], 0x7, 0x0, 0x16);
+ PCI_INT(bus_sp5100[1], 0x7, 0x1, 0x17);
+ PCI_INT(bus_sp5100[1], 0x7, 0x2, 0x14);
+ PCI_INT(bus_sp5100[1], 0x7, 0x3, 0x15);
+
+
+ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
+ IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
+ /* There is no extension information... */
+
+ /* Compute the checksums */
+ mc->mpe_checksum =
+ smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+ mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+ printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
+ mc, smp_next_mpe_entry(mc));
+ return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr);
+ return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/supermicro/h8qgi/platform_oem.c b/src/mainboard/supermicro/h8qgi/platform_oem.c
new file mode 100755
index 0000000..f36b0d8
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/platform_oem.c
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "heapManager.h"
+#include "platform_oem.h"
+#include "Filecode.h"
+
+#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * OemCustomizeInitEarly
+ *
+ * Description:
+ * This is the stub function will call the host environment through the binary block
+ * interface (call-out port) to provide a user hook opportunity
+ *
+ * Parameters:
+ * @param[in] **PeiServices
+ * @param[in] *InitEarly
+ *
+ * @retval VOID
+ *
+ **/
+/*---------------------------------------------------------------------------------------*/
+VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
+{
+ //InitEarly->PlatformConfig.CoreLevelingMode = CORE_LEVEL_TWO;
+}
+
diff --git a/src/mainboard/supermicro/h8qgi/platform_oem.h b/src/mainboard/supermicro/h8qgi/platform_oem.h
new file mode 100755
index 0000000..ab0d6df
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/platform_oem.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _PLATFORM_OEM_H_
+#define _PLATFORM_OEM_H_
+
+#include "Porting.h"
+#include "AGESA.h"
+#include "amdlib.h"
+
+VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly);
+
+#endif //_PLATFORM_OEM_H_
diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c
new file mode 100755
index 0000000..08b0eb2
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/romstage.c
@@ -0,0 +1,132 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <lib.h>
+#include <reset.h>
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <arch/cpu.h>
+#include <console/console.h>
+#include <arch/stages.h>
+#include "cpu/x86/bist.h"
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "agesawrapper.h"
+#include "northbridge/amd/agesa/family10/reset_test.h"
+#include "southbridge/amd/sr5650/sr5650.h"
+#include "southbridge/amd/sb700/sb700.h"
+#include "superio/nuvoton/wpcm450/wpcm450.h"
+
+extern void disable_cache_as_ram(void); /* cache_as_ram.inc */
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+ u32 val;
+
+ agesawrapper_amdinitmmio();
+ if (!cpu_init_detectedx && boot_cpu()) {
+ post_code(0x30);
+ /* SR56x0 pcie bridges block pci_locate_device() before pcie training.
+ * disable all pcie bridges on SR56x0 to work around it
+ */
+ sr5650_disable_pcie_bridge();
+ post_code(0x31);
+ sb7xx_51xx_lpc_port80();
+ post_code(0x32);
+ }
+
+ /* Halt if there was a built in self test failure */
+ post_code(0x33);
+ report_bist_failure(bist);
+
+ enable_sr5650_dev8();
+ sb7xx_51xx_lpc_init();
+ sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */
+ wpcm450_enable_dev(WPCM450_SP1, CONFIG_SIO_PORT, CONFIG_TTYS0_BASE);
+ sb7xx_51xx_disable_wideio(0);
+ post_code(0x34);
+
+ uart_init();
+ post_code(0x35);
+ console_init();
+
+ val = cpuid_eax(1);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+
+ post_code(0x37);
+ val = agesawrapper_amdinitreset();
+ if (val) {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
+ } else {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitreset passed\n");
+ }
+
+ post_code(0x38);
+ val = agesawrapper_amdinitearly();
+ if(val) {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
+ } else {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitearly passed\n");
+ }
+
+ sr5650_early_setup();
+ post_code(0x39);
+
+ sb7xx_51xx_early_setup();
+ sr5650_htinit();
+ /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
+ if (!warm_reset_detect(0)) {
+ print_info("...WARM RESET...\n\n\n");
+ distinguish_cpu_resets(0);
+ soft_reset();
+ die("After soft_reset_x - shouldn't see this message!!!\n");
+ }
+
+ post_code(0x40);
+ val = agesawrapper_amdinitpost();
+ if (val) {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
+ }
+ printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n");
+
+ post_code(0x41);
+ val = agesawrapper_amdinitenv();
+ if(val) {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
+ }
+ printk(BIOS_DEBUG, "agesawrapper_amdinitenv passed\n");
+
+ post_code(0x42);
+ sr5650_before_pci_init();
+ sb7xx_51xx_before_pci_init();
+
+ post_code(0x50);
+ print_debug("Disabling cache as ram ");
+ disable_cache_as_ram();
+ print_debug("done\n");
+
+ post_code(0x51);
+ copy_and_run(0);
+
+ /* We will not return, Should never see this message and post code. */
+ print_debug("should not be here -\n");
+ post_code(0x54);
+}
+
1
0
Re: [coreboot] [PATCH][RFC] A new way using a binary file to add-stage to a rom file on ARM
by Marc Jones 21 Jul '11
by Marc Jones 21 Jul '11
21 Jul '11
On Wed, Jul 20, 2011 at 3:53 PM, Hamo <hamo.by(a)gmail.com> wrote:
> On Wed, Jul 20, 2011 at 11:29 PM, Bari Ari <bari(a)onelabs.com> wrote:
>> http://www.mini-box.com/mini2440v2 Â is an old ARM9 dev board that is still
>> readily available the uses a 2MB NOR Flash for init and bootloader. Most ARM
>> systems that will make use of coreboot won't have a separate SPI or NOR
>> flash to hold the init and bootloader. But you have to start somewhere.
>> We'll just have to make this work from on-board NAND, eMMC or SD Card later.
>
> If we don't add romstage to the romfile and don't compress the
> ramstage since the decompress code is too big for bootblock we can
> boot from the NAND Flash or SD card. In the ramstage, we init the
> Flash controller so that we can read the payload and kernel from the
> NAND flash later.
> I don't test my thought yet. Maybe it doesn't work for that I may
> assume something like we have a romstage in my code.
Why would you exclude romstage? What will setup the RAM? bootblock? i
suspect that the stuff you are doing in bootblock should be done in
romstage.
Marc
--
http://se-eng.com
1
0
Re: [coreboot] [PATCH][RFC] A new way using a binary file to add-stage to a rom file on ARM
by Bari Ari 20 Jul '11
by Bari Ari 20 Jul '11
20 Jul '11
On 07/20/2011 12:27 AM, Hamo wrote:
> Thanks. Since we want to make use of the romstage code, we need a CPU
> that supports boot from SPI or Nor Flash (because we need to run code
> in the rom) and a board that has a SPI or Nor Flash on it.
There are ARM boards around that use a SPI or NOR flash to store the
init and bootloader but most new boards and tablets store it in NAND or
eMMC with support for SD Card, serial or USB boot as well. The boot
device order is set by pin straps. If the cpu doesn't see a boot string
it will scan the next peripheral port until it finds one.
http://www.mini-box.com/mini2440v2 is an old ARM9 dev board that is
still readily available the uses a 2MB NOR Flash for init and
bootloader. Most ARM systems that will make use of coreboot won't have a
separate SPI or NOR flash to hold the init and bootloader. But you have
to start somewhere. We'll just have to make this work from on-board
NAND, eMMC or SD Card later.
-Bari
2
1
20 Jul '11
Frank Vibrans III (frank.vibrans(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/108
-gerrit
commit 00aa106d4f98db6ebfd7b9c38bc2db581bbda1fe
Author: efdesign98 <efdesign98(a)gmail.com>
Date: Wed Jul 20 13:23:04 2011 -0600
Add the SuperMicro H8QGI platform
This set adds support for the SuperMicro H8QGI mainboard.
It is a publicly available 4 socket board using AMD Family
10 cpus and AMD SR5650 and SB700 bridges.
Change-Id: I196704f79db4c45382559c5ee0619dc8d96ff140
Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com>
Signed-off-by: efdesign98 <efdesign98(a)gmail.com>
---
src/mainboard/supermicro/Kconfig | 3 +
src/mainboard/supermicro/h8qgi/BiosCallOuts.c | 516 +++++++
src/mainboard/supermicro/h8qgi/BiosCallOuts.h | 78 +
src/mainboard/supermicro/h8qgi/Kconfig | 129 ++
src/mainboard/supermicro/h8qgi/Makefile.inc | 34 +
src/mainboard/supermicro/h8qgi/OptionsIds.h | 66 +
src/mainboard/supermicro/h8qgi/acpi/cpstate.asl | 75 +
src/mainboard/supermicro/h8qgi/acpi/ide.asl | 244 +++
src/mainboard/supermicro/h8qgi/acpi/routing.asl | 222 +++
src/mainboard/supermicro/h8qgi/acpi/sata.asl | 149 ++
src/mainboard/supermicro/h8qgi/acpi/usb.asl | 161 ++
src/mainboard/supermicro/h8qgi/acpi_tables.c | 295 ++++
src/mainboard/supermicro/h8qgi/agesawrapper.c | 1169 ++++++++++++++
src/mainboard/supermicro/h8qgi/agesawrapper.h | 87 ++
src/mainboard/supermicro/h8qgi/buildOpts.c | 541 +++++++
src/mainboard/supermicro/h8qgi/chip.h | 23 +
src/mainboard/supermicro/h8qgi/cmos.layout | 118 ++
src/mainboard/supermicro/h8qgi/devicetree.cb | 176 +++
src/mainboard/supermicro/h8qgi/dimmSpd.c | 229 +++
src/mainboard/supermicro/h8qgi/dsdt.asl | 1849 +++++++++++++++++++++++
src/mainboard/supermicro/h8qgi/fadt.c | 201 +++
src/mainboard/supermicro/h8qgi/get_bus_conf.c | 154 ++
src/mainboard/supermicro/h8qgi/irq_tables.c | 122 ++
src/mainboard/supermicro/h8qgi/mainboard.c | 73 +
src/mainboard/supermicro/h8qgi/mptable.c | 200 +++
src/mainboard/supermicro/h8qgi/platform_oem.c | 50 +
src/mainboard/supermicro/h8qgi/platform_oem.h | 29 +
src/mainboard/supermicro/h8qgi/romstage.c | 132 ++
28 files changed, 7125 insertions(+), 0 deletions(-)
diff --git a/src/mainboard/supermicro/Kconfig b/src/mainboard/supermicro/Kconfig
old mode 100644
new mode 100755
index 8483d6f..80ffd6a
--- a/src/mainboard/supermicro/Kconfig
+++ b/src/mainboard/supermicro/Kconfig
@@ -13,6 +13,8 @@ config BOARD_SUPERMICRO_H8QME_FAM10
bool "H8QME-2+ (Fam10)"
config BOARD_SUPERMICRO_H8SCM_FAM10
bool "H8SCM (Fam10)"
+config BOARD_SUPERMICRO_H8QGI
+ bool "H8QGI"
config BOARD_SUPERMICRO_X6DAI_G
bool "X6DAi-G"
config BOARD_SUPERMICRO_X6DHE_G2
@@ -31,6 +33,7 @@ source "src/mainboard/supermicro/h8dmr/Kconfig"
source "src/mainboard/supermicro/h8dmr_fam10/Kconfig"
source "src/mainboard/supermicro/h8qme_fam10/Kconfig"
source "src/mainboard/supermicro/h8scm_fam10/Kconfig"
+source "src/mainboard/supermicro/h8qgi/Kconfig"
source "src/mainboard/supermicro/x6dai_g/Kconfig"
source "src/mainboard/supermicro/x6dhe_g2/Kconfig"
source "src/mainboard/supermicro/x6dhe_g/Kconfig"
diff --git a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c
new file mode 100755
index 0000000..b7f0124
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c
@@ -0,0 +1,516 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "agesawrapper.h"
+#include "amdlib.h"
+#include "BiosCallOuts.h"
+#include "Ids.h"
+#include "OptionsIds.h"
+#include "heapManager.h"
+
+STATIC BIOS_CALLOUT_STRUCT BiosCallouts[REQUIRED_CALLOUTS] =
+{
+ {
+ AGESA_ALLOCATE_BUFFER,
+ BiosAllocateBuffer
+ },
+
+ {
+ AGESA_DEALLOCATE_BUFFER,
+ BiosDeallocateBuffer
+ },
+
+ {
+ AGESA_DO_RESET,
+ BiosReset
+ },
+
+ {
+ AGESA_LOCATE_BUFFER,
+ BiosLocateBuffer
+ },
+
+ {
+ AGESA_READ_SPD,
+ BiosReadSpd
+ },
+
+ {
+ AGESA_READ_SPD_RECOVERY,
+ BiosDefaultRet
+ },
+
+ {
+ AGESA_RUNFUNC_ONAP,
+ BiosRunFuncOnAp
+ },
+
+ {
+ AGESA_GET_IDS_INIT_DATA,
+ BiosGetIdsInitData
+ },
+
+ {
+ AGESA_HOOKBEFORE_DQS_TRAINING,
+ BiosHookBeforeDQSTraining
+ },
+
+ {
+ AGESA_HOOKBEFORE_DRAM_INIT,
+ BiosHookBeforeDramInit
+ },
+ {
+ AGESA_HOOKBEFORE_EXIT_SELF_REF,
+ BiosHookBeforeExitSelfRefresh
+ },
+};
+
+extern AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info);
+
+AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ UINTN i;
+ AGESA_STATUS CalloutStatus;
+
+ for (i = 0; i < REQUIRED_CALLOUTS; i++) {
+ if (BiosCallouts[i].CalloutName == Func) {
+ break;
+ }
+ }
+
+ if(i >= REQUIRED_CALLOUTS) {
+ return AGESA_UNSUPPORTED;
+ }
+
+ CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr);
+
+ return CalloutStatus;
+}
+
+
+CONST IDS_NV_ITEM IdsData[] =
+{
+ /*{
+ AGESA_IDS_NV_MAIN_PLL_CON,
+ 0x1
+ },
+ {
+ AGESA_IDS_NV_MAIN_PLL_FID_EN,
+ 0x1
+ },
+ {
+ AGESA_IDS_NV_MAIN_PLL_FID,
+ 0x8
+ },
+
+ {
+ AGESA_IDS_NV_CUSTOM_NB_PSTATE,
+ },
+ {
+ AGESA_IDS_NV_CUSTOM_NB_P0_DIV_CTRL,
+ },
+ {
+ AGESA_IDS_NV_CUSTOM_NB_P1_DIV_CTRL,
+ },
+ {
+ AGESA_IDS_NV_FORCE_NB_PSTATE,
+ },
+ */
+ {
+ 0xFFFF,
+ 0xFFFF
+ }
+};
+
+#define NUM_IDS_ENTRIES (sizeof (IdsData) / sizeof (IDS_NV_ITEM))
+
+AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ UINTN i;
+ IDS_NV_ITEM *IdsPtr;
+
+ IdsPtr = ((IDS_CALLOUT_STRUCT *) ConfigPtr)->IdsNvPtr;
+
+ if (Data == IDS_CALLOUT_INIT) {
+ for (i = 0; i < NUM_IDS_ENTRIES; i++) {
+ IdsPtr[i].IdsNvValue = IdsData[i].IdsNvValue;
+ IdsPtr[i].IdsNvId = IdsData[i].IdsNvId;
+ }
+ }
+ return AGESA_SUCCESS;
+}
+
+
+AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ UINT32 AvailableHeapSize;
+ UINT8 *BiosHeapBaseAddr;
+ UINT32 CurrNodeOffset;
+ UINT32 PrevNodeOffset;
+ UINT32 FreedNodeOffset;
+ UINT32 BestFitNodeOffset;
+ UINT32 BestFitPrevNodeOffset;
+ UINT32 NextFreeOffset;
+ BIOS_BUFFER_NODE *CurrNodePtr;
+ BIOS_BUFFER_NODE *FreedNodePtr;
+ BIOS_BUFFER_NODE *BestFitNodePtr;
+ BIOS_BUFFER_NODE *BestFitPrevNodePtr;
+ BIOS_BUFFER_NODE *NextFreePtr;
+ BIOS_HEAP_MANAGER *BiosHeapBasePtr;
+ AGESA_BUFFER_PARAMS *AllocParams;
+
+ AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr);
+ AllocParams->BufferPointer = NULL;
+
+ AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER);
+ BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
+ BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
+
+ if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) {
+ /* First allocation */
+ CurrNodeOffset = sizeof (BIOS_HEAP_MANAGER);
+ CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+ CurrNodePtr->BufferHandle = AllocParams->BufferHandle;
+ CurrNodePtr->BufferSize = AllocParams->BufferLength;
+ CurrNodePtr->NextNodeOffset = 0;
+ AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof (BIOS_BUFFER_NODE);
+
+ /* Update the remaining free space */
+ FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof (BIOS_BUFFER_NODE);
+ FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+ FreedNodePtr->BufferSize = AvailableHeapSize - sizeof (BIOS_BUFFER_NODE) - CurrNodePtr->BufferSize;
+ FreedNodePtr->NextNodeOffset = 0;
+
+ /* Update the offsets for Allocated and Freed nodes */
+ BiosHeapBasePtr->StartOfAllocatedNodes = CurrNodeOffset;
+ BiosHeapBasePtr->StartOfFreedNodes = FreedNodeOffset;
+ } else {
+ /* Find out whether BufferHandle has been allocated on the heap. */
+ /* If it has, return AGESA_BOUNDS_CHK */
+ CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+ CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+
+ while (CurrNodeOffset != 0) {
+ CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+ if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) {
+ return AGESA_BOUNDS_CHK;
+ }
+ CurrNodeOffset = CurrNodePtr->NextNodeOffset;
+ /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points
+ to the end of the allocated nodes list.
+ */
+
+ }
+ /* Find the node that best fits the requested buffer size */
+ FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
+ PrevNodeOffset = FreedNodeOffset;
+ BestFitNodeOffset = 0;
+ BestFitPrevNodeOffset = 0;
+ while (FreedNodeOffset != 0) {
+ FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+ if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) {
+ if (BestFitNodeOffset == 0) {
+ /* First node that fits the requested buffer size */
+ BestFitNodeOffset = FreedNodeOffset;
+ BestFitPrevNodeOffset = PrevNodeOffset;
+ } else {
+ /* Find out whether current node is a better fit than the previous nodes */
+ BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
+ if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) {
+ BestFitNodeOffset = FreedNodeOffset;
+ BestFitPrevNodeOffset = PrevNodeOffset;
+ }
+ }
+ }
+ PrevNodeOffset = FreedNodeOffset;
+ FreedNodeOffset = FreedNodePtr->NextNodeOffset;
+ } /* end of while loop */
+
+
+ if (BestFitNodeOffset == 0) {
+ /* If we could not find a node that fits the requested buffer */
+ /* size, return AGESA_BOUNDS_CHK */
+ return AGESA_BOUNDS_CHK;
+ } else {
+ BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
+ BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset);
+
+ /* If BestFitNode is larger than the requested buffer, fragment the node further */
+ if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) {
+ NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE);
+
+ NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset);
+ NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE));
+ NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset;
+ } else {
+ /* Otherwise, next free node is NextNodeOffset of BestFitNode */
+ NextFreeOffset = BestFitNodePtr->NextNodeOffset;
+ }
+
+ /* If BestFitNode is the first buffer in the list, then update
+ StartOfFreedNodes to reflect the new free node
+ */
+ if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) {
+ BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset;
+ } else {
+ BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset;
+ }
+
+ /* Add BestFitNode to the list of Allocated nodes */
+ CurrNodePtr->NextNodeOffset = BestFitNodeOffset;
+ BestFitNodePtr->BufferSize = AllocParams->BufferLength;
+ BestFitNodePtr->BufferHandle = AllocParams->BufferHandle;
+ BestFitNodePtr->NextNodeOffset = 0;
+
+ /* Remove BestFitNode from list of Freed nodes */
+ AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof (BIOS_BUFFER_NODE);
+ }
+ }
+
+ return AGESA_SUCCESS;
+}
+
+AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+
+ UINT8 *BiosHeapBaseAddr;
+ UINT32 AllocNodeOffset;
+ UINT32 PrevNodeOffset;
+ UINT32 NextNodeOffset;
+ UINT32 FreedNodeOffset;
+ UINT32 EndNodeOffset;
+ BIOS_BUFFER_NODE *AllocNodePtr;
+ BIOS_BUFFER_NODE *PrevNodePtr;
+ BIOS_BUFFER_NODE *FreedNodePtr;
+ BIOS_BUFFER_NODE *NextNodePtr;
+ BIOS_HEAP_MANAGER *BiosHeapBasePtr;
+ AGESA_BUFFER_PARAMS *AllocParams;
+
+ BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
+ BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
+
+ AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
+
+ /* Find target node to deallocate in list of allocated nodes.
+ Return AGESA_BOUNDS_CHK if the BufferHandle is not found
+ */
+ AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+ AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+ PrevNodeOffset = AllocNodeOffset;
+
+ while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) {
+ if (AllocNodePtr->NextNodeOffset == 0) {
+ return AGESA_BOUNDS_CHK;
+ }
+ PrevNodeOffset = AllocNodeOffset;
+ AllocNodeOffset = AllocNodePtr->NextNodeOffset;
+ AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+ }
+
+ /* Remove target node from list of allocated nodes */
+ PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
+ PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
+
+ /* Zero out the buffer, and clear the BufferHandle */
+ LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof (BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader));
+ AllocNodePtr->BufferHandle = 0;
+ AllocNodePtr->BufferSize += sizeof (BIOS_BUFFER_NODE);
+
+ /* Add deallocated node in order to the list of freed nodes */
+ FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
+ FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+
+ EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize;
+
+ if (AllocNodeOffset < FreedNodeOffset) {
+ /* Add to the start of the freed list */
+ if (EndNodeOffset == FreedNodeOffset) {
+ /* If the freed node is adjacent to the first node in the list, concatenate both nodes */
+ AllocNodePtr->BufferSize += FreedNodePtr->BufferSize;
+ AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset;
+
+ /* Clear the BufferSize and NextNodeOffset of the previous first node */
+ FreedNodePtr->BufferSize = 0;
+ FreedNodePtr->NextNodeOffset = 0;
+
+ } else {
+ /* Otherwise, add freed node to the start of the list
+ Update NextNodeOffset and BufferSize to include the
+ size of BIOS_BUFFER_NODE
+ */
+ AllocNodePtr->NextNodeOffset = FreedNodeOffset;
+ }
+ /* Update StartOfFreedNodes to the new first node */
+ BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset;
+ } else {
+ /* Traverse list of freed nodes to find where the deallocated node
+ should be place
+ */
+ NextNodeOffset = FreedNodeOffset;
+ NextNodePtr = FreedNodePtr;
+ while (AllocNodeOffset > NextNodeOffset) {
+ PrevNodeOffset = NextNodeOffset;
+ if (NextNodePtr->NextNodeOffset == 0) {
+ break;
+ }
+ NextNodeOffset = NextNodePtr->NextNodeOffset;
+ NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
+ }
+
+ /* If deallocated node is adjacent to the next node,
+ concatenate both nodes
+ */
+ if (NextNodeOffset == EndNodeOffset) {
+ NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
+ AllocNodePtr->BufferSize += NextNodePtr->BufferSize;
+ AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset;
+
+ NextNodePtr->BufferSize = 0;
+ NextNodePtr->NextNodeOffset = 0;
+ } else {
+ /*AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; */
+ AllocNodePtr->NextNodeOffset = NextNodeOffset;
+ }
+ /* If deallocated node is adjacent to the previous node,
+ concatenate both nodes
+ */
+ PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
+ EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize;
+ if (AllocNodeOffset == EndNodeOffset) {
+ PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
+ PrevNodePtr->BufferSize += AllocNodePtr->BufferSize;
+
+ AllocNodePtr->BufferSize = 0;
+ AllocNodePtr->NextNodeOffset = 0;
+ } else {
+ PrevNodePtr->NextNodeOffset = AllocNodeOffset;
+ }
+ }
+ return AGESA_SUCCESS;
+}
+
+AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ UINT32 AllocNodeOffset;
+ UINT8 *BiosHeapBaseAddr;
+ BIOS_BUFFER_NODE *AllocNodePtr;
+ BIOS_HEAP_MANAGER *BiosHeapBasePtr;
+ AGESA_BUFFER_PARAMS *AllocParams;
+
+ AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
+
+ BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
+ BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
+
+ AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+ AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+
+ while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) {
+ if (AllocNodePtr->NextNodeOffset == 0) {
+ AllocParams->BufferPointer = NULL;
+ AllocParams->BufferLength = 0;
+ return AGESA_BOUNDS_CHK;
+ } else {
+ AllocNodeOffset = AllocNodePtr->NextNodeOffset;
+ AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+ }
+ }
+
+ AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof (BIOS_BUFFER_NODE));
+ AllocParams->BufferLength = AllocNodePtr->BufferSize;
+
+ return AGESA_SUCCESS;
+
+}
+
+AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ AGESA_STATUS Status;
+
+ Status = agesawrapper_amdlaterunaptask (Data, ConfigPtr);
+ return Status;
+}
+
+AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ AGESA_STATUS Status;
+ UINT8 Value;
+ UINTN ResetType;
+ AMD_CONFIG_PARAMS *StdHeader;
+
+ ResetType = Data;
+ StdHeader = ConfigPtr;
+
+ //
+ // Perform the RESET based upon the ResetType. In case of
+ // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to
+ // AmdResetManager. During the critical condition, where reset is required
+ // immediately, the reset will be invoked directly by writing 0x04 to port
+ // 0xCF9 (Reset Port).
+ //
+ switch (ResetType) {
+ case WARM_RESET_WHENEVER:
+ case COLD_RESET_WHENEVER:
+ break;
+
+ case WARM_RESET_IMMEDIATELY:
+ case COLD_RESET_IMMEDIATELY:
+ Value = 0x06;
+ LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader);
+ break;
+
+ default:
+ break;
+ }
+
+ Status = 0;
+ return Status;
+}
+
+AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ AGESA_STATUS Status;
+ Status = AmdMemoryReadSPD (Func, Data, ConfigPtr);
+
+ return Status;
+}
+
+AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ return AGESA_UNSUPPORTED;
+}
+
+/* Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ return AGESA_SUCCESS;
+}
+
+/* Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ return AGESA_SUCCESS;
+}
+
+/* Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ return AGESA_SUCCESS;
+}
+
diff --git a/src/mainboard/supermicro/h8qgi/BiosCallOuts.h b/src/mainboard/supermicro/h8qgi/BiosCallOuts.h
new file mode 100755
index 0000000..24a05fb
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/BiosCallOuts.h
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BIOS_CALLOUT_H_
+#define _BIOS_CALLOUT_H_
+
+#include "Porting.h"
+#include "AGESA.h"
+
+#define REQUIRED_CALLOUTS 12
+#define BIOS_HEAP_START_ADDRESS 0x00010000
+#define BIOS_HEAP_SIZE 0x20000 /* 64MB */
+
+typedef struct _BIOS_HEAP_MANAGER {
+ //UINT32 AvailableSize;
+ UINT32 StartOfAllocatedNodes;
+ UINT32 StartOfFreedNodes;
+} BIOS_HEAP_MANAGER;
+
+typedef struct _BIOS_BUFFER_NODE {
+ UINT32 BufferHandle;
+ UINT32 BufferSize;
+ UINT32 NextNodeOffset;
+} BIOS_BUFFER_NODE;
+
+/*
+ * CALLOUTS
+ */
+AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+
+/* REQUIRED CALLOUTS
+ * AGESA ADVANCED CALLOUTS - CPU
+ */
+AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+
+/* AGESA ADVANCED CALLOUTS - MEMORY */
+AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr);
+
+/* BIOS DEFAULT RET */
+AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+
+/* Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+/* Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+/* Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+#define SB_GPIO_REG02 2
+#define SB_GPIO_REG09 9
+#define SB_GPIO_REG10 10
+#define SB_GPIO_REG15 15
+#define SB_GPIO_REG17 17
+#define SB_GPIO_REG21 21
+#define SB_GPIO_REG25 25
+#define SB_GPIO_REG28 28
+#endif //_BIOS_CALLOUT_H_
+
diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig
new file mode 100755
index 0000000..286cb17
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/Kconfig
@@ -0,0 +1,129 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+if BOARD_SUPERMICRO_H8QGI
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select ARCH_X86
+ select CPU_AMD_AGESA_FAMILY10
+ select NORTHBRIDGE_AMD_AGESA_FAMILY10_ROOT_COMPLEX
+ select NORTHBRIDGE_AMD_AGESA_FAMILY10
+ select SOUTHBRIDGE_AMD_SR5650
+ select SOUTHBRIDGE_AMD_SP5100
+ select SUPERIO_WINBOND_W83627DHG
+ select BOARD_HAS_FADT
+ select HAVE_BUS_CONFIG
+ select HAVE_OPTION_TABLE
+ select HAVE_PIRQ_TABLE
+ select HAVE_MP_TABLE
+ select HAVE_HARD_RESET
+ select SERIAL_CPU_INIT
+ select AMDMCT
+ select HAVE_ACPI_TABLES
+ select BOARD_ROMSIZE_KB_2048
+ select TINY_BOOTBLOCK
+ #select MMCONF_SUPPORT_DEFAULT #TODO enable it to resolve Multicore IO conflict
+
+config AMD_AGESA
+ bool
+ default y
+
+config MAINBOARD_DIR
+ string
+ default supermicro/h8qgi
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "H8QGI"
+
+config HW_MEM_HOLE_SIZEK
+ hex
+ default 0x200000
+
+config MAX_CPUS
+ int
+ default 64
+
+config MAX_PHYSICAL_CPUS
+ int
+ default 16
+
+config HW_MEM_HOLE_SIZE_AUTO_INC
+ bool
+ default n
+
+config MEM_TRAIN_SEQ
+ int
+ default 2
+
+config IRQ_SLOT_COUNT
+ int
+ default 11
+
+config RAMTOP
+ hex
+ default 0x1000000
+
+config HEAP_SIZE
+ hex
+ default 0xc0000
+
+config STACK_SIZE
+ hex
+ default 0x10000
+
+config ACPI_SSDTX_NUM
+ int
+ default 0
+
+config RAMBASE
+ hex
+ default 0x200000
+
+config SIO_PORT
+ hex
+ default 0x164E
+ help
+ though UARTs are on the NUVOTON BMC, port 0x164E
+ PS2 keyboard and mouse are on SUPERIO_WINBOND_W83627DHG, port 0x2E
+
+config DRIVERS_PS2_KEYBOARD
+ bool
+ default y
+
+config WARNINGS_ARE_ERRORS
+ bool
+ default n
+
+config ONBOARD_VGA_IS_PRIMARY
+ bool
+ default y
+
+config VGA_BIOS
+ bool
+ default n
+
+config VGA_BIOS_ID
+ string
+ depends on VGA_BIOS
+ default "102b,0532"
+
+endif # BOARD_SUPERMICRO_H8QGI
+
diff --git a/src/mainboard/supermicro/h8qgi/Makefile.inc b/src/mainboard/supermicro/h8qgi/Makefile.inc
new file mode 100755
index 0000000..92bc110
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/Makefile.inc
@@ -0,0 +1,34 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+romstage-y += buildOpts.c
+romstage-y += agesawrapper.c
+romstage-y += dimmSpd.c
+romstage-y += BiosCallOuts.c
+romstage-y += platform_oem.c
+romstage-y += ../../../superio/nuvoton/wpcm450/early_init.c
+
+ramstage-y += buildOpts.c
+ramstage-y += agesawrapper.c
+ramstage-y += dimmSpd.c
+ramstage-y += BiosCallOuts.c
+ramstage-y += platform_oem.c
+
+AGESA_ROOT ?= $(src)/vendorcode/amd/agesa/f10/
+subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += ../../../../$(AGESA_ROOT)
diff --git a/src/mainboard/supermicro/h8qgi/OptionsIds.h b/src/mainboard/supermicro/h8qgi/OptionsIds.h
new file mode 100755
index 0000000..eb756df
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/OptionsIds.h
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/**
+ * @file
+ *
+ * IDS Option File
+ *
+ * This file is used to switch on/off IDS features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $
+ */
+#ifndef _OPTION_IDS_H_
+#define _OPTION_IDS_H_
+
+/**
+ *
+ * This file generates the defaults tables for the Integrated Debug Support
+ * Module. The documented build options are imported from a user controlled
+ * file for processing. The build options for the Integrated Debug Support
+ * Module are listed below:
+ *
+ * IDSOPT_IDS_ENABLED
+ * IDSOPT_ERROR_TRAP_ENABLED
+ * IDSOPT_CONTROL_ENABLED
+ * IDSOPT_TRACING_ENABLED
+ * IDSOPT_PERF_ANALYSIS
+ * IDSOPT_ASSERT_ENABLED
+ * IDS_DEBUG_PORT
+ * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+ *
+ **/
+
+#define IDSOPT_IDS_ENABLED TRUE
+//#define IDSOPT_CONTROL_ENABLED TRUE
+#define IDSOPT_TRACING_ENABLED TRUE
+//#define IDSOPT_PERF_ANALYSIS TRUE
+#define IDSOPT_ASSERT_ENABLED TRUE
+//#undef IDSOPT_DEBUG_ENABLED
+//#define IDSOPT_DEBUG_ENABLED FALSE
+//#undef IDSOPT_HOST_SIMNOW
+//#define IDSOPT_HOST_SIMNOW FALSE
+//#undef IDSOPT_HOST_HDT
+//#define IDSOPT_HOST_HDT FALSE
+//#define IDS_DEBUG_PORT 0x80
+
+#endif
diff --git a/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl b/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl
new file mode 100755
index 0000000..5eca9cc
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This file defines the processor and performance state capability
+ * for each core in the system. It is included into the DSDT for each
+ * core. It assumes that each core of the system has the same performance
+ * characteristics.
+*/
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001)
+ {
+ Scope (\_PR) {
+ Processor(CPU0,0,0x808,0x06) {
+ #include "cpstate.asl"
+ }
+ Processor(CPU1,1,0x0,0x0) {
+ #include "cpstate.asl"
+ }
+ Processor(CPU2,2,0x0,0x0) {
+ #include "cpstate.asl"
+ }
+ Processor(CPU3,3,0x0,0x0) {
+ #include "cpstate.asl"
+ }
+ }
+*/
+ /* P-state support: The maximum number of P-states supported by the */
+ /* CPUs we'll use is 6. */
+ /* Get from AMI BIOS. */
+ Name(_PSS, Package(){
+ Package ()
+ {
+ 0x00000AF0,
+ 0x0000BF81,
+ 0x00000002,
+ 0x00000002,
+ 0x00000000,
+ 0x00000000
+ },
+
+ Package ()
+ {
+ 0x00000578,
+ 0x000076F2,
+ 0x00000002,
+ 0x00000002,
+ 0x00000001,
+ 0x00000001
+ }
+ })
+
+ Name(_PCT, Package(){
+ ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
+ ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
+ })
+
+ Method(_PPC, 0){
+ Return(0)
+ }
diff --git a/src/mainboard/supermicro/h8qgi/acpi/ide.asl b/src/mainboard/supermicro/h8qgi/acpi/ide.asl
new file mode 100755
index 0000000..c79c18c
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/acpi/ide.asl
@@ -0,0 +1,244 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+Scope (_SB) {
+ Device(PCI0) {
+ Device(IDEC) {
+ Name(_ADR, 0x00140001)
+ #include "ide.asl"
+ }
+ }
+}
+*/
+
+/* Some timing tables */
+Name(UDTT, Package(){ /* Udma timing table */
+ 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */
+})
+
+Name(MDTT, Package(){ /* MWDma timing table */
+ 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */
+})
+
+Name(POTT, Package(){ /* Pio timing table */
+ 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */
+})
+
+/* Some timing register value tables */
+Name(MDRT, Package(){ /* MWDma timing register table */
+ 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */
+})
+
+Name(PORT, Package(){
+ 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */
+})
+
+OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
+ Field(ICRG, AnyAcc, NoLock, Preserve)
+{
+ PPTS, 8, /* Primary PIO Slave Timing */
+ PPTM, 8, /* Primary PIO Master Timing */
+ OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */
+ PMTM, 8, /* Primary MWDMA Master Timing */
+ OFFSET(0x08), PPCR, 8, /* Primary PIO Control */
+ OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */
+ PPSM, 4, /* Primary PIO slave Mode */
+ OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */
+ OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */
+ PDSM, 4, /* Primary UltraDMA Mode */
+}
+
+Method(GTTM, 1) /* get total time*/
+{
+ Store(And(Arg0, 0x0F), Local0) /* Recovery Width */
+ Increment(Local0)
+ Store(ShiftRight(Arg0, 4), Local1) /* Command Width */
+ Increment(Local1)
+ Return(Multiply(30, Add(Local0, Local1)))
+}
+
+Device(PRID)
+{
+ Name (_ADR, Zero)
+ Method(_GTM, 0)
+ {
+ NAME(OTBF, Buffer(20) { /* out buffer */
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+ })
+
+ CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */
+ CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */
+ CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */
+ CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
+ CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
+
+ /* Just return if the channel is disabled */
+ If(And(PPCR, 0x01)) { /* primary PIO control */
+ Return(OTBF)
+ }
+
+ /* Always tell them independent timing available and IOChannelReady used on both drives */
+ Or(BFFG, 0x1A, BFFG)
+
+ Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */
+ Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */
+
+ If(And(PDCR, 0x01)) { /* It's under UDMA mode */
+ Or(BFFG, 0x01, BFFG)
+ Store(DerefOf(Index(UDTT, PDMM)), DSD0)
+ }
+ Else {
+ Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */
+ }
+
+ If(And(PDCR, 0x02)) { /* It's under UDMA mode */
+ Or(BFFG, 0x04, BFFG)
+ Store(DerefOf(Index(UDTT, PDSM)), DSD1)
+ }
+ Else {
+ Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */
+ }
+
+ Return(OTBF) /* out buffer */
+ } /* End Method(_GTM) */
+
+ Method(_STM, 3, NotSerialized)
+ {
+ NAME(INBF, Buffer(20) { /* in buffer */
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+ })
+
+ CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */
+ CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */
+ CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */
+ CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
+ CreateDwordField(INBF, 16, BFFG) /*buffer flag */
+
+ Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
+ Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
+ Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
+ Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
+
+ Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
+ Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
+
+ If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */
+ Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
+ Divide(Local0, 7, PDMM,)
+ Or(PDCR, 0x01, PDCR)
+ }
+ Else {
+ If(LNotEqual(DSD0, 0xFFFFFFFF)) {
+ Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
+ Store(DerefOf(Index(MDRT, Local0)), PMTM)
+ }
+ }
+
+ If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */
+ Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
+ Divide(Local0, 7, PDSM,)
+ Or(PDCR, 0x02, PDCR)
+ }
+ Else {
+ If(LNotEqual(DSD1, 0xFFFFFFFF)) {
+ Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
+ Store(DerefOf(Index(MDRT, Local0)), PMTS)
+ }
+ }
+ /* Return(INBF) */
+ } /*End Method(_STM) */
+ Device(MST)
+ {
+ Name(_ADR, 0)
+ Method(_GTF) {
+ Name(CMBF, Buffer(21) {
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+ })
+ CreateByteField(CMBF, 1, POMD)
+ CreateByteField(CMBF, 8, DMMD)
+ CreateByteField(CMBF, 5, CMDA)
+ CreateByteField(CMBF, 12, CMDB)
+ CreateByteField(CMBF, 19, CMDC)
+
+ Store(0xA0, CMDA)
+ Store(0xA0, CMDB)
+ Store(0xA0, CMDC)
+
+ Or(PPMM, 0x08, POMD)
+
+ If(And(PDCR, 0x01)) {
+ Or(PDMM, 0x40, DMMD)
+ }
+ Else {
+ Store(Match
+ (MDTT, MLE, GTTM(PMTM),
+ MTR, 0, 0), Local0)
+ If(LLess(Local0, 3)) {
+ Or(0x20, Local0, DMMD)
+ }
+ }
+ Return(CMBF)
+ }
+ } /* End Device(MST) */
+
+ Device(SLAV)
+ {
+ Name(_ADR, 1)
+ Method(_GTF) {
+ Name(CMBF, Buffer(21) {
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+ })
+ CreateByteField(CMBF, 1, POMD)
+ CreateByteField(CMBF, 8, DMMD)
+ CreateByteField(CMBF, 5, CMDA)
+ CreateByteField(CMBF, 12, CMDB)
+ CreateByteField(CMBF, 19, CMDC)
+
+ Store(0xB0, CMDA)
+ Store(0xB0, CMDB)
+ Store(0xB0, CMDC)
+
+ Or(PPSM, 0x08, POMD)
+
+ If(And(PDCR, 0x02)) {
+ Or(PDSM, 0x40, DMMD)
+ }
+ Else {
+ Store(Match
+ (MDTT, MLE, GTTM(PMTS),
+ MTR, 0, 0), Local0)
+ If(LLess(Local0, 3)) {
+ Or(0x20, Local0, DMMD)
+ }
+ }
+ Return(CMBF)
+ }
+ } /* End Device(SLAV) */
+}
diff --git a/src/mainboard/supermicro/h8qgi/acpi/routing.asl b/src/mainboard/supermicro/h8qgi/acpi/routing.asl
new file mode 100755
index 0000000..8bc06f6
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/acpi/routing.asl
@@ -0,0 +1,222 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+ )
+ {
+ #include "routing.asl"
+ }
+*/
+
+/* Routing is in System Bus scope */
+Scope(\_SB) {
+ Name(PR0, Package(){
+ /* NB devices */
+ /* Bus 0, Dev 0 - SR5650 HT */
+ Package() { 0xFFFF, Zero, INTA, Zero },
+
+ /* Bus 0, Dev 1 - CLKCONFIG */
+
+ /* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */
+ Package() {0x0002FFFF, 0, INTE, 0 },
+
+ /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+
+ /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+ Package() {0x0004FFFF, 0, INTE, 0 },
+
+ /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+
+ /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
+
+ /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
+
+ /* Bus 0, Dev 8 - Southbridge port (normally hidden) */
+
+ /* Bus 0, Dev 9 - PCIe Bridge */
+
+ /* Bus 0, Dev a - PCIe Bridge */
+
+ /* Bus 0, Dev b - PCIe Bridge */
+ Package() {0x000BFFFF, 0, INTG, 0 },
+
+ /* Bus 0, Dev c - PCIe Bridge */
+ Package() {0x000CFFFF, 0, INTG, 0 },
+
+ /* Bus 0, Dev d - PCIe Bridge for Intel 82576 Giga NIC*/
+ Package() {0x000DFFFF, 0, INTG, 0 },
+
+ /* SB devices */
+ /* Bus 0, Dev 17 - SATA controller */
+ Package() {0x0011FFFF, 0, INTG, 0 },
+
+ /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
+ * EHCI, dev 18, 19 func 2 */
+ Package() {0x0012FFFF, 0, INTA, 0 },
+ Package() {0x0012FFFF, 1, INTB, 0 },
+ Package() {0x0012FFFF, 2, INTC, 0 },
+ Package() {0x0012FFFF, 3, INTD, 0 },
+
+ Package() {0x0013FFFF, 0, INTC, 0 },
+ Package() {0x0013FFFF, 1, INTD, 0 },
+ Package() {0x0013FFFF, 2, INTA, 0 },
+ Package() {0x0013FFFF, 2, INTB, 0 },
+
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
+ Package(){0x0014FFFF, 0, INTA, 0 },
+ Package(){0x0014FFFF, 1, INTB, 0 },
+ Package(){0x0014FFFF, 2, INTC, 0 },
+ Package(){0x0014FFFF, 3, INTD, 0 },
+ })
+
+ Name(APR0, Package(){
+ /* NB devices in APIC mode */
+ /* Bus 0, Dev 0 - SR5650 HT */
+ Package() { 0xFFFF, Zero, Zero, 16 },
+
+ /* Bus 0, Dev 1 - CLKCONFIG */
+
+ /* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot (GFX0) */
+ Package() {0x0002FFFF, 0, 0, 0x34 },
+
+ /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+
+ /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+ Package() {0x0004FFFF, 0, 0, 0x34 },
+
+ /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+
+ /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
+
+ /* Bus 0, Dev 7 - PCIe Bridge */
+
+ /* Bus 0, Dev 8 - Southbridge port (normally hidden) */
+
+ /* Bus 0, Dev 9 - PCIe Bridge */
+
+ /* Bus 0, Dev A - PCIe Bridge */
+
+ /* Bus 0, Dev B - PCIe Bridge */
+ Package() {0x000BFFFF, 0, 0, 0x36 },
+
+ /* Bus 0, Dev C - PCIe Bridge */
+ Package() {0x000CFFFF, 0, 0, 0x36 },
+
+ /* Bus 0, Dev D - PCIe Bridge For Intel 82576 Giga NIC*/
+ Package() {0x000DFFFF, 0, 0, 0x36 },
+
+ /* SB devices in APIC mode */
+ /* Bus 0, Dev 17 - SATA controller */
+ Package() {0x0011FFFF, 0, 0, 0x16 },
+
+ /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
+ * EHCI, dev 18, 19 func 2 */
+ Package( ){0x0012FFFF, 0, 0, 16 },
+ Package() {0x0012FFFF, 1, 0, 17 },
+ Package() {0x0012FFFF, 2, 0, 18 },
+ Package() {0x0012FFFF, 3, 0, 19 },
+
+ Package() {0x0013FFFF, 0, 0, 18 },
+ Package() {0x0013FFFF, 1, 0, 19 },
+ Package() {0x0013FFFF, 2, 0, 16 },
+ Package() {0x0013FFFF, 3, 0, 17 },
+
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
+ Package() {0x0014FFFF, 0, 0, 16 },
+ Package() {0x0014FFFF, 1, 0, 17 },
+ Package() {0x0014FFFF, 2, 0, 18 },
+ Package() {0x0014FFFF, 3, 0, 19 },
+ })
+
+ Name(PS2, Package(){
+ /* The external GFX - Hooked to PCIe slot 4 */
+ Package() {0x0000FFFF, 0, INTC, 0 },
+ Package() {0x0000FFFF, 1, INTD, 0 },
+ Package() {0x0000FFFF, 2, INTA, 0 },
+ Package() {0x0000FFFF, 3, INTB, 0 },
+ })
+ Name(APS2, Package(){
+ /* The external GFX - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, 0, 0x18 },
+ Package(){0x0000FFFF, 1, 0, 0x19 },
+ Package(){0x0000FFFF, 2, 0, 0x1A },
+ Package(){0x0000FFFF, 3, 0, 0x1B },
+ })
+
+ Name(PS4, Package(){
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+ })
+ Name(APS4, Package(){
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, 0, 0x2C },
+ Package(){0x0000FFFF, 1, 0, 0x2D },
+ Package(){0x0000FFFF, 2, 0, 0x2E },
+ Package(){0x0000FFFF, 3, 0, 0x2F },
+ })
+
+ Name(PSb, Package(){
+ /* PCIe slot - Hooked to PCIe slot 11 */
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+ })
+ Name(APSb, Package(){
+ /* PCIe slot - Hooked to PCIe */
+ Package(){0x0000FFFF, 0, 0, 0x20 },
+ Package(){0x0000FFFF, 1, 0, 0x21 },
+ Package(){0x0000FFFF, 2, 0, 0x22 },
+ Package(){0x0000FFFF, 3, 0, 0x23 },
+ })
+
+ Name(PSc, Package(){
+ /* PCIe slot - Hooked to PCIe slot 12 */
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+ })
+ Name(APSc, Package(){
+ /* PCIe slot - Hooked to PCIe */
+ Package(){0x0000FFFF, 0, 0, 0x24 },
+ Package(){0x0000FFFF, 1, 0, 0x25 },
+ Package(){0x0000FFFF, 2, 0, 0x26 },
+ Package(){0x0000FFFF, 3, 0, 0x27 },
+ })
+
+ Name(PSd, Package(){
+ /* PCIe slot - Hooked to PCIe slot 13 */
+ Package(){0x0000FFFF, 0, INTB, 0 },
+ Package(){0x0000FFFF, 1, INTC, 0 },
+ Package(){0x0000FFFF, 2, INTD, 0 },
+ Package(){0x0000FFFF, 3, INTA, 0 },
+ })
+ Name(APSd, Package(){
+ /* PCIe slot - Hooked to PCIe */
+ Package(){0x0000FFFF, 0, 0, 0x28 },
+ Package(){0x0000FFFF, 1, 0, 0x29 },
+ Package(){0x0000FFFF, 2, 0, 0x2A },
+ Package(){0x0000FFFF, 3, 0, 0x2B },
+ })
+}
diff --git a/src/mainboard/supermicro/h8qgi/acpi/sata.asl b/src/mainboard/supermicro/h8qgi/acpi/sata.asl
new file mode 100755
index 0000000..bd4acf0
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/acpi/sata.asl
@@ -0,0 +1,149 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* simple name description */
+
+/*
+Scope (_SB) {
+ Device(PCI0) {
+ Device(SATA) {
+ Name(_ADR, 0x00110000)
+ #include "sata.asl"
+ }
+ }
+}
+*/
+
+Name(STTM, Buffer(20) {
+ 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+ 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+ 0x1f, 0x00, 0x00, 0x00
+})
+
+/* Start by clearing the PhyRdyChg bits */
+Method(_INI) {
+ \_GPE._L1F()
+}
+
+Device(PMRY)
+{
+ Name(_ADR, 0)
+ Method(_GTM, 0x0, NotSerialized) {
+ Return(STTM)
+ }
+ Method(_STM, 0x3, NotSerialized) {}
+
+ Device(PMST) {
+ Name(_ADR, 0)
+ Method(_STA,0) {
+ if (LGreater(P0IS,0)) {
+ return (0x0F) /* sata is visible */
+ }
+ else {
+ return (0x00) /* sata is missing */
+ }
+ }
+ }/* end of PMST */
+
+ Device(PSLA)
+ {
+ Name(_ADR, 1)
+ Method(_STA,0) {
+ if (LGreater(P1IS,0)) {
+ return (0x0F) /* sata is visible */
+ }
+ else {
+ return (0x00) /* sata is missing */
+ }
+ }
+ } /* end of PSLA */
+} /* end of PMRY */
+
+
+Device(SEDY)
+{
+ Name(_ADR, 1) /* IDE Scondary Channel */
+ Method(_GTM, 0x0, NotSerialized) {
+ Return(STTM)
+ }
+ Method(_STM, 0x3, NotSerialized) {}
+
+ Device(SMST)
+ {
+ Name(_ADR, 0)
+ Method(_STA,0) {
+ if (LGreater(P2IS,0)) {
+ return (0x0F) /* sata is visible */
+ }
+ else {
+ return (0x00) /* sata is missing */
+ }
+ }
+ } /* end of SMST */
+
+ Device(SSLA)
+ {
+ Name(_ADR, 1)
+ Method(_STA,0) {
+ if (LGreater(P3IS,0)) {
+ return (0x0F) /* sata is visible */
+ }
+ else {
+ return (0x00) /* sata is missing */
+ }
+ }
+ } /* end of SSLA */
+} /* end of SEDY */
+
+/* SATA Hot Plug Support */
+Scope(\_GPE) {
+ Method(_L1F,0x0,NotSerialized) {
+ if (\_SB.P0PR) {
+ if (LGreater(\_SB.P0IS,0)) {
+ sleep(32)
+ }
+ Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+ store(one, \_SB.P0PR)
+ }
+
+ if (\_SB.P1PR) {
+ if (LGreater(\_SB.P1IS,0)) {
+ sleep(32)
+ }
+ Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+ store(one, \_SB.P1PR)
+ }
+
+ if (\_SB.P2PR) {
+ if (LGreater(\_SB.P2IS,0)) {
+ sleep(32)
+ }
+ Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+ store(one, \_SB.P2PR)
+ }
+
+ if (\_SB.P3PR) {
+ if (LGreater(\_SB.P3IS,0)) {
+ sleep(32)
+ }
+ Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+ store(one, \_SB.P3PR)
+ }
+ }
+}
diff --git a/src/mainboard/supermicro/h8qgi/acpi/usb.asl b/src/mainboard/supermicro/h8qgi/acpi/usb.asl
new file mode 100755
index 0000000..181d685
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/acpi/usb.asl
@@ -0,0 +1,161 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* simple name description */
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+ )
+ {
+ #include "usb.asl"
+ }
+*/
+Method(UCOC, 0) {
+ Sleep(20)
+ Store(0x13,CMTI)
+ Store(0,GPSL)
+}
+
+/* USB Port 0 overcurrent uses Gpm 0 */
+If(LLessEqual(UOM0,9)) {
+ Scope (\_GPE) {
+ Method (_L13) {
+ UCOC()
+ if(LEqual(GPB0,PLC0)) {
+ Not(PLC0,PLC0)
+ Store(PLC0, \_SB.PT0D)
+ }
+ }
+ }
+}
+
+/* USB Port 1 overcurrent uses Gpm 1 */
+If (LLessEqual(UOM1,9)) {
+ Scope (\_GPE) {
+ Method (_L14) {
+ UCOC()
+ if (LEqual(GPB1,PLC1)) {
+ Not(PLC1,PLC1)
+ Store(PLC1, \_SB.PT1D)
+ }
+ }
+ }
+}
+
+/* USB Port 2 overcurrent uses Gpm 2 */
+If (LLessEqual(UOM2,9)) {
+ Scope (\_GPE) {
+ Method (_L15) {
+ UCOC()
+ if (LEqual(GPB2,PLC2)) {
+ Not(PLC2,PLC2)
+ Store(PLC2, \_SB.PT2D)
+ }
+ }
+ }
+}
+
+/* USB Port 3 overcurrent uses Gpm 3 */
+If (LLessEqual(UOM3,9)) {
+ Scope (\_GPE) {
+ Method (_L16) {
+ UCOC()
+ if (LEqual(GPB3,PLC3)) {
+ Not(PLC3,PLC3)
+ Store(PLC3, \_SB.PT3D)
+ }
+ }
+ }
+}
+
+/* USB Port 4 overcurrent uses Gpm 4 */
+If (LLessEqual(UOM4,9)) {
+ Scope (\_GPE) {
+ Method (_L19) {
+ UCOC()
+ if (LEqual(GPB4,PLC4)) {
+ Not(PLC4,PLC4)
+ Store(PLC4, \_SB.PT4D)
+ }
+ }
+ }
+}
+
+/* USB Port 5 overcurrent uses Gpm 5 */
+If (LLessEqual(UOM5,9)) {
+ Scope (\_GPE) {
+ Method (_L1A) {
+ UCOC()
+ if (LEqual(GPB5,PLC5)) {
+ Not(PLC5,PLC5)
+ Store(PLC5, \_SB.PT5D)
+ }
+ }
+ }
+}
+
+/* USB Port 6 overcurrent uses Gpm 6 */
+If (LLessEqual(UOM6,9)) {
+ Scope (\_GPE) {
+ /* Method (_L1C) { */
+ Method (_L06) {
+ UCOC()
+ if (LEqual(GPB6,PLC6)) {
+ Not(PLC6,PLC6)
+ Store(PLC6, \_SB.PT6D)
+ }
+ }
+ }
+}
+
+/* USB Port 7 overcurrent uses Gpm 7 */
+If (LLessEqual(UOM7,9)) {
+ Scope (\_GPE) {
+ /* Method (_L1D) { */
+ Method (_L07) {
+ UCOC()
+ if (LEqual(GPB7,PLC7)) {
+ Not(PLC7,PLC7)
+ Store(PLC7, \_SB.PT7D)
+ }
+ }
+ }
+}
+
+/* USB Port 8 overcurrent uses Gpm 8 */
+If (LLessEqual(UOM8,9)) {
+ Scope (\_GPE) {
+ Method (_L17) {
+ if (LEqual(G8IS,PLC8)) {
+ Not(PLC8,PLC8)
+ Store(PLC8, \_SB.PT8D)
+ }
+ }
+ }
+}
+
+/* USB Port 9 overcurrent uses Gpm 9 */
+If (LLessEqual(UOM9,9)) {
+ Scope (\_GPE) {
+ Method (_L0E) {
+ if (LEqual(G9IS,0)) {
+ Store(1,\_SB.PT9D)
+ }
+ }
+ }
+}
diff --git a/src/mainboard/supermicro/h8qgi/acpi_tables.c b/src/mainboard/supermicro/h8qgi/acpi_tables.c
new file mode 100755
index 0000000..b8ce0b0
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/acpi_tables.c
@@ -0,0 +1,295 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/io.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <cpu/amd/amdfam10_sysconf.h>
+#include "agesawrapper.h"
+
+#define DUMP_ACPI_TABLES 0
+
+#if DUMP_ACPI_TABLES == 1
+static void dump_mem(u32 start, u32 end)
+{
+
+ u32 i;
+ print_debug("dump_mem:");
+ for (i = start; i < end; i++) {
+ if ((i & 0xf) == 0) {
+ printk(BIOS_DEBUG, "\n%08x:", i);
+ }
+ printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
+ }
+ print_debug("\n");
+}
+#endif
+
+extern const unsigned char AmlCode[];
+extern const unsigned char AmlCode_ssdt[];
+
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+ /* Just a dummy */
+ return current;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ device_t dev;
+ u32 dword;
+ u32 gsi_base = 0;
+ u32 apicid_sp5100;
+ u32 apicid_sr5650;
+
+ /*
+ * AGESA v5 Apply apic enumeration rules
+ * For systems with >= 16 APICs, put the IO-APICs at 0..n and
+ * put the local-APICs at m..z
+ * For systems with < 16 APICs, put the Local-APICs at 0..n and
+ * put the IO-APICs at (n + 1)..z
+ */
+#if CONFIG_MAX_CPUS >= 16
+ apicid_sp5100 = 0x0;
+#else
+ apicid_sp5100 = CONFIG_MAX_CPUS + 1
+#endif
+ apicid_sr5650 = apicid_sp5100 + 1;
+
+ /* create all subtables for processors */
+ current = acpi_create_madt_lapics(current);
+
+ /* Write sp5100 IOAPIC, only one */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ apicid_sp5100,
+ IO_APIC_ADDR,
+ 0
+ );
+
+ /* IOAPIC on rs5690 */
+ gsi_base += IO_APIC_INTERRUPTS; /* SP5100 has 24 IOAPIC entries. */
+ dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+ if (dev) {
+ pci_write_config32(dev, 0xF8, 0x1);
+ dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ apicid_sr5650,
+ dword,
+ gsi_base
+ );
+ }
+
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current,
+ 0, //BUS
+ 0, //SOURCE
+ 2, //gsirq
+ 0 //flags
+ );
+
+ /* 0: mean bus 0--->ISA */
+ /* 0: PIC 0 */
+ /* 2: APIC 2 */
+ /* 5 mean: 0101 --> Edige-triggered, Active high */
+
+ /* create all subtables for processors */
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1);
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1);
+ /* 1: LINT1 connect to NMI */
+
+ return current;
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+ // Not implemented
+ return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+ /* No NUMA, no SRAT */
+ return current;
+}
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+ unsigned long current;
+ acpi_rsdp_t *rsdp;
+ acpi_rsdt_t *rsdt;
+ //acpi_hpet_t *hpet;
+ acpi_madt_t *madt;
+ acpi_srat_t *srat;
+ acpi_slit_t *slit;
+ acpi_fadt_t *fadt;
+ acpi_facs_t *facs;
+ acpi_header_t *dsdt;
+ //acpi_header_t *ssdt;
+
+ get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
+
+ /* Align ACPI tables to 16 bytes */
+ start = (start + 0x0f) & -0x10;
+ current = start;
+
+ printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
+
+ /* We need at least an RSDP and an RSDT Table */
+ rsdp = (acpi_rsdp_t *) current;
+ current += sizeof(acpi_rsdp_t);
+ rsdt = (acpi_rsdt_t *) current;
+ current += sizeof(acpi_rsdt_t);
+
+ /* clear all table memory */
+ memset((void *)start, 0, current - start);
+
+ acpi_write_rsdp(rsdp, rsdt, NULL);
+ acpi_write_rsdt(rsdt);
+
+ /* FACS */
+ printk(BIOS_DEBUG, "ACPI: * FACS\n");
+ facs = (acpi_facs_t *) current;
+ current += sizeof(acpi_facs_t);
+ acpi_create_facs(facs);
+
+ /* DSDT */
+ printk(BIOS_DEBUG, "ACPI: * DSDT\n");
+ dsdt = (acpi_header_t *)current;
+ memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+ current += dsdt->length;
+ memcpy(dsdt, &AmlCode, dsdt->length);
+ printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length);
+ /* FADT */
+ printk(BIOS_DEBUG, "ACPI: * FADT\n");
+ fadt = (acpi_fadt_t *) current;
+ current += sizeof(acpi_fadt_t);
+
+ acpi_create_fadt(fadt, facs, dsdt);
+ acpi_add_table(rsdp, fadt);
+
+ /*
+ * We explicitly add these tables later on:
+ */
+#ifdef UNUSED_CODE // Don't need HPET table. we have one in dsdt
+ current = ( current + 0x07) & -0x08;
+ printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current);
+ hpet = (acpi_hpet_t *) current;
+ current += sizeof(acpi_hpet_t);
+ acpi_create_hpet(hpet);
+ acpi_add_table(rsdp, hpet);
+#endif
+
+ /* If we want to use HPET Timers Linux wants an MADT */
+ current = ( current + 0x07) & -0x08;
+ printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current);
+ madt = (acpi_madt_t *) current;
+ acpi_create_madt(madt);
+ current += madt->header.length;
+ acpi_add_table(rsdp, madt);
+
+ /* SRAT */
+ current = ( current + 0x07) & -0x08;
+ printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current);
+ srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
+ if (srat != NULL) {
+ memcpy((void *)current, srat, srat->header.length);
+ srat = (acpi_srat_t *) current;
+ //acpi_create_srat(srat);
+ current += srat->header.length;
+ acpi_add_table(rsdp, srat);
+ }
+
+ /* SLIT */
+ current = ( current + 0x07) & -0x08;
+ printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current);
+ slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
+ if (slit != NULL) {
+ memcpy((void *)current, slit, slit->header.length);
+ slit = (acpi_slit_t *) current;
+ //acpi_create_slit(slit);
+ current += slit->header.length;
+ acpi_add_table(rsdp, slit);
+ }
+
+ /* SSDT */
+ /* NOTE: we not update_ssdt, so ssdt only contain initialize value from ssdt.asl */
+#ifdef UNUSED_CODE
+ current = ( current + 0x0f) & -0x10;
+ printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current);
+ ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
+ if (ssdt != NULL) {
+ memcpy(current, ssdt, ssdt->length);
+ ssdt = (acpi_header_t *) current;
+ current += ssdt->length;
+ }
+ else {
+ ssdt = (acpi_header_t *) current;
+ memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
+ current += ssdt->length;
+ memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
+ /* recalculate checksum */
+ ssdt->checksum = 0;
+ ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
+ }
+ acpi_add_table(rsdp,ssdt);
+
+ printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current);
+#endif
+
+ /* DSDT */
+ current = ( current + 0x07) & -0x08;
+ printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current);
+ dsdt = (acpi_header_t *)current; // it will used by fadt
+ memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+ current += dsdt->length;
+ memcpy(dsdt, &AmlCode, dsdt->length);
+ printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length);
+
+#if DUMP_ACPI_TABLES == 1
+ printk(BIOS_DEBUG, "rsdp\n");
+ dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
+
+ printk(BIOS_DEBUG, "rsdt\n");
+ dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
+
+ printk(BIOS_DEBUG, "madt\n");
+ dump_mem(madt, ((void *)madt) + madt->header.length);
+
+ printk(BIOS_DEBUG, "srat\n");
+ dump_mem(srat, ((void *)srat) + srat->header.length);
+
+ printk(BIOS_DEBUG, "slit\n");
+ dump_mem(slit, ((void *)slit) + slit->header.length);
+
+ printk(BIOS_DEBUG, "ssdt\n");
+ dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
+
+ printk(BIOS_DEBUG, "fadt\n");
+ dump_mem(fadt, ((void *)fadt) + fadt->header.length);
+#endif
+
+ printk(BIOS_INFO, "ACPI: done.\n");
+ return current;
+}
diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.c b/src/mainboard/supermicro/h8qgi/agesawrapper.c
new file mode 100755
index 0000000..186c708
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/agesawrapper.c
@@ -0,0 +1,1169 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*----------------------------------------------------------------------------------------
+ * M O D U L E S U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include "agesawrapper.h"
+#include "BiosCallOuts.h"
+#include "cpuRegisters.h"
+#include "cpuCacheInit.h"
+#include "cpuApicUtilities.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "Dispatcher.h"
+#include "cpuCacheInit.h"
+#include "amdlib.h"
+#include "platform_oem.h"
+#include "Filecode.h"
+#include "heapManager.h"
+#include <cpuFamilyTranslation.h> /* CPU_SPECIFIC_SERVICES */
+
+#define FILECODE UNASSIGNED_FILE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/* ACPI table pointers returned by AmdInitLate */
+VOID *DmiTable = NULL;
+VOID *AcpiPstate = NULL;
+VOID *AcpiSrat = NULL;
+VOID *AcpiSlit = NULL;
+
+VOID *AcpiWheaMce = NULL;
+VOID *AcpiWheaCmc = NULL;
+//VOID *AcpiAlib = NULL;
+
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S A N D S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * P R O T O T Y P E S O F L O C A L F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * E X P O R T E D F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------
+ * L O C A L F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+static UINT32 agesawrapper_amdinitcpuio(VOID)
+{
+ AGESA_STATUS Status;
+ UINT32 PciData;
+ PCI_ADDR PciAddress;
+ AMD_CONFIG_PARAMS StdHeader;
+ UINT32 nodes;
+ UINT32 node;
+ UINT32 sblink;
+ UINT32 i;
+
+ /* get the number of coherent nodes in the system */
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60);
+ LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ nodes = ((PciData >> 4) & 7) + 1; //NodeCnt[2:0]
+
+ /* Find out the Link ID of Node0 that connects to the
+ * Southbridge (system IO hub). e.g. family10 MCM Processor,
+ * sbLink is Processor0 Link2, internal Node0 Link3
+ */
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64);
+ LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ sblink = (PciData >> 8) & 3; //assume ganged
+
+ /* Enable MMIO on AMD CPU Address Map Controller for all nodes */
+ for (node = 0; node < nodes; node++) {
+ /* clear all MMIO Mapped Base/Limit Registers */
+ for (i = 0; i < 8; i++) {
+ PciData = 0x00000000;
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80 + i*8);
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84 + i*8);
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ }
+
+ /* clear all IO Space Base/Limit Registers */
+ for (i = 0; i < 4; i++) {
+ PciData = 0x00000000;
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4 + i*8);
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0 + i*8);
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ }
+
+ /* Set VGA Ram MMIO 0000A0000-0000BFFFF to Node0 sbLink */
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84);
+ PciData = 0x00000B00;
+ PciData |= sblink << 4;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80);
+ PciData = 0x00000A03;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+ /* Set F0000000-FFFFFFFF to Node0 sbLink. */
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x8C);
+ PciData = 0x00FFFF00;
+ PciData |= sblink << 4;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ PciData = 0x00F00000 | 0x03;
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x88);
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+ /* Set MMCONF space to Node0 sbLink with NP set.
+ * default E0000000-EFFFFFFF
+ * Just have all mmio set to non-posted,
+ * coreboot not implemente the range by range setting yet.
+ */
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xBC);
+ PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000);//1MB each bus
+ PciData = (PciData >> 8) & 0xFFFFFF00;
+ PciData |= 0x80; //NP
+ PciData |= sblink << 4;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xB8);
+ PciData = (PCIE_BASE_ADDRESS >> 8) | 0x03;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+
+ /* Start to set IO 0x9000-0xEFFF to Node0 sbLink with ISA&VGA set. */
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4);
+ PciData = 0x0000E000;
+ PciData |= sblink << 4;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0);
+ PciData = 0x00009033;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ }
+
+ Status = AGESA_SUCCESS;
+ return (UINT32)Status;
+}
+
+UINT32 agesawrapper_amdinitmmio(VOID)
+{
+ AGESA_STATUS Status;
+ UINT64 MsrReg;
+ AMD_CONFIG_PARAMS StdHeader;
+
+ /*
+ * Set the MMIO Configuration Base Address and Bus Range onto
+ * MMIO configuration base Address MSR register.
+ */
+ MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
+ LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
+
+ /*
+ * Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
+ */
+ LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader);
+ MsrReg = MsrReg | (1ULL << 46);
+ LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
+
+ /* Set ROM cache onto WP to decrease post time */
+ MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5;
+ LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
+ MsrReg = (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800;
+ LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
+
+ Status = AGESA_SUCCESS;
+ return (UINT32)Status;
+}
+
+UINT32 agesawrapper_amdinitreset(VOID)
+{
+ AGESA_STATUS status = AGESA_SUCCESS;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ AMD_RESET_PARAMS AmdResetParams;
+
+ LibAmdMemFill(&AmdParamStruct,
+ 0,
+ sizeof(AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ LibAmdMemFill(&AmdResetParams,
+ 0,
+ sizeof(AMD_RESET_PARAMS),
+ &(AmdResetParams.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
+ AmdParamStruct.AllocationMethod = ByHost;
+ AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
+ AmdParamStruct.NewStructPtr = &AmdResetParams;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = NULL;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+ AmdCreateStruct(&AmdParamStruct);
+ AmdResetParams.HtConfig.Depth = 0;
+
+ //MARG34PI disabled AGESA_ENTRY_INIT_RESET by default
+ //but we need to call AmdCreateStruct to call HeapManagerInit, or the event log not work
+#if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE)
+ status = AmdInitReset((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
+#endif
+ if (status != AGESA_SUCCESS)
+ agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
+ AmdReleaseStruct(&AmdParamStruct);
+
+ return (UINT32)status;
+}
+
+UINT32 agesawrapper_amdinitearly(VOID)
+{
+ AGESA_STATUS status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
+ UINT32 TscRateInMhz;
+ CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+ LibAmdMemFill(&AmdParamStruct,
+ 0,
+ sizeof(AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
+ AmdParamStruct.AllocationMethod = PreMemHeap;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+ AmdCreateStruct(&AmdParamStruct);
+
+ AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
+ OemCustomizeInitEarly(AmdEarlyParamsPtr);
+
+ status = AmdInitEarly((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
+ if (status != AGESA_SUCCESS)
+ agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
+
+ GetCpuServicesOfCurrentCore(&FamilySpecificServices, &AmdParamStruct.StdHeader);
+ FamilySpecificServices->GetTscRate(FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader);
+ printk(BIOS_DEBUG, "BSP Frequency: %luMHz\n", TscRateInMhz);
+
+ AmdReleaseStruct(&AmdParamStruct);
+ return (UINT32)status;
+}
+
+UINT32 agesawrapper_amdinitpost(VOID)
+{
+ AGESA_STATUS status;
+ UINT16 i;
+ UINT32 *HeadPtr;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ BIOS_HEAP_MANAGER *BiosManagerPtr;
+ UINT32 TscRateInMhz;
+ CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+ LibAmdMemFill(&AmdParamStruct,
+ 0,
+ sizeof(AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
+ AmdParamStruct.AllocationMethod = PreMemHeap;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+ AmdCreateStruct(&AmdParamStruct);
+ status = AmdInitPost((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
+ if (status != AGESA_SUCCESS)
+ agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
+ AmdReleaseStruct(&AmdParamStruct);
+
+ /* Initialize heap space */
+ BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
+
+ HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof(BIOS_HEAP_MANAGER));
+ for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof(BIOS_HEAP_MANAGER)/4)); i++) {
+ *HeadPtr = 0x00000000;
+ HeadPtr++;
+ }
+ BiosManagerPtr->StartOfAllocatedNodes = 0;
+ BiosManagerPtr->StartOfFreedNodes = 0;
+
+ GetCpuServicesOfCurrentCore (&FamilySpecificServices, &AmdParamStruct.StdHeader);
+ FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader);
+ printk(BIOS_DEBUG, "BSP Frequency: %luMHz\n", TscRateInMhz);
+
+ return (UINT32)status;
+}
+
+UINT32 agesawrapper_amdinitenv(VOID)
+{
+ AGESA_STATUS status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+
+ LibAmdMemFill(&AmdParamStruct,
+ 0,
+ sizeof(AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
+ AmdParamStruct.AllocationMethod = PostMemDram;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+ AmdCreateStruct(&AmdParamStruct);
+ status = AmdInitEnv((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
+ if (status != AGESA_SUCCESS)
+ agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
+
+ AmdReleaseStruct(&AmdParamStruct);
+ return (UINT32)status;
+}
+
+VOID * agesawrapper_getlateinitptr(int pick)
+{
+ switch (pick) {
+ case PICK_DMI:
+ return DmiTable;
+
+ case PICK_PSTATE:
+ return AcpiPstate;
+
+ case PICK_SRAT:
+ return AcpiSrat;
+
+ case PICK_SLIT:
+ return AcpiSlit;
+ case PICK_WHEA_MCE:
+ return AcpiWheaMce;
+ case PICK_WHEA_CMC:
+ return AcpiWheaCmc;
+/*
+ case PICK_ALIB:
+ return AcpiAlib;
+*/
+ default:
+ return NULL;
+ }
+
+ return NULL;
+}
+
+UINT32 agesawrapper_amdinitmid(VOID)
+{
+ AGESA_STATUS status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+
+ /* Enable MMIO on AMD CPU Address Map Controller */
+ agesawrapper_amdinitcpuio();
+
+ LibAmdMemFill(&AmdParamStruct,
+ 0,
+ sizeof(AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
+ AmdParamStruct.AllocationMethod = PostMemDram;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+ AmdCreateStruct(&AmdParamStruct);
+ status = AmdInitMid((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
+ if (status != AGESA_SUCCESS)
+ agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
+ AmdReleaseStruct(&AmdParamStruct);
+
+ return (UINT32)status;
+}
+
+UINT32 agesawrapper_amdinitlate(VOID)
+{
+ AGESA_STATUS Status;
+ AMD_LATE_PARAMS AmdLateParams;
+
+ LibAmdMemFill(&AmdLateParams,
+ 0,
+ sizeof(AMD_LATE_PARAMS),
+ &(AmdLateParams.StdHeader));
+
+ AmdLateParams.StdHeader.AltImageBasePtr = 0;
+ AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdLateParams.StdHeader.Func = 0;
+ AmdLateParams.StdHeader.ImageBasePtr = 0;
+ AmdLateParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
+
+ Status = AmdInitLate(&AmdLateParams);
+ if (Status != AGESA_SUCCESS) {
+ agesawrapper_amdreadeventlog(AmdLateParams.StdHeader.HeapStatus);
+ ASSERT(Status == AGESA_SUCCESS);
+ }
+
+ DmiTable = AmdLateParams.DmiTable;
+ AcpiPstate = AmdLateParams.AcpiPState;
+ AcpiSrat = AmdLateParams.AcpiSrat;
+ AcpiSlit = AmdLateParams.AcpiSlit;
+
+ AcpiWheaMce = AmdLateParams.AcpiWheaMce;
+ AcpiWheaCmc = AmdLateParams.AcpiWheaCmc;
+ //AcpiAlib = AmdLateParams.AcpiAlib;
+
+ return (UINT32)Status;
+}
+
+/**
+ * @param[in] UINTN ApicIdOfCore,
+ * @param[in] AP_EXE_PARAMS *LaunchApParams
+ */
+UINT32 agesawrapper_amdlaterunaptask(UINT32 Data, VOID *ConfigPtr)
+{
+ AGESA_STATUS Status;
+ AMD_LATE_PARAMS AmdLateParams;
+
+ LibAmdMemFill(&AmdLateParams,
+ 0,
+ sizeof(AMD_LATE_PARAMS),
+ &(AmdLateParams.StdHeader));
+
+ AmdLateParams.StdHeader.AltImageBasePtr = 0;
+ AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdLateParams.StdHeader.Func = 0;
+ AmdLateParams.StdHeader.ImageBasePtr = 0;
+ AmdLateParams.StdHeader.HeapStatus = HEAP_TEMP_MEM;
+
+ printk(BIOS_DEBUG, "AmdLateRunApTask on Core: %x\n", (uint32_t)Data);
+ Status = AmdLateRunApTask((AP_EXE_PARAMS *)ConfigPtr);
+ if (Status != AGESA_SUCCESS) {
+ agesawrapper_amdreadeventlog(AmdLateParams.StdHeader.HeapStatus);
+ ASSERT(Status <= AGESA_UNSUPPORTED);
+ }
+
+ DmiTable = AmdLateParams.DmiTable;
+ AcpiPstate = AmdLateParams.AcpiPState;
+ AcpiSrat = AmdLateParams.AcpiSrat;
+ AcpiSlit = AmdLateParams.AcpiSlit;
+
+ AcpiWheaMce = AmdLateParams.AcpiWheaMce;
+ AcpiWheaCmc = AmdLateParams.AcpiWheaCmc;
+ // AcpiAlib = AmdLateParams.AcpiAlib;
+
+ return (UINT32)Status;
+}
+
+/**
+ *
+ */
+static void agesa_bound_check(EVENT_PARAMS *event)
+{
+ switch (event->EventInfo) {
+ case CPU_ERROR_HEAP_IS_FULL:
+ printk(BIOS_DEBUG, "Heap allocation for specified buffer handle failed as heap is full\n");
+ break;
+
+ case CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED:
+ printk(BIOS_DEBUG, "Allocation incomplete as buffer has previously been allocated\n");
+ break;
+
+ case CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT:
+ printk(BIOS_DEBUG, "Unable to locate buffer handle or deallocate heap as buffer handle cannot be located\n");
+ break;
+
+ case CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT:
+ printk(BIOS_DEBUG, "Unable to locate pointer to the heap buffer\n");
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ *
+ */
+static void agesa_alert(EVENT_PARAMS *event)
+{
+ switch (event->EventInfo) {
+ case MEM_ALERT_USER_TMG_MODE_OVERRULED:
+ printk(BIOS_DEBUG, "Socket %lx Dct %lx Channel %lx "
+ "TIMING_MODE_SPECIFIC is requested but can not be applied to current configurations.\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case MEM_ALERT_ORG_MISMATCH_DIMM:
+ printk(BIOS_DEBUG, "Socket %lx Dct %lx Channel %lx "
+ "DIMM organization miss-match\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case MEM_ALERT_BK_INT_DIS:
+ printk(BIOS_DEBUG, "Socket %lx Dct %lx Channel %lx "
+ "Bank interleaving disable for internal issue\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case CPU_EVENT_BIST_ERROR:
+ printk(BIOS_DEBUG, "BIST error: %lx reported on Socket %lx Core %lx\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case HT_EVENT_HW_SYNCFLOOD:
+ printk(BIOS_DEBUG, "HT_EVENT_DATA_HW_SYNCFLOOD error on Socket %lx Link %lx\n",
+ event->DataParam1,
+ event->DataParam2);
+ break;
+
+ case HT_EVENT_HW_HTCRC:
+ printk(BIOS_DEBUG, "HT_EVENT_HW_HTCRC error on Socket %lx Link %lx Lanemask:%lx\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ *
+ */
+static void agesa_warning(EVENT_PARAMS *event)
+{
+/*
+ if (event->EventInfo == CPU_EVENT_STACK_REENTRY) {
+ printk(BIOS_DEBUG,
+ "The stack has already been enabled and this is a
+ redundant invocation of AMD_ENABLE_STACK. There is no event logged and
+ no data values. The event sub-class is returned along with the status code\n");
+ return;
+ }
+*/
+
+ switch (event->EventInfo >> 24) {
+ case 0x04:
+ printk(BIOS_DEBUG, "Memory: Socket %lx Dct %lx Channel%lx ",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case 0x08:
+ printk(BIOS_DEBUG, "Processor: ");
+ break;
+
+ case 0x10:
+ printk(BIOS_DEBUG, "Hyper Transport: ");
+ break;
+
+ default:
+ break;
+ }
+
+ switch (event->EventInfo) {
+ case MEM_WARNING_UNSUPPORTED_QRDIMM:
+ printk(BIOS_DEBUG, "QR DIMMs detected but not supported\n");
+ break;
+
+ case MEM_WARNING_UNSUPPORTED_UDIMM:
+ printk(BIOS_DEBUG, "Unbuffered DIMMs detected but not supported\n");
+ break;
+
+ case MEM_WARNING_UNSUPPORTED_SODIMM:
+ printk(BIOS_DEBUG, "SO-DIMMs detected but not supported");
+ break;
+
+ case MEM_WARNING_UNSUPPORTED_X4DIMM:
+ printk(BIOS_DEBUG, "x4 DIMMs detected but not supported");
+ break;
+
+ case MEM_WARNING_UNSUPPORTED_RDIMM:
+ printk(BIOS_DEBUG, "Registered DIMMs detected but not supported");
+ break;
+
+/*
+ case MEM_WARNING_UNSUPPORTED_LRDIMM:
+ printk(BIOS_DEBUG, "Load Reduced DIMMs detected but not supported");
+ break;
+*/
+
+ case MEM_WARNING_NO_SPDTRC_FOUND:
+ printk(BIOS_DEBUG, "NO_SPDTRC_FOUND");
+ break;
+
+ case MEM_WARNING_EMP_NOT_SUPPORTED:
+ printk(BIOS_DEBUG, "Processor is not capable for EMP");//
+ break;
+
+ case MEM_WARNING_EMP_CONFLICT:
+ printk(BIOS_DEBUG, "EMP cannot be enabled if channel interleaving bank interleaving, or bank swizzle is enabled\n");//
+ break;
+
+ case MEM_WARNING_EMP_NOT_ENABLED:
+ printk(BIOS_DEBUG, "Memory size is not power of two\n");//
+ break;
+
+ case MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED:
+ printk(BIOS_DEBUG, "MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED\n");
+ break;
+
+ case MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED:
+ printk(BIOS_DEBUG, "MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED\n");
+ break;
+
+ case MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED:
+ printk(BIOS_DEBUG, "MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED\n");
+ break;
+
+ case MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED:
+ printk(BIOS_DEBUG, "MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED\n");
+ break;
+
+ case MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED:
+ printk(BIOS_DEBUG, "MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED\n");
+ break;
+
+/*
+ case MEM_WARNING_INITIAL_DDR3VOLT_NONZERO:
+ printk(BIOS_DEBUG, "MEM_WARNING_INITIAL_DDR3VOLT_NONZERO\n");
+ break;
+
+ case MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO:
+ printk(BIOS_DEBUG, "MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO\n");
+ break;
+*/
+
+ case CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR:
+ printk(BIOS_DEBUG, "Allocation rule number that has been violated:");
+ if ((event->EventInfo & 0x000000FF) == 0x01) {
+ printk(BIOS_DEBUG, "AGESA_CACHE_SIZE_REDUCED\n");
+ } else if ((event->EventInfo & 0x000000FF) == 0x02) {
+ printk(BIOS_DEBUG, "AGESA_CACHE_REGIONS_ACROSS_1MB\n");
+ } else if ((event->EventInfo & 0x000000FF) == 0x03) {
+ printk(BIOS_DEBUG, "AGESA_CACHE_REGIONS_ACROSS_4GB\n");
+ }
+ printk(BIOS_DEBUG, "cache region index:%lx, start:%lx size:%lx\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case CPU_WARNING_ADJUSTED_LEVELING_MODE:
+ printk(BIOS_DEBUG, "CPU_WARNING_ADJUSTED_LEVELING_MODE "
+ "requested: %lx, actual level:%lx\n",
+ event->DataParam1,
+ event->DataParam2);
+ break;
+
+ case CPU_EVENT_PM_PSTATE_OVERCURRENT:
+ printk(BIOS_DEBUG, "CPU_EVENT_PM_PSTATE_OVERCURRENT "
+ "Socket: %lx, Pstate:%lx\n",
+ event->DataParam1,
+ event->DataParam2);
+ break;
+
+ case CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG:
+ printk(BIOS_DEBUG, "CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG\n");
+ break;
+
+/*
+ case CPU_EVENT_UNKNOWN_PROCESSOR_REVISION:
+ printk(BIOS_DEBUG, "CPU_EVENT_UNKNOWN_PROCESSOR_REVISION, socket: %lx, cpuid:%lx\n",
+ event->DataParam1,
+ event->DataParam2);
+ break;
+*/
+
+ case HT_EVENT_OPT_REQUIRED_CAP_RETRY:
+ printk(BIOS_DEBUG, "HT_EVENT_OPT_REQUIRED_CAP_RETRY, Socket %lx Link %lx Depth %lx\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case HT_EVENT_OPT_REQUIRED_CAP_GEN3:
+ printk(BIOS_DEBUG, "HT_EVENT_OPT_REQUIRED_CAP_GEN3, Socket %lx Link %lx Depth %lx\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case HT_EVENT_OPT_UNUSED_LINKS:
+ printk(BIOS_DEBUG, "HT_EVENT_OPT_UNUSED_LINKS, SocketA%lx LinkA%lx SocketB%lx LinkB%lx\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3,
+ event->DataParam4);
+ break;
+
+ case HT_EVENT_OPT_LINK_PAIR_EXCEED:
+ printk(BIOS_DEBUG, "HT_EVENT_OPT_LINK_PAIR_EXCEED, SocketA%lx MasterLink%lx SocketB%lx AltLink%lx\n",
+
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3,
+ event->DataParam4);
+ default:
+ break;
+ }
+}
+
+/**
+ *
+ */
+static void agesa_error(EVENT_PARAMS *event)
+{
+
+ switch (event->EventInfo >> 24) {
+ case 0x04:
+ printk(BIOS_DEBUG, "Memory: Socket %lx Dct %lx Channel%lx ",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case 0x08:
+ printk(BIOS_DEBUG, "Processor: ");
+ break;
+
+ case 0x10:
+ printk(BIOS_DEBUG, "Hyper Transport: ");
+ break;
+
+ default:
+ break;
+ }
+
+ switch (event->EventInfo) {
+ case MEM_ERROR_NO_DQS_POS_RD_WINDOW:
+ printk(BIOS_DEBUG, "No DQS Position window for RD DQS\n");
+ break;
+
+ case MEM_ERROR_SMALL_DQS_POS_RD_WINDOW:
+ printk(BIOS_DEBUG, "Small DQS Position window for RD DQS\n");
+ break;
+
+ case MEM_ERROR_NO_DQS_POS_WR_WINDOW:
+ printk(BIOS_DEBUG, "No DQS Position window for WR DQS\n");
+ break;
+
+ case MEM_ERROR_SMALL_DQS_POS_WR_WINDOW:
+ printk(BIOS_DEBUG, "Small DQS Position window for WR DQS\n");
+ break;
+
+ case MEM_ERROR_ECC_DIS:
+ printk(BIOS_DEBUG, "ECC has been disabled as a result of an internal issue\n");
+ break;
+
+ case MEM_ERROR_DIMM_SPARING_NOT_ENABLED:
+ printk(BIOS_DEBUG, "DIMM sparing has not been enabled for an internal issues\n");
+ break;
+
+ case MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE:
+ printk(BIOS_DEBUG, "Receive Enable value is too large\n");
+ break;
+ case MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW:
+ printk(BIOS_DEBUG, "There is no DQS receiver enable window\n");
+ break;
+
+ case MEM_ERROR_DRAM_ENABLED_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling DramEnabled bit\n");
+ break;
+
+ case MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling DctAccessDone bit\n");
+ break;
+
+ case MEM_ERROR_SEND_CTRL_WORD_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling SendCtrlWord bit\n");
+ break;
+
+ case MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling PrefDramTrainMode bit\n");
+ break;
+
+ case MEM_ERROR_ENTER_SELF_REF_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling EnterSelfRef bit\n");
+ break;
+
+ case MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling FreqChgInProg bit\n");
+ break;
+
+ case MEM_ERROR_EXIT_SELF_REF_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling ExitSelfRef bit\n");
+ break;
+
+ case MEM_ERROR_SEND_MRS_CMD_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling SendMrsCmd bit\n");
+ break;
+
+ case MEM_ERROR_SEND_ZQ_CMD_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling SendZQCmd bit\n");
+ break;
+
+ case MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling DctExtraAccessDone bit\n");
+ break;
+
+ case MEM_ERROR_MEM_CLR_BUSY_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling MemClrBusy bit\n");
+ break;
+
+ case MEM_ERROR_MEM_CLEARED_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling MemCleared bit\n");
+ break;
+
+ case MEM_ERROR_FLUSH_WR_TIME_OUT:
+ printk(BIOS_DEBUG, "Time out when polling FlushWr bit\n");
+ break;
+
+ case MEM_ERROR_MAX_LAT_NO_WINDOW:
+ printk(BIOS_DEBUG, "Fail to find pass during Max Rd Latency training\n");
+ break;
+
+ case MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL:
+ printk(BIOS_DEBUG, "Fail to launch training code on an AP\n");
+ break;
+
+ case MEM_ERROR_PARALLEL_TRAINING_TIME_OUT:
+ printk(BIOS_DEBUG, "Fail to finish parallel training\n");
+ break;
+
+ case MEM_ERROR_NO_ADDRESS_MAPPING:
+ printk(BIOS_DEBUG, "No address mapping found for a dimm\n");
+ break;
+
+ case MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT:
+ printk(BIOS_DEBUG, "There is no DQS receiver enable window and the value is equal to the largest value\n");
+ break;
+
+ case MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE:
+ printk(BIOS_DEBUG, "Receive Enable value is too large and is 1 less than limit\n");
+ break;
+
+ case MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR:
+ printk(BIOS_DEBUG, "SPD Checksum error for NV_SPDCHK_RESTRT\n");
+ break;
+
+ case MEM_ERROR_NO_CHIPSELECT:
+ printk(BIOS_DEBUG, "No chipselects found\n");
+ break;
+
+ case MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM:
+ printk(BIOS_DEBUG, "Unbuffered dimm is not supported at 333MHz\n");
+ break;
+
+ case MEM_ERROR_WL_PRE_OUT_OF_RANGE:
+ printk(BIOS_DEBUG, "Returned PRE value during write levelizzation was out of range\n");
+ break;
+
+ case CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE:
+ printk(BIOS_DEBUG, "No heap is allocated for BrandId structure\n");
+ break;
+
+ case CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED:
+ printk(BIOS_DEBUG, "Unable to load micro code patch\n");
+ break;
+
+ case CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE:
+ printk(BIOS_DEBUG, "No heap is allocated for the Pstate structure\n");
+ break;
+
+/*
+ case CPU_ERROR_PM_NB_PSTATE_MISMATCH:
+ printk(BIOS_DEBUG, "NB P-state indicated by Index was disabled due to mismatch between processors\n");
+ break;
+*/
+
+ case CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR:
+ printk(BIOS_DEBUG, "Allocation rule number that has been violated:");
+ if ((event->EventInfo & 0x000000FF) == 0x04) {
+ printk(BIOS_DEBUG, "AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY\n");
+ } else if ((event->EventInfo & 0x000000FF) == 0x05) {
+ printk(BIOS_DEBUG, "AGESA_START_ADDRESS_LESS_D0000\n");
+ } else if ((event->EventInfo & 0x000000FF) == 0x06) {
+ printk(BIOS_DEBUG, "AGESA_THREE_CACHE_REGIONS_ABOVE_1MB\n");
+ } else if ((event->EventInfo & 0x000000FF) == 0x07) {
+ printk(BIOS_DEBUG, "AGESA_DEALLOCATE_CACHE_REGIONS\n");
+ }
+ printk(BIOS_DEBUG, "cache region index:%lx, start:%lx size:%lx\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case HT_EVENT_COH_NO_TOPOLOGY:
+ printk(BIOS_DEBUG, "no Matching Topology was found during coherent initializatio TotalHtNodes: %lx\n",
+ event->DataParam1);
+ break;
+
+ case HT_EVENT_NCOH_BUID_EXCEED:
+ printk(BIOS_DEBUG, "there is a limit of 32 unit IDs per chain Socket%lx Link%lx Depth%lx"
+ "Current BUID: %lx, Unit Count: %lx\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3,
+ event->DataParam4 >> 16,
+ event->DataParam4 & 0x0000FFFF);
+ break;
+
+ case HT_EVENT_NCOH_BUS_MAX_EXCEED:
+ printk(BIOS_DEBUG, "maximum auto bus limit exceeded, Socket %lx Link %lx Bus %lx\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case HT_EVENT_NCOH_CFG_MAP_EXCEED:
+ printk(BIOS_DEBUG, "there is a limit of four non-coherent chains, Socket %lx Link %lx\n",
+ event->DataParam1,
+ event->DataParam2);
+ break;
+
+ case HT_EVENT_NCOH_DEVICE_FAILED:
+ printk(BIOS_DEBUG, "after assigning an IO Device an ID, it does not respond at the new ID"
+ "Socket %lx Link %lx Depth %lx DeviceID %lx\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3,
+ event->DataParam4);
+ default:
+ break;
+ }
+}
+/**
+ *
+ */
+static void agesa_critical(EVENT_PARAMS *event)
+{
+ switch (event->EventInfo) {
+ case MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3:
+ printk(BIOS_DEBUG, "Socket: %lx, Heap allocation error for DMI table for DDR3\n",
+ event->DataParam1);
+ break;
+
+ case MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2:
+ printk(BIOS_DEBUG, "Socket: %lx, Heap allocation error for DMI table for DDR2\n",
+ event->DataParam1);
+ break;
+
+ case MEM_ERROR_UNSUPPORTED_DIMM_CONFIG:
+ printk(BIOS_DEBUG, "Socket: %lx, Dimm population is not supported\n",
+ event->DataParam1);
+ break;
+
+ case HT_EVENT_COH_PROCESSOR_TYPE_MIX:
+ printk(BIOS_DEBUG, "Socket %lx Link %lx TotalSockets %lx, HT_EVENT_COH_PROCESSOR_TYPE_MIX \n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case HT_EVENT_COH_MPCAP_MISMATCH:
+ printk(BIOS_DEBUG, "Socket %lx Link %lx MpCap %lx TotalSockets %lx, HT_EVENT_COH_MPCAP_MISMATCH\n",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3,
+ event->DataParam4);
+ default:
+ break;
+ }
+}
+
+/**
+ *
+ */
+static void agesa_fatal(EVENT_PARAMS *event)
+{
+
+ switch (event->EventInfo >> 24) {
+ case 0x04:
+ printk(BIOS_DEBUG, "Memory: Socket %lx Dct %lx Channel%lx ",
+ event->DataParam1,
+ event->DataParam2,
+ event->DataParam3);
+ break;
+
+ case 0x08:
+ printk(BIOS_DEBUG, "Processor: ");
+ break;
+
+ case 0x10:
+ printk(BIOS_DEBUG, "Hyper Transport: ");
+ break;
+
+ default:
+ break;
+ }
+
+ switch (event->EventInfo) {
+ case MEM_ERROR_MINIMUM_MODE:
+ printk(BIOS_DEBUG, "Running in minimum mode\n");
+ break;
+
+ case MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM:
+ printk(BIOS_DEBUG, "DIMM modules are missmatched\n");
+ break;
+
+ case MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM:
+ printk(BIOS_DEBUG, "No DIMMs have been foun\n");
+ break;
+
+ case MEM_ERROR_MISMATCH_DIMM_CLOCKS:
+ printk(BIOS_DEBUG, "DIMM clocks miss-matched\n");
+ break;
+
+ case MEM_ERROR_NO_CYC_TIME:
+ printk(BIOS_DEBUG, "No cycle time found\n");
+ break;
+ case MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS:
+ printk(BIOS_DEBUG, "Heap allocation error with dynamic storing of trained timings\n");
+ break;
+
+ case MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs:
+ printk(BIOS_DEBUG, "Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT\n");
+ break;
+
+ case MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV:
+ printk(BIOS_DEBUG, "Heap allocation error with REMOTE_TRAINING_ENV\n");
+ break;
+
+ case MEM_ERROR_HEAP_ALLOCATE_FOR_SPD:
+ printk(BIOS_DEBUG, "Heap allocation error for SPD data\n");
+ break;
+
+ case MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA:
+ printk(BIOS_DEBUG, "Heap allocation error for RECEIVED_DATA during parallel training\n");
+ break;
+
+ case MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS:
+ printk(BIOS_DEBUG, "Heap allocation error for S3 \"SPECIAL_CASE_REGISTER\"\n");
+ break;
+
+ case MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA:
+ printk(BIOS_DEBUG, "Heap allocation error for Training Data\n");
+ break;
+
+ case MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK:
+ printk(BIOS_DEBUG, "Heap allocation error for DIMM Identify \"MEM_NB_BLOCK\"\n");
+ break;
+
+ case MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM:
+ printk(BIOS_DEBUG, "No Constructor for DIMM Identify\n");
+ break;
+
+ case MEM_ERROR_VDDIO_UNSUPPORTED:
+ printk(BIOS_DEBUG, "VDDIO of the dimms on the board is not supported\n");
+ break;
+
+ case CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT:
+ printk(BIOS_DEBUG, "Socket: %lx, All PStates exceeded the motherboard current limit on specified socket\n",
+ event->DataParam1);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ *
+ * Interprte the agesa event log to an user readable string
+ */
+static void interpret_agesa_eventlog(EVENT_PARAMS *event)
+{
+ switch (event->EventClass) {
+ case AGESA_BOUNDS_CHK:
+ agesa_bound_check(event);
+ break;
+
+ case AGESA_ALERT:
+ agesa_alert(event);
+ break;
+
+ case AGESA_WARNING:
+ agesa_warning(event);
+ break;
+
+ case AGESA_ERROR:
+ agesa_error(event);
+ break;
+
+ case AGESA_CRITICAL:
+ agesa_critical(event);
+ break;
+
+ case AGESA_FATAL:
+ agesa_fatal(event);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @param HeapStatus -the current HeapStatus
+ */
+UINT32 agesawrapper_amdreadeventlog(UINT8 HeapStatus)
+{
+ AGESA_STATUS Status;
+ EVENT_PARAMS AmdEventParams;
+
+ LibAmdMemFill(&AmdEventParams,
+ 0,
+ sizeof(EVENT_PARAMS),
+ &(AmdEventParams.StdHeader));
+
+ AmdEventParams.StdHeader.AltImageBasePtr = 0;
+ AmdEventParams.StdHeader.CalloutPtr = NULL;
+ AmdEventParams.StdHeader.Func = 0;
+ AmdEventParams.StdHeader.ImageBasePtr = 0;
+ /* I have to know the current HeapStatus to Locate the EventLogHeapPointer */
+ AmdEventParams.StdHeader.HeapStatus = HeapStatus;
+ Status = AmdReadEventLog(&AmdEventParams);
+ while (AmdEventParams.EventClass != 0) {
+ printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
+ printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
+ printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
+ interpret_agesa_eventlog(&AmdEventParams);
+ Status = AmdReadEventLog(&AmdEventParams);
+ }
+
+ return (UINT32)Status;
+}
+
diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.h b/src/mainboard/supermicro/h8qgi/agesawrapper.h
new file mode 100755
index 0000000..43c7d10
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/agesawrapper.h
@@ -0,0 +1,87 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*----------------------------------------------------------------------------------------
+ * M O D U L E S U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#ifndef _AGESAWRAPPER_H_
+#define _AGESAWRAPPER_H_
+
+#include <stdint.h>
+#include "Porting.h"
+#include "AGESA.h"
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
+
+enum {
+ PICK_DMI, /* DMI Interface */
+ PICK_PSTATE, /* Acpi Pstate SSDT Table */
+ PICK_SRAT, /* SRAT Table */
+ PICK_SLIT, /* SLIT Table */
+ PICK_WHEA_MCE, /* WHEA MCE table */
+ PICK_WHEA_CMC, /* WHEA CMV table */
+ PICK_ALIB, /* SACPI SSDT table with ALIB implementation */
+};
+
+
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S A N D S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef struct {
+ UINT32 CalloutName;
+ AGESA_STATUS (*CalloutPtr)(UINT32 Func, UINT32 Data, VOID* ConfigPtr);
+} BIOS_CALLOUT_STRUCT;
+
+/*----------------------------------------------------------------------------------------
+ * P R O T O T Y P E S O F L O C A L F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * E X P O R T E D F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------
+ * L O C A L F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+UINT32 agesawrapper_amdinitreset (void);
+UINT32 agesawrapper_amdinitearly (void);
+UINT32 agesawrapper_amdinitenv (void);
+UINT32 agesawrapper_amdinitlate (void);
+UINT32 agesawrapper_amdinitpost (void);
+UINT32 agesawrapper_amdinitmid (void);
+UINT32 agesawrapper_amdreadeventlog (UINT8 HeapStatus);
+UINT32 agesawrapper_amdinitmmio (void);
+void *agesawrapper_getlateinitptr (int pick);
+UINT32 agesawrapper_amdlaterunaptask(UINT32 Data, VOID *ConfigPtr);
+
+#endif
diff --git a/src/mainboard/supermicro/h8qgi/buildOpts.c b/src/mainboard/supermicro/h8qgi/buildOpts.c
new file mode 100755
index 0000000..02cf79b
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/buildOpts.c
@@ -0,0 +1,541 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "AGESA.h"
+#include "CommonReturns.h"
+#include "AdvancedApi.h"
+#include <PlatformMemoryConfiguration.h>
+#include "Filecode.h"
+#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
+
+/* AGESA will check the OEM configuration during preprocessing stage,
+ * coreboot enable -Wundef option, so we should make sure we have all contanstand defined
+ */
+/* MEMORY_BUS_SPEED */
+#define DDR400_FREQUENCY 200 ///< DDR 400
+#define DDR533_FREQUENCY 266 ///< DDR 533
+#define DDR667_FREQUENCY 333 ///< DDR 667
+#define DDR800_FREQUENCY 400 ///< DDR 800
+#define DDR1066_FREQUENCY 533 ///< DDR 1066
+#define DDR1333_FREQUENCY 667 ///< DDR 1333
+#define DDR1600_FREQUENCY 800 ///< DDR 1600
+#define DDR1866_FREQUENCY 933 ///< DDR 1866
+#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
+
+/* QUANDRANK_TYPE*/
+#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
+#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
+
+/* USER_MEMORY_TIMING_MODE */
+#define TIMING_MODE_AUTO 0 ///< Use best rate possible
+#define TIMING_MODE_LIMITED 1 ///< Set user top limit
+#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
+
+/* POWER_DOWN_MODE */
+#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
+#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
+
+/* User makes option selections here
+ * Comment out the items wanted to be included in the build.
+ * Uncomment those items you with to REMOVE from the build.
+ */
+//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
+//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
+//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
+//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
+//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
+//#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
+//#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
+//#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
+#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE
+//#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
+////#define BLDOPT_REMOVE_ACPI_PSTATES TRUE
+////#define BLDOPT_REMOVE_SRAT TRUE
+////#define BLDOPT_REMOVE_SLIT TRUE
+//#define BLDOPT_REMOVE_WHEA TRUE
+//#define BLDOPT_REMOVE_DMI TRUE
+//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
+//#define BLDOPT_REMOVE_HT_ASSIST TRUE
+//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
+
+/* Build configuration values here.
+ */
+#define BLDCFG_VRM_CURRENT_LIMIT 120000
+#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0
+#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 0
+#define BLDCFG_PLAT_NUM_IO_APICS 3
+#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
+#define BLDCFG_MEM_INIT_PSTATE 0
+#define BLDCFG_AMD_PSTATE_CAP_VALUE 0
+
+#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_SERVER
+
+#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY//1600
+#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
+#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
+#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
+#define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE
+#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE
+#define BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB TRUE
+#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING FALSE//TRUE
+#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE//TRUE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE//TRUE
+#define BLDCFG_MEMORY_POWER_DOWN FALSE
+#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHANNEL
+#define BLDCFG_ONLINE_SPARE FALSE
+#define BLDCFG_BANK_SWIZZLE TRUE
+#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
+#define BLDCFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY
+#define BLDCFG_DQS_TRAINING_CONTROL TRUE
+#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
+#define BLDCFG_USE_BURST_MODE FALSE
+#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
+#define BLDCFG_ENABLE_ECC_FEATURE TRUE
+#define BLDCFG_ECC_REDIRECTION FALSE
+#define BLDCFG_SCRUB_IC_RATE 0
+#define BLDCFG_ECC_SYNC_FLOOD TRUE
+#define BLDCFG_ECC_SYMBOL_SIZE 4
+
+#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
+#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
+
+/**
+ * Enable Message Based C1e CPU feature in multi-socket systems.
+ * BLDCFG_PLATFORM_C1E_OPDATA element be defined with a valid IO port value,
+ * else the feature cannot be enabled.
+ */
+#define BLDCFG_PLATFORM_C1E_MODE C1eModeMsgBased
+#define BLDCFG_PLATFORM_C1E_OPDATA 0x80//TODO
+//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0
+//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0
+
+#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
+#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000
+#define BLDCFG_1GB_ALIGN FALSE
+//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C'
+//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
+//
+
+// Select the platform control flow mode for performance tuning.
+#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm
+
+/**
+ * Enable the probe filtering performance tuning feature.
+ * The probe filter provides filtering of broadcast probes to
+ * improve link bandwidth and performance for multi- node systems.
+ *
+ * This feature may interact with other performance features.
+ * TRUE -Enable the feature (default) if supported by all processors,
+ * based on revision and presence of L3 cache.
+ * The feature is not enabled if there are no coherent HT links.
+ * FALSE -Do not enable the feature regardless of the configuration.
+ */
+//TODO enable it,
+//but AGESA set PFMode = 0; //PF Disable, HW never set PFInitDone
+//hang in F10HtAssistInit() do{...} while(PFInitDone != 1)
+#define BLDCFG_USE_HT_ASSIST FALSE
+
+/**
+ * The socket and link match values are platform specific
+ */
+CONST MANUAL_BUID_SWAP_LIST ROMDATA h8qgi_manual_swaplist[2] =
+{
+ {
+ /* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */
+ HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
+
+ { //BUID Swap List
+ { //BUID Swaps
+ /* Each Non-coherent chain may have a list of device swaps,
+ * Each item specify a device will be swap from its current id to a new one
+ */
+ /* FromID 0x00 is the chain with the southbridge */
+ /* 'Move' device zero to device zero, All others are non applicable */
+ {0x00, 0x00}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
+ {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
+ {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
+ {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
+ {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
+ {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
+ {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
+ {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
+ },
+
+ { //The ordered final BUIDs
+ /* Specify the final BUID to be zero, All others are non applicable */
+ 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ }
+ }
+ },
+
+ /* The 2nd element in the array merely terminates the list */
+ {
+ HT_LIST_TERMINAL,
+ }
+};
+
+#if CONFIG_HT3_SUPPORT == 1
+/**
+ * The socket and link match values are platform specific
+ *
+ */
+CONST CPU_TO_CPU_PCB_LIMITS ROMDATA h8qgi_cpu2cpu_limit_list[2] =
+{
+ {
+ /* On the reference platform, these settings apply to all coherent links */
+ HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
+
+ /* Set incoming and outgoing links to 16 bit widths, and 3.2GHz frequencies */
+ HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_3200M,
+ },
+
+ /* The 2nd element in the array merely terminates the list */
+ {
+ HT_LIST_TERMINAL,
+ }
+};
+
+CONST IO_PCB_LIMITS ROMDATA h8qgi_io_limit_list[2] =
+{
+ {
+ /* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */
+ HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
+
+ /* Set upstream and downstream links to 16 bit widths, and limit frequencies to 3.2GHz */
+ HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_3200M, //Actually IO hub only support 2600M MAX
+ },
+
+ /* The 2nd element in the array merely terminates the list */
+ {
+ HT_LIST_TERMINAL,
+ }
+};
+#else //CONFIG_HT3_SUPPORT == 0
+CONST CPU_TO_CPU_PCB_LIMITS ROMDATA h8qgi_cpu2cpu_limit_list[2] =
+{
+ {
+ /* On the reference platform, these settings apply to all coherent links */
+ HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
+
+ /* Set incoming and outgoing links to 16 bit widths, and 1GHz frequencies */
+ HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_HT1_ONLY,
+ },
+
+ /* The 2nd element in the array merely terminates the list */
+ {
+ HT_LIST_TERMINAL,
+ }
+};
+
+CONST IO_PCB_LIMITS ROMDATA h8qgi_io_limit_list[2] =
+{
+ {
+ /* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */
+ HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
+
+ /* Set incoming and outgoing links to 16 bit widths, and 1GHz frequencies */
+ HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_HT1_ONLY,
+ },
+
+ /* The 2nd element in the array merely terminates the list */
+ {
+ HT_LIST_TERMINAL
+ }
+};
+#endif //CONFIG_HT3_SUPPORT == 0
+
+/**
+ * HyperTransport links will typically require an equalization at high frequencies.
+ * This is called deemphasis.
+ *
+ * Deemphasis is specified as levels, for example, -3 db.
+ * There are two levels for each link, its receiver deemphasis level and its DCV level,
+ * which is based on the far side transmitter's deemphasis.
+ * For each link, different levels may be required at each link frequency.
+ *
+ * Coherent connections between processors should have an entry for the port on each processor.
+ * There should be one entry for the host root port of each non-coherent chain.
+ *
+ * AGESA initialization code does not set deemphasis on IO Devices.
+ * A default is provided for internal links of MCM processors, and
+ * those links will generally not need deemphasis structures.
+ */
+CONST CPU_HT_DEEMPHASIS_LEVEL ROMDATA h8qgi_deemphasis_list[] =
+{
+ /* Socket, Link, LowFreq, HighFreq, Receiver Deemphasis, Dcv Deemphasis */
+
+ /* Non-coherent link deemphasis. */
+ {0, 2, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
+ {0, 2, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5},
+ {0, 2, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5},
+ {0, 2, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7},
+ {0, 2, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7},
+ {0, 2, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9},
+
+ /* Coherent link deemphasis. */
+ {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
+ {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus3},
+ {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus6},
+ {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus6},
+ {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus8},
+ {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2600M, HT_FREQUENCY_MAX, DeemphasisLevelMinus11pre8, DcvLevelMinus11},
+
+ /* End of the list */
+ {
+ HT_LIST_TERMINAL
+ }
+};
+
+/**
+ * For systems using socket infrastructure that permits strapping the SBI
+ * address for each socket, this should be used to provide a socket ID value.
+ * This is referred to as the hardware method for socket naming, and is the
+ * preferred solution.
+ */
+/*
+ * I do NOT know howto config socket id in simnow,
+ * so use this software way to make HT works in simnow,
+ * real hardware do not need this Socket Map.
+ *
+ * A physical socket map for a 4 G34 Sockets MCM processors topology,
+ * reference the mainboard schemantic in detail.
+ *
+ */
+CONST SYSTEM_PHYSICAL_SOCKET_MAP ROMDATA h8qgi_socket_map[] =
+{
+#define HT_SOCKET0 0
+#define HT_SOCKET1 1
+#define HT_SOCKET2 2
+#define HT_SOCKET3 3
+
+/**
+ * 0-3 are sublink 0, 4-7 are sublink 1
+ */
+#define HT_LINK0A 0
+#define HT_LINK1A 1
+#define HT_LINK2A 2
+#define HT_LINK3A 3
+#define HT_LINK0B 4
+#define HT_LINK1B 5
+#define HT_LINK2B 6
+#define HT_LINK3B 7
+
+ /* Source Socket, Link, Target Socket */
+ {HT_SOCKET0, HT_LINK0A, HT_SOCKET1},
+ {HT_SOCKET0, HT_LINK0B, HT_SOCKET3},
+ {HT_SOCKET0, HT_LINK1A, HT_SOCKET1},
+ {HT_SOCKET0, HT_LINK1B, HT_SOCKET3},
+ {HT_SOCKET0, HT_LINK3A, HT_SOCKET2},
+ {HT_SOCKET0, HT_LINK3B, HT_SOCKET2},
+
+ {HT_SOCKET1, HT_LINK0A, HT_SOCKET2},
+ {HT_SOCKET1, HT_LINK0B, HT_SOCKET3},
+ {HT_SOCKET1, HT_LINK1A, HT_SOCKET0},
+ {HT_SOCKET1, HT_LINK1B, HT_SOCKET2},
+ {HT_SOCKET1, HT_LINK3A, HT_SOCKET0},
+ {HT_SOCKET1, HT_LINK3B, HT_SOCKET3},
+
+ {HT_SOCKET2, HT_LINK0A, HT_SOCKET3},
+ {HT_SOCKET2, HT_LINK0B, HT_SOCKET0},
+ {HT_SOCKET2, HT_LINK1A, HT_SOCKET3},
+ {HT_SOCKET2, HT_LINK1B, HT_SOCKET1},
+ {HT_SOCKET2, HT_LINK3A, HT_SOCKET1},
+ {HT_SOCKET2, HT_LINK3B, HT_SOCKET0},
+
+ {HT_SOCKET3, HT_LINK0A, HT_SOCKET2},
+ {HT_SOCKET3, HT_LINK0B, HT_SOCKET1},
+ {HT_SOCKET3, HT_LINK1A, HT_SOCKET1},
+ {HT_SOCKET3, HT_LINK1B, HT_SOCKET0},
+ {HT_SOCKET3, HT_LINK3A, HT_SOCKET0},
+ {HT_SOCKET3, HT_LINK3B, HT_SOCKET2},
+
+};
+
+CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] =
+{
+ {AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull},
+ {AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull},
+ {AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull},
+ {AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000ull},
+ {AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000ull},
+ {AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000ull},
+ {AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000ull},
+ {AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818ull},
+ {AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818ull},
+ {AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818ull},
+ {AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818ull},
+ {CPU_LIST_TERMINAL}
+};
+
+#define BLDCFG_BUID_SWAP_LIST &h8qgi_manual_swaplist
+#define BLDCFG_HTFABRIC_LIMITS_LIST &h8qgi_cpu2cpu_limit_list
+#define BLDCFG_HTCHAIN_LIMITS_LIST &h8qgi_io_limit_list
+#define BLDCFG_PLATFORM_DEEMPHASIS_LIST &h8qgi_deemphasis_list
+#define BLDCFG_AP_MTRR_SETTINGS_LIST &h8qgi_ap_mtrr_list
+//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP &h8qgi_socket_map
+
+
+/* Process the options...
+ * This file include MUST occur AFTER the user option selection settings
+ */
+#define AGESA_ENTRY_INIT_RESET FALSE//TRUE
+#define AGESA_ENTRY_INIT_RECOVERY FALSE
+#define AGESA_ENTRY_INIT_EARLY TRUE
+#define AGESA_ENTRY_INIT_POST TRUE
+#define AGESA_ENTRY_INIT_ENV TRUE
+#define AGESA_ENTRY_INIT_MID TRUE
+#define AGESA_ENTRY_INIT_LATE TRUE
+#define AGESA_ENTRY_INIT_S3SAVE TRUE
+#define AGESA_ENTRY_INIT_RESUME TRUE
+#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
+#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
+
+#include "GnbInterface.h" /*prototype for GnbInterfaceStub*/
+#include "MaranelloInstall.h"
+
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+ //
+ // The following macros are supported (use comma to separate macros):
+ //
+ // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
+ // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
+ // AGESA will base on this value to disable unused MemClk to save power.
+ // Example:
+ // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
+ // Bit AM3/S1g3 pin name
+ // 0 M[B,A]_CLK_H/L[0]
+ // 1 M[B,A]_CLK_H/L[1]
+ // 2 M[B,A]_CLK_H/L[2]
+ // 3 M[B,A]_CLK_H/L[3]
+ // 4 M[B,A]_CLK_H/L[4]
+ // 5 M[B,A]_CLK_H/L[5]
+ // 6 M[B,A]_CLK_H/L[6]
+ // 7 M[B,A]_CLK_H/L[7]
+ // And platform has the following routing:
+ // CS0 M[B,A]_CLK_H/L[4]
+ // CS1 M[B,A]_CLK_H/L[2]
+ // CS2 M[B,A]_CLK_H/L[3]
+ // CS3 M[B,A]_CLK_H/L[5]
+ // Then platform can specify the following macro:
+ // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
+ //
+ // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
+ // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
+ // AGESA will base on this value to tristate unused CKE to save power.
+ //
+ // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
+ // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
+ // AGESA will base on this value to tristate unused ODT pins to save power.
+ //
+ // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
+ // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
+ // AGESA will base on this value to tristate unused Chip select to save power.
+ //
+ // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
+ // Specifies the number of DIMM slots per channel.
+ //
+ // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
+ // Specifies the number of Chip selects per channel.
+ //
+ // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
+ // Specifies the number of channels per socket.
+ //
+ // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
+ // Specifies DDR bus speed of channel ChannelID on socket SocketID.
+ //
+ // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
+ // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
+ //
+ // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
+ // Byte6Seed, Byte7Seed, ByteEccSeed)
+ // Specifies the write leveling seed for a channel of a socket.
+ //
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), //max 3
+ PSO_END
+};
+
+/*
+ * These tables are optional and may be used to adjust memory timing settings
+ */
+
+//HY Customer table
+UINT8 AGESA_MEM_TABLE_HY[][sizeof (MEM_TABLE_ALIAS)] =
+{
+ // Hardcoded Memory Training Values
+
+ // The following macro should be used to override training values for your platform
+ //
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20),
+ //
+ // NOTE:
+ // The following training hardcode values are example values that were taken from a tilapia motherboard
+ // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in
+ // the table and replace the byte lane values with your own.
+ //
+ // ------------------ BYTE LANES ----------------------
+ // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC
+ // Write Data Timing
+ // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0
+ // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1
+ // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0
+ // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1
+
+ // DQS Receiver Enable
+ // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
+ // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1
+ // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0
+ // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1
+
+ // Write DQS Delays
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1
+
+ // Read DQS Delays
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1
+ //--------------------------------------------------------------------------------------------------------------------------------------------------
+ // TABLE END
+ NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table
+};
+UINT8 SizeOfTableHy = sizeof (AGESA_MEM_TABLE_HY) / sizeof (AGESA_MEM_TABLE_HY[0]);
+
diff --git a/src/mainboard/supermicro/h8qgi/chip.h b/src/mainboard/supermicro/h8qgi/chip.h
new file mode 100755
index 0000000..a252705
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/chip.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config {};
diff --git a/src/mainboard/supermicro/h8qgi/cmos.layout b/src/mainboard/supermicro/h8qgi/cmos.layout
new file mode 100755
index 0000000..3b98cbb
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/cmos.layout
@@ -0,0 +1,118 @@
+#*****************************************************************************
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#*****************************************************************************
+
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+#96 288 r 0 temporary_filler
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+386 1 e 1 ECC_memory
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+395 1 e 1 hw_scrubber
+396 1 e 1 interleave_chip_selects
+397 2 e 8 max_mem_clock
+399 1 e 2 multi_core
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+416 4 e 7 boot_first
+420 4 e 7 boot_second
+424 4 e 7 boot_third
+428 4 h 0 boot_index
+432 8 h 0 boot_countdown
+440 4 e 9 slow_cpu
+444 1 e 1 nmi
+445 1 e 1 iommu
+728 256 h 0 user_data
+984 16 h 0 check_sum
+# Reserve the extended AMD configuration registers
+1000 24 r 0 amd_reserved
+
+
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Network
+7 1 HDD
+7 2 Floppy
+7 8 Fallback_Network
+7 9 Fallback_HDD
+7 10 Fallback_Floppy
+#7 3 ROM
+8 0 400Mhz
+8 1 333Mhz
+8 2 266Mhz
+8 3 200Mhz
+9 0 off
+9 1 87.5%
+9 2 75.0%
+9 3 62.5%
+9 4 50.0%
+9 5 37.5%
+9 6 25.0%
+9 7 12.5%
+
+checksums
+
+checksum 392 983 984
+
+
diff --git a/src/mainboard/supermicro/h8qgi/devicetree.cb b/src/mainboard/supermicro/h8qgi/devicetree.cb
new file mode 100755
index 0000000..9afaac7
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/devicetree.cb
@@ -0,0 +1,176 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+chip northbridge/amd/agesa/family10/root_complex
+ device lapic_cluster 0 on
+ chip cpu/amd/agesa/family10
+ device lapic 0x10 on end
+ end
+ end
+ device pci_domain 0 on
+ subsystemid 0x15d9 0xab11 inherit #SuperMicro
+ chip northbridge/amd/agesa/family10 # CPU side of HT root complex
+ device pci 18.0 on end # link 0
+ device pci 18.0 on end # link 1
+ device pci 18.0 on end # link 2
+ device pci 18.0 on # link3 SB on socket0 link 2, on internal Node0 Link 3
+ chip southbridge/amd/sr5650 # Southbridge PCI side of HT Root complex
+ device pci 0.0 on end # HT Root Complex 0x9600
+ device pci 0.1 off end # CLKCONFIG
+ device pci 2.0 on end # GPP1 Port0 x16 SLOT4, 0x5A16
+ device pci 3.0 off end # GPP1 Port1
+ device pci 4.0 off end # GPP3a Port0 x4 SAS
+ device pci 5.0 off end # GPP3a Port1
+ device pci 6.0 off end # GPP3a Port2
+ device pci 7.0 off end # GPP3a Port3
+ device pci 8.0 off end # NB/SB Link P2P bridge, should be hidden at boot time
+ device pci 9.0 off end # GPP3a Port4 x1 NC
+ device pci a.0 off end # GPP3a Port5 x1 NC
+ device pci b.0 off end # GPP2 Port0 (Not for sr5650)
+ device pci c.0 off end # GPP2 Port1 (Not for sr5650/sr5670)
+ device pci d.0 on end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576
+ register "gpp1_configuration" = "0" # Configuration 16:0 default
+ register "gpp2_configuration" = "1" # Configuration 8:8
+ register "gpp3a_configuration" = "2" # Configuration 4:1:1:0:0:0
+ #register "gpp3a_configuration" = "11" # Configuration 1:1:1:1:1:1
+ register "port_enable" = "0x2104"
+ end #southbridge/amd/sr5650
+ chip southbridge/amd/sp5100 # it is under NB/SB Link, but on the same pci bus
+ device pci 11.0 on end # SATA
+ device pci 12.0 on end # USB1
+ device pci 12.1 on end # USB1
+ device pci 12.2 on end # USB1
+ device pci 13.0 on end # USB2
+ device pci 13.1 on end # USB2
+ device pci 13.2 on end # USB2
+ device pci 14.0 on end # SM
+ device pci 14.1 on end # IDE 0x439c
+ device pci 14.2 off end # HDA 0x4383, h8qgi doesnt have codec.
+ device pci 14.3 on # LPC 0x439d
+ chip superio/winbond/w83627dhg
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ ## though UARTs are on the NUVOTON BMC, superio only used to support PS2 KB/MS##
+ device pnp 2e.5 on # PS/2 keyboard & mouse
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 0x01 #keyboard
+ irq 0x72 = 0x0C #mouse
+ end
+ #device pnp 2e.6 off # SPI
+ #end
+ device pnp 2e.307 off # GPIO6
+ end
+ device pnp 2e.8 off # WDTO#, PLED
+ end
+ device pnp 2e.009 off # GPIO2
+ end
+ device pnp 2e.109 off # GPIO3
+ end
+ device pnp 2e.209 off # GPIO4
+ end
+ device pnp 2e.309 off # GPIO5
+ end
+ device pnp 2e.a off # ACPI
+ end
+ device pnp 2e.b off # HWM
+ io 0x60 = 0x290
+ end
+ device pnp 2e.c off # PECI, SST
+ end
+ end #superio/winbond/w83627dhg
+ end # LPC
+ device pci 14.4 on end # PCI 0x4384
+ device pci 14.5 on end # USB 3
+ register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
+ end # southbridge/amd/sp5100
+ end # device pci 18.0
+
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ device pci 18.4 on end
+
+ device pci 19.0 on end
+ device pci 19.1 on end
+ device pci 19.2 on end
+ device pci 19.3 on end
+ device pci 19.4 on end
+
+
+ device pci 1a.0 on end
+ device pci 1a.0 on end
+ device pci 1a.0 on end
+ device pci 1a.0 on # another 56x0 on socket 1 Link 2, internal Node0 link 3
+ end
+ device pci 1a.1 on end
+ device pci 1a.2 on end
+ device pci 1a.3 on end
+ device pci 1a.4 on end
+
+ device pci 1b.0 on end
+ device pci 1b.1 on end
+ device pci 1b.2 on end
+ device pci 1b.3 on end
+ device pci 1b.4 on end
+
+
+ device pci 1c.0 on end
+ device pci 1c.1 on end
+ device pci 1c.2 on end
+ device pci 1c.3 on end
+ device pci 1c.4 on end
+
+ device pci 1d.0 on end
+ device pci 1d.1 on end
+ device pci 1d.2 on end
+ device pci 1d.3 on end
+ device pci 1d.4 on end
+
+
+ device pci 1e.0 on end
+ device pci 1e.1 on end
+ device pci 1e.2 on end
+ device pci 1e.3 on end
+ device pci 1e.4 on end
+
+ device pci 1f.0 on end
+ device pci 1f.1 on end
+ device pci 1f.2 on end
+ device pci 1f.3 on end
+ device pci 1f.4 on end
+
+ end #chip northbridge/amd/agesa/family10 # CPU side of HT root complex
+ end #pci_domain
+end #northbridge/amd/agesa/family10/root_complex
+
diff --git a/src/mainboard/supermicro/h8qgi/dimmSpd.c b/src/mainboard/supermicro/h8qgi/dimmSpd.c
new file mode 100755
index 0000000..4ff21ee
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/dimmSpd.c
@@ -0,0 +1,229 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "Porting.h"
+#include "AGESA.h"
+#include "amdlib.h"
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_ids.h>
+
+AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info);
+#define DIMENSION(array)(sizeof (array)/ sizeof (array [0]))
+
+/* SP5100 GPIO 53-56 contoled by SMBUS PCI_Reg 0x52 */
+#define SP5100_GPIO53_56 0x52
+
+/**
+ * TODO not support all GPIO yet
+ * @param reg -GPIO Cntrl Register
+ * @param out -GPIO bitmap
+ * @param out -GPIO enable bitmap
+ */
+static void sp5100_set_gpio(u8 reg, u8 out, u8 enable)
+{
+ u8 value;
+ device_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBUS
+
+ value = pci_read_config8(sm_dev, reg);
+ value &= ~(enable);
+ value |= out;
+ value &= ~(enable << 4);
+ pci_write_config8(sm_dev, reg, value);
+}
+
+/*-----------------------------------------------------------------------------
+ *
+ * SPD address table - porting required
+ */
+static const UINT8 spdAddressLookup [8] [4] [2] = { // socket, channel, dimm
+ /* socket 0 */
+ {
+ {0xAE, 0xAC},
+ {0xAA, 0xA8},
+ {0xA6, 0xA4},
+ {0xA2, 0xA0},
+ },
+ /* socket 1 */
+ {
+ {0xAE, 0xAC},
+ {0xAA, 0xA8},
+ {0xA6, 0xA4},
+ {0xA2, 0xA0},
+ },
+ /* socket 2 */
+ {
+ {0xAE, 0xAC},
+ {0xAA, 0xA8},
+ {0xA6, 0xA4},
+ {0xA2, 0xA0},
+ },
+ /* socket 3 */
+ {
+ {0xAE, 0xAC},
+ {0xAA, 0xA8},
+ {0xA6, 0xA4},
+ {0xA2, 0xA0},
+ },
+};
+
+/*-----------------------------------------------------------------------------
+ *
+ * readSmbusByteData - read a single SPD byte from any offset
+ */
+
+static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
+{
+ unsigned int status;
+ UINT64 limit;
+
+ address |= 1; // set read bit
+
+ outb(0xFF, iobase + 0); // clear error status
+ outb(0x1F, iobase + 1); // clear error status
+ outb(offset, iobase + 3); // offset in eeprom
+ outb(address, iobase + 4); // slave address and read bit
+ outb(0x48, iobase + 2); // read byte command
+
+ // time limit to avoid hanging for unexpected error status (should never happen)
+ limit = __rdtsc () + 2000000000 / 10;
+ for (;;)
+ {
+ status = inb(iobase);
+ if (__rdtsc () > limit) break;
+ if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting
+ if ((status & 1) == 1) continue; // HostBusy set, keep waiting
+ break;
+ }
+
+ buffer [0] = inb(iobase + 5);
+ if (status == 2) status = 0; // check for done with no errors
+ return status;
+}
+
+/*-----------------------------------------------------------------------------
+ *
+ * readSmbusByte - read a single SPD byte from the default offset
+ * this function is faster function readSmbusByteData
+ */
+
+static int readSmbusByte (int iobase, int address, char *buffer)
+{
+ unsigned int status;
+ UINT64 limit;
+
+ outb(0xFF, iobase + 0); // clear error status
+ outb(0x44, iobase + 2); // read command
+
+ // time limit to avoid hanging for unexpected error status
+ limit = __rdtsc () + 2000000000 / 10;
+ for (;;)
+ {
+ status = inb(iobase);
+ if (__rdtsc () > limit) break;
+ if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting
+ if ((status & 1) == 1) continue; // HostBusy set, keep waiting
+ break;
+ }
+
+ buffer [0] = inb(iobase + 5);
+ if (status == 2) status = 0; // check for done with no errors
+ return status;
+}
+
+/*---------------------------------------------------------------------------
+ *
+ * readspd - Read one or more SPD bytes from a DIMM.
+ * Start with offset zero and read sequentially.
+ * Optimization relies on autoincrement to avoid
+ * sending offset for every byte.
+ * Reads 128 bytes in 7-8 ms at 400 KHz.
+ */
+
+static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count)
+{
+ int index, error;
+
+ /* read the first byte using offset zero */
+ error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0);
+ if (error) {
+ return error;
+ }
+
+ /* read the remaining bytes using auto-increment for speed */
+ for (index = 1; index < count; index++)
+ {
+ error = readSmbusByte (iobase, SmbusSlaveAddress, buffer + index);
+ if (error)
+ return error;
+ }
+
+ return 0;
+}
+
+static void writePmReg (int reg, int data)
+{
+ outb(reg, 0xCD6);
+ outb(data, 0xCD7);
+}
+
+static void setupFch (int ioBase)
+{
+ writePmReg (0x2D, ioBase >> 8);
+ writePmReg (0x2C, ioBase | 1);
+ writePmReg (0x29, 0x80);
+ writePmReg (0x28, 0x61);
+ outb(66000000 / 400000 / 4, ioBase + 0x0E); // set SMBus clock to 400 KHz
+}
+
+AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info)
+{
+ int spdAddress, ioBase;
+ u8 i2c_channel;
+ device_t sm_dev;
+
+ if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR;
+ if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR;
+ if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR;
+ i2c_channel = (UINT8) info->SocketId;
+
+ /* set ght i2c channel
+ * GPIO54,53 control the HC4052 S1,S0
+ * S1 S0 true table
+ * 0 0 channel 1 (Socket1)
+ * 0 1 channel 2 (Socket2)
+ * 1 0 channel 3 (Socket3)
+ * 1 1 channel 4 (Socket4)
+ */
+ sp5100_set_gpio(SP5100_GPIO53_56, i2c_channel, 0x03);
+
+ spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId];
+ if (spdAddress == 0)
+ return AGESA_ERROR;
+
+ /*
+ * SMBus Base Address was set during southbridge early setup.
+ * e.g. sb700 IO mapped SMBUS_IO_BASE 0x6000
+ */
+ sm_dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB700_SM), 0);
+ ioBase = pci_read_config32(sm_dev, 0x90) & (0xFFFFFFF0);
+ setupFch(ioBase);
+
+ return readspd(ioBase, spdAddress, (void *)info->Buffer, 256);
+}
diff --git a/src/mainboard/supermicro/h8qgi/dsdt.asl b/src/mainboard/supermicro/h8qgi/dsdt.asl
new file mode 100755
index 0000000..f509fc6
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/dsdt.asl
@@ -0,0 +1,1849 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* DefinitionBlock Statement */
+DefinitionBlock (
+ "DSDT.AML", /* Output filename */
+ "DSDT", /* Signature */
+ 0x02, /* DSDT Revision, needs to be 2 for 64bit */
+ "AMD ", /* OEMID */
+ "H8QGI ", /* TABLE ID */
+ 0x00010001 /* OEM Revision */
+ )
+{ /* Start of ASL file */
+ /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */
+
+ /* Data to be patched by the BIOS during POST */
+ /* FIXME the patching is not done yet! */
+ /* Memory related values */
+ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
+ Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+ Name(PBLN, 0x0) /* Length of BIOS area */
+
+ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
+ Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
+
+ Name(HPBA, 0xFED00000) /* Base address of HPET table */
+ Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
+
+ /* USB overcurrent mapping pins. */
+ Name(UOM0, 0)
+ Name(UOM1, 2)
+ Name(UOM2, 0)
+ Name(UOM3, 7)
+ Name(UOM4, 2)
+ Name(UOM5, 2)
+ Name(UOM6, 6)
+ Name(UOM7, 2)
+ Name(UOM8, 6)
+ Name(UOM9, 6)
+
+ /* Some global data */
+ Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+ Name(OSV, Ones) /* Assume nothing */
+ Name(PMOD, One) /* Assume APIC */
+
+ /*
+ * Processor Object
+ *
+ */
+ Scope (\_PR) { /* define processor scope */
+ Processor(
+ P000, /* name space name */
+ 0x00, /* Unique number for this processor */
+ 0x810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ //#include "acpi/cpstate.asl"
+ }
+ Processor(P001, 0x01, 0x00000000, 0x00) {}
+ Processor(P002, 0x02, 0x00000000, 0x00) {}
+ Processor(P003, 0x03, 0x00000000, 0x00) {}
+ Processor(P004, 0x04, 0x00000000, 0x00) {}
+ Processor(P005, 0x05, 0x00000000, 0x00) {}
+ Processor(P006, 0x06, 0x00000000, 0x00) {}
+ Processor(P007, 0x07, 0x00000000, 0x00) {}
+ Processor(P008, 0x08, 0x00000000, 0x00) {}
+ Processor(P009, 0x09, 0x00000000, 0x00) {}
+ Processor(P00A, 0x0A, 0x00000000, 0x00) {}
+ Processor(P00B, 0x0B, 0x00000000, 0x00) {}
+ Processor(P00C, 0x0C, 0x00000000, 0x00) {}
+ Processor(P00D, 0x0D, 0x00000000, 0x00) {}
+ Processor(P00E, 0x0E, 0x00000000, 0x00) {}
+ Processor(P00F, 0x0F, 0x00000000, 0x00) {}
+ Processor(P010, 0x10, 0x00000000, 0x00) {}
+ Processor(P011, 0x11, 0x00000000, 0x00) {}
+ Processor(P012, 0x12, 0x00000000, 0x00) {}
+ Processor(P013, 0x13, 0x00000000, 0x00) {}
+ Processor(P014, 0x14, 0x00000000, 0x00) {}
+ Processor(P015, 0x15, 0x00000000, 0x00) {}
+ Processor(P016, 0x16, 0x00000000, 0x00) {}
+ Processor(P017, 0x17, 0x00000000, 0x00) {}
+ Processor(P018, 0x18, 0x00000000, 0x00) {}
+ Processor(P019, 0x19, 0x00000000, 0x00) {}
+ Processor(P01A, 0x1A, 0x00000000, 0x00) {}
+ Processor(P01B, 0x1B, 0x00000000, 0x00) {}
+ Processor(P01C, 0x1C, 0x00000000, 0x00) {}
+ Processor(P01D, 0x1D, 0x00000000, 0x00) {}
+ Processor(P01E, 0x1E, 0x00000000, 0x00) {}
+ Processor(P01F, 0x1F, 0x00000000, 0x00) {}
+ Processor(P020, 0x20, 0x00000000, 0x00) {}
+ Processor(P021, 0x21, 0x00000000, 0x00) {}
+ Processor(P022, 0x22, 0x00000000, 0x00) {}
+ Processor(P023, 0x23, 0x00000000, 0x00) {}
+ Processor(P024, 0x24, 0x00000000, 0x00) {}
+ Processor(P025, 0x25, 0x00000000, 0x00) {}
+ Processor(P026, 0x26, 0x00000000, 0x00) {}
+ Processor(P027, 0x27, 0x00000000, 0x00) {}
+ Processor(P028, 0x28, 0x00000000, 0x00) {}
+ Processor(P029, 0x29, 0x00000000, 0x00) {}
+ Processor(P02A, 0x2A, 0x00000000, 0x00) {}
+ Processor(P02B, 0x2B, 0x00000000, 0x00) {}
+ Processor(P02C, 0x2C, 0x00000000, 0x00) {}
+ Processor(P02D, 0x2D, 0x00000000, 0x00) {}
+ Processor(P02E, 0x2E, 0x00000000, 0x00) {}
+ Processor(P02F, 0x2F, 0x00000000, 0x00) {}
+ Alias (P000, CPU0)
+ Alias (P001, CPU1)
+ Alias (P002, CPU2)
+ Alias (P003, CPU3)
+ Alias (P004, CPU4)
+ Alias (P005, CPU5)
+ Alias (P006, CPU6)
+ Alias (P007, CPU7)
+ Alias (P008, CPU8)
+ } /* End _PR scope */
+
+ /* PIC IRQ mapping registers, C00h-C01h */
+ OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
+ Field(PRQM, ByteAcc, NoLock, Preserve) {
+ PRQI, 0x00000008,
+ PRQD, 0x00000008, /* Offset: 1h */
+ }
+ IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
+ PINA, 0x00000008, /* Index 0 */
+ PINB, 0x00000008, /* Index 1 */
+ PINC, 0x00000008, /* Index 2 */
+ PIND, 0x00000008, /* Index 3 */
+ AINT, 0x00000008, /* Index 4 */
+ SINT, 0x00000008, /* Index 5 */
+ , 0x00000008, /* Index 6 */
+ AAUD, 0x00000008, /* Index 7 */
+ AMOD, 0x00000008, /* Index 8 */
+ PINE, 0x00000008, /* Index 9 */
+ PINF, 0x00000008, /* Index A */
+ PING, 0x00000008, /* Index B */
+ PINH, 0x00000008, /* Index C */
+ }
+
+ /* PCI Error control register */
+ OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
+ Field(PERC, ByteAcc, NoLock, Preserve) {
+ SENS, 0x00000001,
+ PENS, 0x00000001,
+ SENE, 0x00000001,
+ PENE, 0x00000001,
+ }
+
+ /* Client Management index/data registers */
+ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
+ Field(CMT, ByteAcc, NoLock, Preserve) {
+ CMTI, 8,
+ /* Client Management Data register */
+ G64E, 1,
+ G64O, 1,
+ G32O, 2,
+ , 2,
+ GPSL, 2,
+ }
+
+ /* GPM Port register */
+ OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
+ Field(GPT, ByteAcc, NoLock, Preserve) {
+ GPB0,1,
+ GPB1,1,
+ GPB2,1,
+ GPB3,1,
+ GPB4,1,
+ GPB5,1,
+ GPB6,1,
+ GPB7,1,
+ }
+
+ /* Flash ROM program enable register */
+ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
+ Field(FRE, ByteAcc, NoLock, Preserve) {
+ , 0x00000006,
+ FLRE, 0x00000001,
+ }
+
+ /* PM2 index/data registers */
+ OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
+ Field(PM2R, ByteAcc, NoLock, Preserve) {
+ PM2I, 0x00000008,
+ PM2D, 0x00000008,
+ }
+
+ /* Power Management I/O registers */
+ OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
+ Field(PIOR, ByteAcc, NoLock, Preserve) {
+ PIOI, 0x00000008,
+ PIOD, 0x00000008,
+ }
+ IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
+ Offset(0x00), /* MiscControl */
+ , 1,
+ T1EE, 1,
+ T2EE, 1,
+ Offset(0x01), /* MiscStatus */
+ , 1,
+ T1E, 1,
+ T2E, 1,
+ Offset(0x04), /* SmiWakeUpEventEnable3 */
+ , 7,
+ SSEN, 1,
+ Offset(0x07), /* SmiWakeUpEventStatus3 */
+ , 7,
+ CSSM, 1,
+ Offset(0x10), /* AcpiEnable */
+ , 6,
+ PWDE, 1,
+ Offset(0x1C), /* ProgramIoEnable */
+ , 3,
+ MKME, 1,
+ IO3E, 1,
+ IO2E, 1,
+ IO1E, 1,
+ IO0E, 1,
+ Offset(0x1D), /* IOMonitorStatus */
+ , 3,
+ MKMS, 1,
+ IO3S, 1,
+ IO2S, 1,
+ IO1S, 1,
+ IO0S,1,
+ Offset(0x20), /* AcpiPmEvtBlk */
+ APEB, 16,
+ Offset(0x36), /* GEvtLevelConfig */
+ , 6,
+ ELC6, 1,
+ ELC7, 1,
+ Offset(0x37), /* GPMLevelConfig0 */
+ , 3,
+ PLC0, 1,
+ PLC1, 1,
+ PLC2, 1,
+ PLC3, 1,
+ PLC8, 1,
+ Offset(0x38), /* GPMLevelConfig1 */
+ , 1,
+ PLC4, 1,
+ PLC5, 1,
+ , 1,
+ PLC6, 1,
+ PLC7, 1,
+ Offset(0x3B), /* PMEStatus1 */
+ GP0S, 1,
+ GM4S, 1,
+ GM5S, 1,
+ APS, 1,
+ GM6S, 1,
+ GM7S, 1,
+ GP2S, 1,
+ STSS, 1,
+ Offset(0x55), /* SoftPciRst */
+ SPRE, 1,
+ , 1,
+ , 1,
+ PNAT, 1,
+ PWMK, 1,
+ PWNS, 1,
+
+ /* Offset(0x61), */ /* Options_1 */
+ /* ,7, */
+ /* R617,1, */
+
+ Offset(0x65), /* UsbPMControl */
+ , 4,
+ URRE, 1,
+ Offset(0x68), /* MiscEnable68 */
+ , 3,
+ TMTE, 1,
+ , 1,
+ Offset(0x92), /* GEVENTIN */
+ , 7,
+ E7IS, 1,
+ Offset(0x96), /* GPM98IN */
+ G8IS, 1,
+ G9IS, 1,
+ Offset(0x9A), /* EnhanceControl */
+ ,7,
+ HPDE, 1,
+ Offset(0xA8), /* PIO7654Enable */
+ IO4E, 1,
+ IO5E, 1,
+ IO6E, 1,
+ IO7E, 1,
+ Offset(0xA9), /* PIO7654Status */
+ IO4S, 1,
+ IO5S, 1,
+ IO6S, 1,
+ IO7S, 1,
+ }
+
+ /* PM1 Event Block
+ * First word is PM1_Status, Second word is PM1_Enable
+ */
+ OperationRegion(P1EB, SystemIO, APEB, 0x04)
+ Field(P1EB, ByteAcc, NoLock, Preserve) {
+ TMST, 1,
+ , 3,
+ BMST, 1,
+ GBST, 1,
+ Offset(0x01),
+ PBST, 1,
+ , 1,
+ RTST, 1,
+ , 3,
+ PWST, 1,
+ SPWS, 1,
+ Offset(0x02),
+ TMEN, 1,
+ , 4,
+ GBEN, 1,
+ Offset(0x03),
+ PBEN, 1,
+ , 1,
+ RTEN, 1,
+ , 3,
+ PWDA, 1,
+ }
+
+ OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
+ Field (GRAM, ByteAcc, Lock, Preserve)
+ {
+ Offset (0x10),
+ FLG0, 8
+ }
+
+ Scope(\_SB) {
+ /* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */
+ OperationRegion(PCFG, SystemMemory, PCBA, PCLN)
+ Field(PCFG, ByteAcc, NoLock, Preserve) {
+ /* Byte offsets are computed using the following technique:
+ * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
+ * The 8 comes from 8 functions per device, and 4096 bytes per function config space
+ */
+ Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
+ STB5, 32,
+ Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
+ PT0D, 1,
+ PT1D, 1,
+ PT2D, 1,
+ PT3D, 1,
+ PT4D, 1,
+ PT5D, 1,
+ PT6D, 1,
+ PT7D, 1,
+ PT8D, 1,
+ PT9D, 1,
+ Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
+ SBIE, 1,
+ SBME, 1,
+ Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
+ SBRI, 8,
+ Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
+ SBB1, 32,
+ Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
+ ,14,
+ P92E, 1, /* Port92 decode enable */
+ }
+
+ OperationRegion(SB5, SystemMemory, STB5, 0x1000)
+ Field(SB5, AnyAcc, NoLock, Preserve){
+ /* Port 0 */
+ Offset(0x120), /* Port 0 Task file status */
+ P0ER, 1,
+ , 2,
+ P0DQ, 1,
+ , 3,
+ P0BY, 1,
+ Offset(0x128), /* Port 0 Serial ATA status */
+ P0DD, 4,
+ , 4,
+ P0IS, 4,
+ Offset(0x12C), /* Port 0 Serial ATA control */
+ P0DI, 4,
+ Offset(0x130), /* Port 0 Serial ATA error */
+ , 16,
+ P0PR, 1,
+
+ /* Port 1 */
+ offset(0x1A0), /* Port 1 Task file status */
+ P1ER, 1,
+ , 2,
+ P1DQ, 1,
+ , 3,
+ P1BY, 1,
+ Offset(0x1A8), /* Port 1 Serial ATA status */
+ P1DD, 4,
+ , 4,
+ P1IS, 4,
+ Offset(0x1AC), /* Port 1 Serial ATA control */
+ P1DI, 4,
+ Offset(0x1B0), /* Port 1 Serial ATA error */
+ , 16,
+ P1PR, 1,
+
+ /* Port 2 */
+ Offset(0x220), /* Port 2 Task file status */
+ P2ER, 1,
+ , 2,
+ P2DQ, 1,
+ , 3,
+ P2BY, 1,
+ Offset(0x228), /* Port 2 Serial ATA status */
+ P2DD, 4,
+ , 4,
+ P2IS, 4,
+ Offset(0x22C), /* Port 2 Serial ATA control */
+ P2DI, 4,
+ Offset(0x230), /* Port 2 Serial ATA error */
+ , 16,
+ P2PR, 1,
+
+ /* Port 3 */
+ Offset(0x2A0), /* Port 3 Task file status */
+ P3ER, 1,
+ , 2,
+ P3DQ, 1,
+ , 3,
+ P3BY, 1,
+ Offset(0x2A8), /* Port 3 Serial ATA status */
+ P3DD, 4,
+ , 4,
+ P3IS, 4,
+ Offset(0x2AC), /* Port 3 Serial ATA control */
+ P3DI, 4,
+ Offset(0x2B0), /* Port 3 Serial ATA error */
+ , 16,
+ P3PR, 1,
+ }
+ }
+
+ #include "acpi/routing.asl"
+
+ Scope(\_SB) {
+ Method(CkOT, 0){
+ if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */
+ if(CondRefOf(\_OSI,Local1))
+ {
+ Store(1, OSTP) /* Assume some form of XP */
+ if (\_OSI("Windows 2006")) /* Vista */
+ {
+ Store(2, OSTP)
+ }
+ } else {
+ If(WCMP(\_OS,"Linux")) {
+ Store(3, OSTP) /* Linux */
+ } Else {
+ Store(4, OSTP) /* Gotta be WinCE */
+ }
+ }
+ Return(OSTP)
+ }
+
+ Method(_PIC, 0x01, NotSerialized)
+ {
+ If (Arg0)
+ {
+ \_SB.CIRQ()
+ }
+ Store(Arg0, PMOD)
+ }
+ Method(CIRQ, 0x00, NotSerialized){
+ Store(0, PINA)
+ Store(0, PINB)
+ Store(0, PINC)
+ Store(0, PIND)
+ Store(0, PINE)
+ Store(0, PINF)
+ Store(0, PING)
+ Store(0, PINH)
+ }
+
+ Name(IRQB, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Shared){15}
+ })
+
+ Name(IRQP, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
+ })
+
+ Name(PITF, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Exclusive){9}
+ })
+
+ Device(INTA) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 1)
+
+ Method(_STA, 0) {
+ if (PINA) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTA._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKA\\_DIS\n") */
+ Store(0, PINA)
+ } /* End Method(_SB.INTA._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKA\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTA._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKA\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINA, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTA._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKA\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINA)
+ } /* End Method(_SB.INTA._SRS) */
+ } /* End Device(INTA) */
+
+ Device(INTB) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 2)
+
+ Method(_STA, 0) {
+ if (PINB) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTB._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKB\\_DIS\n") */
+ Store(0, PINB)
+ } /* End Method(_SB.INTB._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKB\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTB._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKB\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINB, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTB._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKB\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINB)
+ } /* End Method(_SB.INTB._SRS) */
+ } /* End Device(INTB) */
+
+ Device(INTC) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 3)
+
+ Method(_STA, 0) {
+ if (PINC) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTC._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKC\\_DIS\n") */
+ Store(0, PINC)
+ } /* End Method(_SB.INTC._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKC\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTC._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKC\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINC, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTC._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKC\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINC)
+ } /* End Method(_SB.INTC._SRS) */
+ } /* End Device(INTC) */
+
+ Device(INTD) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 4)
+
+ Method(_STA, 0) {
+ if (PIND) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTD._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKD\\_DIS\n") */
+ Store(0, PIND)
+ } /* End Method(_SB.INTD._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKD\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTD._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKD\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIND, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTD._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKD\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PIND)
+ } /* End Method(_SB.INTD._SRS) */
+ } /* End Device(INTD) */
+
+ Device(INTE) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 5)
+
+ Method(_STA, 0) {
+ if (PINE) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTE._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKE\\_DIS\n") */
+ Store(0, PINE)
+ } /* End Method(_SB.INTE._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKE\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTE._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKE\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINE, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTE._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKE\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINE)
+ } /* End Method(_SB.INTE._SRS) */
+ } /* End Device(INTE) */
+
+ Device(INTF) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 6)
+
+ Method(_STA, 0) {
+ if (PINF) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTF._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKF\\_DIS\n") */
+ Store(0, PINF)
+ } /* End Method(_SB.INTF._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKF\\_PRS\n") */
+ Return(PITF)
+ } /* Method(_SB.INTF._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKF\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINF, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTF._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKF\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINF)
+ } /* End Method(_SB.INTF._SRS) */
+ } /* End Device(INTF) */
+
+ Device(INTG) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 7)
+
+ Method(_STA, 0) {
+ if (PING) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTG._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKG\\_DIS\n") */
+ Store(0, PING)
+ } /* End Method(_SB.INTG._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKG\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTG._CRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKG\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PING, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTG._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKG\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PING)
+ } /* End Method(_SB.INTG._SRS) */
+ } /* End Device(INTG) */
+
+ Device(INTH) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 8)
+
+ Method(_STA, 0) {
+ if (PINH) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTH._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKH\\_DIS\n") */
+ Store(0, PINH)
+ } /* End Method(_SB.INTH._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKH\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTH._CRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKH\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PINH, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTH._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKH\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PINH)
+ } /* End Method(_SB.INTH._SRS) */
+ } /* End Device(INTH) */
+
+ } /* End Scope(_SB) */
+
+
+ /* Supported sleep states: */
+ Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
+
+ If (LAnd(SSFG, 0x01)) {
+ Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
+ }
+ If (LAnd(SSFG, 0x02)) {
+ Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
+ }
+ If (LAnd(SSFG, 0x04)) {
+ Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
+ }
+ If (LAnd(SSFG, 0x08)) {
+ Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
+ }
+
+ Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
+
+ Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
+ Name(CSMS, 0) /* Current System State */
+
+ /* Wake status package */
+ Name(WKST,Package(){Zero, Zero})
+
+ /*
+ * \_PTS - Prepare to Sleep method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2, etc
+ *
+ * Exit:
+ * -none-
+ *
+ * The _PTS control method is executed at the beginning of the sleep process
+ * for S1-S5. The sleeping value is passed to the _PTS control method. This
+ * control method may be executed a relatively long time before entering the
+ * sleep state and the OS may abort the operation without notification to
+ * the ACPI driver. This method cannot modify the configuration or power
+ * state of any device in the system.
+ */
+ Method(\_PTS, 1) {
+ /* DBGO("\\_PTS\n") */
+ /* DBGO("From S0 to S") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+
+ /* Don't allow PCIRST# to reset USB */
+ if (LEqual(Arg0,3)){
+ Store(0,URRE)
+ }
+
+ /* Clear sleep SMI status flag and enable sleep SMI trap. */
+ /*Store(One, CSSM)
+ Store(One, SSEN)*/
+
+ /* On older chips, clear PciExpWakeDisEn */
+ /*if (LLessEqual(\_SB.SBRI, 0x13)) {
+ * Store(0,\_SB.PWDE)
+ *}
+ */
+
+ /* Clear wake status structure. */
+ Store(0, Index(WKST,0))
+ Store(0, Index(WKST,1))
+ \_SB.PCI0.SIOS (Arg0)
+ } /* End Method(\_PTS) */
+
+ /*
+ * The following method results in a "not a valid reserved NameSeg"
+ * warning so I have commented it out for the duration. It isn't
+ * used, so it could be removed.
+ *
+ *
+ * \_GTS OEM Going To Sleep method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
+ *
+ * Exit:
+ * -none-
+ *
+ * Method(\_GTS, 1) {
+ * DBGO("\\_GTS\n")
+ * DBGO("From S0 to S")
+ * DBGO(Arg0)
+ * DBGO("\n")
+ * }
+ */
+
+ /*
+ * \_BFS OEM Back From Sleep method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
+ *
+ * Exit:
+ * -none-
+ */
+ Method(\_BFS, 1) {
+ /* DBGO("\\_BFS\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+ }
+
+ /*
+ * \_WAK System Wake method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
+ *
+ * Exit:
+ * Return package of 2 DWords
+ * Dword 1 - Status
+ * 0x00000000 wake succeeded
+ * 0x00000001 Wake was signaled but failed due to lack of power
+ * 0x00000002 Wake was signaled but failed due to thermal condition
+ * Dword 2 - Power Supply state
+ * if non-zero the effective S-state the power supply entered
+ */
+ Method(\_WAK, 1) {
+ /* DBGO("\\_WAK\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+
+ /* Re-enable HPET */
+ Store(1,HPDE)
+
+ /* Restore PCIRST# so it resets USB */
+ if (LEqual(Arg0,3)){
+ Store(1,URRE)
+ }
+
+ /* Arbitrarily clear PciExpWakeStatus */
+ Store(PWST, PWST)
+
+ /* if(DeRefOf(Index(WKST,0))) {
+ * Store(0, Index(WKST,1))
+ * } else {
+ * Store(Arg0, Index(WKST,1))
+ * }
+ */
+ \_SB.PCI0.SIOW (Arg0)
+ Return(WKST)
+ } /* End Method(\_WAK) */
+
+ Scope(\_GPE) { /* Start Scope GPE */
+ /* General event 0 */
+ /* Method(_L00) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 1 */
+ /* Method(_L01) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 2 */
+ /* Method(_L02) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 3 */
+ Method(_L03) {
+ /* DBGO("\\_GPE\\_L00\n") */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* General event 4 */
+ /* Method(_L04) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 5 */
+ /* Method(_L05) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 6 - Used for GPM6, moved to USB.asl */
+ /* Method(_L06) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 7 - Used for GPM7, moved to USB.asl */
+ /* Method(_L07) {
+ * DBGO("\\_GPE\\_L07\n")
+ * }
+ */
+
+ /* Legacy PM event */
+ Method(_L08) {
+ /* DBGO("\\_GPE\\_L08\n") */
+ }
+
+ /* Temp warning (TWarn) event */
+ Method(_L09) {
+ /* DBGO("\\_GPE\\_L09\n") */
+ Notify (\_TZ.TZ00, 0x80)
+ }
+
+ /* Reserved */
+ /* Method(_L0A) {
+ * DBGO("\\_GPE\\_L0A\n")
+ * }
+ */
+
+ /* USB controller PME# */
+ Method(_L0B) {
+ /* DBGO("\\_GPE\\_L0B\n") */
+ Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* AC97 controller PME# */
+ /* Method(_L0C) {
+ * DBGO("\\_GPE\\_L0C\n")
+ * }
+ */
+
+ /* OtherTherm PME# */
+ /* Method(_L0D) {
+ * DBGO("\\_GPE\\_L0D\n")
+ * }
+ */
+
+ /* GPM9 SCI event - Moved to USB.asl */
+ /* Method(_L0E) {
+ * DBGO("\\_GPE\\_L0E\n")
+ * }
+ */
+
+ /* PCIe HotPlug event */
+ /* Method(_L0F) {
+ * DBGO("\\_GPE\\_L0F\n")
+ * }
+ */
+
+ /* ExtEvent0 SCI event */
+ Method(_L10) {
+ /* DBGO("\\_GPE\\_L10\n") */
+ }
+
+
+ /* ExtEvent1 SCI event */
+ Method(_L11) {
+ /* DBGO("\\_GPE\\_L11\n") */
+ }
+
+ /* PCIe PME# event */
+ /* Method(_L12) {
+ * DBGO("\\_GPE\\_L12\n")
+ * }
+ */
+
+ /* GPM0 SCI event - Moved to USB.asl */
+ /* Method(_L13) {
+ * DBGO("\\_GPE\\_L13\n")
+ * }
+ */
+
+ /* GPM1 SCI event - Moved to USB.asl */
+ /* Method(_L14) {
+ * DBGO("\\_GPE\\_L14\n")
+ * }
+ */
+
+ /* GPM2 SCI event - Moved to USB.asl */
+ /* Method(_L15) {
+ * DBGO("\\_GPE\\_L15\n")
+ * }
+ */
+
+ /* GPM3 SCI event - Moved to USB.asl */
+ /* Method(_L16) {
+ * DBGO("\\_GPE\\_L16\n")
+ * }
+ */
+
+ /* GPM8 SCI event - Moved to USB.asl */
+ /* Method(_L17) {
+ * DBGO("\\_GPE\\_L17\n")
+ * }
+ */
+
+ /* GPIO0 or GEvent8 event */
+ Method(_L18) {
+ /* DBGO("\\_GPE\\_L18\n") */
+ Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* GPM4 SCI event - Moved to USB.asl */
+ /* Method(_L19) {
+ * DBGO("\\_GPE\\_L19\n")
+ * }
+ */
+
+ /* GPM5 SCI event - Moved to USB.asl */
+ /* Method(_L1A) {
+ * DBGO("\\_GPE\\_L1A\n")
+ * }
+ */
+
+ /* Azalia SCI event */
+ Method(_L1B) {
+ /* DBGO("\\_GPE\\_L1B\n") */
+ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* GPM6 SCI event - Reassigned to _L06 */
+ /* Method(_L1C) {
+ * DBGO("\\_GPE\\_L1C\n")
+ * }
+ */
+
+ /* GPM7 SCI event - Reassigned to _L07 */
+ /* Method(_L1D) {
+ * DBGO("\\_GPE\\_L1D\n")
+ * }
+ */
+
+ /* GPIO2 or GPIO66 SCI event */
+ /* Method(_L1E) {
+ * DBGO("\\_GPE\\_L1E\n")
+ * }
+ */
+
+ /* SATA SCI event - Moved to sata.asl */
+ /* Method(_L1F) {
+ * DBGO("\\_GPE\\_L1F\n")
+ * }
+ */
+
+ } /* End Scope GPE */
+
+ #include "acpi/usb.asl"
+
+ /* System Bus */
+ Scope(\_SB) { /* Start \_SB scope */
+ #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */
+
+ /* _SB.PCI0 */
+ /* Note: Only need HID on Primary Bus */
+ Device(PCI0) {
+ External (TOM1) //assigned when update_ssdt()
+ External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
+
+ Name(_HID, EISAID("PNP0A03"))
+ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
+ Method(_BBN, 0) { /* Bus number = 0 */
+ Return(0)
+ }
+ Method(_STA, 0) {
+ /* DBGO("\\_SB\\PCI0\\_STA\n") */
+ Return(0x0B) /* Status is visible */
+ }
+
+ Method(_PRT,0) {
+ If(PMOD){ Return(APR0) } /* APIC mode */
+ Return (PR0) /* PIC Mode */
+ } /* end _PRT */
+
+ /* Describe the Northbridge devices */
+ Device(AMRT) {
+ Name(_ADR, 0x00000000)
+ } /* end AMRT */
+
+ /* The external GFX bridge */
+ Device(PBR2) {
+ Name(_ADR, 0x00020000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS2) } /* APIC mode */
+ Return (PS2) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR2 */
+
+ /* Dev3 is also an external GFX bridge */
+
+ Device(PBR4) {
+ Name(_ADR, 0x00040000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS4) } /* APIC mode */
+ Return (PS4) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR4 */
+
+ Device(PBRb) {
+ Name(_ADR, 0x000b0000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APSb) } /* APIC mode */
+ Return (PSb) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBRb */
+
+ Device(PBRc) {
+ Name(_ADR, 0x000c0000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APSc) } /* APIC mode */
+ Return (PSc) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBRc */
+
+ Device(PBRd) {
+ Name(_ADR, 0x000d0000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APSd) } /* APIC mode */
+ Return (PSd) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBRd */
+
+ /* Describe the Southbridge devices */
+ Device(STCR) {
+ Name(_ADR, 0x00110000)
+ #include "acpi/sata.asl"
+ } /* end STCR */
+
+ Device(UOH1) {
+ Name(_ADR, 0x00130000)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH1 */
+
+ Device(UOH2) {
+ Name(_ADR, 0x00130001)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH2 */
+
+ Device(UOH3) {
+ Name(_ADR, 0x00130002)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH3 */
+
+ Device(UOH4) {
+ Name(_ADR, 0x00130003)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH4 */
+
+ Device(UOH5) {
+ Name(_ADR, 0x00130004)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH5 */
+
+ Device(UEH1) {
+ Name(_ADR, 0x00130005)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UEH1 */
+
+ Device(SBUS) {
+ Name(_ADR, 0x00140000)
+ } /* end SBUS */
+
+ /* Primary (and only) IDE channel */
+ Device(IDEC) {
+ Name(_ADR, 0x00140001)
+ #include "acpi/ide.asl"
+ } /* end IDEC */
+
+ Device(AZHD) {
+ Name(_ADR, 0x00140002)
+ OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
+ Field(AZPD, AnyAcc, NoLock, Preserve) {
+ offset (0x42),
+ NSDI, 1,
+ NSDO, 1,
+ NSEN, 1,
+ offset (0x44),
+ IPCR, 4,
+ offset (0x54),
+ PWST, 2,
+ , 6,
+ PMEB, 1,
+ , 6,
+ PMST, 1,
+ offset (0x62),
+ MMCR, 1,
+ offset (0x64),
+ MMLA, 32,
+ offset (0x68),
+ MMHA, 32,
+ offset (0x6C),
+ MMDT, 16,
+ }
+
+ Method(_INI) {
+ If(LEqual(OSTP,3)){ /* If we are running Linux */
+ Store(zero, NSEN)
+ Store(one, NSDO)
+ Store(one, NSDI)
+ }
+ }
+ } /* end AZHD */
+
+ Device(LIBR) {
+ Name(_ADR, 0x00140003)
+ /* Method(_INI) {
+ * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
+ } */ /* End Method(_SB.SBRDG._INI) */
+
+ /* Real Time Clock Device */
+ Device(RTC0) {
+ Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
+ Name(_CRS, ResourceTemplate() {
+ IRQNoFlags(){8}
+ IO(Decode16,0x0070, 0x0070, 0, 2)
+ /* IO(Decode16,0x0070, 0x0070, 0, 4) */
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
+
+ Device(TMR) { /* Timer */
+ Name(_HID,EISAID("PNP0100")) /* System Timer */
+ Name(_CRS, ResourceTemplate() {
+ IRQNoFlags(){0}
+ IO(Decode16, 0x0040, 0x0040, 0, 4)
+ /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
+
+ Device(SPKR) { /* Speaker */
+ Name(_HID,EISAID("PNP0800")) /* AT style speaker */
+ Name(_CRS, ResourceTemplate() {
+ IO(Decode16, 0x0061, 0x0061, 0, 1)
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
+
+ Device(PIC) {
+ Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
+ Name(_CRS, ResourceTemplate() {
+ IRQNoFlags(){2}
+ IO(Decode16,0x0020, 0x0020, 0, 2)
+ IO(Decode16,0x00A0, 0x00A0, 0, 2)
+ /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
+ /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
+
+ Device(MAD) { /* 8257 DMA */
+ Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
+ Name(_CRS, ResourceTemplate() {
+ DMA(Compatibility,BusMaster,Transfer8){4}
+ IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
+ IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
+ IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
+ IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
+ IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
+ IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
+ }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
+ } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
+
+ Device(COPR) {
+ Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
+ Name(_CRS, ResourceTemplate() {
+ IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
+ IRQNoFlags(){13}
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+
+ Device (PS2M) {
+ Name (_HID, EisaId ("PNP0F13"))
+ Name (_CRS, ResourceTemplate () {
+ IO (Decode16, 0x0060, 0x0060, 0x00, 0x01)
+ IO (Decode16, 0x0064, 0x0064, 0x00, 0x01)
+ IRQNoFlags () {12}
+ })
+ Method (_STA, 0, NotSerialized) {
+ And (FLG0, 0x04, Local0)
+ If (LEqual (Local0, 0x04)) {
+ Return (0x0F)
+ } Else {
+ Return (0x00)
+ }
+ }
+ }
+
+ Device (PS2K) {
+ Name (_HID, EisaId ("PNP0303"))
+ Method (_STA, 0, NotSerialized) {
+ And (FLG0, 0x04, Local0)
+ If (LEqual (Local0, 0x04)) {
+ Return (0x0F)
+ } Else {
+ Return (0x00)
+ }
+ }
+ Name (_CRS, ResourceTemplate () {
+ IO (Decode16, 0x0060, 0x0060, 0x00, 0x01)
+ IO (Decode16, 0x0064, 0x0064, 0x00, 0x01)
+ IRQNoFlags () {1}
+ })
+ }
+
+#if 0 //acpi_create_hpet
+ Device(HPET) {
+ Name(_HID,EISAID("PNP0103"))
+ Name(CRS, ResourceTemplate() {
+ IRQNoFlags () {0}
+ IRQNoFlags () {2}
+ IRQNoFlags () {8}
+ Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, MNT) /* 1kb reserved space */
+ })
+ Method(_STA, 0, NotSerialized) {
+ Return(0x0F) /* sata is visible */
+ }
+ Method(_CRS, 0, NotSerialized) {
+ CreateDwordField(CRS, ^MNT._BAS, HPT)
+ Store(HPBA, HPT)
+ Return(CRS)
+ }
+ } /* End Device(_SB.PCI0.LIBR.HPET) */
+#endif
+ } /* end LIBR */
+
+ Device(HPBR) {
+ Name(_ADR, 0x00140004)
+ } /* end HostPciBr */
+
+ Device(ACAD) {
+ Name(_ADR, 0x00140005)
+ } /* end Ac97audio */
+
+ Device(ACMD) {
+ Name(_ADR, 0x00140006)
+ } /* end Ac97modem */
+
+ /* ITE8718 Support */
+ OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */
+ Field (IOID, ByteAcc, NoLock, Preserve)
+ {
+ SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */
+ }
+
+ IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x07),
+ LDN, 8, /* Logical Device Number */
+ Offset (0x20),
+ CID1, 8, /* Chip ID Byte 1, 0x87 */
+ CID2, 8, /* Chip ID Byte 2, 0x12 */
+ Offset (0x30),
+ ACTR, 8, /* Function activate */
+ Offset (0xF0),
+ APC0, 8, /* APC/PME Event Enable Register */
+ APC1, 8, /* APC/PME Status Register */
+ APC2, 8, /* APC/PME Control Register 1 */
+ APC3, 8, /* Environment Controller Special Configuration Register */
+ APC4, 8 /* APC/PME Control Register 2 */
+ }
+
+ /* Enter the 8718 MB PnP Mode */
+ Method (EPNP)
+ {
+ Store(0x87, SIOI)
+ Store(0x01, SIOI)
+ Store(0x55, SIOI)
+ Store(0x55, SIOI) /* 8718 magic number */
+ }
+ /* Exit the 8718 MB PnP Mode */
+ Method (XPNP)
+ {
+ Store (0x02, SIOI)
+ Store (0x02, SIOD)
+ }
+ /*
+ * Keyboard PME is routed to SB700 Gevent3. We can wake
+ * up the system by pressing the key.
+ */
+ Method (SIOS, 1)
+ {
+ /* We only enable KBD PME for S5. */
+ If (LLess (Arg0, 0x05))
+ {
+ EPNP()
+ /* DBGO("8718F\n") */
+
+ Store (0x4, LDN)
+ Store (One, ACTR) /* Enable EC */
+ /*
+ Store (0x4, LDN)
+ Store (0x04, APC4)
+ */ /* falling edge. which mode? Not sure. */
+
+ Store (0x4, LDN)
+ Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
+ Store (0x4, LDN)
+ Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
+
+ XPNP()
+ }
+ }
+ Method (SIOW, 1)
+ {
+ EPNP()
+ Store (0x4, LDN)
+ Store (Zero, APC0) /* disable keyboard PME */
+ Store (0x4, LDN)
+ Store (0xFF, APC1) /* clear keyboard PME status */
+ XPNP()
+ }
+
+ Name (CRS, ResourceTemplate ()
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x00FF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0100, // Length
+ ,,)
+ IO (Decode16,
+ 0x0CF8, // Range Minimum
+ 0x0CF8, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x03AF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x03B0, // Length
+ ,, , TypeStatic)
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x03E0, // Range Minimum
+ 0x0CF7, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0918, // Length
+ ,, , TypeStatic)
+
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x03B0, // Range Minimum
+ 0x03BB, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x000C, // Length
+ ,, , TypeStatic)
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x03C0, // Range Minimum
+ 0x03DF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0020, // Length
+ ,, , TypeStatic)
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x9000, // Range Minimum
+ 0xefff, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x6000, // Length
+ ,, , TypeStatic)
+ Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) // VGA memory space
+
+ Memory32Fixed (ReadOnly,
+ 0xE0000000, // Address Base
+ 0x10000000, // Address Length, (1MB each Bus, 256 Buses by default)
+ MMIO)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0xF0000000, // Range Minimum
+ 0xFFFFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x10000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ })
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ CreateDWordField (CRS, \_SB.PCI0.MMIO._BAS, BAS1)
+ CreateDWordField (CRS, \_SB.PCI0.MMIO._LEN, LEN1)
+ Store (PCBA, BAS1)
+ Store (PCLN, LEN1)
+
+ Return (CRS)
+ }
+
+ /*
+ *
+ * FIRST METHOD CALLED UPON BOOT
+ *
+ * 1. If debugging, print current OS and ACPI interpreter.
+ * 2. Get PCI Interrupt routing from ACPI VSM, this
+ * value is based on user choice in BIOS setup.
+ */
+ Method(_INI, 0) {
+ /* DBGO("\\_SB\\_INI\n") */
+ /* DBGO(" DSDT.ASL code from ") */
+ /* DBGO(__DATE__) */
+ /* DBGO(" ") */
+ /* DBGO(__TIME__) */
+ /* DBGO("\n Sleep states supported: ") */
+ /* DBGO("\n") */
+ /* DBGO(" \\_OS=") */
+ /* DBGO(\_OS) */
+ /* DBGO("\n \\_REV=") */
+ /* DBGO(\_REV) */
+ /* DBGO("\n") */
+
+ /* Determine the OS we're running on */
+ CkOT()
+ /* On older chips, clear PciExpWakeDisEn */
+ /*if (LLessEqual(\SBRI, 0x13)) {
+ * Store(0,\PWDE)
+ *}
+ */
+ } /* End Method(_SB._INI) */
+ } /* End Device(PCI0) */
+
+ Device(PWRB) { /* Start Power button device */
+ Name(_HID, EISAID("PNP0C0C"))
+ Name(_UID, 0xAA)
+ Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
+ Name(_STA, 0x0B) /* sata is invisible */
+ }
+ } /* End \_SB scope */
+
+ Scope(\_SI) {
+ Method(_SST, 1) {
+ /* DBGO("\\_SI\\_SST\n") */
+ /* DBGO(" New Indicator state: ") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+ }
+ } /* End Scope SI */
+
+ /* SMBUS Support */
+ Mutex (SBX0, 0x00)
+ OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
+ Field (SMB0, ByteAcc, NoLock, Preserve) {
+ HSTS, 8, /* SMBUS status */
+ SSTS, 8, /* SMBUS slave status */
+ HCNT, 8, /* SMBUS control */
+ HCMD, 8, /* SMBUS host cmd */
+ HADD, 8, /* SMBUS address */
+ DAT0, 8, /* SMBUS data0 */
+ DAT1, 8, /* SMBUS data1 */
+ BLKD, 8, /* SMBUS block data */
+ SCNT, 8, /* SMBUS slave control */
+ SCMD, 8, /* SMBUS shaow cmd */
+ SEVT, 8, /* SMBUS slave event */
+ SDAT, 8 /* SMBUS slave data */
+ }
+
+ Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
+ Store (0x1E, HSTS)
+ Store (0xFA, Local0)
+ While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
+ Stall (0x64)
+ Decrement (Local0)
+ }
+
+ Return (Local0)
+ }
+
+ Method (SWTC, 1, NotSerialized) {
+ Store (Arg0, Local0)
+ Store (0x07, Local2)
+ Store (One, Local1)
+ While (LEqual (Local1, One)) {
+ Store (And (HSTS, 0x1E), Local3)
+ If (LNotEqual (Local3, Zero)) { /* read sucess */
+ If (LEqual (Local3, 0x02)) {
+ Store (Zero, Local2)
+ }
+
+ Store (Zero, Local1)
+ }
+ Else {
+ If (LLess (Local0, 0x0A)) { /* read failure */
+ Store (0x10, Local2)
+ Store (Zero, Local1)
+ }
+ Else {
+ Sleep (0x0A) /* 10 ms, try again */
+ Subtract (Local0, 0x0A, Local0)
+ }
+ }
+ }
+
+ Return (Local2)
+ }
+
+ Method (SMBR, 3, NotSerialized) {
+ Store (0x07, Local0)
+ If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
+ Store (WCLR (), Local0) /* clear SMBUS status register before read data */
+ If (LEqual (Local0, Zero)) {
+ Release (SBX0)
+ Return (0x0)
+ }
+
+ Store (0x1F, HSTS)
+ Store (Or (ShiftLeft (Arg1, One), One), HADD)
+ Store (Arg2, HCMD)
+ If (LEqual (Arg0, 0x07)) {
+ Store (0x48, HCNT) /* read byte */
+ }
+
+ Store (SWTC (0x03E8), Local1) /* 1000 ms */
+ If (LEqual (Local1, Zero)) {
+ If (LEqual (Arg0, 0x07)) {
+ Store (DAT0, Local0)
+ }
+ }
+ Else {
+ Store (Local1, Local0)
+ }
+
+ Release (SBX0)
+ }
+
+ /* DBGO("the value of SMBusData0 register ") */
+ /* DBGO(Arg2) */
+ /* DBGO(" is ") */
+ /* DBGO(Local0) */
+ /* DBGO("\n") */
+
+ Return (Local0)
+ }
+
+ /* THERMAL */
+ Scope(\_TZ) {
+ Name (KELV, 2732)
+ Name (THOT, 800)
+ Name (TCRT, 850)
+
+ ThermalZone(TZ00) {
+ Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */
+ /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
+ Return(Add(0, 2730))
+ }
+ Method(_AL0,0) { /* Returns package of cooling device to turn on */
+ /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
+ Return(Package() {\_TZ.TZ00.FAN0})
+ }
+ Device (FAN0) {
+ Name(_HID, EISAID("PNP0C0B"))
+ Name(_PR0, Package() {PFN0})
+ }
+
+ PowerResource(PFN0,0,0) {
+ Method(_STA) {
+ Store(0xF,Local0)
+ Return(Local0)
+ }
+ Method(_ON) {
+ /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
+ }
+ Method(_OFF) {
+ /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
+ }
+ }
+
+ Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */
+ /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
+ Return (Add (THOT, KELV))
+ }
+ Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */
+ /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
+ Return (Add (TCRT, KELV))
+ }
+ Method(_TMP,0) { /* return current temp of this zone */
+ Store (SMBR (0x07, 0x4C,, 0x00), Local0)
+ If (LGreater (Local0, 0x10)) {
+ Store (Local0, Local1)
+ }
+ Else {
+ Add (Local0, THOT, Local0)
+ Return (Add (400, KELV))
+ }
+
+ Store (SMBR (0x07, 0x4C, 0x01), Local0)
+ /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
+ /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
+ If (LGreater (Local0, 0x10)) {
+ If (LGreater (Local0, Local1)) {
+ Store (Local0, Local1)
+ }
+
+ Multiply (Local1, 10, Local1)
+ Return (Add (Local1, KELV))
+ }
+ Else {
+ Add (Local0, THOT, Local0)
+ Return (Add (400 , KELV))
+ }
+ } /* end of _TMP */
+ } /* end of TZ00 */
+ }
+}
+/* End of ASL file */
diff --git a/src/mainboard/supermicro/h8qgi/fadt.c b/src/mainboard/supermicro/h8qgi/fadt.c
new file mode 100755
index 0000000..c2f714d
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/fadt.c
@@ -0,0 +1,201 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+/*
+ * ACPI - create the Fixed ACPI Description Tables (FADT)
+ */
+
+
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include "southbridge/amd/sb700/sb700.h"
+
+u16 pm_base = SB700_ACPI_IO_BASE;
+/* pm_base should be set in sb acpi */
+/* pm_base should be got from bar2 of sb700. Here I compact ACPI
+ * registers into 32 bytes limit.
+ * */
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+
+ pm_base &= 0xFFFF;
+ printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
+
+ /* Prepare the header */
+ memset((void *)fadt, 0, sizeof(acpi_fadt_t));
+ memcpy(header->signature, "FACP", 4);
+ header->length = 244;
+ header->revision = 3;
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, "AMD ", 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+ header->asl_compiler_revision = 0;
+
+ fadt->firmware_ctrl = (u32) facs;
+ fadt->dsdt = (u32) dsdt;
+ /* 3=Workstation,4=Enterprise Server, 7=Performance Server */
+ fadt->preferred_pm_profile = 0x03;
+ fadt->sci_int = 9;
+ /* disable system management mode by setting to 0: */
+ fadt->smi_cmd = 0;
+ fadt->acpi_enable = 0xf0;
+ fadt->acpi_disable = 0xf1;
+ fadt->s4bios_req = 0x0;
+ fadt->pstate_cnt = 0xe2;
+
+ pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF);
+ pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8);
+ pm_iowrite(0x62, ACPI_PM1_CNT_BLK & 0xFF);
+ pm_iowrite(0x63, ACPI_PM1_CNT_BLK >> 8);
+ pm_iowrite(0x64, ACPI_PM_TMR_BLK & 0xFF);
+ pm_iowrite(0x65, ACPI_PM_TMR_BLK >> 8);
+ pm_iowrite(0x68, ACPI_GPE0_BLK & 0xFF);
+ pm_iowrite(0x69, ACPI_GPE0_BLK >> 8);
+
+ /* CpuControl is in \_PR.CPU0, 6 bytes */
+ pm_iowrite(0x66, ACPI_CPU_CONTROL & 0xFF);
+ pm_iowrite(0x67, ACPI_CPU_CONTROL >> 8);
+
+ pm_iowrite(0x6A, 0); /* AcpiSmiCmdLo */
+ pm_iowrite(0x6B, 0); /* AcpiSmiCmdHi */
+
+ pm_iowrite(0x6C, ACPI_PMA_CNT_BLK & 0xFF);
+ pm_iowrite(0x6D, ACPI_PMA_CNT_BLK >> 8);
+
+ pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses
+ * the contents of the PM registers at
+ * index 60-6B to decode ACPI I/O address.
+ * AcpiSmiEn & SmiCmdEn*/
+ /* RTC_En_En, TMR_En_En, GBL_EN_EN */
+ outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
+ fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
+ fadt->pm1b_evt_blk = 0x0000;
+ fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
+ fadt->pm1b_cnt_blk = 0x0000;
+ fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
+ fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
+ fadt->gpe0_blk = ACPI_GPE0_BLK;
+ fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */
+
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ fadt->pm2_cnt_len = 1;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = 8;
+ fadt->gpe1_blk_len = 0;
+ fadt->gpe1_base = 0;
+
+ fadt->cst_cnt = 0xe3;
+ fadt->p_lvl2_lat = 101;
+ fadt->p_lvl3_lat = 1001;
+ fadt->flush_size = 0;
+ fadt->flush_stride = 0;
+ fadt->duty_offset = 1;
+ fadt->duty_width = 3;
+ fadt->day_alrm = 0; /* 0x7d these have to be */
+ fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */
+ fadt->century = 0; /* 0x7f to make rtc alrm work */
+ fadt->iapc_boot_arch = 0x3; /* See table 5-11 */
+ fadt->flags = 0x0001c1a5;/* 0x25; */
+
+ fadt->res2 = 0;
+
+ fadt->reset_reg.space_id = 1;
+ fadt->reset_reg.bit_width = 8;
+ fadt->reset_reg.bit_offset = 0;
+ fadt->reset_reg.resv = 0;
+ fadt->reset_reg.addrl = 0xcf9;
+ fadt->reset_reg.addrh = 0x0;
+
+ fadt->reset_value = 6;
+ fadt->x_firmware_ctl_l = (u32) facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (u32) dsdt;
+ fadt->x_dsdt_h = 0;
+
+ fadt->x_pm1a_evt_blk.space_id = 1;
+ fadt->x_pm1a_evt_blk.bit_width = 32;
+ fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.resv = 0;
+ fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
+ fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_evt_blk.space_id = 1;
+ fadt->x_pm1b_evt_blk.bit_width = 4;
+ fadt->x_pm1b_evt_blk.bit_offset = 0;
+ fadt->x_pm1b_evt_blk.resv = 0;
+ fadt->x_pm1b_evt_blk.addrl = 0x0;
+ fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+
+ fadt->x_pm1a_cnt_blk.space_id = 1;
+ fadt->x_pm1a_cnt_blk.bit_width = 16;
+ fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.resv = 0;
+ fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
+ fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_cnt_blk.space_id = 1;
+ fadt->x_pm1b_cnt_blk.bit_width = 2;
+ fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ fadt->x_pm1b_cnt_blk.resv = 0;
+ fadt->x_pm1b_cnt_blk.addrl = 0x0;
+ fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+
+ fadt->x_pm2_cnt_blk.space_id = 1;
+ fadt->x_pm2_cnt_blk.bit_width = 0;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.resv = 0;
+ fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;
+ fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = 32;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.resv = 0;
+ fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+
+
+ fadt->x_gpe0_blk.space_id = 1;
+ fadt->x_gpe0_blk.bit_width = 32;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.resv = 0;
+ fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
+ fadt->x_gpe0_blk.addrh = 0x0;
+
+
+ fadt->x_gpe1_blk.space_id = 1;
+ fadt->x_gpe1_blk.bit_width = 0;
+ fadt->x_gpe1_blk.bit_offset = 0;
+ fadt->x_gpe1_blk.resv = 0;
+ fadt->x_gpe1_blk.addrl = 0;
+ fadt->x_gpe1_blk.addrh = 0x0;
+
+ header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
+}
+
diff --git a/src/mainboard/supermicro/h8qgi/get_bus_conf.c b/src/mainboard/supermicro/h8qgi/get_bus_conf.c
new file mode 100755
index 0000000..14e6bca
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/get_bus_conf.c
@@ -0,0 +1,154 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <cpu/amd/amdfam10_sysconf.h>
+#include "agesawrapper.h"
+
+
+/* Global variables for MB layouts and these will be shared by irqtable mptable
+ * and acpi_tables busnum is default.
+ */
+u8 bus_isa;
+u8 bus_sp5100[2];
+u8 bus_sr5650[14];
+
+/*
+ * Here you only need to set value in pci1234 for HT-IO that could be installed or not
+ * You may need to preset pci1234 for HTIO board,
+ * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+ */
+u32 pci1234x[] = {
+ 0x0000ff0,
+};
+
+/*
+ * HT Chain device num, actually it is unit id base of every ht device in chain,
+ * assume every chain only have 4 ht device at most
+ */
+u32 hcdnx[] = {
+ 0x20202020,
+};
+
+u32 bus_type[256];
+
+u32 sbdn_sr5650;
+u32 sbdn_sp5100;
+
+static u32 get_bus_conf_done = 0;
+
+
+void get_bus_conf(void)
+{
+ u32 status;
+
+ device_t dev;
+ int i, j;
+
+ if (get_bus_conf_done == 1)
+ return; /* do it only once */
+
+ get_bus_conf_done = 1;
+
+ /*
+ * This is the call to AmdInitLate. It is really in the wrong place, conceptually,
+ * but functionally within the coreboot model, this is the best place to make the
+ * call. The logically correct place to call AmdInitLate is after PCI scan is done,
+ * after the decision about S3 resume is made, and before the system tables are
+ * written into RAM. The routine that is responsible for writing the tables is
+ * "write_tables", called near the end of "hardwaremain". There is no platform
+ * specific entry point between the S3 resume decision point and the call to
+ * "write_tables", and the next platform specific entry points are the calls to
+ * the ACPI table write functions. The first of ose would seem to be the right
+ * place, but other table write functions, e.g. the PIRQ table write function, are
+ * called before the ACPI tables are written. This routine is called at the beginning
+ * of each of the write functions called prior to the ACPI write functions, so this
+ * becomes the best place for this call.
+ */
+ status = agesawrapper_amdinitlate();
+ if(status) {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
+ }
+
+ sbdn_sp5100 = 0;
+
+ for (i = 0; i < 0; i++) {
+ bus_sp5100[i] = 0;
+ }
+ for (i = 0; i < ARRAY_SIZE(bus_sr5650); i++) {
+ bus_sr5650[i] = 0;
+ }
+
+ for (i = 0; i < 256; i++) {
+ bus_type[i] = 0; /* default ISA bus. */
+ }
+
+ bus_type[0] = 1; /* pci */
+
+ bus_sr5650[0] = (pci1234x[0] >> 16) & 0xff;
+ // bus_sp5100[0] = (sysconf.pci1234[0] >> 16) & 0xff;
+ bus_sp5100[0] = bus_sr5650[0];
+
+ /* sp5100 */
+ dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, 4));
+
+ if (dev) {
+ bus_sp5100[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+
+ bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_isa++;
+ for (j = bus_sp5100[1]; j < bus_isa; j++)
+ bus_type[j] = 1;
+ }
+
+ /* sr5650 */
+ for (i = 1; i < ARRAY_SIZE(bus_sr5650); i++) {
+ dev = dev_find_slot(bus_sr5650[0], PCI_DEVFN(sbdn_sr5650 + i, 0));
+ if (dev) {
+ bus_sr5650[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ if(255 != bus_sr5650[i]) {
+ bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_isa++;
+ bus_type[bus_sr5650[i]] = 1; /* PCI bus. */
+ }
+ }
+ }
+
+/*
+ for (i = 0; i < 4; i++) {
+ dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, i));
+ if (dev) {
+ bus_sp5100[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_isa++;
+ }
+ }
+ for (j = bus_sp5100[2]; j < bus_isa; j++)
+ bus_type[j] = 1;
+*/
+
+
+ /* I/O APICs: APIC ID Version State Address */
+ bus_isa = 10;
+}
diff --git a/src/mainboard/supermicro/h8qgi/irq_tables.c b/src/mainboard/supermicro/h8qgi/irq_tables.c
new file mode 100755
index 0000000..640a0a6
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/irq_tables.c
@@ -0,0 +1,122 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/pirq_routing.h>
+#include <cpu/amd/amdfam10_sysconf.h>
+
+
+static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
+ u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+ u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
+ u8 slot, u8 rfu)
+{
+ pirq_info->bus = bus;
+ pirq_info->devfn = devfn;
+ pirq_info->irq[0].link = link0;
+ pirq_info->irq[0].bitmap = bitmap0;
+ pirq_info->irq[1].link = link1;
+ pirq_info->irq[1].bitmap = bitmap1;
+ pirq_info->irq[2].link = link2;
+ pirq_info->irq[2].bitmap = bitmap2;
+ pirq_info->irq[3].link = link3;
+ pirq_info->irq[3].bitmap = bitmap3;
+ pirq_info->slot = slot;
+ pirq_info->rfu = rfu;
+}
+extern u8 bus_isa;
+extern u8 bus_sp5100[2];
+extern unsigned long sbdn_sp5100;
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+
+ struct irq_routing_table *pirq;
+ struct irq_info *pirq_info;
+ u32 slot_num;
+ u8 *v;
+
+ u8 sum = 0;
+ int i;
+
+
+ get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
+
+
+ /* Align the table to be 16 byte aligned. */
+ addr += 15;
+ addr &= ~15;
+
+ /* This table must be betweeen 0xf0000 & 0x100000 */
+ printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
+
+ pirq = (void *)(addr);
+ v = (u8 *) (addr);
+
+ pirq->signature = PIRQ_SIGNATURE;
+ pirq->version = PIRQ_VERSION;
+
+ pirq->rtr_bus = bus_sp5100[0];
+ pirq->rtr_devfn = ((sbdn_sp5100 + 0x14) << 3) | 4;
+
+ pirq->exclusive_irqs = 0;
+
+ pirq->rtr_vendor = 0x1002;
+ pirq->rtr_device = 0x4384;
+
+ pirq->miniport_data = 0;
+
+ memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+ pirq_info = (void *)(&pirq->checksum + 1);
+ slot_num = 0;
+
+
+ /* pci bridge */
+ write_pirq_info(pirq_info, bus_sp5100[0], ((sbdn_sp5100 + 0x14) << 3) | 4,
+ 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
+ 0);
+ pirq_info++;
+
+
+
+ slot_num++;
+
+
+
+ pirq->size = 32 + 16 * slot_num;
+
+ for (i = 0; i < pirq->size; i++)
+ sum += v[i];
+
+ sum = pirq->checksum - sum;
+
+ if (sum != pirq->checksum) {
+ pirq->checksum = sum;
+ }
+
+ printk(BIOS_INFO, "write_pirq_routing_table done.\n");
+
+ return (unsigned long)pirq_info;
+
+}
diff --git a/src/mainboard/supermicro/h8qgi/mainboard.c b/src/mainboard/supermicro/h8qgi/mainboard.c
new file mode 100755
index 0000000..f00b5a0
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/mainboard.c
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include "southbridge/amd/sr5650/cmn.h"
+#include "chip.h"
+
+void set_pcie_dereset(void);
+void set_pcie_reset(void);
+
+/**
+ *
+ */
+void set_pcie_reset(void)
+{
+}
+
+/**
+ * Release Resets to PCIe Links
+ * PCIE_RESET_GPIO1,2,4,5
+ */
+void set_pcie_dereset(void)
+{
+ device_t pcie_core_dev;
+
+ pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+ set_htiu_enable_bits(pcie_core_dev, 0xA8, 0x07000707, 0x07000707);
+ set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x00000007, 0x00000007);
+}
+
+
+/*************************************************
+* enable the dedicated function in h8qgi board.
+*************************************************/
+static void h8qgi_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+}
+
+#if (CONFIG_HAVE_MAINBOARD_RESOURCES == 1)
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return 0;
+}
+#endif
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
+ .enable_dev = h8qgi_enable,
+};
diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c
new file mode 100755
index 0000000..4d32f39
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/mptable.c
@@ -0,0 +1,200 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/cpu.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/amd/amdfam10_sysconf.h>
+
+extern u8 bus_sr5650[14];
+extern u8 bus_sp5100[2];
+extern u32 bus_type[256];
+extern u32 sbdn_sr5650;
+extern u32 sbdn_sp5100;
+
+
+static void *smp_write_config_table(void *v)
+{
+ struct mp_config_table *mc;
+ int bus_isa;
+ u32 apicid_sp5100;
+ u32 apicid_sr5650;
+ device_t dev;
+ u32 dword;
+ u8 byte;
+
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+ mptable_init(mc, LAPIC_ADDR);
+
+ smp_write_processors(mc);
+ get_bus_conf();
+ mptable_write_buses(mc, NULL, &bus_isa);
+
+ /*
+ * AGESA v5 Apply apic enumeration rules
+ * For systems with >= 16 APICs, put the IO-APICs at 0..n and
+ * put the local-APICs at m..z
+ * For systems with < 16 APICs, put the Local-APICs at 0..n and
+ * put the IO-APICs at (n + 1)..z
+ */
+#if CONFIG_MAX_CPUS >= 16
+ apicid_sp5100 = 0x0;
+#else
+ apicid_sp5100 = CONFIG_MAX_CPUS + 1
+#endif
+ apicid_sr5650 = apicid_sp5100 + 1;
+
+ //bus_sp5100[0], TODO: why bus_sp5100[0] use same value of bus_sr5650[0] assigned by get_pci1234(), instead of 0.
+ dev = dev_find_slot(0, PCI_DEVFN(sbdn_sp5100 + 0x14, 0));
+ if (dev) {
+ /* Set SP5100 IOAPIC ID */
+ dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
+ smp_write_ioapic(mc, apicid_sp5100, 0x20, dword);
+
+ /* Initialize interrupt mapping */
+ /* aza */
+ byte = pci_read_config8(dev, 0x63);
+ byte &= 0xf8;
+ byte |= 0; /* 0: INTA, ...., 7: INTH */
+ pci_write_config8(dev, 0x63, byte);
+ /* SATA */
+ dword = pci_read_config32(dev, 0xAC);
+ dword &= ~(7 << 26);
+ dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
+ /* dword |= 1<<22; PIC and APIC co exists */
+ pci_write_config32(dev, 0xAC, dword);
+
+ /*
+ * 00:12.0: PROG SATA : INT F
+ * 00:13.0: INTA USB_0
+ * 00:13.1: INTB USB_1
+ * 00:13.2: INTC USB_2
+ * 00:13.3: INTD USB_3
+ * 00:13.4: INTC USB_4
+ * 00:13.5: INTD USB2
+ * 00:14.1: INTA IDE
+ * 00:14.2: Prog HDA : INT E
+ * 00:14.5: INTB ACI
+ * 00:14.6: INTB MCI
+ */
+
+ /* Set RS5650 IOAPIC ID */
+ dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+ if (dev) {
+ pci_write_config32(dev, 0xF8, 0x1);
+ dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
+ smp_write_ioapic(mc, apicid_sr5650, 0x20, dword);
+ }
+
+ }
+
+ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+#define IO_LOCAL_INT(type, intr, apicid, pin) \
+ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+
+ mptable_add_isa_interrupts(mc, bus_isa, apicid_sp5100, 0);
+
+ /* PCI interrupts are level triggered, and are
+ * associated with a specific bus/device/function tuple.
+ */
+#define PCI_INT(bus, dev, int_sign, pin) \
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sp5100, (pin))
+
+ /* SMBUS */
+ //PCI_INT(0x0, 0x14, 0x0, 0x10); //not generate interrupt, 3Ch hardcoded to 0
+
+ /* HD Audio */
+ PCI_INT(0x0, 0x14, 0x2, 0x10);
+
+ /* USB */
+ /* OHCI0, OHCI1 hard-wired to 01h, corresponding to using INTA# */
+ /* EHCI hard-wired to 02h, corresponding to using INTB# */
+ /* USB1 */
+ PCI_INT(0x0, 0x12, 0x0, 0x10); /* OHCI0 Port 0~2 */
+ PCI_INT(0x0, 0x12, 0x1, 0x10); /* OHCI1 Port 3~5 */
+ PCI_INT(0x0, 0x12, 0x2, 0x11); /* EHCI Port 0~5 */
+
+ /* USB2 */
+ PCI_INT(0x0, 0x13, 0x0, 0x10); /* OHCI0 Port 6~8 */
+ PCI_INT(0x0, 0x13, 0x1, 0x10); /* OHCI1 Port 9~11 */
+ PCI_INT(0x0, 0x13, 0x2, 0x11); /* EHCI Port 6~11 */
+
+ /* USB3 EHCI hard-wired to 03h, corresponding to using INTC# */
+ PCI_INT(0x0, 0x14, 0x5, 0x12); /* OHCI0 Port 12~13 */
+
+ /* SATA */
+ PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG
+
+ /* on board NIC & Slot PCIE. */
+ /* configuration B doesnt need dev 5,6,7 */
+ /*
+ * PCI_INT(bus_sr5650[0x5], 0x0, 0x0, 0x11);
+ * PCI_INT(bus_sr5650[0x6], 0x0, 0x0, 0x12);
+ * PCI_INT(bus_sr5650[0x7], 0x0, 0x0, 0x13);
+ */
+
+ //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 28); /* dev d */
+ //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[13], (((0)<<2)|(1)), apicid_sr5650, 0); /* card behind dev13 */
+
+ /* PCI slots */
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14);
+ PCI_INT(bus_sp5100[1], 0x5, 0x1, 0x15);
+ PCI_INT(bus_sp5100[1], 0x5, 0x2, 0x16);
+ PCI_INT(bus_sp5100[1], 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_sp5100[1], 0x6, 0x0, 0x15);
+ PCI_INT(bus_sp5100[1], 0x6, 0x1, 0x16);
+ PCI_INT(bus_sp5100[1], 0x6, 0x2, 0x17);
+ PCI_INT(bus_sp5100[1], 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_sp5100[1], 0x7, 0x0, 0x16);
+ PCI_INT(bus_sp5100[1], 0x7, 0x1, 0x17);
+ PCI_INT(bus_sp5100[1], 0x7, 0x2, 0x14);
+ PCI_INT(bus_sp5100[1], 0x7, 0x3, 0x15);
+
+
+ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
+ IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
+ /* There is no extension information... */
+
+ /* Compute the checksums */
+ mc->mpe_checksum =
+ smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+ mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+ printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
+ mc, smp_next_mpe_entry(mc));
+ return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr);
+ return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/supermicro/h8qgi/platform_oem.c b/src/mainboard/supermicro/h8qgi/platform_oem.c
new file mode 100755
index 0000000..f36b0d8
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/platform_oem.c
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "heapManager.h"
+#include "platform_oem.h"
+#include "Filecode.h"
+
+#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * OemCustomizeInitEarly
+ *
+ * Description:
+ * This is the stub function will call the host environment through the binary block
+ * interface (call-out port) to provide a user hook opportunity
+ *
+ * Parameters:
+ * @param[in] **PeiServices
+ * @param[in] *InitEarly
+ *
+ * @retval VOID
+ *
+ **/
+/*---------------------------------------------------------------------------------------*/
+VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
+{
+ //InitEarly->PlatformConfig.CoreLevelingMode = CORE_LEVEL_TWO;
+}
+
diff --git a/src/mainboard/supermicro/h8qgi/platform_oem.h b/src/mainboard/supermicro/h8qgi/platform_oem.h
new file mode 100755
index 0000000..ab0d6df
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/platform_oem.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _PLATFORM_OEM_H_
+#define _PLATFORM_OEM_H_
+
+#include "Porting.h"
+#include "AGESA.h"
+#include "amdlib.h"
+
+VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly);
+
+#endif //_PLATFORM_OEM_H_
diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c
new file mode 100755
index 0000000..08b0eb2
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/romstage.c
@@ -0,0 +1,132 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <lib.h>
+#include <reset.h>
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <arch/cpu.h>
+#include <console/console.h>
+#include <arch/stages.h>
+#include "cpu/x86/bist.h"
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "agesawrapper.h"
+#include "northbridge/amd/agesa/family10/reset_test.h"
+#include "southbridge/amd/sr5650/sr5650.h"
+#include "southbridge/amd/sb700/sb700.h"
+#include "superio/nuvoton/wpcm450/wpcm450.h"
+
+extern void disable_cache_as_ram(void); /* cache_as_ram.inc */
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+ u32 val;
+
+ agesawrapper_amdinitmmio();
+ if (!cpu_init_detectedx && boot_cpu()) {
+ post_code(0x30);
+ /* SR56x0 pcie bridges block pci_locate_device() before pcie training.
+ * disable all pcie bridges on SR56x0 to work around it
+ */
+ sr5650_disable_pcie_bridge();
+ post_code(0x31);
+ sb7xx_51xx_lpc_port80();
+ post_code(0x32);
+ }
+
+ /* Halt if there was a built in self test failure */
+ post_code(0x33);
+ report_bist_failure(bist);
+
+ enable_sr5650_dev8();
+ sb7xx_51xx_lpc_init();
+ sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */
+ wpcm450_enable_dev(WPCM450_SP1, CONFIG_SIO_PORT, CONFIG_TTYS0_BASE);
+ sb7xx_51xx_disable_wideio(0);
+ post_code(0x34);
+
+ uart_init();
+ post_code(0x35);
+ console_init();
+
+ val = cpuid_eax(1);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+
+ post_code(0x37);
+ val = agesawrapper_amdinitreset();
+ if (val) {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
+ } else {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitreset passed\n");
+ }
+
+ post_code(0x38);
+ val = agesawrapper_amdinitearly();
+ if(val) {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
+ } else {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitearly passed\n");
+ }
+
+ sr5650_early_setup();
+ post_code(0x39);
+
+ sb7xx_51xx_early_setup();
+ sr5650_htinit();
+ /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
+ if (!warm_reset_detect(0)) {
+ print_info("...WARM RESET...\n\n\n");
+ distinguish_cpu_resets(0);
+ soft_reset();
+ die("After soft_reset_x - shouldn't see this message!!!\n");
+ }
+
+ post_code(0x40);
+ val = agesawrapper_amdinitpost();
+ if (val) {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
+ }
+ printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n");
+
+ post_code(0x41);
+ val = agesawrapper_amdinitenv();
+ if(val) {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
+ }
+ printk(BIOS_DEBUG, "agesawrapper_amdinitenv passed\n");
+
+ post_code(0x42);
+ sr5650_before_pci_init();
+ sb7xx_51xx_before_pci_init();
+
+ post_code(0x50);
+ print_debug("Disabling cache as ram ");
+ disable_cache_as_ram();
+ print_debug("done\n");
+
+ post_code(0x51);
+ copy_and_run(0);
+
+ /* We will not return, Should never see this message and post code. */
+ print_debug("should not be here -\n");
+ post_code(0x54);
+}
+
1
0
Frank Vibrans III (frank.vibrans(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/107
-gerrit
commit 68af5f681f9af7a769c62554130f8122c00c55de
Author: efdesign98 <efdesign98(a)gmail.com>
Date: Wed Jul 20 12:37:58 2011 -0600
Update AMD SR5650 and SB700
This updates the code for the AMD SR5650 and SB700 southbridges.
Among other things, it changes the romstage.c files by replacing a
.C file include with a pair of .H file includes. The .C file is
now added to the romstage in the SB700 or SR5650 Makefile.inc.
file to the romstage and ramstage elements. This particular change
affects all mainboards that use the SB700, and their changes are
include herein. These mainboards are:
Advansus a785e,
AMD Mahogany, Mahogany-fam10, Tilapia-fam10,
Asrock 939a785gmh,
Asus m4a78-em, m4a785-m,
Gigabyte ma785gm,
Iei Kino-780am2-fam10
Jetway pa78vm5
Supermicro h8scm_fam10
The nuvoton/wpcm450 earlysetup interface is changed because the file
is no longer included in the mainboard romstage.c files.
Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33
Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com>
Signed-off-by: efdesign98 <efdesign98(a)gmail.com>
---
src/cpu/amd/car/post_cache_as_ram.c | 1 +
src/mainboard/advansus/a785e-i/Makefile.inc | 15 +-
src/mainboard/amd/inagua/Makefile.inc | 4 +
src/mainboard/amd/mahogany/mainboard.c | 5 +-
src/mainboard/amd/mahogany/romstage.c | 5 +-
src/mainboard/amd/mahogany_fam10/mainboard.c | 5 +-
src/mainboard/amd/mahogany_fam10/romstage.c | 6 +-
src/mainboard/amd/tilapia_fam10/Kconfig | 9 +
src/mainboard/amd/tilapia_fam10/mainboard.c | 7 +-
src/mainboard/amd/tilapia_fam10/romstage.c | 5 +-
src/mainboard/asrock/939a785gmh/mainboard.c | 5 +-
src/mainboard/asrock/939a785gmh/romstage.c | 7 +-
src/mainboard/asus/m4a78-em/mainboard.c | 10 +-
src/mainboard/asus/m4a78-em/romstage.c | 5 +-
src/mainboard/asus/m4a785-m/mainboard.c | 9 +-
src/mainboard/asus/m4a785-m/romstage.c | 5 +-
src/mainboard/gigabyte/ma785gmt/mainboard.c | 9 +-
src/mainboard/gigabyte/ma785gmt/romstage.c | 5 +-
src/mainboard/gigabyte/ma78gm/mainboard.c | 5 +-
src/mainboard/gigabyte/ma78gm/romstage.c | 5 +-
src/mainboard/iei/kino-780am2-fam10/mainboard.c | 5 +-
src/mainboard/iei/kino-780am2-fam10/romstage.c | 5 +-
src/mainboard/jetway/pa78vm5/mainboard.c | 5 +-
src/mainboard/jetway/pa78vm5/romstage.c | 5 +-
src/mainboard/supermicro/h8scm_fam10/Kconfig | 2 -
src/mainboard/supermicro/h8scm_fam10/Makefile.inc | 21 +++
src/mainboard/supermicro/h8scm_fam10/mainboard.c | 37 +----
src/mainboard/supermicro/h8scm_fam10/romstage.c | 15 +-
src/northbridge/amd/amdk8/reset_test.c | 3 +-
src/southbridge/amd/sb700/Makefile.inc | 5 +
src/southbridge/amd/sb700/early_setup.c | 44 ++---
src/southbridge/amd/sb700/pmio.c | 55 ++++++
src/southbridge/amd/sb700/pmio.h | 34 ++++
src/southbridge/amd/sb700/reset.c | 46 +++++-
src/southbridge/amd/sb700/sata.c | 2 +-
src/southbridge/amd/sb700/sb700.h | 10 +
src/southbridge/amd/sb700/sm.c | 28 +++-
src/southbridge/amd/sb700/smbus.c | 89 +++++-----
src/southbridge/amd/sb700/smbus.h | 10 +-
src/southbridge/amd/sb700/usb.c | 1 +
src/southbridge/amd/sr5650/Makefile.inc | 2 +
src/southbridge/amd/sr5650/cmn.h | 10 +-
src/southbridge/amd/sr5650/early_setup.c | 196 ++++++++++----------
src/southbridge/amd/sr5650/pcie.c | 86 +++++++--
src/southbridge/amd/sr5650/sr5650.c | 25 ++-
src/southbridge/amd/sr5650/sr5650.h | 7 +-
src/superio/nuvoton/wpcm450/early_init.c | 4 +-
src/superio/nuvoton/wpcm450/wpcm450.h | 2 +
src/vendorcode/amd/agesa/f14/Lib/amdlib.c | 24 ++--
49 files changed, 557 insertions(+), 348 deletions(-)
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index e8f0c92..270c542 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -4,6 +4,7 @@
#include <string.h>
#include <arch/stages.h>
#include <cpu/x86/mtrr.h>
+#include "cbmem.h"
#include "cpu/amd/car/disable_cache_as_ram.c"
#include "cpu/x86/mtrr/earlymtrr.c"
diff --git a/src/mainboard/advansus/a785e-i/Makefile.inc b/src/mainboard/advansus/a785e-i/Makefile.inc
old mode 100644
new mode 100755
index a81d135..cf8ec26
--- a/src/mainboard/advansus/a785e-i/Makefile.inc
+++ b/src/mainboard/advansus/a785e-i/Makefile.inc
@@ -6,14 +6,15 @@ ramstage-y += pmio.c
#SB800 CIMx share AGESA V5 lib code
ifneq ($(CONFIG_AMD_AGESA),y)
- romstage-y += ../../../vendorcode/amd/agesa/f14/Lib/amdlib.c
- ramstage-y += ../../../vendorcode/amd/agesa/f14/Lib/amdlib.c
+ AGESA_ROOT ?= src/vendorcode/amd/agesa/f14
+ romstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c
+ ramstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c
- AGESA_INC := -Isrc/vendorcode/amd/agesa/f14/ \
- -Isrc/vendorcode/amd/agesa/f14/Include \
- -Isrc/vendorcode/amd/agesa/f14/Proc/IDS/ \
- -Isrc/vendorcode/amd/agesa/f14/Proc/CPU/ \
- -Isrc/vendorcode/amd/agesa/f14/Proc/CPU/Family
+ AGESA_INC := -I$(AGESA_ROOT)/ \
+ -I$(AGESA_ROOT)/Include \
+ -I$(AGESA_ROOT)/Proc/IDS/ \
+ -I$(AGESA_ROOT)/Proc/CPU/ \
+ -I$(AGESA_ROOT)/Proc/CPU/Family
CFLAGS += $(AGESA_INC)
endif
diff --git a/src/mainboard/amd/inagua/Makefile.inc b/src/mainboard/amd/inagua/Makefile.inc
old mode 100644
new mode 100755
index 88af2b7..564d196
--- a/src/mainboard/amd/inagua/Makefile.inc
+++ b/src/mainboard/amd/inagua/Makefile.inc
@@ -31,3 +31,7 @@ ramstage-y += PlatformGnbPcie.c
ramstage-y += reset.c
ramstage-y += pmio.c
+
+AGESA_ROOT ?= src/vendorcode/amd/agesa/f14
+subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += ../../../../$(AGESA_ROOT)
+#subdirs-$(CONFIG_AMD_CIMX) += ../../../vendorcode/amd/cimx
diff --git a/src/mainboard/amd/mahogany/mainboard.c b/src/mainboard/amd/mahogany/mainboard.c
index 9d471d0..0ccef10 100644
--- a/src/mainboard/amd/mahogany/mainboard.c
+++ b/src/mainboard/amd/mahogany/mainboard.c
@@ -25,11 +25,10 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
-#include <southbridge/amd/sb700/sb700.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "chip.h"
-#define SMBUS_IO_BASE 0x6000
-
uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c
index b4c9635..5c9d538 100644
--- a/src/mainboard/amd/mahogany/romstage.c
+++ b/src/mainboard/amd/mahogany/romstage.c
@@ -44,7 +44,8 @@
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
-#include "southbridge/amd/sb700/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */
static void memreset(int controllers, const struct mem_controller *ctrl) { }
@@ -52,7 +53,7 @@ static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(u32 device, u32 address)
{
- return smbus_read_byte(device, address);
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdk8/amdk8.h"
diff --git a/src/mainboard/amd/mahogany_fam10/mainboard.c b/src/mainboard/amd/mahogany_fam10/mainboard.c
index 7ed615d..2cbeaf1 100644
--- a/src/mainboard/amd/mahogany_fam10/mainboard.c
+++ b/src/mainboard/amd/mahogany_fam10/mainboard.c
@@ -25,11 +25,10 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
-#include <southbridge/amd/sb700/sb700.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "chip.h"
-#define SMBUS_IO_BASE 0x6000
-
uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 680e60d..4d26ca3 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -48,7 +48,8 @@
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
-#include "southbridge/amd/sb700/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdfam10/debug.c"
#include <spd.h>
@@ -56,7 +57,7 @@ static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
- return smbus_read_byte(device, address);
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
@@ -73,7 +74,6 @@ static int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
-#include "southbridge/amd/sb700/early_setup.c"
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
diff --git a/src/mainboard/amd/tilapia_fam10/Kconfig b/src/mainboard/amd/tilapia_fam10/Kconfig
old mode 100644
new mode 100755
index b18115b..e9d6081
--- a/src/mainboard/amd/tilapia_fam10/Kconfig
+++ b/src/mainboard/amd/tilapia_fam10/Kconfig
@@ -83,4 +83,13 @@ config RAMBASE
hex
default 0x200000
+config VGA_BIOS
+ bool
+ default n
+
+config VGA_BIOS_ID
+ string
+ depends on VGA_BIOS
+ default "1002,9615"
+
endif # BOARD_AMD_TILAPIA_FAM10
diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c
old mode 100644
new mode 100755
index 84ff928..357bdac
--- a/src/mainboard/amd/tilapia_fam10/mainboard.c
+++ b/src/mainboard/amd/tilapia_fam10/mainboard.c
@@ -26,15 +26,12 @@
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include <southbridge/amd/sb700/sb700.h>
+#include "southbridge/amd/sb700/smbus.h"
#include "chip.h"
#define ADT7461_ADDRESS 0x4C
#define ARA_ADDRESS 0x0C /* Alert Response Address */
-extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
-extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
- u8 val);
-
#define ADT7461_read_byte(address) \
do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
#define ARA_read_byte(address) \
@@ -42,8 +39,6 @@ extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
#define ADT7461_write_byte(address, val) \
do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
-#define SMBUS_IO_BASE 0x6000
-
uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
old mode 100644
new mode 100755
index 3a85a15..48b13be
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -48,14 +48,15 @@
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
-#include "southbridge/amd/sb700/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdfam10/debug.c"
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
- return smbus_read_byte(device, address);
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
diff --git a/src/mainboard/asrock/939a785gmh/mainboard.c b/src/mainboard/asrock/939a785gmh/mainboard.c
index 1cf1731..945a19f 100644
--- a/src/mainboard/asrock/939a785gmh/mainboard.c
+++ b/src/mainboard/asrock/939a785gmh/mainboard.c
@@ -25,11 +25,10 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
-#include <southbridge/amd/sb700/sb700.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "chip.h"
-#define SMBUS_IO_BASE 0x6000
-
uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c
index b0ae247..bd45c16 100644
--- a/src/mainboard/asrock/939a785gmh/romstage.c
+++ b/src/mainboard/asrock/939a785gmh/romstage.c
@@ -45,7 +45,8 @@
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
-#include "southbridge/amd/sb700/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */
#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
@@ -56,7 +57,7 @@ static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(u32 device, u32 address)
{
- return smbus_read_byte(device, address);
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdk8/amdk8.h"
@@ -101,7 +102,7 @@ static void sio_init(void)
pnp_write_config(GPIO2345_DEV, 0xe4, 0x0e); /* data */
pnp_write_config(GPIO2345_DEV, 0xe5, 0x00); /* No inversion */
- /* GPIO30 - unknown output, set to 0
+ /* GPIO30 - unknown output, set to 0
GPI31 - unknown input NC?
GPI32 - unknown input NC?
GPIO33 - unknown output, set to 0.
diff --git a/src/mainboard/asus/m4a78-em/mainboard.c b/src/mainboard/asus/m4a78-em/mainboard.c
index 910fce1..6042d07 100644
--- a/src/mainboard/asus/m4a78-em/mainboard.c
+++ b/src/mainboard/asus/m4a78-em/mainboard.c
@@ -24,17 +24,11 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
-#include <southbridge/amd/sb700/sb700.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "chip.h"
-extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
-extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
- u8 val);
-
-
-#define SMBUS_IO_BASE 0x6000
-
uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index 0675ee6..b14a7c6 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -48,14 +48,15 @@
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
-#include "southbridge/amd/sb700/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdfam10/debug.c"
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
- return smbus_read_byte(device, address);
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c
index a5a15e8..e490f31 100644
--- a/src/mainboard/asus/m4a785-m/mainboard.c
+++ b/src/mainboard/asus/m4a785-m/mainboard.c
@@ -24,16 +24,13 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
-#include <southbridge/amd/sb700/sb700.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "chip.h"
#define ADT7461_ADDRESS 0x4C
#define ARA_ADDRESS 0x0C /* Alert Response Address */
-extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
-extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
- u8 val);
-
#define ADT7461_read_byte(address) \
do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
#define ARA_read_byte(address) \
@@ -41,8 +38,6 @@ extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
#define ADT7461_write_byte(address, val) \
do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
-#define SMBUS_IO_BASE 0x6000
-
uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 0675ee6..b14a7c6 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -48,14 +48,15 @@
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
-#include "southbridge/amd/sb700/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdfam10/debug.c"
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
- return smbus_read_byte(device, address);
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
diff --git a/src/mainboard/gigabyte/ma785gmt/mainboard.c b/src/mainboard/gigabyte/ma785gmt/mainboard.c
index d6c95e0..768c9e1 100644
--- a/src/mainboard/gigabyte/ma785gmt/mainboard.c
+++ b/src/mainboard/gigabyte/ma785gmt/mainboard.c
@@ -25,16 +25,13 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
-#include <southbridge/amd/sb700/sb700.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "chip.h"
#define ADT7461_ADDRESS 0x4C
#define ARA_ADDRESS 0x0C /* Alert Response Address */
-extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
-extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
- u8 val);
-
#define ADT7461_read_byte(address) \
do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
#define ARA_read_byte(address) \
@@ -42,8 +39,6 @@ extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
#define ADT7461_write_byte(address, val) \
do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
-#define SMBUS_IO_BASE 0x6000
-
uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index 8f3f55d..fcf023b 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -44,14 +44,15 @@
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
-#include "southbridge/amd/sb700/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdfam10/debug.c"
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
- return smbus_read_byte(device, address);
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
diff --git a/src/mainboard/gigabyte/ma78gm/mainboard.c b/src/mainboard/gigabyte/ma78gm/mainboard.c
index dcb3799..1a00af6 100644
--- a/src/mainboard/gigabyte/ma78gm/mainboard.c
+++ b/src/mainboard/gigabyte/ma78gm/mainboard.c
@@ -26,11 +26,10 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
-#include <southbridge/amd/sb700/sb700.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "chip.h"
-#define SMBUS_IO_BASE 0x6000
-
uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index c34fa5b..80b8d90 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -48,14 +48,15 @@
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
-#include "southbridge/amd/sb700/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdfam10/debug.c"
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
- return smbus_read_byte(device, address);
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
diff --git a/src/mainboard/iei/kino-780am2-fam10/mainboard.c b/src/mainboard/iei/kino-780am2-fam10/mainboard.c
index 379efe5..4d0cd09 100644
--- a/src/mainboard/iei/kino-780am2-fam10/mainboard.c
+++ b/src/mainboard/iei/kino-780am2-fam10/mainboard.c
@@ -25,11 +25,10 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
-#include <southbridge/amd/sb700/sb700.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "chip.h"
-#define SMBUS_IO_BASE 0x6000
-
uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index 192b47a..58b1845 100644
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -48,7 +48,8 @@
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
-#include "southbridge/amd/sb700/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdfam10/debug.c"
#define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1)
@@ -57,7 +58,7 @@ static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
- return smbus_read_byte(device, address);
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
diff --git a/src/mainboard/jetway/pa78vm5/mainboard.c b/src/mainboard/jetway/pa78vm5/mainboard.c
index 188cadf..6d0ceba 100644
--- a/src/mainboard/jetway/pa78vm5/mainboard.c
+++ b/src/mainboard/jetway/pa78vm5/mainboard.c
@@ -26,11 +26,10 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
-#include <southbridge/amd/sb700/sb700.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "chip.h"
-#define SMBUS_IO_BASE 0x6000
-
uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index 4ffcade..11bda6a 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -49,7 +49,8 @@
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
-#include "southbridge/amd/sb700/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdfam10/debug.c"
#if CONFIG_TTYS0_BASE == 0x2f8
@@ -62,7 +63,7 @@ static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
- return smbus_read_byte(device, address);
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
diff --git a/src/mainboard/supermicro/h8scm_fam10/Kconfig b/src/mainboard/supermicro/h8scm_fam10/Kconfig
old mode 100644
new mode 100755
index e0547ab..7742133
--- a/src/mainboard/supermicro/h8scm_fam10/Kconfig
+++ b/src/mainboard/supermicro/h8scm_fam10/Kconfig
@@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_OPTION_TABLE
select GENERATE_PIRQ_TABLE
select GENERATE_MP_TABLE
- select HAVE_MAINBOARD_RESOURCES
select HAVE_HARD_RESET
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select LIFT_BSP_APIC_ID
@@ -24,7 +23,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select BOARD_ROMSIZE_KB_2048
select RAMINIT_SYSINFO
select ENABLE_APIC_EXT_ID
- select GFXUMA
config MAINBOARD_DIR
string
diff --git a/src/mainboard/supermicro/h8scm_fam10/Makefile.inc b/src/mainboard/supermicro/h8scm_fam10/Makefile.inc
new file mode 100755
index 0000000..4f60aac
--- /dev/null
+++ b/src/mainboard/supermicro/h8scm_fam10/Makefile.inc
@@ -0,0 +1,21 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+romstage-y += ../../../superio/nuvoton/wpcm450/early_init.c
+
diff --git a/src/mainboard/supermicro/h8scm_fam10/mainboard.c b/src/mainboard/supermicro/h8scm_fam10/mainboard.c
old mode 100644
new mode 100755
index e6ed22b..90b5335
--- a/src/mainboard/supermicro/h8scm_fam10/mainboard.c
+++ b/src/mainboard/supermicro/h8scm_fam10/mainboard.c
@@ -29,9 +29,6 @@
#include <southbridge/amd/sr5650/cmn.h>
#include "chip.h"
-#define SMBUS_IO_BASE 0x6000
-
-uint64_t uma_memory_base, uma_memory_size;
void set_pcie_reset(void);
void set_pcie_dereset(void);
@@ -95,47 +92,17 @@ static void h8scm_enable(device_t dev)
printk
(BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
__func__, msr2.lo, msr2.hi);
-#if (CONFIG_GFXUMA == 1)
-
- /* refer to UMA Size Consideration in 780 BDG. */
- switch (msr.lo) {
- case 0x10000000: /* 256M system memory */
- uma_memory_size = 0x4000000; /* 64M recommended UMA */
- break;
-
- case 0x20000000: /* 512M system memory */
- uma_memory_size = 0x8000000; /* 128M recommended UMA */
- break;
-
- default: /* 1GB and above system memory */
- uma_memory_size = 0x10000000; /* 256M recommended UMA */
- break;
- }
-#else
- /* TODO: TOP_MEM2 */
- uma_memory_size = 0;//0x8000000; /* 128M recommended UMA */
-#endif
- uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */
- printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
- __func__, uma_memory_size, uma_memory_base);
set_pcie_dereset();
/* get_ide_dma66(); */
}
+#if (CONFIG_HAVE_MAINBOARD_RESOURCES == 1)
int add_mainboard_resources(struct lb_memory *mem)
{
- /* UMA is removed from system memory in the northbridge code, but
- * in some circumstances we want the memory mentioned as reserved.
- */
-#if (CONFIG_GFXUMA == 1)
- printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
- uma_memory_base, uma_memory_size);
- lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
- uma_memory_size);
-#endif
return 0;
}
+#endif
struct chip_operations mainboard_ops = {
CHIP_NAME("AMD H8SCM Mainboard")
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
old mode 100644
new mode 100755
index 8101d2f..6e6e394
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -42,13 +42,14 @@
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
-#include "superio/nuvoton/wpcm450/early_init.c"
#include <usbdebug.h>
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/amd/sb700/early_setup.c"
-#include "southbridge/amd/sr5650/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
+#include "southbridge/amd/sr5650/sr5650.h"
+#include "superio/nuvoton/wpcm450/wpcm450.h"
#include "northbridge/amd/amdfam10/debug.c"
static void activate_spd_rom(const struct mem_controller *ctrl)
@@ -57,7 +58,7 @@ static void activate_spd_rom(const struct mem_controller *ctrl)
static int spd_read_byte(u32 device, u32 address)
{
- return smbus_read_byte(device, address);
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
@@ -102,7 +103,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
- disable_pcie_bridge();
+ /* SR56x0 pcie bridges block pci_locate_device() before pcie training.
+ * disable all pcie bridges on SR56x0 to work around it
+ */
+ sr5650_disable_pcie_bridge();
sb7xx_51xx_lpc_port80();
}
@@ -181,7 +185,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* run _early_setup before soft-reset. */
sr5650_early_setup();
- disable_pcie_bridge();
sb7xx_51xx_early_setup();
#if CONFIG_SET_FIDVID
diff --git a/src/northbridge/amd/amdk8/reset_test.c b/src/northbridge/amd/amdk8/reset_test.c
index b775813..bee3faa 100644
--- a/src/northbridge/amd/amdk8/reset_test.c
+++ b/src/northbridge/amd/amdk8/reset_test.c
@@ -44,7 +44,8 @@ static inline void distinguish_cpu_resets(unsigned nodeid)
pci_write_config32(device, HT_INIT_CONTROL, htic);
}
-static void set_bios_reset(void)
+void __attribute__ ((weak)) set_bios_reset(void);
+void __attribute__ ((weak)) set_bios_reset(void)
{
u32 htic;
htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
diff --git a/src/southbridge/amd/sb700/Makefile.inc b/src/southbridge/amd/sb700/Makefile.inc
old mode 100644
new mode 100755
index 8e8e029..e174e8b
--- a/src/southbridge/amd/sb700/Makefile.inc
+++ b/src/southbridge/amd/sb700/Makefile.inc
@@ -1,11 +1,16 @@
driver-y += sb700.c
driver-y += usb.c
driver-y += lpc.c
+driver-y += smbus.c
driver-y += sm.c
driver-y += ide.c
driver-y += sata.c
driver-y += hda.c
driver-y += pci.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c
+romstage-y += reset.c
ramstage-y += reset.c
romstage-y += enable_usbdebug.c
+
+romstage-y += early_setup.c
+romstage-y += smbus.c
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
old mode 100644
new mode 100755
index a5e76c7..1f46da2
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -20,14 +20,19 @@
#ifndef _SB700_EARLY_SETUP_C_
#define _SB700_EARLY_SETUP_C_
+#include <stdint.h>
+#include <arch/cpu.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+
#include <reset.h>
#include <arch/cpu.h>
#include <cbmem.h>
#include "sb700.h"
-#include "smbus.c"
+#include "smbus.h"
-#define SMBUS_IO_BASE 0x6000 /* Is it a temporary SMBus I/O base address? */
- /*SIZE 0x40 */
static void pmio_write(u8 reg, u8 value)
{
@@ -129,7 +134,7 @@ static u8 set_sb700_revision(void)
* Console output through any port besides 0x3f8 is unsupported.
* If you use FWH ROMs, you have to setup IDSEL.
***************************************/
-static void sb7xx_51xx_lpc_init(void)
+void sb7xx_51xx_lpc_init(void)
{
u8 reg8;
u32 reg32;
@@ -216,7 +221,7 @@ void sb7xx_51xx_disable_wideio(u8 wio_index)
}
/* what is its usage? */
-static u32 get_sbdn(u32 bus)
+u32 __attribute__ ((weak)) get_sbdn(u32 bus)
{
device_t dev;
@@ -233,7 +238,7 @@ static u8 dual_core(void)
/*
* RPR 2.4 C-state and VID/FID change for the K8 platform.
*/
-static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
+void __attribute__((weak)) enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
{
u8 byte;
byte = pmio_read(0x9a);
@@ -284,22 +289,6 @@ static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
pmio_write(0x67, 0x6);
}
-void hard_reset(void)
-{
- set_bios_reset();
-
- /* full reset */
- outb(0x0a, 0x0cf9);
- outb(0x0e, 0x0cf9);
-}
-
-void soft_reset(void)
-{
- set_bios_reset();
- /* link reset */
- outb(0x06, 0x0cf9);
-}
-
void sb7xx_51xx_pci_port80(void)
{
u8 byte;
@@ -681,7 +670,7 @@ static void sb700_por_init(void)
/*
* It should be called during early POST after memory detection and BIOS shadowing but before PCI bus enumeration.
*/
-static void sb7xx_51xx_before_pci_init(void)
+void sb7xx_51xx_before_pci_init(void)
{
sb700_pci_cfg();
}
@@ -689,18 +678,13 @@ static void sb7xx_51xx_before_pci_init(void)
/*
* This function should be called after enable_sb700_smbus().
*/
-static void sb7xx_51xx_early_setup(void)
+void sb7xx_51xx_early_setup(void)
{
printk(BIOS_INFO, "sb700_early_setup()\n");
sb700_por_init();
sb700_acpi_init();
}
-static int smbus_read_byte(u32 device, u32 address)
-{
- return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
-}
-
int s3_save_nvram_early(u32 dword, int size, int nvram_pos)
{
int i;
@@ -732,7 +716,7 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
}
#if CONFIG_HAVE_ACPI_RESUME == 1
-static int acpi_is_wakeup_early(void)
+int acpi_is_wakeup_early(void)
{
u16 tmp;
tmp = inw(ACPI_PM1_CNT_BLK);
diff --git a/src/southbridge/amd/sb700/pmio.c b/src/southbridge/amd/sb700/pmio.c
new file mode 100755
index 0000000..baded54
--- /dev/null
+++ b/src/southbridge/amd/sb700/pmio.c
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#include <arch/io.h> /*inb, outb*/
+#include "pmio.h"
+
+static void pmio_write_index(u16 port_base, u8 reg, u8 value)
+{
+ outb(reg, port_base);
+ outb(value, port_base + 1);
+}
+
+static u8 pmio_read_index(u16 port_base, u8 reg)
+{
+ outb(reg, port_base);
+ return inb(port_base + 1);
+}
+
+void pm_iowrite(u8 reg, u8 value)
+{
+ pmio_write_index(PM_INDEX, reg, value);
+}
+
+u8 pm_ioread(u8 reg)
+{
+ return pmio_read_index(PM_INDEX, reg);
+}
+
+void pm2_iowrite(u8 reg, u8 value)
+{
+ pmio_write_index(PM2_INDEX, reg, value);
+}
+
+u8 pm2_ioread(u8 reg)
+{
+ return pmio_read_index(PM2_INDEX, reg);
+}
+
diff --git a/src/southbridge/amd/sb700/pmio.h b/src/southbridge/amd/sb700/pmio.h
new file mode 100755
index 0000000..207fdc2
--- /dev/null
+++ b/src/southbridge/amd/sb700/pmio.h
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#ifndef _PMIO_H_
+#define _PMIO_H_
+
+#define PM_INDEX 0xCD6
+#define PM_DATA 0xCD7
+#define PM2_INDEX 0xCD0
+#define PM2_DATA 0xCD1
+
+void pm_iowrite(u8 reg, u8 value);
+u8 pm_ioread(u8 reg);
+void pm2_iowrite(u8 reg, u8 value);
+u8 pm2_ioread(u8 reg);
+
+#endif
diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c
old mode 100644
new mode 100755
index 32ee66b..27ca32e
--- a/src/southbridge/amd/sb700/reset.c
+++ b/src/southbridge/amd/sb700/reset.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ * Copyright (C) 2010 - 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,17 +17,51 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <reset.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
+#include <reset.h> /* hard_reset, soft_rest*/
+#include <arch/io.h> /* inb, outb */
+#include <arch/romcc_io.h> /* pci_read_config32, device_t, PCI_DEV */
-#include "../../../northbridge/amd/amdk8/reset_test.c"
+#define HT_INIT_CONTROL 0x6C
+#define HTIC_BIOSR_Detect (1<<5)
+
+#if CONFIG_MAX_PHYSICAL_CPUS > 32
+#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
+#else
+#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
+#endif
+
+static void set_bios_reset(void)
+{
+ u32 nodes;
+ u32 htic;
+ device_t dev;
+ int i;
+
+ nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
+ for(i = 0; i < nodes; i++) {
+ dev = NODE_PCI(i, 0);
+ htic = pci_read_config32(dev, HT_INIT_CONTROL);
+ htic &= ~HTIC_BIOSR_Detect;
+ pci_write_config32(dev, HT_INIT_CONTROL, htic);
+ }
+}
void hard_reset(void)
{
set_bios_reset();
+
/* Try rebooting through port 0xcf9 */
- /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
+ /* Actually it is not a real hard_reset
+ * --- it only reset coherent link table, but not reset link freq and width
+ */
outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
}
+
+void soft_reset(void)
+{
+ set_bios_reset();
+ /* link reset */
+ outb(0x06, 0x0cf9);
+}
+
diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c
old mode 100644
new mode 100755
index 89eba4b..411baf5
--- a/src/southbridge/amd/sb700/sata.c
+++ b/src/southbridge/amd/sb700/sata.c
@@ -280,7 +280,7 @@ static void sata_init(struct device *dev)
}
static struct pci_operations lops_pci = {
- /* .set_subsystem = pci_dev_set_subsystem, */
+ .set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations sata_ops = {
diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h
old mode 100644
new mode 100755
index 60eea47..794dd96
--- a/src/southbridge/amd/sb700/sb700.h
+++ b/src/southbridge/amd/sb700/sb700.h
@@ -63,8 +63,11 @@ void sb7xx_51xx_enable(device_t dev);
#ifdef __PRE_RAM__
void sb7xx_51xx_lpc_port80(void);
void sb7xx_51xx_pci_port80(void);
+void sb7xx_51xx_lpc_init(void);
void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base);
void sb7xx_51xx_disable_wideio(u8 wio_index);
+void sb7xx_51xx_early_setup(void);
+void sb7xx_51xx_before_pci_init(void);
#else
#include <device/pci.h>
/* allow override in mainboard.c */
@@ -72,8 +75,15 @@ void sb7xx_51xx_setup_sata_phys(struct device *dev);
#endif
+#if CONFIG_HAVE_ACPI_RESUME == 1
+int acpi_is_wakeup_early(void);
+#endif
+
int s3_save_nvram_early(u32 dword, int size, int nvram_pos);
int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
void enable_usbdebug(unsigned int port);
+
+u32 __attribute__ ((weak)) get_sbdn(u32 bus);
+void __attribute__((weak)) enable_fid_change_on_sb(u32 sbbusn, u32 sbdn);
#endif /* SB700_H */
diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c
old mode 100644
new mode 100755
index 7d341df..05065b6
--- a/src/southbridge/amd/sb700/sm.c
+++ b/src/southbridge/amd/sb700/sm.c
@@ -30,7 +30,7 @@
#include <arch/ioapic.h>
#include <stdlib.h>
#include "sb700.h"
-#include "smbus.c"
+#include "smbus.h"
#define NMI_OFF 0
@@ -95,6 +95,20 @@ static void sm_init(device_t dev)
byte |= 4 << 2; /* set NumSerIrqBits=4 */
pci_write_config8(dev, 0x69, byte);
+ /* Sx State Settings
+ * Note: These 2 registers need to be set correctly for the S-state
+ * to work properly. Otherwise the system may hang during resume
+ * from the S-state.
+ */
+ /*Use 8us clock for delays in the S-state resume timing sequence.*/
+ byte = pm_ioread(0x65);
+ byte &= ~(1 << 7);
+ pm_iowrite(0x65, byte);
+ /* Delay the APIC interrupt to the CPU until the system has fully resumed from the S-state. */
+ byte = pm_ioread(0x68);
+ byte |= 1 << 2;
+ pm_iowrite(0x68, byte);
+
/* IRQ0From8254 */
byte = pci_read_config8(dev, 0x41);
byte &= ~(1 << 7);
@@ -219,10 +233,10 @@ static void sm_init(device_t dev)
* Transactions for the K8 Platform (for All Revisions) */
abcfg_reg(0x10090, 1 << 8, 1 << 8);
- /* ACPI_SOFT_CLOCK_THROTTLE_PERIOD */
+ /* Set ACPI Software clock Throttling Period to 244 us*/
byte = pm_ioread(0x68);
byte &= ~(3 << 6);
- byte |= (2 << 6); /* 224us */
+ byte |= (2 << 6); /* 244us */
pm_iowrite(0x68, byte);
if (REV_SB700_A15 == rev) {
@@ -367,16 +381,16 @@ static void sb700_sm_read_resources(device_t dev)
res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */
res->align = 8;
res->gran = 8;
- res->flags = IORESOURCE_MEM | IORESOURCE_FIXED;
+ res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED;
- /* Linux ACPI crashes when it is 1. For late debugging. */
+ /* HPET */
res = new_resource(dev, 0xB4); /* TODO: test hpet */
res->base = 0xfed00000; /* reset hpet to widely accepted address */
res->size = 0x400;
res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */
res->align = 8;
res->gran = 8;
- res->flags = IORESOURCE_MEM | IORESOURCE_FIXED;
+ res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED;
/* dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; */
@@ -387,7 +401,7 @@ static void sb700_sm_read_resources(device_t dev)
res->limit = 0xFFFFUL; /* res->base + res->size -1; */
res->align = 8;
res->gran = 8;
- res->flags = IORESOURCE_IO | IORESOURCE_FIXED;
+ res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED;
compact_resources(dev);
}
diff --git a/src/southbridge/amd/sb700/smbus.c b/src/southbridge/amd/sb700/smbus.c
old mode 100644
new mode 100755
index e47bcee..6edc3de
--- a/src/southbridge/amd/sb700/smbus.c
+++ b/src/southbridge/amd/sb700/smbus.c
@@ -22,6 +22,51 @@
#include "smbus.h"
+void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val)
+{
+ u32 tmp;
+
+ outl((reg_space & 0x3) << 30 | reg_addr, AB_INDX);
+ tmp = inl(AB_DATA);
+ /* rpr 4.2
+ * For certain revisions of the chip, the ABCFG registers,
+ * with an address of 0x100NN (where 'N' is any hexadecimal
+ * number), require an extra programming step.*/
+ reg_addr & 0x10000 ? outl(0, AB_INDX) : NULL;
+
+ tmp &= ~mask;
+ tmp |= val;
+
+ /* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<30 | reg_addr); */
+ outl((reg_space & 0x3) << 30 | reg_addr, AB_INDX); /* probably we dont have to do it again. */
+ outl(tmp, AB_DATA);
+ reg_addr & 0x10000 ? outl(0, AB_INDX) : NULL;
+}
+
+/* space = 0: AX_INDXC, AX_DATAC
+ * space = 1: AX_INDXP, AX_DATAP
+ */
+void alink_ax_indx(u32 space, u32 axindc, u32 mask, u32 val)
+{
+ u32 tmp;
+
+ /* read axindc to tmp */
+ outl(space << 30 | space << 3 | 0x30, AB_INDX);
+ outl(axindc, AB_DATA);
+ outl(space << 30 | space << 3 | 0x34, AB_INDX);
+ tmp = inl(AB_DATA);
+
+ tmp &= ~mask;
+ tmp |= val;
+
+ /* write tmp */
+ outl(space << 30 | space << 3 | 0x30, AB_INDX);
+ outl(axindc, AB_DATA);
+ outl(space << 30 | space << 3 | 0x34, AB_INDX);
+ outl(tmp, AB_DATA);
+}
+
+
static inline void smbus_delay(void)
{
outb(inb(0x80), 0x80);
@@ -177,48 +222,4 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val)
return 0;
}
-static void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val)
-{
- u32 tmp;
-
- outl((reg_space & 0x3) << 30 | reg_addr, AB_INDX);
- tmp = inl(AB_DATA);
- /* rpr 4.2
- * For certain revisions of the chip, the ABCFG registers,
- * with an address of 0x100NN (where 'N' is any hexadecimal
- * number), require an extra programming step.*/
- reg_addr & 0x10000 ? outl(0, AB_INDX) : NULL;
-
- tmp &= ~mask;
- tmp |= val;
-
- /* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<30 | reg_addr); */
- outl((reg_space & 0x3) << 30 | reg_addr, AB_INDX); /* probably we dont have to do it again. */
- outl(tmp, AB_DATA);
- reg_addr & 0x10000 ? outl(0, AB_INDX) : NULL;
-}
-
-/* space = 0: AX_INDXC, AX_DATAC
- * space = 1: AX_INDXP, AX_DATAP
- */
-static inline void alink_ax_indx(u32 space /*c or p? */ , u32 axindc,
- u32 mask, u32 val)
-{
- u32 tmp;
-
- /* read axindc to tmp */
- outl(space << 30 | space << 3 | 0x30, AB_INDX);
- outl(axindc, AB_DATA);
- outl(space << 30 | space << 3 | 0x34, AB_INDX);
- tmp = inl(AB_DATA);
-
- tmp &= ~mask;
- tmp |= val;
-
- /* write tmp */
- outl(space << 30 | space << 3 | 0x30, AB_INDX);
- outl(axindc, AB_DATA);
- outl(space << 30 | space << 3 | 0x34, AB_INDX);
- outl(tmp, AB_DATA);
-}
#endif
diff --git a/src/southbridge/amd/sb700/smbus.h b/src/southbridge/amd/sb700/smbus.h
old mode 100644
new mode 100755
index c21a1dc..9ddfc35
--- a/src/southbridge/amd/sb700/smbus.h
+++ b/src/southbridge/amd/sb700/smbus.h
@@ -20,6 +20,13 @@
#ifndef SB700_SMBUS_H
#define SB700_SMBUS_H
+#include <stdint.h>
+#include "stddef.h"
+#include <arch/io.h>
+
+#define SMBUS_IO_BASE 0x6000 /* Is it a temporary SMBus I/O base address? */
+ /*SIZE 0x40 */
+
#define SMBHSTSTAT 0x0
#define SMBSLVSTAT 0x1
#define SMBHSTCTRL 0x2
@@ -56,10 +63,11 @@
#define axindxp_reg(reg, mask, val) \
alink_ax_indx(1, (reg), (mask), (val))
+void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val);
+void alink_ax_indx(u32 space, u32 axindc, u32 mask, u32 val);
int do_smbus_recv_byte(u32 smbus_io_base, u32 device);
int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val);
int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
-
#endif
diff --git a/src/southbridge/amd/sb700/usb.c b/src/southbridge/amd/sb700/usb.c
old mode 100644
new mode 100755
index 2957dc5..7932401
--- a/src/southbridge/amd/sb700/usb.c
+++ b/src/southbridge/amd/sb700/usb.c
@@ -178,6 +178,7 @@ static void usb_init2(struct device *dev)
dword |= 1 << 8;
dword &= ~(1 << 27); /* 6.23 */
}
+ pci_write_config32(dev, 0x50, dword);
printk(BIOS_DEBUG, "rpr 6.23, final dword=%x\n", dword);
}
diff --git a/src/southbridge/amd/sr5650/Makefile.inc b/src/southbridge/amd/sr5650/Makefile.inc
index a2d10d7..0a4ce39 100644
--- a/src/southbridge/amd/sr5650/Makefile.inc
+++ b/src/southbridge/amd/sr5650/Makefile.inc
@@ -1,3 +1,5 @@
driver-y += sr5650.c
driver-y += pcie.c
driver-y += ht.c
+
+romstage-y += early_setup.c
diff --git a/src/southbridge/amd/sr5650/cmn.h b/src/southbridge/amd/sr5650/cmn.h
old mode 100644
new mode 100755
index e94fcdd..6692b86
--- a/src/southbridge/amd/sr5650/cmn.h
+++ b/src/southbridge/amd/sr5650/cmn.h
@@ -20,13 +20,21 @@
#ifndef __SR5650_CMN_H__
#define __SR5650_CMN_H__
+#include <arch/io.h>
+
#define NBMISC_INDEX 0x60
#define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */
#define NBMC_INDEX 0xE8
#define NBPCIE_INDEX 0xE0
-#define EXT_CONF_BASE_ADDRESS 0xE0000000
+#define EXT_CONF_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
#define TEMP_MMIO_BASE_ADDRESS 0xC0000000
+#define axindxc_reg(reg, mask, val) \
+ alink_ax_indx(0, (reg), (mask), (val))
+
+#define AB_INDX 0xCD8
+#define AB_DATA (AB_INDX+4)
+
static inline u32 nb_read_index(device_t dev, u32 index_reg, u32 index)
{
pci_write_config32(dev, index_reg, index);
diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c
old mode 100644
new mode 100755
index 5f7438c..50f836e
--- a/src/southbridge/amd/sr5650/early_setup.c
+++ b/src/southbridge/amd/sr5650/early_setup.c
@@ -17,20 +17,50 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <stdint.h>
+#include <arch/cpu.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/msr.h>
#include "sr5650.h"
#include "cmn.h"
+/* space = 0: AX_INDXC, AX_DATAC
+ * space = 1: AX_INDXP, AX_DATAP
+ */
+static void alink_ax_indx(u32 space, u32 axindc, u32 mask, u32 val)
+{
+ u32 tmp;
+
+ /* read axindc to tmp */
+ outl(space << 30 | space << 3 | 0x30, AB_INDX);
+ outl(axindc, AB_DATA);
+ outl(space << 30 | space << 3 | 0x34, AB_INDX);
+ tmp = inl(AB_DATA);
+
+ tmp &= ~mask;
+ tmp |= val;
+
+ /* write tmp */
+ outl(space << 30 | space << 3 | 0x30, AB_INDX);
+ outl(axindc, AB_DATA);
+ outl(space << 30 | space << 3 | 0x34, AB_INDX);
+ outl(tmp, AB_DATA);
+}
+
+
/* family 10 only, for reg > 0xFF */
-#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1
+#if (CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1) || (CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 == 1)
static void set_fam10_ext_cfg_enable_bits(device_t fam10_dev, u32 reg_pos, u32 mask,
u32 val)
{
u32 reg_old, reg;
- reg = reg_old = Get_NB32(fam10_dev, reg_pos);
+ reg = reg_old = pci_read_config32(fam10_dev, reg_pos);
reg &= ~mask;
reg |= val;
if (reg != reg_old) {
- Set_NB32(fam10_dev, reg_pos, reg);
+ pci_write_config32(fam10_dev, reg_pos, reg);
}
}
#else
@@ -113,17 +143,19 @@ static const u8 sr5650_ibias[] = {
[0xe] = 0xC6, /* 2.6Ghz HyperTransport 3 only */
};
-static void sr5650_htinit(void)
+void sr5650_htinit(void)
{
/*
* About HT, it has been done in enumerate_ht_chain().
*/
- device_t cpu_f0, sr5650_f0, clk_f1, cpu1_f0;
+ device_t cpu_f0, sr5650_f0, clk_f1;
u32 reg;
- u8 cpu_ht_freq, ibias;
+ u8 cpu_ht_freq, cpu_htfreq_max, ibias;
+ u8 sbnode;
+ u8 sblink;
+ u16 linkfreq_reg;
+ u16 linkfreqext_reg;
- cpu_f0 = PCI_DEV(0, 0x18, 0);
- cpu1_f0 = PCI_DEV(0, 0x19, 0);
/************************
* get cpu's ht freq, in cpu's function 0, offset 0x88
* bit11-8, specifics the maximum operation frequency of the link's transmitter clock.
@@ -133,16 +165,36 @@ static void sr5650_htinit(void)
* please see the table sr5650_ibias about the value and its corresponding frequency.
************************/
/* Link0, Link1 are for connection between P0 and P1.
- * Link2 should be 0xC8?
* TODO: Check the topology of the MP and NB. Or we just read the nbconfig? */
/* NOTE: In most cases, we only have one CPU. In that case, we should read 0x88. */
- reg = pci_read_config32(cpu1_f0, 0x0);
- reg = pci_read_config32(cpu_f0,
- reg == 0 || reg == -1 ? 0x88 : 0xC8
- );
+ /* Find out the node ID and the Link ID that
+ * connects to the Southbridge (system IO hub).
+ */
+ sbnode = (pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60) >> 8) & 7;
+ sblink = (pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64) >> 8) & 3; /* bit[10] sublink, bit[9,8] link. */
+ cpu_f0 = PCI_DEV(0, (0x18 + sbnode), 0);
+
+ /*
+ * link freq reg of Link0, 1, 2, 3 is 0x88, 0xA8, 0xC8, 0xE8 respectively
+ * link freq ext reg of Link0, 1, 2, 3 is 0x9C, 0xBC, 0xDC, 0xFC respectively
+ */
+ linkfreq_reg = 0x88 + (sblink << 5);
+ linkfreqext_reg = 0x9C + (sblink << 5);
+ reg = pci_read_config32(cpu_f0, linkfreq_reg);
+
cpu_ht_freq = (reg & 0xf00) >> 8;
- printk(BIOS_INFO, "sr5650_htinit cpu_ht_freq=%x.\n", cpu_ht_freq);
+
+ /* Freq[4] is only valid for revision D and later processors */
+ if (cpuid_eax(1) >= 0x100F80) {
+ cpu_htfreq_max = 0x14;
+ cpu_ht_freq |= ((pci_read_config32(cpu_f0, linkfreqext_reg) & 0x01) << 4);
+ } else {
+ cpu_htfreq_max = 0x0F;
+ }
+
+ printk(BIOS_INFO, "sr5650_htinit: Node %x Link %x, HT freq=%x.\n",
+ sbnode, sblink, cpu_ht_freq);
sr5650_f0 = PCI_DEV(0, 0, 0);
clk_f1 = PCI_DEV(0, 0, 1); /* We need to make sure the F1 is accessible. */
@@ -162,13 +214,13 @@ static void sr5650_htinit(void)
set_nbcfg_enable_bits(clk_f1, 0xD8, 0x3FF, ibias);
/* Optimizes chipset HT transmitter drive strength */
set_htiu_enable_bits(sr5650_f0, 0x2A, 0x3, 0x3);
- } else if ((cpu_ht_freq > 0x6) && (cpu_ht_freq < 0xf)) {
+ } else if ((cpu_ht_freq > 0x6) && (cpu_ht_freq < cpu_htfreq_max)) {
printk(BIOS_INFO, "sr5650_htinit: HT3 mode\n");
/* Enable Protocol checker */
set_htiu_enable_bits(sr5650_f0, 0x1E, 0xFFFFFFFF, 0x7FFFFFFC);
- #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 /* save some spaces */
+#if (CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1) || (CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 == 1) /* save some spaces */
/* HT3 mode, RPR 5.4.3 */
set_nbcfg_enable_bits(sr5650_f0, 0x9c, 0x3 << 16, 0);
@@ -189,83 +241,36 @@ static void sr5650_htinit(void)
/* Enables strict TM4 detection */
set_htiu_enable_bits(sr5650_f0, 0x15, 0x1 << 22, 0x1 << 22);
+ /* Optimizes chipset HT transmitter drive strength */
+ set_htiu_enable_bits(sr5650_f0, 0x2A, 0x3 << 0, 0x1 << 0);
+
/* HyperTransport 3 Processor register settings to be done in northbridge */
+
/* Enables error-retry mode */
- set_fam10_ext_cfg_enable_bits(cpu_f0, 0x130, 1 << 0, 1 << 0);
- set_fam10_ext_cfg_enable_bits(cpu_f0, 0x134, 1 << 0, 1 << 0); /* TODO: Check if it is needed to set other node. */
- set_fam10_ext_cfg_enable_bits(cpu_f0, 0x138, 1 << 0, 1 << 0);
+ set_fam10_ext_cfg_enable_bits(cpu_f0, 0x130 + (sblink << 2), 1 << 0, 1 << 0);
+
/* Enables scrambling */
- set_fam10_ext_cfg_enable_bits(cpu_f0, 0x170, 1 << 3, 1 << 3);
- set_fam10_ext_cfg_enable_bits(cpu_f0, 0x174, 1 << 3, 1 << 3); /* TODO: Check if it is needed to set other node. */
- set_fam10_ext_cfg_enable_bits(cpu_f0, 0x178, 1 << 3, 1 << 3);
+ set_fam10_ext_cfg_enable_bits(cpu_f0, 0x170 + (sblink << 2), 1 << 3, 1 << 3);
+
/* Enables transmitter de-emphasis
- * This depends on the PCB design and the trace */
+ * This depends on the PCB design and the trace
+ */
/* Disables command throttling */
set_fam10_ext_cfg_enable_bits(cpu_f0, 0x168, 1 << 10, 1 << 10);
+
/* Sets Training 0 Time. See T0Time table for encodings */
- set_fam10_ext_cfg_enable_bits(cpu_f0, 0x16C, 0x3F, 0x20);
+ /* AGESA have set it to recommanded value already
+ * The recommended values are 14h(2us) if F0x[18C:170][LS2En]=0
+ * and 26h(12us) if F0x[18C:170][LS2En]=1
+ */
+ //set_fam10_ext_cfg_enable_bits(cpu_f0, 0x16C, 0x3F, 0x26);
+
/* HT Buffer Allocation for Ganged Links!!! */
- #endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 */
+#endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 */
}
}
-#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 != 1 /* save some spaces */
-/*******************************************************
-* Optimize k8 with UMA.
-* See BKDG_NPT_0F guide for details.
-* The processor node is addressed by its Node ID on the HT link and can be
-* accessed with a device number in the PCI configuration space on Bus0.
-* The Node ID 0 is mapped to Device 24 (0x18), the Node ID 1 is mapped
-* to Device 25, and so on.
-* The processor implements configuration registers in PCI configuration
-* space using the following four headers
-* Function0: HT technology configuration
-* Function1: Address map configuration
-* Function2: DRAM and HT technology Trace mode configuration
-* Function3: Miscellaneous configuration
-*******************************************************/
-static void k8_optimization(void)
-{
- device_t k8_f0, k8_f2, k8_f3;
- msr_t msr;
-
- printk(BIOS_INFO, "k8_optimization()\n");
- k8_f0 = PCI_DEV(0, 0x18, 0);
- k8_f2 = PCI_DEV(0, 0x18, 2);
- k8_f3 = PCI_DEV(0, 0x18, 3);
-
- pci_write_config32(k8_f0, 0x90, 0x01700169); /* CIM NPT_Optimization */
- set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 28, 0 << 28);
- set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 26 | 1 << 27,
- 1 << 26 | 1 << 27);
- set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 11, 1 << 11);
- /* set_nbcfg_enable_bits(k8_f0, 0x84, 1 << 11 | 1 << 13 | 1 << 15, 1 << 11 | 1 << 13 | 1 << 15); */ /* TODO */
-
- pci_write_config32(k8_f3, 0x70, 0x51220111); /* CIM NPT_Optimization */
- pci_write_config32(k8_f3, 0x74, 0x50404021);
- pci_write_config32(k8_f3, 0x78, 0x08002A00);
- if (pci_read_config32(k8_f3, 0xE8) & 0x3<<12)
- pci_write_config32(k8_f3, 0x7C, 0x0000211A); /* dual core */
- else
- pci_write_config32(k8_f3, 0x7C, 0x0000212B); /* single core */
- set_nbcfg_enable_bits_8(k8_f3, 0xDC, 0xFF, 0x25);
-
- set_nbcfg_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5);
- set_nbcfg_enable_bits(k8_f2, 0x94, 0xF << 24, 7 << 24);
- set_nbcfg_enable_bits(k8_f2, 0x90, 1 << 10, 0 << 10);
- set_nbcfg_enable_bits(k8_f2, 0xA0, 3 << 2, 3 << 2);
- set_nbcfg_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5);
-
- msr = rdmsr(0xC001001F);
- msr.lo &= ~(1 << 9);
- msr.hi &= ~(1 << 4);
- wrmsr(0xC001001F, msr);
-}
-#else
-#define k8_optimization() do{}while(0)
-#endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 != 1 */
-
-#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 /* save some spaces */
+#if (CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1) || (CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 == 1) /* save some spaces */
void fam10_optimization(void)
{
device_t cpu_f0, cpu_f2, cpu_f3;
@@ -340,13 +345,12 @@ static void sr5650_por_misc_index_init(device_t nb_dev)
set_nbmisc_enable_bits(nb_dev, 0x2B, 1 << 15 | 1 << 27, 1 << 15 | 1 << 27);
set_nbmisc_enable_bits(nb_dev, 0x2C, 1 << 0 | 1 << 1 | 1 << 5 | 1 << 4 | 1 << 10, 1 << 0 | 1 << 1 | 1 << 5);
set_nbmisc_enable_bits(nb_dev, 0x32, 0x3F << 20, 0x2A << 20);
- set_nbmisc_enable_bits(nb_dev, 0x34, 1 << 7 | 1 << 15 | 1 << 23 | 1 << 31, 0); /* bit31 BTS fail */
+ set_nbmisc_enable_bits(nb_dev, 0x34, 1 << 7 | 1 << 15 | 1 << 23, 0);
set_nbmisc_enable_bits(nb_dev, 0x35, 0x3F << 26, 0x2A << 26);
set_nbmisc_enable_bits(nb_dev, 0x37, 0xfff << 20, 0xddd << 20);
set_nbmisc_enable_bits(nb_dev, 0x37, 7 << 11, 0);
/* PCIE CDR setting */
set_nbmisc_enable_bits(nb_dev, 0x38, 0xFFFFFFFF, 0xC0C0C0);
- set_nbmisc_enable_bits(nb_dev, 0x39, 1 << 31, 0); /* bit31 BTS fail */
set_nbmisc_enable_bits(nb_dev, 0x22, 0xFFFFFFFF, (1 << 27) | (0x8 << 12) | (0x8 << 16) | (0x8 << 20));
set_nbmisc_enable_bits(nb_dev, 0x22, 1 << 1 | 1 << 2 | 1 << 6 | 1 << 7, 1 << 1 | 1 << 2 | 1 << 6 | 1 << 7);
@@ -381,7 +385,7 @@ static void sr5650_por_misc_index_init(device_t nb_dev)
set_nbmisc_enable_bits(nb_dev, 0x47, 0xFFFFFFFF, 0x0000000B);
set_nbmisc_enable_bits(nb_dev, 0x12, 0xFFFFFFFF, 0x00FB5555);
- set_nbmisc_enable_bits(nb_dev, 0x0C, 0xFFFFFFFF, 0x001f37EC);
+ set_nbmisc_enable_bits(nb_dev, 0x0C, 0xFFFFFFFF, 0x001F37FC);
set_nbmisc_enable_bits(nb_dev, 0x15, 0xFFFFFFFF, 0x0);
/* NB_PROG_DEVICE_REMAP */
@@ -478,7 +482,7 @@ static void sr5650_por_init(device_t nb_dev)
}
/* enable CFG access to Dev8, which is the SB P2P Bridge */
-static void enable_sr5650_dev8(void)
+void enable_sr5650_dev8(void)
{
set_nbmisc_enable_bits(PCI_DEV(0, 0, 0), 0x00, 1 << 6, 1 << 6);
}
@@ -486,14 +490,14 @@ static void enable_sr5650_dev8(void)
/*
* Compliant with CIM_33's AtiNBInitEarlyPost (AtiInitNBBeforePCIInit).
*/
-static void sr5650_before_pci_init(void)
+void sr5650_before_pci_init(void)
{
}
/*
* The calling sequence is same as CIM.
*/
-static void sr5650_early_setup(void)
+void sr5650_early_setup(void)
{
device_t nb_dev = PCI_DEV(0, 0, 0);
printk(BIOS_INFO, "sr5650_early_setup()\n");
@@ -513,28 +517,24 @@ static void sr5650_early_setup(void)
break;
}
-#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1
-
fam10_optimization();
-#else
- k8_optimization();
-#endif
-
sr5650_por_init(nb_dev);
}
/**
- * @brief disable GPP1 Port0,1, GPP3a Port0,1,2,3,4,5
+ * @brief disable GPP1 Port0,1, GPP2, GPP3a Port0,1,2,3,4,5, GPP3b
*
*/
-void disable_pcie_bridge(void)
+void sr5650_disable_pcie_bridge(void)
{
u32 mask;
u32 reg;
device_t nb_dev = PCI_DEV(0, 0, 0);
- mask = (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) |
- (1 << 16) | (1 << 17);
+ mask = (1 << 2) | (1 << 3); /*GPP1*/
+ mask |= (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | (1 << 16) | (1 << 17); /*GPP3a*/
+ mask |= (1 << 18) | (1 << 19); /*GPP2*/
+ mask |= (1 << 20); /*GPP3b*/
reg = mask;
set_nbmisc_enable_bits(nb_dev, 0x0c, mask, reg);
}
diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c
old mode 100644
new mode 100755
index 3ad5a7d..37743ca
--- a/src/southbridge/amd/sr5650/pcie.c
+++ b/src/southbridge/amd/sr5650/pcie.c
@@ -267,23 +267,25 @@ void disable_pcie_bar3(device_t nb_dev)
}
/*
-*/
+ * GEN2 Software Compliance
+ */
void init_gen2(device_t nb_dev, device_t dev, u8 port)
{
u32 reg, val;
+
/* for A11 (0x89 == 0) */
reg = 0x34;
- if (port <= 3){
+ if (port <= 3) {
val = 1<<5;
- }else{
+ } else {
val = 1<<31;
- if (port >= 9 )
+ if (port >= 9)
reg = 0x39;
}
- /* todo: check for rev > a11
+ /* TODO: check for rev > a11 */
switch (port) {
- case 2;
+ case 2:
reg = 0x34;
val = 1<<5;
break;
@@ -300,7 +302,9 @@ void init_gen2(device_t nb_dev, device_t dev, u8 port)
reg = 0x39;
val = 1<<31;
break;
- case 7..9:
+ case 7:
+ case 8:
+ case 9:
reg = 0x37;
val = 1<<port;
break;
@@ -312,9 +316,11 @@ void init_gen2(device_t nb_dev, device_t dev, u8 port)
reg = 0;
break;
}
- */
+
+ /* Enables GEN2 capability of the device */
set_pcie_enable_bits(dev, 0xA4, 0x1, 0x1);
- pci_ext_write_config32(nb_dev, dev, 0x88, 0xF0, 1<<2); /* LINK_CRTL2*/
+ /* Advertise the link speed to be Gen2 */
+ pci_ext_write_config32(nb_dev, dev, 0x88, 0xF0, 1<<2); /* LINK_CRTL2 */
set_nbmisc_enable_bits(nb_dev, reg, val, val);
}
@@ -409,7 +415,7 @@ static void gpp12_cpl_buf_alloc(device_t nb_dev, device_t dev)
}
}
-#if 0 /* BTS report error without this function. But some board
+#if 1 /* BTS report error without this function. But some board
* fail to boot. Leave it here for future debug. */
/*
@@ -424,6 +430,7 @@ static void EnableLclkGating(device_t dev)
device_t nb_dev = dev_find_slot(0, 0);
device_t clk_f1= dev_find_slot(0, 1);
+ reg = 0xE8;
port = dev->path.pci.devfn >> 3;
switch (port) {
//PCIE_CORE_INDEX_GPP1
@@ -436,7 +443,6 @@ static void EnableLclkGating(device_t dev)
//PCIE_CORE_INDEX_GPP2
case 11:
case 12:
- reg = 0xE8;
value = 1 << 28;
break;
@@ -444,13 +450,11 @@ static void EnableLclkGating(device_t dev)
case 4 ... 7:
case 9:
case 10:
- reg = 0xE8;
value = 1 << 31;
break;
//PCIE_CORE_INDEX_GPP3b;
case 13:
- reg = 0xE8;
value = 1 << 25;
break;
@@ -541,6 +545,14 @@ void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
/* 4.4.2.step13.6. Set REGS_LC_ALLOW_TX_L1_CONTROL to allow TX to
prevent LC from going to L1 when there are outstanding completions.*/
set_pcie_enable_bits(dev, 0x02, 1 << 15, 1 << 15);
+
+ /* Enables the PLL power down when all lanes are inactive.
+ * It should be on in GPP.
+ */
+ if (gpp_sb_sel == PCIE_CORE_INDEX_GPP3a || gpp_sb_sel == PCIE_CORE_INDEX_GPP3b || gpp_sb_sel == PCIE_CORE_INDEX_SB) {
+ set_pcie_enable_bits(nb_dev, 0x02 | gpp_sb_sel, 1 << 3, 1 << 3);
+ }
+
/* 4.4.2.step13.7. Set REGS_LC_DONT_GO_TO_L0S_IF_L1_ARMED to prevent
lc to go to from L0 to Rcv_L0s if L1 is armed. */
set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11);
@@ -594,8 +606,11 @@ void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
* RPR typo- it says enable but the bit setting says disable.
* Disable it here and we enable it later. */
set_pcie_enable_bits(dev, 0xA4, 1 << 0, 1 << 0);
- /* 4.4.2.step13.21. */
- /* 4.4.2.step13.22 */
+
+ /* 4.4.2.step13.21. Legacy Hot Plug -CMOS Option */
+ /* NOTE: This feature can be enabled only for Hot-Plug slots implemented on SR5690 platform. */
+
+ /* 4.4.2.step13.22. Native PCIe Mode -CMOS Option */
/* Enable native PME. */
set_pcie_enable_bits(dev, 0x10, 1 << 3, 1 < 3);
/* This bit when set indicates that the PCIe Link associated with this port
@@ -607,7 +622,7 @@ void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
/* Enables flushing of TLPs when Data Link is down. */
set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19);
- /* 4.4.2.step14. Server Class Hot Plug Feature */
+ /* 4.4.2.step14. Server Class Hot Plug Feature. NOTE: This feature is not supported on SR5670 and SR5650 */
/* 4.4.2 step14.1: Advertising Hot Plug Capabilities */
/* 4.4.2.step14.2: Firmware Upload */
/* 4.4.2.Step14.3: SBIOS Acknowledgment to Firmware of Successful Firmware Upload */
@@ -630,11 +645,13 @@ void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
if ( port == 8 )
set_pcie_enable_bits(dev, 0xA0, 0, 1 << 23);
+#if 0 //SR56x0 pcie Gen2 code is not tested yet, we should enable it again when test finished.
/* set automatic Gen2 support, needs mainboard config option as Gen2 can cause issues on some platforms. */
init_gen2(nb_dev, dev, port);
set_pcie_enable_bits(dev, 0xA4, 1 << 29, 1 << 29);
set_pcie_enable_bits(dev, 0xC0, 1 << 15, 0);
set_pcie_enable_bits(dev, 0xA2, 1 << 13, 0);
+#endif
/* Hotplug Support - bit5 + bit6 capable and surprise */
pci_ext_write_config32(nb_dev, dev, 0x6c, 0x60, 0x60);
@@ -715,12 +732,13 @@ void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
/* 4.4..7.1 TXCLK Gating in L1, Enables powering down TXCLK clock pads on the receive side. */
set_pcie_enable_bits(nb_dev, 0x40 | gpp_sb_sel, 1 << 6, 1 << 6);
- /* Step 21: Register Locking PCIE Misc. Late Core sttting - Must move somewhere do PciInitLate FIXME */
- /* Lock HWInit Register */
- //set_pcie_enable_bits(nb_dev, 0x10 | gpp_sb_sel, 1 << 0, 1 << 0);
+ /* Step 20: Disables immediate RCB timeout on link down */
+ if (!((pci_read_config32(dev, 0x6C ) >> 6) & 0x01)) {
+ set_pcie_enable_bits(dev, 0x70, 1 << 19, 0 << 19);
+ }
/* Step 27: LCLK Gating */
- //EnableLclkGating(dev);
+ EnableLclkGating(dev);
/* Set Common Clock */
/* If dev present, set PcieCapPtr+0x10, BIT6);
@@ -734,6 +752,34 @@ void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
}
}
+/**
+ * Step 21: Register Locking
+ * Lock HWInit Register of each pcie core
+ */
+static void lock_hwinitreg(device_t nb_dev)
+{
+ /* Step 21: Register Locking, Lock HWInit Register */
+ set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_GPP1, 1 << 0, 1 << 0);
+ set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_SB, 1 << 0, 1 << 0);
+ set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_GPP2, 1 << 0, 1 << 0);
+ set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_GPP3a, 1 << 0, 1 << 0);
+ set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_GPP3b, 1 << 0, 1 << 0);
+}
+
+/**
+ * Lock HWInit Register
+ */
+void sr56x0_lock_hwinitreg(void)
+{
+ device_t nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+
+ /* Lock HWInit Register */
+ lock_hwinitreg(nb_dev);
+
+ /* Lock HWInit Register NBMISCIND:0x0 NBCNTL[7] HWINIT_WR_LOCK */
+ set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 7, 1 << 7);
+}
+
/*****************************************
* Compliant with CIM_33's PCIEConfigureGPPCore
*****************************************/
diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c
old mode 100644
new mode 100755
index 616ca44..14b919d
--- a/src/southbridge/amd/sr5650/sr5650.c
+++ b/src/southbridge/amd/sr5650/sr5650.c
@@ -266,15 +266,21 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
}
/*
-* Compliant with CIM_33's ATINB_SetToms.
-* Set Top Of Memory below and above 4G.
-*/
+ * Set Top Of Memory below and above 4G.
+ */
void sr5650_set_tom(device_t nb_dev)
{
- extern u64 uma_memory_base;
+ msr_t sysmem;
+
+ /* The system top memory in SR56X0. */
+ sysmem = rdmsr(0xc001001A);
+ printk(BIOS_DEBUG, "Sysmem TOM = %x_%x\n", sysmem.hi, sysmem.lo);
+ pci_write_config32(nb_dev, 0x90, sysmem.lo);
- /* set TOM */
- pci_write_config32(nb_dev, 0x90, uma_memory_base);
+ sysmem = rdmsr(0xc001001D);
+ printk(BIOS_DEBUG, "Sysmem TOM2 = %x_%x\n", sysmem.hi, sysmem.lo);
+ htiu_write_index(nb_dev, 0x31, sysmem.hi);
+ htiu_write_index(nb_dev, 0x30, sysmem.lo | 1);
}
u32 get_vid_did(device_t dev)
@@ -308,7 +314,7 @@ void sr5650_nb_pci_table(device_t nb_dev)
temp8 &= ~(1<<1);
pci_write_config8(nb_dev, 0x8d, temp8);
- /* set temporary NB TOM to 0x40000000. */
+ /* The system top memory in SR56X0. */
sr5650_set_tom(nb_dev);
/* Program NB HTIU table. */
@@ -424,6 +430,11 @@ void sr5650_enable(device_t dev)
default:
printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev));
}
+
+ /* Lock HWInit Register after the last device was done */
+ if (dev_ind == 13) {
+ sr56x0_lock_hwinitreg();
+ }
}
struct chip_operations southbridge_amd_sr5650_ops = {
diff --git a/src/southbridge/amd/sr5650/sr5650.h b/src/southbridge/amd/sr5650/sr5650.h
old mode 100644
new mode 100755
index 5da3544..1b5112b
--- a/src/southbridge/amd/sr5650/sr5650.h
+++ b/src/southbridge/amd/sr5650/sr5650.h
@@ -103,6 +103,10 @@ void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add);
void enable_pcie_bar3(device_t nb_dev);
void disable_pcie_bar3(device_t nb_dev);
+void enable_sr5650_dev8(void);
+void sr5650_htinit(void);
+void sr5650_early_setup(void);
+void sr5650_before_pci_init(void);
void sr5650_enable(device_t dev);
void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port);
void sr5650_gfx_init(device_t nb_dev, device_t dev, u32 port);
@@ -112,8 +116,9 @@ void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port);
u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port);
void pcie_config_misc_clk(device_t nb_dev);
void fam10_optimization(void);
-void disable_pcie_bridge(void);
+void sr5650_disable_pcie_bridge(void);
u32 get_vid_did(device_t dev);
void sr5650_nb_pci_table(device_t nb_dev);
void init_gen2(device_t nb_dev, device_t dev, u8 port);
+void sr56x0_lock_hwinitreg(void);
#endif /* SR5650_H */
diff --git a/src/superio/nuvoton/wpcm450/early_init.c b/src/superio/nuvoton/wpcm450/early_init.c
old mode 100644
new mode 100755
index eb80c94..94bef02
--- a/src/superio/nuvoton/wpcm450/early_init.c
+++ b/src/superio/nuvoton/wpcm450/early_init.c
@@ -18,7 +18,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <arch/io.h>
#include <arch/romcc_io.h>
+#include <device/pnp_def.h>
#include "wpcm450.h"
static void wpcm450_pnp_set_logical_device(u8 dev, u16 port)
@@ -41,7 +43,7 @@ static void wpcm450_pnp_set_iobase(u8 dev, u16 port, u8 index, u16 iobase)
outb(iobase&0xFF, port+1);
}
-static void wpcm450_enable_dev(u8 dev, u16 port, u16 iobase)
+void wpcm450_enable_dev(u8 dev, u16 port, u16 iobase)
{
wpcm450_pnp_set_logical_device(dev, port);
wpcm450_pnp_set_enable(dev, port, 0);
diff --git a/src/superio/nuvoton/wpcm450/wpcm450.h b/src/superio/nuvoton/wpcm450/wpcm450.h
old mode 100644
new mode 100755
index bf50c85..46f3cc5
--- a/src/superio/nuvoton/wpcm450/wpcm450.h
+++ b/src/superio/nuvoton/wpcm450/wpcm450.h
@@ -25,4 +25,6 @@
#define WPCM450_SP1 0x03 /* Com1 */
#define WPCM450_KBCK 0x06 /* Keyboard */
+void wpcm450_enable_dev(u8 dev, u16 port, u16 iobase);
+
#endif
diff --git a/src/vendorcode/amd/agesa/f14/Lib/amdlib.c b/src/vendorcode/amd/agesa/f14/Lib/amdlib.c
index c3364d3..3fc5112 100644
--- a/src/vendorcode/amd/agesa/f14/Lib/amdlib.c
+++ b/src/vendorcode/amd/agesa/f14/Lib/amdlib.c
@@ -551,8 +551,8 @@ LibAmdIoRMW (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
- UINT32 TempData;
- UINT32 TempMask;
+ UINT32 TempData = 0;
+ UINT32 TempMask = 0;
UINT32 Value;
LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask);
LibAmdIoRead (AccessWidth, IoAddress, &Value, StdHeader);
@@ -584,8 +584,8 @@ LibAmdIoPoll (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
- UINT32 TempData;
- UINT32 TempMask;
+ UINT32 TempData = 0;
+ UINT32 TempMask = 0;
UINT32 Value;
LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask);
do {
@@ -688,8 +688,8 @@ LibAmdMemRMW (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
- UINT32 TempData;
- UINT32 TempMask;
+ UINT32 TempData = 0;
+ UINT32 TempMask = 0;
UINT32 Value;
LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask);
LibAmdMemRead (AccessWidth, MemAddress, &Value, StdHeader);
@@ -721,8 +721,8 @@ LibAmdMemPoll (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
- UINT32 TempData;
- UINT32 TempMask;
+ UINT32 TempData = 0;
+ UINT32 TempMask = 0;
UINT32 Value;
LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask);
do {
@@ -849,8 +849,8 @@ LibAmdPciRMW (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
- UINT32 TempData;
- UINT32 TempMask;
+ UINT32 TempData = 0;
+ UINT32 TempMask = 0;
UINT32 Value;
LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask);
LibAmdPciRead (AccessWidth, PciAddress, &Value, StdHeader);
@@ -882,8 +882,8 @@ LibAmdPciPoll (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
- UINT32 TempData;
- UINT32 TempMask;
+ UINT32 TempData = 0;
+ UINT32 TempMask = 0;
UINT32 Value;
LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask);
do {
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Patch set updated: 2df3019 Libpayload: default DESTDIR for 'make install'
by Frank Vibrans III 20 Jul '11
by Frank Vibrans III 20 Jul '11
20 Jul '11
Frank Vibrans III (efdesign98(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/102
-gerrit
commit 2df301924ace4d1792e60424091ff29745a3f658
Author: Tadas Slotkus <devtadas(a)gmail.com>
Date: Fri Jul 15 03:41:11 2011 +0300
Libpayload: default DESTDIR for 'make install'
If you would try download FILO via svn, then you probably
get error message about libpayload install. This enables
manually installing libpayload in legacy style :)
Change-Id: I9f52be939303c5913611f21477d681e11d286382
Signed-off-by: Tadas Slotkus <devtadas(a)gmail.com>
---
payloads/libpayload/Makefile.inc | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc
index 08f7c9f..03862ca 100644
--- a/payloads/libpayload/Makefile.inc
+++ b/payloads/libpayload/Makefile.inc
@@ -33,6 +33,7 @@ export KERNELVERSION := 0.2.0
ARCHDIR-$(CONFIG_TARGET_I386) := i386
ARCHDIR-$(CONFIG_TARGET_POWERPC) := powerpc
+DESTDIR ?= install
real-target: lib
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Hello,
i'm aiming to try this incredible prject :)
In order to do this i wanted to ask if the laptop model described over
the object, does match with the lenovo T60p T7200 marked on your
compatibility list.
(Note: in fact the seller says at the mark: IBM/Lenovo)
But i just wanted to know if it maybe the compatibility rejects if it
was released when it was under IBM.
(Furhter question: if i get a T60p but with another CPU, does the
compatibility remains the same?)
My Regards, Matias
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