coreboot July 2011

coreboot@coreboot.org

52 participants
244 discussions

Re: [coreboot] Questions about the resource allocator of PCI
by Marc Jones 29 Jul '11

29 Jul '11

On Thu, Jul 28, 2011 at 5:25 PM, Hamo <hamo.by(a)gmail.com> wrote: > On Fri, Jul 29, 2011 at 1:17 AM, Marc Jones <marcj303(a)gmail.com> wrote: >> IORESOURCE_IO? MMIO is memory. > Yes. But I want to map all PCI devices' IO address to this address > space. So I set it to IORESOURCE_IO. Does ARM have an IO instructions, in and out? I think it is MMIO so this is the wrong type. > Are these devices on the PCI bus or on >> the root bus? > They are PCI devices and on the PCI bus. >> I am not certain how the allocator handles root vs PCI, >> which is why I ask. For x86 the CPUs APIC area is reserved and not on >> the PCI bus. > If the devices are on the PCI bus, they should have PCI headers. If they are directly on the root bus, they don't and you can reserve the space there. There is an assumed top of memory for PCI BUS of 0xF0000000 that you may need to adjust or make an option. Marc -- http://se-eng.com

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Re: [coreboot] Questions about the resource allocator of PCI
by Hamo 29 Jul '11

29 Jul '11

On Fri, Jul 29, 2011 at 1:17 AM, Marc Jones <marcj303(a)gmail.com> wrote: > IORESOURCE_IO? MMIO is memory. Yes. But I want to map all PCI devices' IO address to this address space. So I set it to IORESOURCE_IO. Are these devices on the PCI bus or on > the root bus? They are PCI devices and on the PCI bus. > I am not certain how the allocator handles root vs PCI, > which is why I ask. For x86 the CPUs APIC area is reserved and not on > the PCI bus.

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Patch set updated: 70d49a6 libpayload: Add liblzma, libcbfs
by Patrick Georgi 28 Jul '11

28 Jul '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/115 -gerrit commit 70d49a6ab5036edd254261d4b3045590eadb7cbe Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Jul 21 15:43:14 2011 +0200 libpayload: Add liblzma, libcbfs Add cbfs core from coreboot into libpayload, and to support lzma decode, add coreboot's lzma code, too. Carl-Daniel agreed to relicense the lzmadecode wrapper as BSD-l, solving licensing problems. Change-Id: Id28990fe7e951d99447e265a4880d70a8f208dd2 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- payloads/libpayload/Config.in | 9 +- payloads/libpayload/Makefile.inc | 4 + payloads/libpayload/configs/defconfig | 7 +- payloads/libpayload/include/cbfs.h | 2 + payloads/libpayload/include/cbfs_core.h | 180 ++++++++++++++ payloads/libpayload/include/lzma.h | 40 +++ payloads/libpayload/libc/Makefile.inc | 1 - payloads/libpayload/libcbfs/Makefile.inc | 31 +++ payloads/libpayload/libcbfs/cbfs.c | 78 ++++++ payloads/libpayload/libcbfs/cbfs_core.c | 174 +++++++++++++ payloads/libpayload/liblzma/Makefile.inc | 31 +++ payloads/libpayload/liblzma/lzma.c | 47 ++++ payloads/libpayload/liblzma/lzmadecode.c | 398 ++++++++++++++++++++++++++++++ payloads/libpayload/liblzma/lzmadecode.h | 67 +++++ 14 files changed, 1065 insertions(+), 4 deletions(-) diff --git a/payloads/libpayload/Config.in b/payloads/libpayload/Config.in index 028dd33..0ce4ae5 100644 --- a/payloads/libpayload/Config.in +++ b/payloads/libpayload/Config.in @@ -129,7 +129,14 @@ config CBFS bool "CBFS support" default y help - CBFS is the archive format of (obsolete) coreboot v3 + CBFS is the archive format of coreboot + +config LZMA + bool "LZMA decoder" + default y + help + LZMA decoder implementation, usable eg. by CBFS, + but also externally. endmenu menu "Console Options" diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc index 5a7d142..9e40d0f 100644 --- a/payloads/libpayload/Makefile.inc +++ b/payloads/libpayload/Makefile.inc @@ -41,6 +41,8 @@ classes-$(CONFIG_PCI) += libpci classes-$(CONFIG_LIBC) += libc classes-$(CONFIG_CURSES) += libcurses classes-$(CONFIG_PDCURSES) += libmenu libform libpanel +classes-$(CONFIG_CBFS) += libcbfs +classes-$(CONFIG_LZMA) += liblzma libraries := $(classes-y) classes-y += head.o @@ -52,6 +54,8 @@ head.o-S-deps = $(obj)/libpayload-config.h subdirs-y := arch/$(ARCHDIR-y) subdirs-y += crypto libc drivers libpci subdirs-$(CONFIG_CURSES) += curses +subdirs-$(CONFIG_CBFS) += libcbfs +subdirs-$(CONFIG_LZMA) += liblzma INCLUDES := -Iinclude -Iinclude/$(ARCHDIR-y) -I$(obj) CFLAGS = $(INCLUDES) -O2 -pipe -g diff --git a/payloads/libpayload/configs/defconfig b/payloads/libpayload/configs/defconfig index 6d514d6..8d50f56 100644 --- a/payloads/libpayload/configs/defconfig +++ b/payloads/libpayload/configs/defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # libpayload version: 0.2.0 -# Tue Jul 12 15:54:09 2011 +# Thu Jul 21 15:45:38 2011 # # @@ -23,8 +23,11 @@ CONFIG_TARGET_I386=y # Standard Libraries # CONFIG_LIBC=y +CONFIG_CURSES=y +# CONFIG_TINYCURSES is not set CONFIG_PDCURSES=y -# CONFIG_CBFS is not set +CONFIG_CBFS=y +CONFIG_LZMA=y # # Console Options diff --git a/payloads/libpayload/include/cbfs.h b/payloads/libpayload/include/cbfs.h new file mode 100644 index 0000000..681caeb --- /dev/null +++ b/payloads/libpayload/include/cbfs.h @@ -0,0 +1,2 @@ +#include <arch/types.h> +#include "cbfs_core.h" diff --git a/payloads/libpayload/include/cbfs_core.h b/payloads/libpayload/include/cbfs_core.h new file mode 100644 index 0000000..fbe0081 --- /dev/null +++ b/payloads/libpayload/include/cbfs_core.h @@ -0,0 +1,180 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Jordan Crouse <jordan(a)cosmicpenguin.net> + * + * This file is dual-licensed. You can choose between: + * - The GNU GPL, version 2, as published by the Free Software Foundation + * - The revised BSD license (without advertising clause) + * + * --------------------------------------------------------------------------- + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + * --------------------------------------------------------------------------- + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * --------------------------------------------------------------------------- + */ + +#ifndef _CBFS_CORE_H_ +#define _CBFS_CORE_H_ + +/** These are standard values for the known compression + alogrithms that coreboot knows about for stages and + payloads. Of course, other CBFS users can use whatever + values they want, as long as they understand them. */ + +#define CBFS_COMPRESS_NONE 0 +#define CBFS_COMPRESS_LZMA 1 + +/** These are standard component types for well known + components (i.e - those that coreboot needs to consume. + Users are welcome to use any other value for their + components */ + +#define CBFS_TYPE_STAGE 0x10 +#define CBFS_TYPE_PAYLOAD 0x20 +#define CBFS_TYPE_OPTIONROM 0x30 +#define CBFS_TYPE_BOOTSPLASH 0x40 +#define CBFS_TYPE_RAW 0x50 +#define CBFS_TYPE_VSA 0x51 +#define CBFS_TYPE_MBI 0x52 +#define CBFS_TYPE_MICROCODE 0x53 +#define CBFS_COMPONENT_CMOS_DEFAULT 0xaa +#define CBFS_COMPONENT_CMOS_LAYOUT 0x01aa + + +/** this is the master cbfs header - it need to be + located somewhere in the bootblock. Where it + actually lives is up to coreboot. A pointer to + this header will live at 0xFFFFFFFc, so we can + easily find it. */ + +#define CBFS_HEADER_MAGIC 0x4F524243 +#define CBFS_HEADPTR_ADDR 0xFFFFFFFc +#define VERSION1 0x31313131 + +struct cbfs_header { + uint32_t magic; + uint32_t version; + uint32_t romsize; + uint32_t bootblocksize; + uint32_t align; + uint32_t offset; + uint32_t pad[2]; +} __attribute__((packed)); + +/** This is a component header - every entry in the CBFS + will have this header. + + This is how the component is arranged in the ROM: + + -------------- <- 0 + component header + -------------- <- sizeof(struct component) + component name + -------------- <- offset + data + ... + -------------- <- offset + len +*/ + +#define CBFS_FILE_MAGIC "LARCHIVE" + +struct cbfs_file { + char magic[8]; + uint32_t len; + uint32_t type; + uint32_t checksum; + uint32_t offset; +} __attribute__((packed)); + +/*** Component sub-headers ***/ + +/* Following are component sub-headers for the "standard" + component types */ + +/** This is the sub-header for stage components. Stages are + loaded by coreboot during the normal boot process */ + +struct cbfs_stage { + uint32_t compression; /** Compression type */ + uint64_t entry; /** entry point */ + uint64_t load; /** Where to load in memory */ + uint32_t len; /** length of data to load */ + uint32_t memlen; /** total length of object in memory */ +} __attribute__((packed)); + +/** this is the sub-header for payload components. Payloads + are loaded by coreboot at the end of the boot process */ + +struct cbfs_payload_segment { + uint32_t type; + uint32_t compression; + uint32_t offset; + uint64_t load_addr; + uint32_t len; + uint32_t mem_len; +} __attribute__((packed)); + +struct cbfs_payload { + struct cbfs_payload_segment segments; +}; + +#define PAYLOAD_SEGMENT_CODE 0x45444F43 +#define PAYLOAD_SEGMENT_DATA 0x41544144 +#define PAYLOAD_SEGMENT_BSS 0x20535342 +#define PAYLOAD_SEGMENT_PARAMS 0x41524150 +#define PAYLOAD_SEGMENT_ENTRY 0x52544E45 + +struct cbfs_optionrom { + uint32_t compression; + uint32_t len; +} __attribute__((packed)); + +#define CBFS_NAME(_c) (((char *) (_c)) + sizeof(struct cbfs_file)) +#define CBFS_SUBHEADER(_p) ( (void *) ((((uint8_t *) (_p)) + ntohl((_p)->offset))) ) + +/* returns pointer to file inside CBFS or NULL */ +struct cbfs_file *cbfs_find(const char *name); + +/* returns pointer to file data inside CBFS */ +void *cbfs_get_file(const char *name); + +/* returns pointer to file data inside CBFS after if type is correct */ +void *cbfs_find_file(const char *name, int type); + +/* returns 0 on success, -1 on failure */ +int cbfs_decompress(int algo, void *src, void *dst, int len); +#endif + diff --git a/payloads/libpayload/include/lzma.h b/payloads/libpayload/include/lzma.h new file mode 100644 index 0000000..35f4c02 --- /dev/null +++ b/payloads/libpayload/include/lzma.h @@ -0,0 +1,40 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2011 secunet Security Networks AG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _LZMA_H +#define _LZMA_H + +/* decompresses the data stream at src to dst, determining its length from + * the data stream itself. + * + * returns the decompressed size, or 0 on error + */ +unsigned long ulzma(unsigned char *src, unsigned char *dst); + +#endif diff --git a/payloads/libpayload/libc/Makefile.inc b/payloads/libpayload/libc/Makefile.inc index 0dab8c1..eef4f46 100644 --- a/payloads/libpayload/libc/Makefile.inc +++ b/payloads/libpayload/libc/Makefile.inc @@ -38,4 +38,3 @@ libc-$(CONFIG_LIBC) += qsort.c # should be moved to coreboot directory libc-$(CONFIG_LAR) += lar.c -#libc-$(CONFIG_CBFS) += cbfs.c diff --git a/payloads/libpayload/libcbfs/Makefile.inc b/payloads/libpayload/libcbfs/Makefile.inc new file mode 100644 index 0000000..50f4821 --- /dev/null +++ b/payloads/libpayload/libcbfs/Makefile.inc @@ -0,0 +1,31 @@ +## +## This file is part of the libpayload project. +## +## Copyright (C) 2011 secunet Security Networks AG +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions +## are met: +## 1. Redistributions of source code must retain the above copyright +## notice, this list of conditions and the following disclaimer. +## 2. Redistributions in binary form must reproduce the above copyright +## notice, this list of conditions and the following disclaimer in the +## documentation and/or other materials provided with the distribution. +## 3. The name of the author may not be used to endorse or promote products +## derived from this software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +## SUCH DAMAGE. +## + +libcbfs-$(CONFIG_CBFS) += cbfs.c + diff --git a/payloads/libpayload/libcbfs/cbfs.c b/payloads/libpayload/libcbfs/cbfs.c new file mode 100644 index 0000000..c7173e0 --- /dev/null +++ b/payloads/libpayload/libcbfs/cbfs.c @@ -0,0 +1,78 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2011 secunet Security Networks AG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <arch/endian.h> +#include <stdio.h> +#include <string.h> +#include <cbfs.h> + +#ifdef CONFIG_LZMA +#define CBFS_CORE_WITH_LZMA +#include <lzma.h> +#endif + +#define ERROR(x...) printf(x) +#define LOG(x...) + +uint32_t host_virt_to_phys(void *addr); +void *host_phys_to_virt(uint32_t addr); + +uint32_t romstart(void); +uint32_t romend(void); + +#include <arch/virtual.h> +uint32_t host_virt_to_phys(void *addr) { + return virt_to_phys(addr); +} + +void *host_phys_to_virt(uint32_t addr) { + return phys_to_virt(addr); +} +#undef virt_to_phys +#undef phys_to_virt + +uint32_t (*virt_to_phys)(void *) = host_virt_to_phys; +void* (*phys_to_virt)(uint32_t) = host_phys_to_virt; + + +uint32_t _romstart = 0xffffffff; +uint32_t _romend = 0; + +uint32_t romstart(void) +{ + return _romstart; +} + +uint32_t romend(void) +{ + return _romend; +} + +#include "cbfs_core.c" + diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c new file mode 100644 index 0000000..52ba58d --- /dev/null +++ b/payloads/libpayload/libcbfs/cbfs_core.c @@ -0,0 +1,174 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2011 secunet Security Networks AG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* The CBFS core requires a couple of #defines or functions to adapt it to the target environment: + * + * CBFS_CORE_WITH_LZMA (must be #define) + * if defined, ulzma() must exist for decompression of data streams + * + * phys_to_virt(x), virt_to_phys(x) + * translate physical addresses to virtual and vice versa + * can be idempotent if no mapping is necessary. + * + * ERROR(x...) + * print an error message x (in printf format) + * + * LOG(x...) + * print a debug message x (in printf format) + * + * romstart() + * returns the start address of the ROM image, or 0xffffffff if ROM is + * top-aligned. This is a physical address. + * + * romend() + * returns the highest address of the ROM image + 1, for use if + * romstart() == 0xffffffff. This is a physical address. + */ + +#include <cbfs_core.h> + + +/* returns pointer to master header or 0xffffffff if not found */ +static struct cbfs_header *get_cbfs_header(void) +{ + struct cbfs_header *header; + + /* find header */ + if (romstart() == 0xffffffff) { + header = (struct cbfs_header*)phys_to_virt(*(uint32_t*)phys_to_virt(romend() + CBFS_HEADPTR_ADDR)); + } else { + // FIXME: where's the master header on ARM (our current bottom-aligned platform)? + header = NULL; + } + if (CBFS_HEADER_MAGIC != ntohl(header->magic)) { + ERROR("Could not find valid CBFS master header at %p: %x vs %x.\n", header, CBFS_HEADER_MAGIC, ntohl(header->magic)); + if (header->magic == 0xffffffff) { + ERROR("Maybe ROM is not mapped properly?\n"); + } + return (void*)0xffffffff; + } + return header; +} + +// by must be power-of-two +#define CBFS_ALIGN(val, by) (typeof(val))((uint32_t)(val + by - 1) & (uint32_t)~(by - 1)) +#define CBFS_ALIGN_UP(val, by) CBFS_ALIGN(val + 1, by) + +/* public API starts here*/ +struct cbfs_file *cbfs_find(const char *name) +{ + struct cbfs_header *header = get_cbfs_header(); + if (header == (void*)0xffffffff) return NULL; + + LOG("Searching for %s\n", name); + + void *data, *dataend, *origdata; + /* find first entry */ + if (romstart() == 0xffffffff) { + data = (void*)phys_to_virt(romend()) - ntohl(header->romsize) + ntohl(header->offset); + dataend = (void*)phys_to_virt(romend()); + } else { + data = (void*)phys_to_virt(romstart()) + ntohl(header->offset); + dataend = (void*)phys_to_virt(romstart()) + ntohl(header->romsize); + } + + int align = ntohl(header->align); + + origdata = data; + while ((data < (dataend - 1)) && (data >= origdata)) { + struct cbfs_file *file = data; + if (memcmp(CBFS_FILE_MAGIC, file->magic, strlen(CBFS_FILE_MAGIC)) != 0) { + // no file header found. corruption? + // proceed in aligned steps to resynchronize + LOG("No file header found at %p, searching for header\n", data); + data = phys_to_virt(CBFS_ALIGN_UP(virt_to_phys(data), align)); + continue; + } + LOG("Check %s\n", CBFS_NAME(file)); + if (strcmp(CBFS_NAME(file), name) == 0) { + return file; + } + void *olddata = data; + data = phys_to_virt(CBFS_ALIGN(virt_to_phys(data) + ntohl(file->len) + ntohl(file->offset), align)); + if (olddata > data) { + LOG("Something is wrong here. File chain moved from %p to %p\n", olddata, data); + return NULL; + } + } + return NULL; +} + +void *cbfs_get_file(const char *name) +{ + struct cbfs_file *file = cbfs_find(name); + + if (file == NULL) { + ERROR("Could not find file '%s'.\n", name); + return NULL; + } + + return (void*)CBFS_SUBHEADER(file); +} + +void *cbfs_find_file(const char *name, int type) +{ + struct cbfs_file *file = cbfs_find(name); + + if (file == NULL) { + ERROR("Could not find file '%s'.\n", name); + return NULL; + } + + if (ntohl(file->type) != type) { + ERROR("File '%s' is of type %x, but we requested %x.\n", name, ntohl(file->type), type); + return NULL; + } + + return (void*)CBFS_SUBHEADER(file); +} + +int cbfs_decompress(int algo, void *src, void *dst, int len) +{ + switch (algo) { + case CBFS_COMPRESS_NONE: + memcpy(dst, src, len); + return 0; +#ifdef CBFS_CORE_WITH_LZMA + case CBFS_COMPRESS_LZMA: + if (ulzma(src, dst) != 0) { + return 0; + } + return -1; +#endif + default: + ERROR("tried to decompress %d bytes with algorithm #%x, but that algorithm id is unsupported.\n", len, algo); + return -1; + } +} + diff --git a/payloads/libpayload/liblzma/Makefile.inc b/payloads/libpayload/liblzma/Makefile.inc new file mode 100644 index 0000000..2dd4a2d --- /dev/null +++ b/payloads/libpayload/liblzma/Makefile.inc @@ -0,0 +1,31 @@ +## +## This file is part of the libpayload project. +## +## Copyright (C) 2011 secunet Security Networks AG +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions +## are met: +## 1. Redistributions of source code must retain the above copyright +## notice, this list of conditions and the following disclaimer. +## 2. Redistributions in binary form must reproduce the above copyright +## notice, this list of conditions and the following disclaimer in the +## documentation and/or other materials provided with the distribution. +## 3. The name of the author may not be used to endorse or promote products +## derived from this software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +## SUCH DAMAGE. +## + +liblzma-$(CONFIG_LZMA) += lzma.c + diff --git a/payloads/libpayload/liblzma/lzma.c b/payloads/libpayload/liblzma/lzma.c new file mode 100644 index 0000000..fdda30d --- /dev/null +++ b/payloads/libpayload/liblzma/lzma.c @@ -0,0 +1,47 @@ +/* + * coreboot interface to memory-saving variant of LZMA decoder + * + * Copyright (C) 2006 Carl-Daniel Hailfinger + * Released under the BSD license + * + * Parts of this file are based on C/7zip/Compress/LZMA_C/LzmaTest.c from the LZMA + * SDK 4.42, which is written and distributed to public domain by Igor Pavlov. + * + */ + +#include <lzma.h> +#include <stdio.h> +#include <string.h> +#include "lzmadecode.c" + +unsigned long ulzma(unsigned char * src, unsigned char * dst) +{ + unsigned char properties[LZMA_PROPERTIES_SIZE]; + UInt32 outSize; + SizeT inProcessed; + SizeT outProcessed; + int res; + CLzmaDecoderState state; + SizeT mallocneeds; + unsigned char scratchpad[15980]; + + memcpy(properties, src, LZMA_PROPERTIES_SIZE); + outSize = *(UInt32 *)(src + LZMA_PROPERTIES_SIZE); + if (LzmaDecodeProperties(&state.Properties, properties, LZMA_PROPERTIES_SIZE) != LZMA_RESULT_OK) { + printf("lzma: Incorrect stream properties.\n"); + return 0; + } + mallocneeds = (LzmaGetNumProbs(&state.Properties) * sizeof(CProb)); + if (mallocneeds > 15980) { + printf("lzma: Decoder scratchpad too small!\n"); + return 0; + } + state.Probs = (CProb *)scratchpad; + res = LzmaDecode(&state, src + LZMA_PROPERTIES_SIZE + 8, (SizeT)0xffffffff, &inProcessed, + dst, outSize, &outProcessed); + if (res != 0) { + printf("lzma: Decoding error = %d\n", res); + return 0; + } + return outSize; +} diff --git a/payloads/libpayload/liblzma/lzmadecode.c b/payloads/libpayload/liblzma/lzmadecode.c new file mode 100644 index 0000000..1cf647d --- /dev/null +++ b/payloads/libpayload/liblzma/lzmadecode.c @@ -0,0 +1,398 @@ +/* + LzmaDecode.c + LZMA Decoder (optimized for Speed version) + + LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01) + http://www.7-zip.org/ + + LZMA SDK is licensed under two licenses: + 1) GNU Lesser General Public License (GNU LGPL) + 2) Common Public License (CPL) + It means that you can select one of these two licenses and + follow rules of that license. + + SPECIAL EXCEPTION: + Igor Pavlov, as the author of this Code, expressly permits you to + statically or dynamically link your Code (or bind by name) to the + interfaces of this file without subjecting your linked Code to the + terms of the CPL or GNU LGPL. Any modifications or additions + to this file, however, are subject to the LGPL or CPL terms. +*/ + +#include "lzmadecode.h" + +#define kNumTopBits 24 +#define kTopValue ((UInt32)1 << kNumTopBits) + +#define kNumBitModelTotalBits 11 +#define kBitModelTotal (1 << kNumBitModelTotalBits) +#define kNumMoveBits 5 + +#define RC_READ_BYTE (*Buffer++) + +#define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \ + { int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }} + + +#define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; } + +#define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2 + + +#define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; } + +#define IfBit0(p) RC_NORMALIZE; bound = (Range >> kNumBitModelTotalBits) * *(p); if (Code < bound) +#define UpdateBit0(p) Range = bound; *(p) += (kBitModelTotal - *(p)) >> kNumMoveBits; +#define UpdateBit1(p) Range -= bound; Code -= bound; *(p) -= (*(p)) >> kNumMoveBits; + +#define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \ + { UpdateBit0(p); mi <<= 1; A0; } else \ + { UpdateBit1(p); mi = (mi + mi) + 1; A1; } + +#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;) + +#define RangeDecoderBitTreeDecode(probs, numLevels, res) \ + { int i = numLevels; res = 1; \ + do { CProb *cp = probs + res; RC_GET_BIT(cp, res) } while(--i != 0); \ + res -= (1 << numLevels); } + + +#define kNumPosBitsMax 4 +#define kNumPosStatesMax (1 << kNumPosBitsMax) + +#define kLenNumLowBits 3 +#define kLenNumLowSymbols (1 << kLenNumLowBits) +#define kLenNumMidBits 3 +#define kLenNumMidSymbols (1 << kLenNumMidBits) +#define kLenNumHighBits 8 +#define kLenNumHighSymbols (1 << kLenNumHighBits) + +#define LenChoice 0 +#define LenChoice2 (LenChoice + 1) +#define LenLow (LenChoice2 + 1) +#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits)) +#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits)) +#define kNumLenProbs (LenHigh + kLenNumHighSymbols) + + +#define kNumStates 12 +#define kNumLitStates 7 + +#define kStartPosModelIndex 4 +#define kEndPosModelIndex 14 +#define kNumFullDistances (1 << (kEndPosModelIndex >> 1)) + +#define kNumPosSlotBits 6 +#define kNumLenToPosStates 4 + +#define kNumAlignBits 4 +#define kAlignTableSize (1 << kNumAlignBits) + +#define kMatchMinLen 2 + +#define IsMatch 0 +#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax)) +#define IsRepG0 (IsRep + kNumStates) +#define IsRepG1 (IsRepG0 + kNumStates) +#define IsRepG2 (IsRepG1 + kNumStates) +#define IsRep0Long (IsRepG2 + kNumStates) +#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax)) +#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits)) +#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex) +#define LenCoder (Align + kAlignTableSize) +#define RepLenCoder (LenCoder + kNumLenProbs) +#define Literal (RepLenCoder + kNumLenProbs) + +#if Literal != LZMA_BASE_SIZE +StopCompilingDueBUG +#endif + +int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size) +{ + unsigned char prop0; + if (size < LZMA_PROPERTIES_SIZE) + return LZMA_RESULT_DATA_ERROR; + prop0 = propsData[0]; + if (prop0 >= (9 * 5 * 5)) + return LZMA_RESULT_DATA_ERROR; + { + for (propsRes->pb = 0; prop0 >= (9 * 5); propsRes->pb++, prop0 -= (9 * 5)); + for (propsRes->lp = 0; prop0 >= 9; propsRes->lp++, prop0 -= 9); + propsRes->lc = prop0; + /* + unsigned char remainder = (unsigned char)(prop0 / 9); + propsRes->lc = prop0 % 9; + propsRes->pb = remainder / 5; + propsRes->lp = remainder % 5; + */ + } + + return LZMA_RESULT_OK; +} + +#define kLzmaStreamWasFinishedId (-1) + +int LzmaDecode(CLzmaDecoderState *vs, + const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed, + unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed) +{ + CProb *p = vs->Probs; + SizeT nowPos = 0; + Byte previousByte = 0; + UInt32 posStateMask = (1 << (vs->Properties.pb)) - 1; + UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1; + int lc = vs->Properties.lc; + + + int state = 0; + UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1; + int len = 0; + const Byte *Buffer; + const Byte *BufferLim; + UInt32 Range; + UInt32 Code; + + *inSizeProcessed = 0; + *outSizeProcessed = 0; + + { + UInt32 i; + UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp)); + for (i = 0; i < numProbs; i++) + p[i] = kBitModelTotal >> 1; + } + + RC_INIT(inStream, inSize); + + + while(nowPos < outSize) + { + CProb *prob; + UInt32 bound; + int posState = (int)( + (nowPos + ) + & posStateMask); + + prob = p + IsMatch + (state << kNumPosBitsMax) + posState; + IfBit0(prob) + { + int symbol = 1; + UpdateBit0(prob) + prob = p + Literal + (LZMA_LIT_SIZE * + ((( + (nowPos + ) + & literalPosMask) << lc) + (previousByte >> (8 - lc)))); + + if (state >= kNumLitStates) + { + int matchByte; + matchByte = outStream[nowPos - rep0]; + do + { + int bit; + CProb *probLit; + matchByte <<= 1; + bit = (matchByte & 0x100); + probLit = prob + 0x100 + bit + symbol; + RC_GET_BIT2(probLit, symbol, if (bit != 0) break, if (bit == 0) break) + } + while (symbol < 0x100); + } + while (symbol < 0x100) + { + CProb *probLit = prob + symbol; + RC_GET_BIT(probLit, symbol) + } + previousByte = (Byte)symbol; + + outStream[nowPos++] = previousByte; + if (state < 4) state = 0; + else if (state < 10) state -= 3; + else state -= 6; + } + else + { + UpdateBit1(prob); + prob = p + IsRep + state; + IfBit0(prob) + { + UpdateBit0(prob); + rep3 = rep2; + rep2 = rep1; + rep1 = rep0; + state = state < kNumLitStates ? 0 : 3; + prob = p + LenCoder; + } + else + { + UpdateBit1(prob); + prob = p + IsRepG0 + state; + IfBit0(prob) + { + UpdateBit0(prob); + prob = p + IsRep0Long + (state << kNumPosBitsMax) + posState; + IfBit0(prob) + { + UpdateBit0(prob); + + if (nowPos == 0) + return LZMA_RESULT_DATA_ERROR; + + state = state < kNumLitStates ? 9 : 11; + previousByte = outStream[nowPos - rep0]; + outStream[nowPos++] = previousByte; + + continue; + } + else + { + UpdateBit1(prob); + } + } + else + { + UInt32 distance; + UpdateBit1(prob); + prob = p + IsRepG1 + state; + IfBit0(prob) + { + UpdateBit0(prob); + distance = rep1; + } + else + { + UpdateBit1(prob); + prob = p + IsRepG2 + state; + IfBit0(prob) + { + UpdateBit0(prob); + distance = rep2; + } + else + { + UpdateBit1(prob); + distance = rep3; + rep3 = rep2; + } + rep2 = rep1; + } + rep1 = rep0; + rep0 = distance; + } + state = state < kNumLitStates ? 8 : 11; + prob = p + RepLenCoder; + } + { + int numBits, offset; + CProb *probLen = prob + LenChoice; + IfBit0(probLen) + { + UpdateBit0(probLen); + probLen = prob + LenLow + (posState << kLenNumLowBits); + offset = 0; + numBits = kLenNumLowBits; + } + else + { + UpdateBit1(probLen); + probLen = prob + LenChoice2; + IfBit0(probLen) + { + UpdateBit0(probLen); + probLen = prob + LenMid + (posState << kLenNumMidBits); + offset = kLenNumLowSymbols; + numBits = kLenNumMidBits; + } + else + { + UpdateBit1(probLen); + probLen = prob + LenHigh; + offset = kLenNumLowSymbols + kLenNumMidSymbols; + numBits = kLenNumHighBits; + } + } + RangeDecoderBitTreeDecode(probLen, numBits, len); + len += offset; + } + + if (state < 4) + { + int posSlot; + state += kNumLitStates; + prob = p + PosSlot + + ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << + kNumPosSlotBits); + RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot); + if (posSlot >= kStartPosModelIndex) + { + int numDirectBits = ((posSlot >> 1) - 1); + rep0 = (2 | ((UInt32)posSlot & 1)); + if (posSlot < kEndPosModelIndex) + { + rep0 <<= numDirectBits; + prob = p + SpecPos + rep0 - posSlot - 1; + } + else + { + numDirectBits -= kNumAlignBits; + do + { + RC_NORMALIZE + Range >>= 1; + rep0 <<= 1; + if (Code >= Range) + { + Code -= Range; + rep0 |= 1; + } + } + while (--numDirectBits != 0); + prob = p + Align; + rep0 <<= kNumAlignBits; + numDirectBits = kNumAlignBits; + } + { + int i = 1; + int mi = 1; + do + { + CProb *prob3 = prob + mi; + RC_GET_BIT2(prob3, mi, ; , rep0 |= i); + i <<= 1; + } + while(--numDirectBits != 0); + } + } + else + rep0 = posSlot; + if (++rep0 == (UInt32)(0)) + { + /* it's for stream version */ + len = kLzmaStreamWasFinishedId; + break; + } + } + + len += kMatchMinLen; + if (rep0 > nowPos) + return LZMA_RESULT_DATA_ERROR; + + + do + { + previousByte = outStream[nowPos - rep0]; + len--; + outStream[nowPos++] = previousByte; + } + while(len != 0 && nowPos < outSize); + } + } + RC_NORMALIZE; + + + *inSizeProcessed = (SizeT)(Buffer - inStream); + *outSizeProcessed = nowPos; + return LZMA_RESULT_OK; +} diff --git a/payloads/libpayload/liblzma/lzmadecode.h b/payloads/libpayload/liblzma/lzmadecode.h new file mode 100644 index 0000000..34c9f14 --- /dev/null +++ b/payloads/libpayload/liblzma/lzmadecode.h @@ -0,0 +1,67 @@ +/* + LzmaDecode.h + LZMA Decoder interface + + LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01) + http://www.7-zip.org/ + + LZMA SDK is licensed under two licenses: + 1) GNU Lesser General Public License (GNU LGPL) + 2) Common Public License (CPL) + It means that you can select one of these two licenses and + follow rules of that license. + + SPECIAL EXCEPTION: + Igor Pavlov, as the author of this code, expressly permits you to + statically or dynamically link your code (or bind by name) to the + interfaces of this file without subjecting your linked code to the + terms of the CPL or GNU LGPL. Any modifications or additions + to this file, however, are subject to the LGPL or CPL terms. +*/ + +#ifndef __LZMADECODE_H +#define __LZMADECODE_H + +typedef unsigned char Byte; +typedef unsigned short UInt16; +typedef unsigned int UInt32; +typedef UInt32 SizeT; + +#define CProb UInt16 + +#define LZMA_RESULT_OK 0 +#define LZMA_RESULT_DATA_ERROR 1 + + +#define LZMA_BASE_SIZE 1846 +#define LZMA_LIT_SIZE 768 + +#define LZMA_PROPERTIES_SIZE 5 + +typedef struct _CLzmaProperties +{ + int lc; + int lp; + int pb; +}CLzmaProperties; + +int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size); + +#define LzmaGetNumProbs(Properties) (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((Properties)->lc + (Properties)->lp))) + +#define kLzmaNeedInitId (-2) + +typedef struct _CLzmaDecoderState +{ + CLzmaProperties Properties; + CProb *Probs; + + +} CLzmaDecoderState; + + +int LzmaDecode(CLzmaDecoderState *vs, + const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed, + unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed); + +#endif

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new coreboot twitter account
by Stefan Tauner 28 Jul '11

28 Jul '11

hi there! not so sure this justifies spam, but i have set up a twitter account for coreboot (and flashrom): http://twitter.com/coreboot_org the current plan is to setup a wordpress plugin to push headlines of new blog posts there. currently marjc, stepan and i know the password (at least)... just in case. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [coreboot] Questions about the resource allocator of PCI
by Marc Jones 28 Jul '11

28 Jul '11

On Thu, Jul 28, 2011 at 5:44 AM, Hamo <hamo.by(a)gmail.com> wrote: > On Thu, Jul 28, 2011 at 7:00 PM, Patrick Georgi > <Patrick.Georgi(a)secunet.com> wrote: >> For static regions, we have IORESOURCE_FIXED. Look up that symbol in the >> coreboot code to see how it's used. >> >> You will need to determine a good place for where to define those, >> either per board (eg. mainboard.c) or per coreboot device driver >> (whereever these drivers belong to). >> > Thanks Patrick. Thanks for your quick reply. I tried your idea by > adding those resources to the PCI DOMAIN 0: > int idx = 1; > struct resource *iores; > iores = new_resource(dev, idx++); > iores->base = (resource_t)0x43000000; > iores->size = (resource_t)(16 << 20); > iores->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_ASSIGNED; > iores->limit = 0xffffffffUL; > > struct resource *memres1; > memres1 = new_resource(dev, idx++); > memres1->base = (resource_t)0x50000000; > memres1->size = (resource_t)(256 << 20); > memres1->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_ASSIGNED; > memres1->limit = 0xffffffffUL; > > struct resource *memres2; > memres2 = new_resource(dev, idx++); > memres2->base = (resource_t)0x60000000; > memres2->size = (resource_t)(256 << 20); > memres2->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | > IORESOURCE_FIXED | IORESOURCE_ASSIGNED; > memres2->limit = 0xffffffffUL; > > resources reading show this: > Show resources in subtree (Root Device)...After reading. > Root Device child on link 0 PCI_DOMAIN: 0000 > Root Device resource base 0 size 8000000 align 0 gran 0 limit 0 flags > e0004200 index 0 > PCI_DOMAIN: 0000 child on link 0 PCI: 00:0b.0 > PCI_DOMAIN: 0000 resource base 43000000 size 1000000 align 0 gran 0 > limit ffffffff flags c0000100 index 10000000 > PCI_DOMAIN: 0000 resource base 50000000 size 10000000 align 0 gran 0 > limit ffffffff flags c0000200 index 10000100 > PCI_DOMAIN: 0000 resource base 60000000 size 10000000 align 0 gran 0 > limit ffffffff flags c0001200 index 10000200 > PCI: 00:0b.0 > PCI: 00:0c.0 > PCI: 00:0c.0 resource base 0 size 100 align 8 gran 8 limit ffff > flags 100 index 10 > PCI: 00:0c.0 resource base 0 size 400 align 10 gran 10 limit > ffffffff flags 200 index 14 > PCI: 00:0c.0 resource base 0 size 2000 align 13 gran 13 limit > ffffffff flags 200 index 18 > > But after assigning, it shows: > Show resources in subtree (Root Device)...After assigning values. > Root Device child on link 0 PCI_DOMAIN: 0000 > Root Device resource base 0 size 8000000 align 0 gran 0 limit 0 flags > e0004200 index 0 > PCI_DOMAIN: 0000 child on link 0 PCI: 00:0b.0 > PCI_DOMAIN: 0000 resource base 43000000 size 1000000 align 0 gran 0 > limit ffffffff flags c0000100 index 10000000 > PCI_DOMAIN: 0000 resource base 50000000 size 10000000 align 0 gran 0 > limit ffffffff flags c0000200 index 10000100 > PCI_DOMAIN: 0000 resource base 60000000 size 10000000 align 0 gran 0 > limit ffffffff flags c0001200 index 10000200 > PCI: 00:0b.0 > PCI: 00:0c.0 > PCI: 00:0c.0 resource base 0 size 100 align 8 gran 8 limit ffff > flags 100 index 10 > PCI: 00:0c.0 resource base 0 size 400 align 10 gran 10 limit > ffffffff flags 200 index 14 > PCI: 00:0c.0 resource base 0 size 2000 align 13 gran 13 limit > ffffffff flags 200 index 18 > > I think I misunderstanding your idea. Could you please explain it in detail? > IORESOURCE_IO? MMIO is memory. Are these devices on the PCI bus or on the root bus? I am not certain how the allocator handles root vs PCI, which is why I ask. For x86 the CPUs APIC area is reserved and not on the PCI bus. Marc -- http://se-eng.com

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Re: [coreboot] Questions about the resource allocator of PCI
by Patrick Georgi 28 Jul '11

28 Jul '11

Am Donnerstag, den 28.07.2011, 18:27 +0800 schrieb Hamo: > But this is different on ARM. Every PCI device's memory address space > should be in a certain address space provided by CPU and IO address > space should be in another, like MMIO on X86. For my versatile PB > board, the address space is at here.[2] > I tried some ways and talked with my mentor about it, but we didn't > find a way to tell dev_configure to allocate device's mem and IO > address in the certain address space. For static regions, we have IORESOURCE_FIXED. Look up that symbol in the coreboot code to see how it's used. You will need to determine a good place for where to define those, either per board (eg. mainboard.c) or per coreboot device driver (whereever these drivers belong to). Patrick -- Patrick Georgi Fachbereich SINA-Entwicklung Geschäftsbereich Hochsicherheit secunet Security Networks AG Mergenthalerallee 77 65760 Eschborn, Germany Telefon +49 201 54 54-3610 Telefax +49 201 54 54-1325 Patrick.Georgi(a)secunet.com www.secunet.com Sitz: Kronprinzenstraße 30, 45128 Essen Amtsgericht Essen HRB 13615 Vorstand: Dr. Rainer Baumgart (Vors.), Thomas Koelzer, Thomas Pleines Aufsichtsratsvorsitzender: Dr. Karsten Ottenberg

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Questions about the resource allocator of PCI
by Hamo 28 Jul '11

28 Jul '11

Hi lists, I have moved forward to the PCI part. Now coreboot can enumerate the PCI devices but got some problems about allocating resources to the PCI devices. As I know, on X86, the IO address space is below 0xffff [1] and the memory address is from the top of address space (say, 0xffffffff) down. Those resources for every PCI devices will be allocated by the dev_configure function automatically. But this is different on ARM. Every PCI device's memory address space should be in a certain address space provided by CPU and IO address space should be in another, like MMIO on X86. For my versatile PB board, the address space is at here.[2] I tried some ways and talked with my mentor about it, but we didn't find a way to tell dev_configure to allocate device's mem and IO address in the certain address space. Can you help me on this? I have searched the mailing lists and found some information about the MMIO PCI I/O address space, but all of them don't make a conclusion. [1]http://www.coreboot.org/pipermail/coreboot/2010-May/058384.html [2]http://infocenter.arm.com/help/topic/com.arm.doc.dui0224i/Bbajjbce.html#C… (Table 4.49) Thanks, Hamo

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New patch to review: 34c80fc cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.
by Keith Hui 28 Jul '11

28 Jul '11

Keith Hui (buurin(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/122 -gerrit commit 34c80fc9097f9ba73667bfc6b6ac13003afe2b3b Author: Keith Hui <buurin(a)gmail.com> Date: Wed Jul 27 23:06:16 2011 -0400 cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs. Bring from coreboot v1 support for initializing L2 cache on Slot 1 Pentium II/III CPUs, code names Klamath, Deschutes and Katmai. Build tested on ASUS P2B-LS and P3B-F. Boot tested on P2B-LS with Pentium III 600MHz, Katmai core. Also add missing include of model_68x in slot_1, to address a similar problem seen before r5945. Change-Id: I502e8481d1a20f0a2504685e7be16b57f59c8257 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- src/cpu/intel/model_65x/model_65x_init.c | 3 + src/cpu/intel/model_67x/model_67x_init.c | 4 + src/cpu/intel/slot_1/Makefile.inc | 2 + src/cpu/intel/slot_1/l2_cache.c | 810 ++++++++++++++++++++++++++++++ src/include/cpu/intel/l2_cache.h | 102 ++++ 5 files changed, 921 insertions(+), 0 deletions(-) diff --git a/src/cpu/intel/model_65x/model_65x_init.c b/src/cpu/intel/model_65x/model_65x_init.c index 8f9fc66..dc889d8 100644 --- a/src/cpu/intel/model_65x/model_65x_init.c +++ b/src/cpu/intel/model_65x/model_65x_init.c @@ -27,6 +27,7 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> +#include <cpu/intel/l2_cache.h> static u32 microcode_updates[] = { #include "microcode-410-MU16522d.h" @@ -64,6 +65,8 @@ static void model_65x_init(device_t dev) /* Update the microcode */ intel_update_microcode(microcode_updates); + p6_configure_l2_cache(); + /* Enable the local cpu apics */ setup_lapic(); }; diff --git a/src/cpu/intel/model_67x/model_67x_init.c b/src/cpu/intel/model_67x/model_67x_init.c index 76a840e..12cb3a1 100644 --- a/src/cpu/intel/model_67x/model_67x_init.c +++ b/src/cpu/intel/model_67x/model_67x_init.c @@ -26,6 +26,7 @@ #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> #include <cpu/x86/msr.h> +#include <cpu/intel/l2_cache.h> static const uint32_t microcode_updates[] = { /* Include microcode updates here. */ @@ -46,6 +47,9 @@ static void model_67x_init(device_t cpu) /* Update the microcode */ intel_update_microcode(microcode_updates); + /* Initialize L2 cache */ + p6_configure_l2_cache(); + /* Turn on caching if we haven't already */ x86_enable_cache(); diff --git a/src/cpu/intel/slot_1/Makefile.inc b/src/cpu/intel/slot_1/Makefile.inc index 297ef18..a4de6e0 100644 --- a/src/cpu/intel/slot_1/Makefile.inc +++ b/src/cpu/intel/slot_1/Makefile.inc @@ -19,9 +19,11 @@ ## ramstage-y += slot_1.c +ramstage-y += l2_cache.c subdirs-y += ../model_6xx subdirs-y += ../model_65x subdirs-y += ../model_67x +subdirs-y += ../model_68x subdirs-y += ../model_6bx subdirs-y += ../../x86/tsc subdirs-y += ../../x86/mtrr diff --git a/src/cpu/intel/slot_1/l2_cache.c b/src/cpu/intel/slot_1/l2_cache.c new file mode 100644 index 0000000..9185722 --- /dev/null +++ b/src/cpu/intel/slot_1/l2_cache.c @@ -0,0 +1,810 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 Denis Dowling <dpd(a)alphalink.com.au> + * Copyright (C) 2010 Keith Hui <buurin(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Intel Pentium L2 Cache initialization. + * This code was developed by reverse engineering + * the BIOS. Where the code accesses documented + * registers I have added comments as best I can. + * Some undocumented registers on the Pentium II are + * used so some of the documentation is incomplete. + * + * References: + * Intel Architecture Software Developer's Manual + * Volume 3B: System Programming Guide, Part 2 (#253669) + * Appendix B.9 + */ + +/* This code is ported from coreboot v1. + * The L2 cache initalization sequence here only apply to SECC/SECC2 P6 family + * CPUs with Klamath (63x), Deschutes (65x) and Katmai (67x) cores. + * It is not required for Coppermine (68x) and Tualatin (6bx) cores. + * It is currently not known if Celerons with Mendocino (66x) core require the + * special initialization. + * Covington-core Celerons do not have L2 cache. + */ + +#include <stdint.h> +#include <console/console.h> +#include <string.h> +#include <cpu/cpu.h> +#include <cpu/x86/mtrr.h> +#include <cpu/intel/l2_cache.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/msr.h> + +/* Latency Tables */ +struct latency_entry { + u8 key; + u8 value; +}; +/* +Latency maps for Deschutes and Katmai. +No such mapping is available for Klamath. + +Cache latency to +be written to L2 -----++++ +control register |||| +0000 xx 00 -----> 000 cccc 0 +|||| 00 66MHz +|||| 10 100MHz +|||| 01 133MHz (Katmai "B" only) +++++------ CPU frequency multiplier + +0000 2x +0001 3x +0010 4x +0011 5x +0100 2.5x +0101 3.5x +0110 4.5x +0111 5.5x +1000 6x +1001 7x +1010 8x +1011 Reserved +1100 6.5x +1101 7.5x +1110 1.5x +1111 2x + +*/ +static const struct latency_entry latency_650_t0[] = { + {0x10, 0x02}, {0x50, 0x02}, {0x20, 0x04}, {0x60, 0x06}, + {0x00, 0x08}, {0x40, 0x0C}, {0x12, 0x06}, {0x52, 0x0A}, + {0x22, 0x0E}, {0x62, 0x10}, {0x02, 0x10}, {0xFF, 0x00} +}; + +static const struct latency_entry latency_650_t1[] = { + {0x12, 0x14}, {0x52, 0x16}, {0x22, 0x16}, {0x62, 0x16}, + {0xFF, 0x00} +}; + +static const struct latency_entry latency_670_t0[] = { + {0x60, 0x06}, {0x00, 0x08}, {0x12, 0x06}, {0x52, 0x0A}, + {0x22, 0x0E}, {0x62, 0x10}, {0x02, 0x10}, {0x42, 0x02}, + {0x11, 0x0E}, {0x51, 0x0C}, {0x21, 0x02}, {0x61, 0x10}, + {0x01, 0x10}, {0x41, 0x02}, {0xFF, 0x00} +}; + +static const struct latency_entry latency_670_t1[] = { + {0x22, 0x18}, {0x62, 0x18}, {0x02, 0x1A}, {0x11, 0x18}, + {0xFF, 0x00} +}; + +static const struct latency_entry latency_670_t2[] = { + {0x22, 0x12}, {0x62, 0x14}, {0x02, 0x16}, {0x42, 0x1E}, + {0x11, 0x12}, {0x51, 0x16}, {0x21, 0x1E}, {0x61, 0x14}, + {0x01, 0x16}, {0x41, 0x1E}, {0xFF, 0x00} +}; + +/* Latency tables for 650 model/type */ +static const struct latency_entry *latency_650[] = { + latency_650_t0, latency_650_t1, latency_650_t1 +}; + +/* Latency tables for 670 model/type */ +static const struct latency_entry *latency_670[] = { + latency_670_t0, latency_670_t1, latency_670_t2 +}; + +int calculate_l2_latency(void) +{ + u32 eax, l, signature; + const struct latency_entry *latency_table, *le; + msr_t msr; + + /* First, attempt to get cache latency value from + IA32_PLATFORM_ID[56:53]. (L2 Cache Latency Read) + */ + msr = rdmsr(IA32_PLATFORM_ID); + + printk(BIOS_DEBUG,"rdmsr(IA32_PLATFORM_ID) = %x:%x\n", msr.hi, msr.lo); + + l = (msr.hi >> 20) & 0x1e; + + if (l == 0) { + /* If latency value isn't available from + IA32_PLATFORM_ID[56:53], read it from + L2 control register 0 for lookup from + tables. */ + int t, a; + + /* The raw code is read from L2 register 0, bits [7:4]. */ + a = read_l2(0); + if (a < 0) + return -1; + + a &= 0xf0; + + if ((a & 0x20) == 0) + t = 0; + else if (a == 0x20) + t = 1; + else if (a == 0x30) + t = 2; + else + return -1; + + printk(BIOS_DEBUG,"L2 latency type = %x\n", t); + + /* Get CPUID family/model */ + signature = cpuid_eax(1) & 0xfff0; + + /* Read EBL_CR_POWERON */ + msr = rdmsr(EBL_CR_POWERON); + /* Get clock multiplier and FSB frequency. + * Multiplier is in [25:22]. + * FSB is in [19:18] in Katmai, [19] in Deschutes ([18] is zero for them). + */ + eax = msr.lo >> 18; + if (signature == 0x650) { + eax &= ~0xf2; + latency_table = latency_650[t]; + } else if (signature == 0x670) { + eax &= ~0xf3; + latency_table = latency_670[t]; + } else + return -1; + + /* Search table for matching entry */ + for (le = latency_table; le->key != eax; le++) { + /* Fail if we get to the end of the table */ + if (le->key == 0xff) { + printk(BIOS_DEBUG, "Could not find key %02x in latency table\n", eax); + return -1; + } + } + + l = le->value; + } + + printk(BIOS_DEBUG,"L2 Cache latency is %d\n", l / 2); + + /* Writes the calculated latency in BBL_CR_CTL3[4:1]. */ + msr = rdmsr(BBL_CR_CTL3); + msr.lo &= 0xffffffe1; + msr.lo |= l; + wrmsr(BBL_CR_CTL3, msr); + + return 0; +} + + +/* Setup address, data_high:data_low into the L2 + * control registers and then issue command with correct cache way + */ +int signal_l2(u32 address, u32 data_high, u32 data_low, int way, u8 command) +{ + int i; + msr_t msr; + + /* Write L2 Address to BBL_CR_ADDR */ + msr.lo = address; + msr.hi = 0; + wrmsr(BBL_CR_ADDR, msr); + + /* Write data to BBL_CR_D{0..3} */ + msr.lo = data_low; + msr.hi = data_high; + for (i = BBL_CR_D0; i <= BBL_CR_D3; i++) { + wrmsr(i, msr); + } + + /* Put the command and way into BBL_CR_CTL */ + msr = rdmsr(BBL_CR_CTL); + msr.lo = (msr.lo & 0xfffffce0) | command | (way << 8); + wrmsr(BBL_CR_CTL, msr); + + /* Trigger L2 controller */ + msr.lo = 0; + msr.hi = 0; + wrmsr(BBL_CR_TRIG, msr); + + /* Poll the controller to see when done */ + for (i = 0; i < 0x100; i++) { + /* Read BBL_CR_BUSY */ + msr = rdmsr(BBL_CR_BUSY); + /* If not busy then return */ + if ((msr.lo & 1) == 0) + return 0; + } + + /* Return timeout code */ + return -1; +} + +/* Read the L2 Cache controller register at given address */ +int read_l2(u32 address) +{ + msr_t msr; + + /* Send a L2 Control Register Read to L2 controller */ + if (signal_l2(address << 5, 0, 0, 0, L2CMD_CR) != 0) + return -1; + + /* If OK then get the result from BBL_CR_ADDR */ + msr = rdmsr(BBL_CR_ADDR); + return (msr.lo >> 0x15); + +} + +/* Write data into the L2 controller register at address */ +int write_l2(u32 address, u32 data) +{ + int v1, v2, i; + + v1 = read_l2(0); + if (v1 < 0) + return -1; + + v2 = read_l2(2); + if (v2 < 0) + return -1; + + if ((v1 & 0x20) == 0) { + v2 &= 0x3; + v2++; + } else + v2 &= 0x7; + + /* This write has to be replicated to a number of places. Not sure what. */ + + for (i = 0; i < v2; i++) { + + u32 data1, data2; + // Bits legend + // data1 = ffffffff + // data2 = 000000dc + // address = 00aaaaaa + // Final address signalled: + // 000fffff fff000c0 000dcaaa aaa00000 + data1 = data & 0xff; + data1 = data1 << 21; + data2 = (i << 11) & 0x1800; + data1 |= data2; + data2 <<= 6; + data2 &= 0x20000; + data1 |= data2; + + /* Signal L2 controller */ + if (signal_l2((address << 5) | data1, 0, 0, 0, 3)) + return -1; + } + return 0; +} + +/* Write data_high:data_low into the cache at address1. Test address2 + * to see if the same data is returned. Return 0 if the data matches. + * return lower 16 bits if mismatched data if mismatch. Return -1 + * on error + */ +int test_l2_address_alias(u32 address1, u32 address2, + u32 data_high, u32 data_low) +{ + int d; + msr_t msr; + + /* Tag Write with Data Write for L2 */ + if (signal_l2(address1, data_high, data_low, 0, L2CMD_TWW)) + return -1; + + /* Tag Read with Data Read for L2 */ + if (signal_l2(address2, 0, 0, 0, L2CMD_TRR)) + return -1; + + /* Read data from BBL_CR_D[0-3] */ + for (d = BBL_CR_D0; d <= BBL_CR_D3; d++) { + msr = rdmsr(d); + if (msr.lo != data_low || msr.hi != data_high) + return (msr.lo & 0xffff); + } + + return 0; +} + +/* Calculates the L2 cache size. + * + * Reference: Intel(R) 64 and IA-32 Architectures Software Developer�s Manual + * Volume 3B: System Programming Guide, Part 2, Intel pub. 253669, pg. B-172. + * + */ +int calculate_l2_cache_size(void) +{ + int v; + msr_t msr; + u32 cache_setting; + u32 address, size, eax, bblcr3; + + v = read_l2(0); + if (v < 0) + return -1; + if ((v & 0x20) == 0) { + msr = rdmsr(BBL_CR_CTL3); + bblcr3 = msr.lo & ~BBLCR3_L2_SIZE; + /* + * Successively write in all the possible cache size per bank + * into BBL_CR_CTL3[17:13], starting from 256KB (00001) to 4MB (10000), + * and read the last value written and accepted by the cache. + * + * No idea why these bits are writable at all. + */ + for (cache_setting = BBLCR3_L2_SIZE_256K; + cache_setting <= BBLCR3_L2_SIZE_4M; cache_setting <<= 1) { + + eax = bblcr3 | cache_setting; + msr.lo = eax; + wrmsr(BBL_CR_CTL3, msr); + msr = rdmsr(BBL_CR_CTL3); + + /* Value not accepted */ + if (msr.lo != eax) + break; + } + + /* Backtrack to the last value that worked... */ + cache_setting >>= 1; + + /* and write it into BBL_CR_CTL3 */ + msr.lo &= ~BBLCR3_L2_SIZE; + msr.lo |= (cache_setting & BBLCR3_L2_SIZE); + + wrmsr(BBL_CR_CTL3, msr); + + printk(BIOS_DEBUG,"Maximum cache mask is %x\n", cache_setting); + + /* For now, BBL_CR_CTL3 has the highest cache "size" that register + * will accept. Now we'll ping the cache and see where it wraps. + */ + + /* Write aaaaaaaa:aaaaaaaa to address 0 in the l2 cache. + * If this "alias test" returns an "address", it means the + * cache cannot be written to properly, and we have a problem. + */ + v = test_l2_address_alias(0, 0, 0xaaaaaaaa, 0xaaaaaaaa); + if (v != 0) + return -1; + + /* Start with 32K wrap point (256KB actually) */ + size = 1; + address = 0x8000; + + while (1) { + v = test_l2_address_alias(address, 0, 0x55555555, + 0x55555555); + // Write failed. + if (v < 0) + return -1; + // It wraps here. + else if (v == 0) + break; + + size <<= 1; + address <<= 1; + + if (address > 0x200000) + return -1; + } + + /* Mask size */ + size &= 0x3e; + + /* Shift to [17:13] */ + size <<= 12; + + /* Set this into BBL_CR_CTL3 */ + msr = rdmsr(BBL_CR_CTL3); + msr.lo &= ~BBLCR3_L2_SIZE; + msr.lo |= size; + wrmsr(BBL_CR_CTL3, msr); + + printk(BIOS_DEBUG,"L2 Cache Mask is %x\n", size); + + /* Shift to [6:2] */ + size >>= 11; + + v = read_l2(2); + + if (v < 0) + return -1; + + printk(BIOS_DEBUG,"L2(2): %x ", v); + + v &= 0x3; + + /* Shift size right by v */ + size >>= v; + + /* Or in this size */ + v |= size; + + printk(BIOS_DEBUG,"-> %x\n", v); + + if (write_l2(2, v) != 0) + return -1; + } else { + // Some cache size information is available from L2 registers. + // Work from there. + int b, c; + + v = read_l2(2); + + printk(BIOS_DEBUG,"L2(2) = %x\n", v); + + if (v < 0) + return -1; + + // L2 register 2 bitmap: cc---bbb + b = v & 0x7; + c = v >> 6; + + v = 1 << c * b; + + v &= 0xf; + + printk(BIOS_DEBUG,"Calculated a = %x\n", v); + + if (v == 0) + return -1; + + /* Shift to 17:14 */ + v <<= 14; + + /* Write this size into BBL_CR_CTL3 */ + msr = rdmsr(BBL_CR_CTL3); + msr.lo &= ~BBLCR3_L2_SIZE; + msr.lo |= v; + wrmsr(BBL_CR_CTL3, msr); + } + + return 0; +} + +// L2 physical address range can be found from L2 control register 3, bits [2:0]. +int calculate_l2_physical_address_range(void) +{ + int r0, r3; + msr_t msr; + + r3 = read_l2(3); + if (r3 < 0) + return -1; + + r0 = read_l2(0); + if (r0 < 0) + return -1; + + if (r0 & 0x20) + r3 = 0x7; + else + r3 &= 0x7; + + printk(BIOS_DEBUG,"L2 Physical Address Range is %dM\n", (1 << r3) * 512); + + /* Shift into [22:20] to be saved into BBL_CR_CTL3. */ + r3 = r3 << 20; + + msr = rdmsr(BBL_CR_CTL3); + msr.lo &= ~BBLCR3_L2_PHYSICAL_RANGE; + msr.lo |= r3; + wrmsr(BBL_CR_CTL3, msr); + + return 0; +} + +int set_l2_ecc(void) +{ + u32 eax; + const u32 data1 = 0xaa55aa55; + const u32 data2 = 0xaaaaaaaa; + msr_t msr; + + /* Set User Supplied ECC in BBL_CR_CTL */ + msr = rdmsr(BBL_CR_CTL); + msr.lo |= BBLCR3_L2_SUPPLIED_ECC; + wrmsr(BBL_CR_CTL, msr); + + /* Write a value into the L2 Data ECC register BBL_CR_DECC */ + msr.lo = data1; + msr.hi = 0; + wrmsr(BBL_CR_DECC, msr); + + if (test_l2_address_alias(0, 0, data2, data2) < 0) + return -1; + + /* Read back ECC from BBL_CR_DECC */ + msr = rdmsr(BBL_CR_DECC); + eax = msr.lo; + + if (eax == data1) { + printk(BIOS_DEBUG,"L2 ECC Checking is enabled\n"); + + /* Set ECC Check Enable in BBL_CR_CTL3 */ + msr = rdmsr(BBL_CR_CTL3); + msr.lo |= BBLCR3_L2_ECC_CHECK_ENABLE; + wrmsr(BBL_CR_CTL3, msr); + } + + /* Clear User Supplied ECC in BBL_CR_CTL */ + msr = rdmsr(BBL_CR_CTL); + msr.lo &= ~BBLCR3_L2_SUPPLIED_ECC; + wrmsr(BBL_CR_CTL, msr); + + return 0; +} + +/* + * This is the function called from CPU initialization + * driver to set up P6 family L2 cache. + */ + +int p6_configure_l2_cache(void) +{ + msr_t msr, bblctl3; + unsigned int eax; + u16 signature; + int cache_size, bank; + int result, calc_eax; + int v, a; + + int badclk1, badclk2, clkratio; + int crctl3_or; + + printk(BIOS_INFO, "Configuring L2 cache... "); + + /* Read BBL_CR_CTL3 */ + bblctl3 = rdmsr(BBL_CR_CTL3); + /* If bit 23 (L2 Hardware disable) is set then done */ + /* These would be Covington core Celerons with no L2 cache */ + if (bblctl3.lo & BBLCR3_L2_NOT_PRESENT) { + printk(BIOS_INFO,"hardware disabled\n"); + return 0; + } + + signature = cpuid_eax(1) & 0xfff0; + + /* Klamath-specific bit settings for certain + preliminary checks. + */ + if (signature == 0x630) { + clkratio = 0x1c00000; + badclk2 = 0x1000000; + crctl3_or = 0x44000; + } else { + clkratio = 0x3c00000; + badclk2 = 0x3000000; + crctl3_or = 0x40000; + } + badclk1 = 0xc00000; + + /* Read EBL_CR_POWERON */ + msr = rdmsr(EBL_CR_POWERON); + eax = msr.lo; + /* Mask out [22-25] Clock frequency ratio */ + eax &= clkratio; + if (eax == badclk1 || eax == badclk2) { + printk(BIOS_ERR, "Incorrect clock frequency ratio %x\n", eax); + return -1; + } + + disable_cache(); + + /* Mask out from BBL_CR_CTL3: + * [0] L2 Configured + * [5] ECC Check Enable + * [6] Address Parity Check Enable + * [7] CRTN Parity Check Enable + * [8] L2 Enabled + * [12:11] Number of L2 banks + * [17:13] Cache size per bank + * [18] (Set below) + * [22:20] L2 Physical Address Range Support + */ + bblctl3.lo &= 0xff88061e; + /* Set: + * [17:13] = 00010 = 512Kbyte Cache size per bank (63x) + * [17:13] = 00000 = 128Kbyte Cache size per bank (all others) + * [18] Cache state error checking enable + */ + bblctl3.lo |= crctl3_or; + + /* Write BBL_CR_CTL3 */ + wrmsr(BBL_CR_CTL3, bblctl3); + + if (signature != 0x630) { + eax = bblctl3.lo; + + /* Set the l2 latency in BBL_CR_CTL3 */ + if (calculate_l2_latency() != 0) + goto bad; + + /* Read the new latency values back */ + bblctl3 = rdmsr(BBL_CR_CTL3); + calc_eax = bblctl3.lo; + + /* Write back the original default value */ + bblctl3.lo = eax; + wrmsr(BBL_CR_CTL3, bblctl3); + + /* Write BBL_CR_CTL3[27:26] (reserved??) to bits [1:0] of L2 register 4. + * Apparently all other bits must be preserved, hence these code. + */ + + v = (calc_eax >> 26) & 0x3; + + printk(BIOS_DEBUG,"write_l2(4, %x)\n", v); + + a = read_l2(4); + if (a >= 0) + { + a &= 0xfffc; + a |= v; + a = write_l2(4, a); + /* a now contains result code from write_l2() */ + } + if (a != 0) + goto bad; + + /* Restore the correct latency value into BBL_CR_CTL3 */ + bblctl3.lo = calc_eax; + wrmsr(BBL_CR_CTL3, bblctl3); + } /* ! 63x CPU */ + + /* Read L2 register 0 */ + v = read_l2(0); + + /* If L2(0)[5] set (and can be read properly), enable CRTN and address parity + */ + if (v >= 0 && (v & 0x20)) { + bblctl3 = rdmsr(BBL_CR_CTL3); + bblctl3.lo |= (BBLCR3_L2_ADDR_PARITY_ENABLE | + BBLCR3_L2_CRTN_PARITY_ENABLE); + wrmsr(BBL_CR_CTL3, bblctl3); + } + + /* If something goes wrong at L2 ECC setup, cache ECC + * will just remain disabled. + */ + set_l2_ecc(); + + if (calculate_l2_physical_address_range() != 0) { + printk(BIOS_ERR, "Failed to calculate L2 physical address range"); + goto bad; + } + + if (calculate_l2_cache_size() != 0) { + printk(BIOS_ERR, "Failed to calculate L2 cache size"); + goto bad; + } + + /* Turn on cache. Only L1 is active at this time. */ + enable_cache(); + + /* Get the calculated cache size from BBL_CR_CTL3[17:13] */ + bblctl3 = rdmsr(BBL_CR_CTL3); + cache_size = (bblctl3.lo & BBLCR3_L2_SIZE); + if (cache_size == 0) + cache_size = 0x1000; + cache_size = cache_size << 3; + + /* TODO: Cache size above is per bank. We're supposed to get + * the number of banks from BBL_CR_CTL3[12:11]. + * Confirm that this still provides the correct answer. + */ + bank = (bblctl3.lo >> 11) & 0x3; + if (bank == 0) + bank = 1; + + printk(BIOS_INFO, "size %dK... ", cache_size * bank * 4 / 1024); + + /* Write to all cache lines to initialize */ + + while (cache_size > 0) { + + /* Each cache line is 32 bytes. */ + cache_size -= 32; + + /* Update each way */ + + /* We're supposed to get L2 associativity from BBL_CR_CTL3[10:9]. + * But this code only applies to certain members of the P6 processor family + * and since all P6 processors have 4-way L2 cache, we can safely assume + * 4 way for all cache operations. + */ + + for (v = 0; v < 4; v++) { + /* Send Tag Write w/Data Write (TWW) to L2 controller + * MESI = Invalid + */ + if (signal_l2(cache_size, 0, 0, v, L2CMD_TWW | L2CMD_MESI_I) != 0) { + printk(BIOS_ERR, "Failed on signal_l2(%x, %x)\n", + cache_size, v); + goto bad; + } + } + } + printk(BIOS_DEBUG, "L2 Cache lines initialized\n"); + + /* Disable cache */ + disable_cache(); + + /* Set L2 cache configured in BBL_CR_CTL3 */ + bblctl3 = rdmsr(BBL_CR_CTL3); + bblctl3.lo |= BBLCR3_L2_CONFIGURED; + wrmsr(BBL_CR_CTL3, bblctl3); + + /* Invalidate cache and discard unsaved writes */ + asm volatile ("invd"); + + /* Write 0 to L2 control register 5 */ + if (write_l2(5, 0) != 0) { + printk(BIOS_ERR,"write_l2(5, 0) failed\n"); + goto done; + } + + bblctl3 = rdmsr(BBL_CR_CTL3); + if (signature == 0x650) { + /* Change the L2 latency to 0101 then back to + * original value. I don't know why this is needed - dpd + */ + eax = bblctl3.lo; + bblctl3.lo &= ~BBLCR3_L2_LATENCY; + bblctl3.lo |= 0x0a; + wrmsr(BBL_CR_CTL3, bblctl3); + bblctl3.lo = eax; + wrmsr(BBL_CR_CTL3, bblctl3); + } + + /* Enable L2 in BBL_CR_CTL3 */ + bblctl3.lo |= BBLCR3_L2_ENABLED; + wrmsr(BBL_CR_CTL3, bblctl3); + + /* Turn on cache. Both L1 and L2 are now active. Wahoo! */ +done: + result = 0; + goto out; +bad: + result = -1; +out: + printk(BIOS_INFO, "done.\n"); + return result; +} + diff --git a/src/include/cpu/intel/l2_cache.h b/src/include/cpu/intel/l2_cache.h new file mode 100644 index 0000000..fb81129 --- /dev/null +++ b/src/include/cpu/intel/l2_cache.h @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Keith Hui <buurin(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + */ + +/* The L2 cache definitions here only apply to SECC/SECC2 P6 family CPUs + * with Klamath (63x), Deschutes (65x) and Katmai (67x) cores. + * It is not required for Coppermine (68x) and Tualatin (6bx) cores. + * It is currently not known if Celerons with Mendocino core require + * the special initialization. + * Covington-core Celerons do not have L2 cache. + */ + +/* This is a straight port from coreboot v1. */ + +#ifndef __P6_L2_CACHE_H +#define __P6_L2_CACHE_H + +#define IA32_PLATFORM_ID 0x17 +#define EBL_CR_POWERON 0x2A + +#define BBL_CR_D0 0x88 +#define BBL_CR_D1 0x89 +#define BBL_CR_D2 0x8A +#define BBL_CR_D3 0x8B + +#define BBL_CR_ADDR 0x116 +#define BBL_CR_DECC 0x118 +#define BBL_CR_CTL 0x119 +#define BBL_CR_TRIG 0x11A +#define BBL_CR_BUSY 0x11B +#define BBL_CR_CTL3 0x11E + +#define BBLCR3_L2_CONFIGURED (1<<0) +/* bits [4:1] */ +#define BBLCR3_L2_LATENCY 0x1e +#define BBLCR3_L2_ECC_CHECK_ENABLE (1<<5) +#define BBLCR3_L2_ADDR_PARITY_ENABLE (1<<6) +#define BBLCR3_L2_CRTN_PARITY_ENABLE (1<<7) +#define BBLCR3_L2_ENABLED (1<<8) +/* bits [17:13] */ +#define BBLCR3_L2_SIZE (0x1f << 13) +#define BBLCR3_L2_SIZE_256K (0x01 << 13) +#define BBLCR3_L2_SIZE_512K (0x02 << 13) +#define BBLCR3_L2_SIZE_1M (0x04 << 13) +#define BBLCR3_L2_SIZE_2M (0x08 << 13) +#define BBLCR3_L2_SIZE_4M (0x10 << 13) +/* bits [22:20] */ +#define BBLCR3_L2_PHYSICAL_RANGE (0x7 << 20); +/* TODO: This bitmask does not agree with Intel's documentation. + * Get confirmation one way or another. + */ +#define BBLCR3_L2_SUPPLIED_ECC 0x40000 + +#define BBLCR3_L2_HARDWARE_DISABLE (1<<23) +/* Also known as... */ +#define BBLCR3_L2_NOT_PRESENT (1<<23) + +/* L2 commands */ +#define L2CMD_RLU 0x0c /* 01100 Data read w/ LRU update */ +#define L2CMD_TRR 0x0e /* 01110 Tag read with data read */ +#define L2CMD_TI 0x0f /* 01111 Tag inquiry */ +#define L2CMD_CR 0x02 /* 00010 L2 control register read */ +#define L2CMD_CW 0x03 /* 00011 L2 control register write */ +#define L2CMD_TWR 0x08 /* 010-- Tag read w/ data read */ +#define L2CMD_TWW 0x1c /* 111-- Tag write w/ data write */ +#define L2CMD_TW 0x10 /* 100-- Tag write */ +/* MESI encode for L2 commands above */ +#define L2CMD_MESI_M 3 +#define L2CMD_MESI_E 2 +#define L2CMD_MESI_S 1 +#define L2CMD_MESI_I 0 + +extern int calculate_l2_latency(void); +extern int signal_l2(u32 address_low, u32 data_high, u32 data_low, int way, u8 command); +extern int read_l2(u32 address); +extern int write_l2(u32 address, u32 data); +extern int test_l2_address_alias(u32 address1, u32 address2, + u32 data_high, u32 data_low); +extern int calculate_l2_cache_size(void); +extern int calculate_l2_physical_address_range(void); +extern int set_l2_ecc(void); + +extern int p6_configure_l2_cache(void); + +#endif /* __P6_L2_CACHE_H */

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Patch set updated: e83dd24 AMD family10 northbridge wrapper, supermicro/h8qgi mainboard
by Kerry She 28 Jul '11

28 Jul '11

Kerry She (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/121 -gerrit commit e83dd24e1d779dd72ccdada77d382aa089e3855f Author: Kerry She <shekairui(a)gmail.com> Date: Thu Jul 28 11:02:43 2011 +0800 AMD family10 northbridge wrapper, supermicro/h8qgi mainboard update southbridge (IO hub) search function and VGA destination link setting in amd family10 northbridge wrapper. family10_scan_chains() not check link_num any more during IO hub searching, amdfam10_create_vga_resource() using SbLink ID to set VGA destination link, instead of link_num of the device link list. This change make a more clean devicetree of mainboard using amd family10 wrapper, and supermicro/h8qgi mainboard family10 devicetree changes are include herein. Change-Id: I45e071ec2a7735ededd056e0ff38ba016f700ff4 Signed-off-by: Kerry She <kerry.she(a)amd.com> Signed-off-by: Kerry She <shekairui(a)gmail.com> --- src/mainboard/supermicro/h8qgi/devicetree.cb | 62 +--------------------- src/northbridge/amd/agesa/family10/northbridge.c | 7 +-- 2 files changed, 5 insertions(+), 64 deletions(-) diff --git a/src/mainboard/supermicro/h8qgi/devicetree.cb b/src/mainboard/supermicro/h8qgi/devicetree.cb index 9afaac7..a1a0bdf 100755 --- a/src/mainboard/supermicro/h8qgi/devicetree.cb +++ b/src/mainboard/supermicro/h8qgi/devicetree.cb @@ -25,10 +25,7 @@ chip northbridge/amd/agesa/family10/root_complex device pci_domain 0 on subsystemid 0x15d9 0xab11 inherit #SuperMicro chip northbridge/amd/agesa/family10 # CPU side of HT root complex - device pci 18.0 on end # link 0 - device pci 18.0 on end # link 1 - device pci 18.0 on end # link 2 - device pci 18.0 on # link3 SB on socket0 link 2, on internal Node0 Link 3 + device pci 18.0 on # IO-HUB on socket0 link 2(internal Node0 Link 3) chip southbridge/amd/sr5650 # Southbridge PCI side of HT Root complex device pci 0.0 on end # HT Root Complex 0x9600 device pci 0.1 off end # CLKCONFIG @@ -46,8 +43,7 @@ chip northbridge/amd/agesa/family10/root_complex device pci d.0 on end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576 register "gpp1_configuration" = "0" # Configuration 16:0 default register "gpp2_configuration" = "1" # Configuration 8:8 - register "gpp3a_configuration" = "2" # Configuration 4:1:1:0:0:0 - #register "gpp3a_configuration" = "11" # Configuration 1:1:1:1:1:1 + register "gpp3a_configuration" = "2" # 2 Configuration 4:1:1:0:0:0, 11 Configuration 1:1:1:1:1:1 register "port_enable" = "0x2104" end #southbridge/amd/sr5650 chip southbridge/amd/sp5100 # it is under NB/SB Link, but on the same pci bus @@ -115,61 +111,7 @@ chip northbridge/amd/agesa/family10/root_complex register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE end # southbridge/amd/sp5100 end # device pci 18.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - device pci 19.4 on end - - - device pci 1a.0 on end - device pci 1a.0 on end - device pci 1a.0 on end - device pci 1a.0 on # another 56x0 on socket 1 Link 2, internal Node0 link 3 - end - device pci 1a.1 on end - device pci 1a.2 on end - device pci 1a.3 on end - device pci 1a.4 on end - - device pci 1b.0 on end - device pci 1b.1 on end - device pci 1b.2 on end - device pci 1b.3 on end - device pci 1b.4 on end - - - device pci 1c.0 on end - device pci 1c.1 on end - device pci 1c.2 on end - device pci 1c.3 on end - device pci 1c.4 on end - - device pci 1d.0 on end - device pci 1d.1 on end - device pci 1d.2 on end - device pci 1d.3 on end - device pci 1d.4 on end - - - device pci 1e.0 on end - device pci 1e.1 on end - device pci 1e.2 on end - device pci 1e.3 on end - device pci 1e.4 on end - - device pci 1f.0 on end - device pci 1f.1 on end - device pci 1f.2 on end - device pci 1f.3 on end - device pci 1f.4 on end - end #chip northbridge/amd/agesa/family10 # CPU side of HT root complex end #pci_domain end #northbridge/amd/agesa/family10/root_complex diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index b3e4c63..8e8a84c 100755 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -693,8 +693,8 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) if (link == NULL) return; - printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link->link_num); - set_vga_enable_reg(nodeid, link->link_num); + printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, sysconf.sblk); + set_vga_enable_reg(nodeid, sysconf.sblk); } static void amdfam10_set_resources(device_t dev) @@ -728,14 +728,13 @@ static unsigned amdfam10_scan_chains(device_t dev, unsigned max) { unsigned nodeid; struct bus *link; - unsigned sblink = sysconf.sblk; device_t io_hub = NULL; u32 next_unitid = 0xff; nodeid = amdfam10_nodeid(dev); if (nodeid == 0) { for (link = dev->link_list; link; link = link->next) { - if (link->link_num == sblink) { /* devicetree put IO Hub on link_lsit[3] */ + if (link->link_num == 0) { /* IO Hub on link_lsit[0] in devicetree */ io_hub = link->children; if (!io_hub || !io_hub->enabled) { die("I can't find the IO Hub, or IO Hub not enabled, please check the device tree.\n");

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ASRock e350m1: network problems
by perh52＠runbox.com 28 Jul '11

28 Jul '11

On the SATA MSI disable problem: calling sbAfterPciInit from cpu_bus_init succeeds in disabling MSI for SATA. So now the linux driver correctly does not try to enable MSI for SATA. But that code is not minimal and might not be the right thing to do. Back to the ethernet problem. Comparing PCI configuration spaces for 00:15.1 I see that coreboot : runs at 2.5GT/s (PCIe generation 1 speed), and vendor fw: runs at 5GT/s (PCIe generation 2 speed). PCI config 0x88 is the relevant one. See SB800 RPR Section 5.19 "GPP Gen2 Speed Change" and vendorcode/amd/cimx/sb800/Gpp.c If I enable GppGen2 in the config as in the patch below then the kernel irq errors disappear and incoming ethernet transmissions seem ok. This could be made settable for each mainboard (e.g. from devicetree.cb) if necessary, but is there any need ? The SB800 BIOS Dev Guide Section 1.3 (small print) says only SB810 and SB850 support Gen2 (so I guess we have one of those), so perhaps. Does anyone know? Signed-off-by: Per Hansen <perh52(a)runbox.com> diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index 0a09e11..09b4a64 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -101,7 +101,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config) //sb_config->PORTCONFIG[0].PortCfg.PortHotPlug = TRUE; sb_config->GppUnhidePorts = TRUE; //visable always, even port empty //sb_config->NbSbGen2 = TRUE; - //sb_config->GppGen2 = TRUE; + sb_config->GppGen2 = TRUE; //cimx BTS fix sb_config->GppMemWrImprove = TRUE;

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coreboot July 2011