coreboot July 2011

coreboot@coreboot.org

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Patch merged into master: e1bf4df Add the AMD Family10 Agesa code
by gerrit＠coreboot.org 15 Jul '11

15 Jul '11

the following patch was just integrated into master: commit e1bf4df28b64e4758f3220afb37f14fcea97669d Author: efdesign98 <efdesign98(a)gmail.com> Date: Wed Jul 13 16:43:39 2011 -0700 Add the AMD Family10 Agesa code This change officially adds the Agesa code for the AMD Family 10 cpus. This code supports the G34 and C32 sockets. Change-Id: Idae50417e530ad40a29fb6fff5b427f6b138126c Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com> Signed-off-by: efdesign98 <efdesign98(a)gmail.com> See http://review.coreboot.org/95 for details. -gerrit

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New patch to review: 85b6888 libpayload: Provide dummy getenv()
by Patrick Georgi 15 Jul '11

15 Jul '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/105 -gerrit commit 85b688852fe4d3d3e5b76edbb91cdd553d7bd3ca Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Jul 12 15:50:54 2011 +0200 libpayload: Provide dummy getenv() Change-Id: I419fcb16e0b10dee9195072e0e6befa6c9e61a69 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- payloads/libpayload/include/stdlib.h | 2 +- payloads/libpayload/libc/lib.c | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletions(-) diff --git a/payloads/libpayload/include/stdlib.h b/payloads/libpayload/include/stdlib.h index 52162fe..47b666a 100644 --- a/payloads/libpayload/include/stdlib.h +++ b/payloads/libpayload/include/stdlib.h @@ -143,5 +143,5 @@ void exit(int status) __attribute__ ((noreturn)); /** @} */ void qsort(void *aa, size_t n, size_t es, int (*cmp)(const void *, const void *)); - +char *getenv(const char*); #endif diff --git a/payloads/libpayload/libc/lib.c b/payloads/libpayload/libc/lib.c index c8539cb..616a7c6 100644 --- a/payloads/libpayload/libc/lib.c +++ b/payloads/libpayload/libc/lib.c @@ -120,3 +120,9 @@ void exit(int status) } int errno; + +char *getenv(const char *name) +{ + return NULL; +} +

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New patch to review: 40fcefc libpayload: Improve compatibility
by Patrick Georgi 15 Jul '11

15 Jul '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/104 -gerrit commit 40fcefcdcfa74405fc3c6fba571557520d4c3096 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Jul 12 15:02:04 2011 +0200 libpayload: Improve compatibility Define INT_MAX, EOF and make sure size_t is available. Change-Id: I1b4b717d2545ea8312ec52339300307a5bd68f8a Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- payloads/libpayload/include/limits.h | 1 + payloads/libpayload/include/stdarg.h | 1 + payloads/libpayload/include/stdio.h | 2 ++ 3 files changed, 4 insertions(+), 0 deletions(-) diff --git a/payloads/libpayload/include/limits.h b/payloads/libpayload/include/limits.h index be7dde0..2fecf23 100644 --- a/payloads/libpayload/include/limits.h +++ b/payloads/libpayload/include/limits.h @@ -41,5 +41,6 @@ #endif #define UINT_MAX (unsigned int)0xffffffff +#define INT_MAX (unsigned int)0x7fffffff #endif diff --git a/payloads/libpayload/include/stdarg.h b/payloads/libpayload/include/stdarg.h index 7a6244e..077645f 100644 --- a/payloads/libpayload/include/stdarg.h +++ b/payloads/libpayload/include/stdarg.h @@ -30,6 +30,7 @@ #ifndef _LIBPAYLOAD_STDARG_H #define _LIBPAYLOAD_STDARG_H +#include <stddef.h> #include_next <stdarg.h> /** diff --git a/payloads/libpayload/include/stdio.h b/payloads/libpayload/include/stdio.h index d39e9f8..924d17e 100644 --- a/payloads/libpayload/include/stdio.h +++ b/payloads/libpayload/include/stdio.h @@ -32,6 +32,8 @@ #include <stddef.h> +#define EOF (-1) + typedef struct _FILE FILE; extern FILE *stdout, *stdin, *stderr;

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New patch to review: 8fc9a65 libpayload: update defconfig
by Patrick Georgi 15 Jul '11

15 Jul '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/103 -gerrit commit 8fc9a65e9d4579e64d7a6470c2ab7b4ed61a1aec Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Jul 7 15:41:53 2011 +0200 libpayload: update defconfig Change-Id: I99c18a6ba867df53b7c6bc9dcaafc96f56132242 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- payloads/libpayload/configs/defconfig | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/payloads/libpayload/configs/defconfig b/payloads/libpayload/configs/defconfig index 77b71b7..5c467a3 100644 --- a/payloads/libpayload/configs/defconfig +++ b/payloads/libpayload/configs/defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # libpayload version: 0.2.0 -# Sat Sep 25 14:01:26 2010 +# Thu Jul 7 13:19:13 2011 # # @@ -16,6 +16,7 @@ # CONFIG_TARGET_I386=y # CONFIG_TARGET_POWERPC is not set +# CONFIG_MEMMAP_RAM_ONLY is not set # CONFIG_MULTIBOOT is not set #

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make crossgcc failure
by Hongyuan Zhu 15 Jul '11

15 Jul '11

My board is AMD X64. And when I git the most recent version and make crossgcc, the error message shows eddy@EddyPC:~/trunk$ make crossgcc Welcome to the coresystems cross toolchain builder v1.03 (December 16th, 2010) Downloading tar balls ... * gmp-5.0.1.tar.bz2 (downloading) * mpfr-3.0.0.tar.bz2 (downloading) * mpc-0.8.2.tar.gz (downloading) * libelf-0.8.13.tar.gz (downloading) * gcc-core-4.5.2.tar.bz2 (downloading) * binutils-2.20.1.tar.bz2 (downloading) * gdb-7.2.tar.bz2 (downloading) Downloaded tar balls ... ok Unpacking and patching ... * gmp-5.0.1.tar.bz2 * mpfr-3.0.0.tar.bz2 o mpfr-3.0.0_allpatches_20101216.patch * mpc-0.8.2.tar.gz * libelf-0.8.13.tar.gz * gcc-core-4.5.2.tar.bz2 o gcc-4.5.2_pragma.patch * binutils-2.20.1.tar.bz2 o binutils-2.20.1_no-bfd-doc.patch * gdb-7.2.tar.bz2 Unpacked and patched ... ok Building GMP 5.0.1 ... failed make[1]: *** [build] 错误 1 make: *** [crossgcc] 错误 2 -- Sincerely, Edward Z.(Hongyuan Zhu) Biomedical Engineering of Master SCSB, Shanghai Jiaotong Univ. NO.800, Dongchuan RD, Shanghai Nantong, Jiangsu Province, PR China

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New patch to review: b631f90 Libpayload: default DESTDIR for 'make install'
by Tadas Slotkus 15 Jul '11

15 Jul '11

Tadas Slotkus (devtadas(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/102 -gerrit commit b631f903a8660dba9bdb9611d7b985f00d2a4872 Author: Tadas Slotkus <devtadas(a)gmail.com> Date: Fri Jul 15 03:41:11 2011 +0300 Libpayload: default DESTDIR for 'make install' If you would try download FILO via svn, then you probably get error message about libpayload install. This enables manually installing libpayload in legacy style :) Change-Id: I9f52be939303c5913611f21477d681e11d286382 Signed-off-by: Tadas Slotkus <devtadas(a)gmail.com> --- payloads/libpayload/Makefile.inc | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc index 08f7c9f..03862ca 100644 --- a/payloads/libpayload/Makefile.inc +++ b/payloads/libpayload/Makefile.inc @@ -33,6 +33,7 @@ export KERNELVERSION := 0.2.0 ARCHDIR-$(CONFIG_TARGET_I386) := i386 ARCHDIR-$(CONFIG_TARGET_POWERPC) := powerpc +DESTDIR ?= install real-target: lib

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New patch to review: b551855 Do not use C bit-fields to manipulate EHCI host bridge portsc_t register.
by Steven A. Falco 15 Jul '11

15 Jul '11

Steven A. Falco (sfalco(a)coincident.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/101 -gerrit commit b551855e895382b7570881bebcf28809a5619d63 Author: Steven A. Falco <sfalco(a)coincident.com> Date: Thu Jul 14 19:56:50 2011 -0400 Do not use C bit-fields to manipulate EHCI host bridge portsc_t register. I have observed two separate EHCI host bridges that do not tolerate using C bit-fields to manipulate the portsc_t register. The reason for this is that the EHCI spec says that PORT_PE must go to 0 at the time that PORT_RESET goes to 1. Naturally this cannot be done using separate bit-fields for each bit. Instead, we use a temporary register and do explicit read-modify-write cycles. Signed-off-by: Steven A. Falco <sfalco(a)coincident.com> Change-Id: If138faee43e0293efa203b86f7893fdf1e811269 --- payloads/libpayload/drivers/usb/ehci_private.h | 29 +++++++++++++- payloads/libpayload/drivers/usb/ehci_rh.c | 49 +++++++++++++++++------ 2 files changed, 64 insertions(+), 14 deletions(-) diff --git a/payloads/libpayload/drivers/usb/ehci_private.h b/payloads/libpayload/drivers/usb/ehci_private.h index e63a81d..07c1a2f 100644 --- a/payloads/libpayload/drivers/usb/ehci_private.h +++ b/payloads/libpayload/drivers/usb/ehci_private.h @@ -37,8 +37,34 @@ #define FLADJ 0x61 #define FLADJ_framelength(x) (((x)-59488)/16) +#define PORT_WKOC_E (1<<22) +#define PORT_WKDISC_E (1<<21) +#define PORT_WKCONN_E (1<<20) +#define PORT_TEST_PKT (0x4<<16) +#define PORT_LED_OFF (0<<14) +#define PORT_LED_AMBER (1<<14) +#define PORT_LED_GREEN (2<<14) +#define PORT_LED_MASK (3<<14) +#define PORT_OWNER (1<<13) +#define PORT_POWER (1<<12) +#define PORT_LINESTATUS_MASK (3<<10) +#define PORT_LINESTATUS_KSTATE (1<<10) +#define PORT_RESET (1<<8) +#define PORT_SUSPEND (1<<7) +#define PORT_RESUME (1<<6) +#define PORT_OCC (1<<5) +#define PORT_OC (1<<4) +#define PORT_PEC (1<<3) +#define PORT_PE (1<<2) +#define PORT_CSC (1<<1) +#define PORT_CONNECT (1<<0) + typedef union { - u32 val; + volatile u32 val; + // WARNING - some controllers require port_enable and port_reset to + // change atomically. Therefore, using these separate bits is not + // recommended. +#if 0 volatile struct { unsigned long current_conn_status:1; unsigned long conn_status_change:1; @@ -60,6 +86,7 @@ typedef union { unsigned long wake_on_overcurrent_en:1; unsigned long:9; } __attribute__ ((packed)); +#endif } __attribute__ ((packed)) portsc_t; typedef struct { diff --git a/payloads/libpayload/drivers/usb/ehci_rh.c b/payloads/libpayload/drivers/usb/ehci_rh.c index 5eaeeb6..c588a3d 100644 --- a/payloads/libpayload/drivers/usb/ehci_rh.c +++ b/payloads/libpayload/drivers/usb/ehci_rh.c @@ -54,14 +54,19 @@ static void ehci_rh_hand_over_port (usbdev_t *dev, int port) { volatile portsc_t *p = &(RH_INST(dev)->ports[port]); + volatile u32 tmp; printf("giving up port %x, it's USB1\n", port+1); /* Lowspeed device. Hand over to companion */ - p->port_owner = 1; - do {} while (!p->conn_status_change); + tmp = p->val; + tmp |= PORT_OWNER; + p->val = tmp; + while (!(p->val & PORT_CSC)); /* RW/C register, so clear it by writing 1 */ - p->conn_status_change = 1; + tmp = p->val; + tmp |= PORT_CSC; + p->val = tmp; return; } @@ -69,41 +74,54 @@ static void ehci_rh_scanport (usbdev_t *dev, int port) { volatile portsc_t *p = &(RH_INST(dev)->ports[port]); + volatile u32 tmp; if (RH_INST(dev)->devices[port]!=-1) { printf("Unregister device at port %x\n", port+1); usb_detach_device(dev->controller, RH_INST(dev)->devices[port]); RH_INST(dev)->devices[port]=-1; } /* device connected, handle */ - if (p->current_conn_status) { + if (p->val & PORT_CONNECT) { mdelay(100); - if (p->line_status == 0x1) { + if ((p->val & PORT_LINESTATUS_MASK) == PORT_LINESTATUS_KSTATE) { ehci_rh_hand_over_port(dev, port); return; } - p->port_enable = 0; - p->port_reset = 1; + + /* Remove port_enable, set port_reset. This must be atomic. */ + tmp = p->val; + tmp &= ~PORT_PE; + tmp |= PORT_RESET; + p->val = tmp; + mdelay(50); - p->port_reset = 0; + tmp &= ~PORT_RESET; + p->val = tmp; + /* Wait for flag change to finish. The controller might take a while */ - while (p->port_reset) ; - if (!p->port_enable) { + while(p->val & PORT_RESET) ; + if (!(p->val & PORT_PE)) { ehci_rh_hand_over_port(dev, port); return; } printf("port %x hosts a USB2 device\n", port+1); RH_INST(dev)->devices[port] = usb_attach_device(dev->controller, dev->address, port, 2); } + /* RW/C register, so clear it by writing 1 */ - p->conn_status_change = 1; + tmp = p->val; + tmp |= PORT_CSC; + p->val = tmp; } static int ehci_rh_report_port_changes (usbdev_t *dev) { + volatile portsc_t *p; int i; for (i=0; i<RH_INST(dev)->n_ports; i++) { - if (RH_INST(dev)->ports[i].conn_status_change) + p = &(RH_INST(dev)->ports[i]); + if (p->val & PORT_CSC) return i; } return -1; @@ -121,6 +139,8 @@ ehci_rh_poll (usbdev_t *dev) void ehci_rh_init (usbdev_t *dev) { + volatile portsc_t *p; + volatile u32 tmp; int i; dev->destroy = ehci_rh_destroy; @@ -135,8 +155,11 @@ ehci_rh_init (usbdev_t *dev) RH_INST(dev)->devices = malloc(RH_INST(dev)->n_ports * sizeof(int)); for (i=0; i < RH_INST(dev)->n_ports; i++) { + p = &(RH_INST(dev)->ports[i]); + tmp = p->val; + tmp |= PORT_POWER; + p->val = tmp; RH_INST(dev)->devices[i] = -1; - RH_INST(dev)->ports[i].pp = 1; } dev->address = 0;

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Coreboot on AMD Geode; No VGA
by Nils 14 Jul '11

14 Jul '11

Hi Andrew, As i understand it the description of the problem belongs to the previous V2 version of the VGA patch witch this V3 version (at the bottom off the tread) together with the mode hack patch (little patch to vgatables.c) addresses. Thanks, Nils.

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MSI E350IA-E45 Board Developments
by Andrew Bolster 14 Jul '11

14 Jul '11

I'm getting my hands on this board soon for another project and would like to try coreboot off of it. The Mainboard is a Model MS-7698; not currently in the CB list, although it appears that most of the other pieces are already there in one shape or form so it *should* just be a case of stitching it all together as a mainboard descriptor. After some google fu, I came across this [1] thread that indicated that Tom Sylla had been looking into porting coreboot to this board. This is kinda a two fold post; Tom, if you're out there, can you give an update to your progress if any, and do you want an understudy to help out? I'm not very experienced in this area but I'm stubborn, so would love to actually contribute something useful back to the community for a change! PS, Anyone else can answer too... :P [1] http://comments.gmane.org/gmane.linux.bios/65839 Regards Andrew Bolster <http://andrewbolster.info/blog/?utm_source=correspondence&utm_medium=email&…><http://www.linkedin.com/in/andrewbolster><http://facebook.com/andrew.bolster><http://twitter.com/bolster> No trees were killed to send this message, but a large number of electrons were terribly inconvenienced.I enjoy the massacre of ads. This sentence will slaughter ads without a messy bloodbath.

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Coreboot on AMD Geode; No VGA
by Nils 14 Jul '11

14 Jul '11

Andrew Bolster wrote: > Can anyone point me in the direction of how to set up coreboot + > seabios so that it actually uses the VGA? I am struggling with the same problem for some time now. Extracting the original VGA as Peter suggests won't work because the LX VSA we use is stripped down and doesn't have the graphics init routines in it anymore. The most promising solution that should work (i didn't test it yet) i could find is this: http://patchwork.coreboot.org/patch/190/ It seems Chris is not working on it anymore and Kevin did not approve it in it's current state for inclusion in Seabios. Thanks, Nils.

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coreboot July 2011